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Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese
Concurrent statements 2
• with-select-when output_signal: output(s),
sel: input
• when-else signals in expa, expb, …, expx: inputs
Kuruvilla Varghese 1
2
with … select 3
with a select
with a select y <= b when “00”,
y <= ‘0’ when “00”, not(b) when “01”,
‘0’ when “01”, c when “10”,
‘0’ when “10”, b when “11”,
‘1’ when “11”, c when others;
‘0’ when others;
a(1) a(0) b c y
• Truth Table
0 0 0 x 0
a(1) a(0) y 0 0 1 x 1
0 0 0 0 1 0 x 1
0 1 0 0 1 1 x 0
1 0 0 1 0 x 0 0
1 1 1 1 0 x 1 1
y = a(1) and a(0) 1 1 0 x 0
Kuruvilla Varghese
1 1 1 x 1
with … select 4
Truth Table
a(1) a(0) b c y
0 0 0 x 0
0 0 1 x 1 Equation
0 1 0 x 1
y = a(1)/ and a(0)/ and b or
0 1 1 x 0
a(1)/ and a(0) and b/or
1 0 x 0 0
1 0 x 1 1 a(1) and a(0)/ and c or
1 1 0 x 0 a(1) and a(0) and b
1 1 1 x 1
Kuruvilla Varghese 2
4
with - select 5
• For all the mutually exclusive values of an • It is very easy to work out the equations
input signal (‘select’ signal) or signals, from the descriptions, each choice
output is expressed, sometime as function forming a minterm or ‘OR’ of minterms
of other inputs. (in case, if an expression is used).
• In the simplest case, when output values • For Simulator, event on any input signal
are specified, it is a plain truth table and (select signal, signals in expression)
the choices specify the minterms of input would trigger a computation of the output
signals. signal.
• When output is expressed as a function of • Synthesis tool do not use the truth table,
other inputs for a choice of ‘select’ signal, if the standard operators/structures could
that may expand to multiple rows of truth be inferred from the code.
table.
Kuruvilla Varghese
With-select-when 6
4-to-1 Multiplexer • Equations
Kuruvilla Varghese 3
6
With-select-when 7
a • Example - choices
b y
c with numb select
prime <= ‘1’ when “010” | “011” | “101”
with b select | 111”,
y <= func1(a, c) when value_1, ‘0’ when others;
func2(a, c) when value_2,
…
funci(a, c) when value_i,
…
funcn(a, c) when others;
when - else 8
• Syntax • General conditions
e.g. condition1: (a = b)
output_signal <= expa when cond1 else condition2: (d > 3)
expb when cond2 else
• Priority
…
expx when condx else
expy;
• Truth Table ?
output_signal: output(s), • Yes, much more abstract
condi: condition in terms of inputs
expi: expression in terms of inputs
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when - else 9
Kuruvilla Varghese
when - else 10
p(1) p(0) q(1) q(0) r(1) r(0) y
0 0 0 0 0 0 c
0 0 0 0 0 1 c
0 0 0 0 1 0 b
0 1 1 0 0 0 c
0 1 1 0 0 1 c
0 1 1 0 1 0 b
1 1 1 1 1 1 c
Kuruvilla Varghese 5
10
when - else 11
• For the simulator, an event on any of
y <= a when (p > q) else the signals in conditions or
b when (r = 2) else expressions will trigger the
c; computation of the output signal.
• In the code above, first condition • Synthesis tool may not use the truth
translates to all those values of p and table, if the standard operators/
q for which (p > q). i.e. it translates structures could be inferred from the
to multiple rows of the truth table. In code
this case, signal ‘r’ is a don’t care
• When it comes to second condition, prio <= “00” when (a = ‘1’) else
it translates to all those values of p, q “01” when (b = ‘1’) else
and r for which p <= q and r = 2.
Once again, it means multiple rows “10” when (c = ‘1’) else
of the truth table. “11”;
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when - else 13
en
dir architecture dflow of transc is
begin
a b b <= a when (dir = ‘1’ and en = ‘1’) else
(others => ‘Z’) ;
a <= b when (dir = ‘0’ and en = ‘1’ ) else
library ieee; (others => ‘Z’ ) ;
use ieee.std_logic_1164.all; end dflow;
Kuruvilla Varghese
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Sequential Statements 14
• if-then-else a, b, signals of cond1: inputs
• case-when y: output
15
if-then-else 16
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if-then-else 17
if cond1 then
if cond2 then
y <= a;
elsif
…
end if;
elsif
…
end if;
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if-then-else 18
if cond1 then
if cond1 then
y <= a;
y <= a;
end if; else
0
y <= y; y
end if; a 1
cond1
• Implied Memory / Inferred
latch
Kuruvilla Varghese 9
18
Implied Memory / Inferred latch 19
• Concurrent equivalents • Implied Memory / Inferred latch is
with en select useful in specifying the behaviour of
latches and flip-flops or registers
y <= a when ‘1’;
with en select
y <= a when ‘1’,
unaffected when others;
y <= a when en = ‘1’;
y <= a when en = ‘1’ else
unaffected;
• Concurrent: unaffected
• Sequential: null
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Kuruvilla Varghese 10
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Implied Memory / Inferred latch 21
• It is difficult to expose this error in • If the designer has inadvertently
simulation, as just verifying all missed specifying an output, then
conditions would not be enough. working out the condition for
• Suppose, one output was missing in exposing such an error would be
condition 3, and the previous remote.
condition simulated has the same
value expected of this output in
condition 3, then output will be
correct.
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Case-when 22
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Case-when Nesting 24
• “case … when …’’ can be nested • Equation
with “if .. then ..’’ to specify
complex structure / behavior.
y = a and decode of (sel = val1)
case sel is and cond2 or …
when val1 =>
if cond2 then
y <= a;
elsif
…
end if;
when val2 =>
…
end case;
Kuruvilla Varghese 12
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Case-when 25
library ieee;
use ieee.std_logic_1164.all;
entity dmux1t4 is
a
1 0
a, b, c, d: out std_logic_vector(3
d
3
downto 0));
end dmux1t4;
s
25
Demultiplexer 26
process (s, y) when others =>
begin a <= “0000”; b <= “0000”; c <= “0000”;
case s is d <= “0000”;
when “00” => end case;
a <= y; b <= “0000”; c <= “0000”; end process;
d <= “0000”; end arch_dmux1t4;
when “01” =>
b <= y; a <= “0000”; c <= “0000”;
d <= “0000”;
when “10” =>
c <= y; a <= “0000”; b <= “0000”;
d <= “0000”;
when “11” =>
d <= y; a <= “0000”; b <= “0000”;
c <= “0000”;
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Demultiplexer 27
process (s, y) when others =>
begin a <= “0000”; b <= “0000”;
a <= “0000”; b <= “0000”; c <= “0000”; d <= “0000”;
c <= “0000”; d <= “0000”; end case;
case s is end process;
when “00” => end arch_dmux1t4;
a <= y;
when “01” =>
b <= y;
when “10” =>
c <= y;
when “11” =>
d <= y;
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Loops 28
• Concurrent: generate
• Sequential: loop
• Generate
– Equations
– Component Instantiations
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Generate - Example 29
carry(0)
sum(0)
a(0)
a sum b(0) carry(1)
b
cin
a sum(1)
a(1)
b
b(1) carry(2)
b
cout
cin
a
cin
carry(7) sum(7)
a(7)
b(7) carry(8)
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Generate 30
carry(0)
sum(0) • Equations
a(0)
carry(1) for i in 0 to 7 generate
b(0)
sum(i) <= a(i) xor b(i) xor carry(i);
carry(i+1) <= (a(i) and b(i)) or ((a(i) or
sum(1)
a(1) b(i)) and carry(i));
b(1) carry(2) end generate;
• Component Instantiations
for i in 0 to 7 generate
carry(7) sum(7) u1: fulladd port map (carry(i), a(i), b(i),
a(7)
carry(8) sum(i), carry(i+1));
b(7)
end generate;
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Conditional Loops 31
• if ... Generate (Concurrent • If the condition is true, then the
statement, no else /elsif) generate is done
• Useful to generate irregular
loop_label: if (condition / expression) structures, i.e. Conditional on
generate loop index (e.g. i = 2) different
… structures can be generated
…
end generate;
Kuruvilla Varghese
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if condition then
if condition then
exit;
next;
end if;
end if;
Kuruvilla Varghese
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17