Sequential Circuits: D Flip Flop 34

d q • Flip Flops behavior is modeled in

clk VHDL, not their equivalent circuit.
• Behavior: Up on the active edge of
the clock the input is transferred to
the output and is held (Memory)
until the next active clock edge.
d

clk

Kuruvilla Varghese

34

Flip Flop - Simulator 35

process (clk) • ‘clk’ in the sensitivity list computes

begin the process on both the edges of
if (clk = ‘1’) then clocks.
q <= d; • The clause (clk = ‘1’) selects the
positive edge of the clock.
end if;
• The Implied memory / Inferred latch
end process; takes care of memory

Kuruvilla Varghese 1
35
 Flip Flop - Simulator 36
• But synthesis tools ignore d q
sensitivity list, hence the above
clk
code would mean a (transparent)
latch, as the events on ‘clk’ is not
considered. Whenever ‘clk’ is
high ‘q’ gets ‘d’ and on the
negative edge the last value of d

‘q’ is held. (Memory) clk

Kuruvilla Varghese

36

FF – Synthesis, Simulation 37

• clk’event is a predefined attribute

process (clk) which is true whenever there is an
begin event on the signal ‘clk’. The
if (clk’event and clk = ‘1’) then statement clk’event and clk = ‘1’,
q <= d; would mean the positive edge of
end if; clock. Statement clk’event would be
end process; redundant for simulation.
• The statement clk’event and clk =
‘1’, would also be true when clk
transits from ‘U’ to ‘1’ (std_logic),
this could occur at the beginning of
simulation.

Kuruvilla Varghese 2
37
 FF – Synthesis, Simulation 38

• To avoid this, functions

‘rising_edge(clk)’ and
‘falling_edge(clk)’ in
ieee.std_logic_1164 package
could be used

• Equivalent concurrent statement

q <= d when clk’event and clk = ‘1’;

Kuruvilla Varghese

38

D Latch 39

d
process (clk, d)
clk begin
if (clk = ‘1’) then
q
q <= d;
end if;
Synthesis Tool end process;

process (clk)
begin
if (clk = ‘1’) then
q <= d;
end if;
end process;
Kuruvilla Varghese 3
39
 D Latch 40

• ‘clk’ in the sensitivity list invokes • wait

process for computation only on clock
edges, hence ‘d’ is added to sensitivity
list to respond to changes in the input ‘d’ process
• The statement clk = ‘1’ takes care of the
begin
transparent latch behavior. if (clk = ‘1’) then
• Implied memory takes care of the latch q <= d;
operation end if;
wait on clk, d;
end process;
• Equivalent concurrent statement

q <= d when clk = ‘1’;

Kuruvilla Varghese

40

Wait 41

• wait on sensitivity-list;
• wait until boolean-expression;
• wait for time-expression;

• Examples
wait on clk, d;
wait until count = 10;
wait for 10 ns;
wait on clk for 17 ns;
wait until sum > 100 for 50 ns;

Kuruvilla Varghese 4
41
 Asynchronous Reset 42

process (clk, reset)

d q begin
clk if (reset = ‘1’) then
AR
q <= ‘0’;
elsif (clk’event and clk = ‘1’) then
q <= d;
end if;
process (clk) end process;
begin
• Concurrent statements
if (clk’event and clk = ‘1’) then
q <= d;
q <= ‘0’ when (reset = ‘1’) else
end if;
d when (clk’event and clk = ‘1’);
end process;

Kuruvilla Varghese

42

Registers with comb circuit 43

process (clk)
begin a
d q
if (clk’event and clk = ‘1’) then b
q <= a xor b; clk

end if;
end process;
• This means a single process can
code registers preceded by any
combinational circuit

Kuruvilla Varghese 5
43
 Registers with comb circuit 44

process (clk)
begin
comb
if (clk’event and clk = ‘1’) then
a
d q
b
** code for combinational
circuit ** clk

end if;
end process; • Note: Any assignment you do
here will have flip-flop/register

Kuruvilla Varghese

44

Registers with comb circuit 45

• Combinational circuit at the
input ‘d’ can be coded within the
clk’event and clk = ‘1’ statement
• This code being in process
should be using if … then, case
… when, for … etc.
• Any signal connected to ‘d’ is
synchronous with clock, hence
such code always represent
synchronous behavior

Kuruvilla Varghese 6
45
 FF Synchronous Reset 46

• Asynchronous Reset
d q process (clk, reset)
clk begin
if (reset = ‘1’) then
SR q <= ‘0’;
elsif (clk’event and clk = ‘1’) then
q <= d;
end if;
end process;

Kuruvilla Varghese

46

FF Synchronous Reset 47

d q process (clk)
clk begin
if (clk’event and clk = ‘1’) then
SR
if (reset = ‘1’) then
q <= ‘0’;
• if … then allows nesting and else
synchronous circuit can be coded q <= d;
end if;
• Nesting isn’t possible with
end if;
concurrent statement, hence
doesn’t make sense to code
synchronous circuit.

Kuruvilla Varghese 7
47
 Sync Reset, Synthesis 48

d 0 D Q q
1
‘0’
reset
clk CK

Kuruvilla Varghese

48

Synchronous circuit - synthesis 49

d q r

process (clk) ck ck

begin clk

if (clk’event and clk = ‘1’) then

q <= d; • Above process executes sequentially,
r <= q; but both the assignments happens
end if; after ‘t + delta’ time. This along with
end process; implied memory makes cascaded flip-
flops.

Kuruvilla Varghese 8
49
 Shift Register 50

d(0) q(0) q(1) q(2) q(7)

ck ck ck ck
clk

Kuruvilla Varghese

50

Shift Register 51

process (clk)
begin process (clk)
if (clk’event and clk = ‘1’) then begin
q(0) <= d(0); if (clk’event and clk = ‘1’) then
for i in 0 to 6 loop
q(i+1) <= q(i); q <= q(6 downto 0) & d(0);
end loop; end if;
end if; end process;
end process;

Kuruvilla Varghese 9
51
 Counter 52

library ieee; count <= q;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; process (clk, reset)
begin
entity count8 is if (reset = ‘1’) then
port (clk, reset: in std_logic; q <= (others => '0‘);
count: out std_logic_vector(7 downto 0)); elsif (clk'event and clk = ‘1’) then
end count8; q <= q + 1;
end if;
architecture arch_count8 of count8 is end process;
signal q: std_logic_vector(7 downto 0);
begin end arch_count8;

Kuruvilla Varghese

52

Counter 53

library ieee;
use ieee.std_logic_1164.all;
+1 d q count use ieee.std_logic_unsigned.all;
q
clk clk
AR entity count8 is port
(clk, reset, load: in std_logic;
reset
din: in std_logic_vector(7 downto 0);
count: out std_logic_vector(7 downto 0));
end count8;

architecture arch_count8 of count8 is

signal q: std_logic_vector(7 downto 0);
begin

Kuruvilla Varghese 10
53
 Counter 54
count <= q;
process (clk, reset)
+1 0 count
begin 1
d q
din q
if (reset = ‘1’) then load
clk clk
q <= (others => '0‘); AR
elsif (clk'event and clk = ‘1’) then
reset
if (load = ‘1’) then q <= din;
else q <= q + 1;
end if; • Synthesis Tools might optimize
end if; further to get efficient target specific
end process; circuits
end arch_count8;

Kuruvilla Varghese

54

Coding Scenario 55
Topmost Level
Structural code

Components

Structural code

Bottom most level

Single Component
Behavioral / Dataflow
Descriptions
Processes

Concurrent statements

Kuruvilla Varghese 11
55
 Test bench: Timing Simulation 56

D Q
ts: Setup time: Minimum time input
must be valid before the active clock
CLK
edge

th: Hold time: Minimum time input

CLK must be valid after the active clock
edge
D
ts tco: Propagation delay for input to
th
appear at the output from active clock
Q
edge
tco

Kuruvilla Varghese

56

Test bench: Timing Simulation 57

• Setting up input

tclk

Input
tclk
ts

CLK tco

Output

Kuruvilla Varghese 12
57
 Test bench: Timing Simulation 58
• Clock Generation
– Period, Initial offset, Duty cycle Note: Period, setup time, and tco should be
• Asynchronous Reset noted from the Static Timing Analysis for
– Remove tRR time before clock edge test bench and is with respect to
corresponding input/output pin/pad.
– Example uses ts instead of tRR
• Applying Inputs
– Apply ts time before active clock
edge
– Detect the clock edge explicitly or
implicitly (e.g. add clock period –
setup)

Kuruvilla Varghese

58

Testbench – Sequential Circuits 59

library ieee; count <= q;
use ieee.std_logic_1164.all; process (clk, reset)
use ieee.std_logic_unsigned.all; begin
if (reset = '1') then
entity count8 is port
q <= (others => '0‘);
(clk, reset, load: in std_logic;
elsif (clk'event and clk = '1') then
din: in std_logic_vector(7 downto 0);
count: out std_logic_vector(7 downto if (load = '1') then q <= din;
0)); else q <= q + 1;
end count8; end if;
end if;
architecture arch_count8 of count8 is end process;
signal q: std_logic_vector(7 downto 0); end arch_count8;
begin

Kuruvilla Varghese 13
59
 Testbench – Sequential Circuits
library ieee;
use ieee.std_logic_1164.all;
entity count8tb is
end count8tb;
architecture behavioral of count8tb is
component count8
port (clk, reset, load: in std_logic;
din: in std_logic_vector(7 downto 0) ;
count: out std_logic_vector(7 downto 0));
end component;
60
signal clk, reset, load: std_logic := ‘0’;
signal din: std_logic_vector(7 downto 0) :=
(others => ‘0’);
signal count: std_logic_vector(7 downto 0);
constant period: time := 20 ns;
constant setup: time := 2 ns;
begin
uut: count8 port map (clk, reset, load, din,
count);

Kuruvilla Varghese

60

Testbench – Sequential Circuits 61

process process
begin begin
wait for 100 ns; wait for 100 ns;
reset <= ‘1’; -- Asynchronous Reset
cloop: loop wait for (period/2 - setup);
clk <= ‘0’; reset <= ‘0’; -- Reset Recovery
wait for (period/2); wait for (6 * period);
clk <= ‘1’; din <= X”E0”; load <= ‘1’; wait for period;
wait for (period/2);
load <= ‘0’;
end loop;
wait for (16 * period);
wait;
end process;
end process;
end behavioral;
Kuruvilla Varghese 14
61
 Packages: Operators, Functions 62

ieee.std_logic_arith (synopsys) Overloaded operators

• Arithmetic Operators
type unsigned is array ( natural +, -, *, /
range <> ) of std_logic;
• Relational Operators
type signed is array ( natural range
<> ) of std_logic; <, >, =, /=, <=, >=
• Shift Operators
SHR, SHL
(unsigned – logical
signed – arithmetic)

Kuruvilla Varghese

62

Packages: Operators, Functions 63

ieee.std_logic_arith (synopsys) • Usage

library ieee ;
Conversion Functions
use ieee.std_logic_1164.all ;
from: std_logic_vector, use ieee.std_logic_arith.all ;
unsigned, signed, integer use ieee.std_logic_unsigned.all;
• Recommendations
– Use std_logic_arith for numeric
conv_integer
operations
conv_unsigned – Use std_logic_unsigned only for
conv_signed counters and testbenches
conv_std_logic_vector – Do not use the package
std_logic_signed
Kuruvilla Varghese 15
63
 Packages: Operators, Functions 64

ieee.numeric_std (ieee) Overloaded operators

• Arithmetic Operators
type unsigned is array ( natural range <> +, -, *, /, abs, rem, mod
) of std_logic;
type signed is array ( natural range <> )
• Relational Operators
of std_logic; <, >, =, /=, <=, >=
• Logical operators
and, nand, or, nor, xor, xnor, not

Kuruvilla Varghese

64

Packages: Operators, Functions 65

ieee.numeric_std (ieee) • Usage
• Shift operators (signed,
unsigned) library ieee ;
use ieee.std_logic_1164.all ;
shift_left, shift_right use ieee.numeric_std.all ;
rotate_left, rotate_right
sll, srl, rol, ror
• Conversion Functions
to_integer
to_unsigned
to_signed
Kuruvilla Varghese 16
65
 Type Conversions
• Automatic
– Between base types and
subtypes
• Using Conversion Functions
– e.g. to_integer, conv_integer
• Type Casting
between signed, unsigned,
and std_logic_vector
66
sl_vect <= std_logic_vector(usg_vect)
sl_vect <= std_logic_vector(sg_vect)
usg_vect <= unsigned(sl_vect)
sg_vect <= signed(sl_vect)
signed(“1101”)

Kuruvilla Varghese

66

Type Conversion and synthesis 67

• Type conversion is required

when you connect a signal of one
data type (e.g. integer) to another
(e.g. std_logic_vector), as VHDL
is a strict type checking language
• Type conversion implies no
hardware, Hence directives (user
defined attributes) are given to
synthesis tool, not to synthesize
the code.

Kuruvilla Varghese 17
67
 Arithmetic 68
signal a,b,s: unsigned(7 downto 0) ; signal a, b, s: unsigned(7 downto 0);
signal s9: unsigned(8 downto 0) ; signal s9: unsigned(8 downto 0) ;
signal s7: unsigned(6 downto 0) ; signal cin: std_logic ;
-- Carry in
-- Simple Addition, no carry out s9 <= (a & '1') + (b & cin);
s <= a + b ; s <= s9(8 downto 1) ;
-- Carry Out in result
s9 <= ('0' & a) + ('0' & b) ;
-- For smaller result, slice input
arrays
s7 <= a(6 downto 0) + b(6 downto 0)
;
Kuruvilla Varghese

68

Arithmetic with time 69

• Suppose you want to do some
computation with ‘time’ data
type
• Then it is better to remove time
unit and cast it to real and do the
arithmetic operations like
multiplication, division etc.

variable period: real;

period := real(time_data / 1 ns)

Kuruvilla Varghese 18
69