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Introduction
x Combinational y
(I/P) (O/P) x NS Memory O/P
Circuit y
(I/P) q’ Elements
Memory Logic Logic (O/P)
q q’ q (NS)
(PS) (NS) Elements (PS)
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-2
Clock period
✯ Clock period: time between successive transitions in the same direction (mea-
sured in ms, ns, or ps).
✯ Clock frequency: the reciprocal of clock period (measured in KHz, MHz, or
GHz).
✯ Clock width: time during which the clock signal is high (value is 1).
✩ A clock signal is active high if the state changes occur at the clock’s
rising edge or during the clock width. It is active low otherwise.
✯ Clock duty cycle: ratio of clock width and clock period.
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-3
SR Latch
✯ The SR latch is a basic memory element which can store one bit of informa-
tion.
✩ It consists of two cross-coupled NOR gates or two cross-coupled NAND
gates.
✩ It has two input signals, the set signal (S ) and the reset signal (R).
✩ It has two output signals, Q and Q0 .
✩ It has two states, the set state (when Q = 1 and Q
0 = 0 ) and the reset
state (when Q = 0 and Q0 = 1).
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-4
S R Q Q (next) Q’(next)
S 1.4 Q’
0 0 0 0 1
0 0 1 1 0
0 1 X 0 1
1.4 Q 1 0 X 1 0
R
1 1 X 0 0
1.4
1.4
1.4 Undefined
Q 2.8 2.8
1.4
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
0 1 X 1 0
1 0 X 0 1
1.4 Q’ 1 1 0 0 1
R
1 1 1 1 0
1.4 Undefined
Q’ 2.8 2.8 1.4 1.4
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-5
✯ The gated SR latch is one that has a third input, C (usually the clock signal),
which enables or disables the SR latch (see Fig. 4).
✯ The designer must make sure that the input signals do not change during the
time window around the falling edge of C .
✏ The window starts at setup time tsetup before the falling edge of C and
ends with hold time thold after the falling edge of C .
✏ In Fig. 5, e.g., the following conditions must hold for C :
C S R Next state of Q
S
• • • Q 0 X X No change
1 0 0 No change
C • 1 0 1 Q = 0; Reset state
1 1 0 Q = 1; Set state
• • • Q 1 1 1 Undefined
R
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6. Synchronous Sequential Logic 6-6
C S R Q Q (next)
0 X X 0 0
R 0 X X 1 1
2.0 Q
S Q 1 0 0 0 0
C C
1 0 0 1 1
R Q’
2.0 Q’ 1 0 1 X 0
S
1 1 0 X 1
1 1 1 X NA
2.0
2.0
Q 4.0 4.0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t 9 t 10 t 11 t 12 t 13
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6. Synchronous Sequential Logic 6-7
Gated D Latch
✯ The gated D latch has only one input D (the data input).
✩ Constructed from a gated SR latch by connecting the D input to S and
0
D to R.
D C D Q Q (next)
2.0 Q 0 X 0 0
D Q
C
0 X 1 1
C Q’ 1 0 X 0
2.0 Q’
1 1 X 1
3.0
3.0
Q 4.0 4.0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
t t t t t t
setup hold setup hold setup hold
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6. Synchronous Sequential Logic 6-8
Flip-Flops
X Y
D Q1 D Q2 D Q3
C C C
Clk
Q1 4.0 3.0
Q2 4.0 3.0
Q3 4.0 3.0
t0 t1 t2 t3 t4 t5 t6 t7
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6. Synchronous Sequential Logic 6-9
Master Slave
latch latch
D D Qm D Qs Q
4.0/3.0 4.0/3.0
C C
Clk
Clk
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-10
C C C C C C
Clk
Q3s 4.0
t0 t1 t2 t3 t4 t5 t6 t7
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-11
Set latch
A
1.4
S
1.4 1.4 Q
Clk
R
1.4 1.4 Q’
Output latch
D 1.4 B
Reset latch
(a) Logic schematic
Clk
R 1.4 1.4
Q 2.8 4.2
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
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6. Synchronous Sequential Logic 6-12
S R Q (next) Q Q(next) S R
0 0 Q 0 0 0 X
S Q
Q (next) = S + R’Q
Clk 0 1 0 0 1 1 0
SR
SR = 0
R Q’ 1 0 1 1 0 0 1
1 1 NA 1 1 X 0
J K Q (next) Q Q(next) J K
0 0 Q 0 0 0 X
J Q
Clk 0 1 0 Q (next) = JQ’+ K ’Q 0 1 1 X
JK
K Q’ 1 0 1 1 0 X 1
1 1 Q’ 1 1 X 0
Q Q(next) D
0 0 0
D Q (next)
D Q 1
0 1
Clk 0 0 Q (next) = D
D
1 0 0
Q’ 1 1
1 1 1
Q Q(next) T
0 0 0
T Q (next)
T Q 0 1 1
0 Q
T Clk Q (next) = TQ ’+ T ’Q
1 0 1
Q’ 1 Q’
1 1 0
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6. Synchronous Sequential Logic 6-13
Flip-Flop Types
S,R = 1,0
S,R = 0,0 S,R = 0,0
SR Q=0 Q=1
S,R = 0,1
D=1
D= 0 D= 1
D Q=0 Q=1
D=0
T=1
T= 0 T= 0
T Q=0 Q=1
T=1
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6. Synchronous Sequential Logic 6-14
✏ They are used to preset and clear the FF independently of other inputs.
✏ They are not controlled by the clock signal.
CLR
D
Q PRS
D Q
C
Clk Q’
Q’ CLR
PRS
(a) D latch (b) Graphic symbol
Set latch
PRS
A
S
Q PRS
D Q
Clk
R Clk Q’
Q’
CLR
Output latch
D B
CLR
Reset latch
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6. Synchronous Sequential Logic 6-15
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6. Synchronous Sequential Logic 6-16
Cnt
D0 Q0
Q’0
D1 Q1
Q’1
Clk
0 0 0 0 0 1
0 1 0 1 1 0
1 0 1 0 1 1
1 1 1 1 0 0
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6. Synchronous Sequential Logic 6-17
Cnt = 0 Cnt = 0
Cnt = 1
Q1 Q0 = 00 Q1 Q0 = 01
Cnt = 1 Cnt = 1
Cnt = 0 Cnt = 0
Cnt = 1
Q1 Q0 = 11 Q1 Q0 = 10
Clk
Cnt
Q1
Q0
t0 t1 t2 t3 t4 t5
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6. Synchronous Sequential Logic 6-18
Cnt
D0 Q0 Y
Q’0
D1 Q1
Q ’1
Clk
Y = Q1 Q0
(c) Next−state and output equations
0 0 0 0 0 1 0
0 1 0 1 1 0 0
1 0 1 0 1 1 0
1 1 1 1 0 0 1
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6. Synchronous Sequential Logic 6-19
Cnt = 0 Cnt = 0
Q1 Q0 = 00 Cnt = 1 Q1 Q0 = 01
Y=0 Y=0
Cnt = 1 Cnt = 1
Cnt = 0 Cnt = 0
Q1 Q0 = 11 Cnt = 1 Q1 Q0 = 10
Y=1 Y=0
Clk
clock cycle 1 clock cycle 2 clock cycle 3 clock cycle 4
Cnt
Q1
Q0
t0 t1 t2 t3 t4 t5
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-20
Cnt
D0 Q0 Y
Q’0
D1 Q1
Q ’1
Clk
Y = Cnt Q1 Q0
(c) Next−state and output equations
0 0 0 0/0 0 1/0
0 1 0 1/0 1 0/0
1 0 1 0/0 1 1/0
1 1 1 1/0 0 0/1
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-21
Clk
clock cycle 1 clock cycle 2 clock cycle 3 clock cycle 4
Cnt
Q1
Q0
t0 t1 t2 t3 t4 t5
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-22
Develop
state diagram
Generate next−state
and output tables
Minimize
states
Encode inputs,
states, outputs
Choose
memory elements
Derive excitation
equations
Optimize
logic implementation
Simulate
logic schematic
Verify functionality
and timing
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-23
CD = 10
CD = 10 CD = 10
D Y u0 u1 u2
Modulo−3
C up/down
Clk counter
CD = 11 CD = 11
d0 d1 d2
CD = 11
(a) Counter symbol (b) Partial state diagram (up and down counting)
CD = 10
CD = 10 CD = 0X CD = 0X CD = 0X
CD = 10 CD = 10 CD = 10 CD = 10
u0 u1 u2 u0 u1 u2
11 11
=
10
= CD
10
CD D D
CD = 10 C
=
CD = 10 C
=
= 1
CD
=1
= 1
CD = 1
CD
=1
CD = 1
10
1
10
1
CD
CD
CD = 11 CD = 11 d0 CD = 11 d1 CD = 11 d2
d0 d1 d2
CD = 11
CD = 0X CD = 0X CD = 0X
CD = 11
(c) Partial state diagram (changing direction) (d) Final state diagram
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6. Synchronous Sequential Logic 6-24
Example 1 (State Diagram for the BCD-to-Excess-3 Decoder)
✯ The inputs are applied serially, with LSB first, and the outputs are generated
serially, too.
TABLE 4-6
Sequence Tables for Code Converter Example
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0
1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1
0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0
0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1
1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0
0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1
1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 1
0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0
1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1
Init Init
0/1 1/0 0/1 1/0
(b)
Init Init
0/0 or 1/1
0/1 1/0
1/0
0/1
(c) (d)
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6. Synchronous Sequential Logic 6-25
State Minimization
☞ We would like to reduce the number of gates and FFs during the design of a
sequential circuit (they sometimes are competing objectives).
✏ The number of gates and the number of inputs per gate for the next state
and output functions can be reduced by state minimization.
✏ The number of FFs required is directly related to the number of states of
the FSM.
✍ For an FSM with m states, we would need dlog2 me FFs.
0/0
a NS O/P
PS 0 1 0 1
0/0
1/0 0/0 a a b 0 0
0/0 0/0
b c b c d 0 0
1/0 c a d 0 0
1/0
0/0 d e f 0 1
g 1/1 d e
e a f 0 1
1/1
0/0 f g f 0 1
1/1
f g a f 0 1
1/1
t 0 1 2 3 4 5 6 7 8 9 10 11
q a a b c d e f f g f g a
x 0 1 0 1 0 1 1 0 1 0 0
y 0 0 0 0 0 1 1 0 1 0 0
Figure 20: An FSM example.
✍ Given the FSM as shown above, can we find an equivalent FSM with fewer than
7 states?
Definition 1
Two FSMs are said to be (behaviorally) equivalent if given any input sequence,
starting from any identical initial state, they produce the same output sequence.
Definition 2
Two states, sj and sk , in an FSM are said to be equivalent, denoted as sj sk , iff
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-26
1. 8 2x
i ; h(sj ; i) = h(sk ; i) ;
2. 8 2 x
i ; f (sj ; i) = f (sk ; i) .
➀ Find rows in the state table that have identical NS and O/P entries. They
correspond to equivalent states. If there are no equivalent states, stop.
➁ When 2 states are equivalent, one of them can be removed. Update the entries
of the remaining table to reflect the change. Go to ➀.
t 0 1 2 3 4 5 6 7 8 9 10 11
q a a b c d e d d e d e a
x 0 1 0 1 0 1 1 0 1 0 0
y 0 0 0 0 0 1 1 0 1 0 0
☞ The same output sequence results although the state sequence is different.
☞ Note that in either machine, 3 FFs are required to represent the states.
☞ Three FFs can represent up to 8 states. Unused states are treated as don’t-
cares.
☞ In general, reducing the state table is likely (but does not guarantee) to result
in a smaller number of FFs or gates.
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-27
Present Next−state
state
CD = 0X CD = 10 CD = 11
{u 0 , u1 , u2 , d 0 , d1 , d2 }
CD = 0X 0 0 0 0 0 0
Output
10 0 0 1 0 0 1 values
11 1 0 0 1 0 0
CD = 0X G0 G0 G1 G1 G2 G2
Next
10 G1 G1 G2 G2 G0 G0 states
11 G2 G2 G0 G0 G1 G1
Present Next−state
state
CD = 0X CD = 10 CD = 11
s0 s0 / 0 s1 / 0 s2/ 1
s1 s1 / 0 s2 / 0 s0/ 0
s2 s2 / 0 s0 / 1 s1/ 0
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6. Synchronous Sequential Logic 6-28
s 1
s 2
s 3
s 4
<s2 , s6 >
s 5 <s3 , s4 >
<s0 , s4 >
s 6
s 0 s 1
s 2
s 3
s 4
s 5
➀ Enter a for every pair of states that differ in their output values for at least
one set of input values.
☞ Pairs of states that are not equivalent are eliminated.
➁ For the remaining pairs of states, enter into each entry the next-state pairs
that would have to be equivalent if the pair of states represented by the entry
are to be equivalent.
☞ The equivalence of the next-state pair is implied.
☞ For example, the equivalence of < s1 ; s5 > implies the equivalence of
< s3 ; s4 >.
➂ Scan the table from top to bottom one row at a time, and from left to right
one column at a time, and enter a into any square having at least one
nonequivalent next-state pair.
☞ May be iterated several times until no ’s are entered during the table
scan.
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6. Synchronous Sequential Logic 6-29
u1
u2
d0
d1 <u 0 , d 2 >
d2
u 0
u 1
u2 d0 d1
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6. Synchronous Sequential Logic 6-30
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6. Synchronous Sequential Logic 6-31
1 1
00 01 00 01
2 2 1 1
1 1
11 10 10 11
Figure 24: Two different encodings for a 2-bit binary counter [Gajski].
0/0 0/0
s0 s1 01 11
Priority 1: (s1 , s2 )
(a) Initial state diagram (b) Adjacency priorities (c) Possible encoding
s0 0 0 0 1 0 0 1
s1 0 1 0 0 0 1 0
s2 1 0 1 0 1 0 0
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6. Synchronous Sequential Logic 6-32
CD
Q1 Q0 00 01 11 10 00 01 11 10
00 0 0 0 0 1 0 0 1 00 0 0 1 0
01 0 1 0 1 0 0 1 0 01 0 0 0 0
11 XX XX XX XX 11 X X X X
10 1 0 1 0 0 1 0 0 10 0 0 0 1
Q1 (next) Q0 (next) Y
(a) Next−state map (b) Output map
Q0 (next) = Q C + Q C D + Q’Q0’C D’
0
0 1
Y = Q1 C D + Q’1 Q0’C D
1.4 1.4
Q1 (next) Q0 (next)
1.8
Y
1.8 1.8 1.8 1.8 1.4
2.2
2.2 2.2
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6. Synchronous Sequential Logic 6-33
CD
Q1 Q0 00 01 11 10 00 01 11 10
00 0 0 0 0 0 1 1 0 00 0 0 0 0
01 0 1 0 1 1 0 0 0 01 0 0 1 0
11 XX XX XX XX 11 X X X X
10 1 0 1 0 0 0 0 1 10 0 0 0 1
Q1 (next) Q0 (next) Y
(a) Next−state map (b) Output map
Q1 (next) = Q C ’+ Q C D + Q’Q0’C D’
1 0 1
Y = Q1’C D + Q0’C D
1.4 1.4
Q1 (next) Q0 (next)
1.8
Y
1.8 1.8 1.8 1.8 1.4
1.8
2.2 2.2
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6. Synchronous Sequential Logic 6-34
CD
Q2 Q1 Q0 00 01 11 10 00 01 11 10
000 X X X X X X X X X X X X 000 X X X X
001 0 0 1 0 0 1 1 0 0 0 1 0 001 0 0 1 0
011 X X X X X X X X X X X X 011 X X X X
010 0 1 0 0 1 0 0 0 1 1 0 0 010 0 0 0 0
100 1 0 0 1 0 0 0 1 0 0 0 1 100 0 0 0 1
101 X X X X X X X X X X X X 101 X X X X
111 X X X X X X X X X X X X 111 X X X X
110 X X X X X X X X X X X X 110 X X X X
Q2 (next) Q1 (next) Q0 (next) Y
Q2 (next) = Q C ’+ Q C D + Q C D’
2 0 1
Q1 (next) = Q C ’+ Q2 C D + Q0 C D’
1
Y = Q0 C D + Q2 C D’
1.4
Q2 (next) 1.8
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6. Synchronous Sequential Logic 6-35
☞ After state minimization and state encoding, we choose the proper type of FF
for implementation.
☞ Given the state transition table, we wish to find the FF input conditions that
will cause the required transitions.
✏ A tool for such a purpose is the excitation table, which can be derived
from the characteristic table (or equation).
✏ SR FFs are generally used when different signals set and reset the FFs.
✏ D FFs are good for applications requiring data transfer (e.g., shift regis-
ters).
✏ T FFs are good for those involving complementation (e.g., binary coun-
ters).
✏ Many digital systems are constructed entirely with JK FFs because they
are the most versatile available.
✍ JK is useful when we need to combine the behavior of T and SR.
✏ The excitation table for the JK flip-flop has many don’t-cares, which are
more likely to result in simpler combinational circuits.
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6. Synchronous Sequential Logic 6-36
CD
Q1 Q0 00 01 11 10
00 00 00 10 01
01 01 01 00 10
11 XX XX XX XX
10 10 10 01 00
Q1 (next) Q (next)
0
Q (present) Q (next) S R J K T D
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
CD
Q1 Q0 00 01 11 10
00 0 X 0 X 0 X 0 X 1 0 0 X 0 X 1 0
01 0 X X 0 0 X X 0 0 X 0 1 1 0 0 1
11 X X X X X X X X X X X X X X X X
10 X 0 0 X X 0 0 X 0 1 1 0 0 1 0 X
S 0 S1 R 0 R 1
S 1 = Q0 C D’+ Q’Q’C D
1 0
[cost = 18, delay = 3.6]
R1 = Q1 C = (Q’1 + C’)’ [cost = 9, delay = 1.4]
S 0 = Q1 C D + Q’Q’C D’ [cost = 18, delay = 3.6]
1 0
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6. Synchronous Sequential Logic 6-37
CD
Q1 Q0 00 01 11 10
00 0 X 0 X 0 X 0 X 1 X 0 X 0 X 1 X
01 0 X X 0 0 X X 0 0 X X 1 1 X X 1
11 X X X X X X X X X X X X X X X X
10 X 0 0 X X 0 0 X X 1 1 X X 1 0 X
J0 K 1 J0 K1
T1 = Q1 C + Q’0 C D + Q0 C D’ [cost = 22, delay = 3.6] D1 = Q C ’+ Q0 C D’+ Q’Q0’C D [cost = 24, delay = 4.0]
1 1
T0 = Q0 C + Q1 C D + Q1’C D’ [cost = 22, delay = 3.6] D1 = Q C’+ Q0 C D + Q’Q0’C D’ [cost = 24, delay = 4.0]
0 1
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6. Synchronous Sequential Logic 6-38
1 1
2.4 J1 Q1
4.0
K1 Q’1
1.8
1.4 Y
2.2
Input−output delays
Clk
Q0 4.0 4.0
t0 t1 t2 t3 t4 t5 t6
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6. Synchronous Sequential Logic 6-39
We are going to design a divide-by-6 counter (modulo-6 counter) with the counting
sequence (0,1,2,3,4,5), which produces a ‘1’ if the state ‘5’ is encountered, and ‘0’
otherwise. We are going to use T FFs. The state diagram and table are shown
below.
PS NS O/P Excitation
ABC ABC y TA TB TC
0 -/0 1 000 001 0 0 0 1
-/1 -/0 001 010 0 0 1 1
010 011 0 0 0 1
5 2 011 100 0 1 1 1
100 101 0 0 0 1
-/0 -/0 101 000 1 1 0 1
4 -/0 3 110 XXX X X X X
111 XXX X X X X
From the table, the simplified output function and the excitation functions can be
derived using the K-maps:
BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 0 1 0 1 1 0 1 1 1 1
1 1 X X 1 1 X X 1 X X 1 1 1 X X
y = AC TA = AC + BC TB = A C 0
TC = 1
TA = A B
T Q T Q 1 T Q y
Q0
Q0
Q 0
A B C
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