VLSI SYSTEM DESIGN

(LAB - TASK = 04)

Programme : B.Tech-ECE Semester : FALL-(2019-20)

Name : Pranav Kumar Course Code : ECE3002

REG-NO. : 17BEC0473 Slot : L15+L16

Faculty : Prof. Jagannadha Naidu K Max. Marks : 10

(SUB - SYSTEM DESIGN (4 - BIT ALU))

 TASK-04
AIM : - To design a 4-BIT ALU for FULL ADDER (A+B) and FULL SUBTRACTOR (A-B) and
checking the functionality and also finding the average propagation delay and
average power.

CIRCUIT-DIAGRAM : - 1. 4-BIT ALU WITH VOLTAGE SOURCES(SCHEMATIC)

CIRCUIT-DIAGRAM : - 2. CMOS INVERTER WITHOUT VOLTAGE SOURCES (SCHEMATIC)

3. SYMBOL:- CMOS INVERTER

CIRCUIT-DIAGRAM : - 4. 2X1 MUX WITHOUT VOLTAGE SOURCES(SCHEMATIC)

5. SYMBOL:- 2X1 MUX

CIRCUIT-DIAGRAM : - 6. TRANSMISSION GATE WITHOUT VOLTAGE SOURCES(SCHEMATIC)

 7. SYMBOL:- TRANSMISSION GATE

CIRCUIT-DIAGRAM : - 8. 1-BIT FULL ADDER WITHOUT VOLTAGE SOURCES (SCHEMATIC)

9. SYMBOL:- 1-BIT FULL ADDER
PLOTS : - 1. TRANSIENT-ANALYSIS (STOP-TIME = 5 us)

1. CHECKING-FUNCTIONALITY :- (A + B) i.e., Cin = 0 & A<3> = 1 , A<2> = 0 , A<1> =

1, A<0> = 1 & B<3> = 0 , B<2> = 1 , B<1> = 0 , B<0> = 0 .
Hence, S<3> = S<2> = S<1> = S<0> = 1 , Co = 0 .

2. CHECKING-FUNCTIONALITY :- (A - B) i.e., Cin = 1 & A<3> = 1 , A<2> = 0 , A<1> =

1, A<0> = 1 & B<3> = 0 , B<2> = 1 , B<1> = 0 , B<0> = 0 .
Hence, S<3> = 0 , S<2> = S<1> = S<0> = 1 , Co = 1 .
 3. PLOTTING POWER SIGNAL :-

CALCULATIONS AND OBSERVATIONS :-

1. AVERAGE POWER DISSIPATED = 1.315 uW (SIMULATION RESULT SHOWN BELOW)

 2. AVERAGE PROPAGATION DELAY :- (BETWEEN Cin (I/P) TO S<3> (O/P))

RISE-PROPAGATION DELAY (AT 50 PERCENT OF THE FINAL VALUE (VDD = 1.2 V)) :-

(I/P) t1 = 500.399 ns , (O/P) t2 = 500.002 ns

tpdr = t1-t2 = 0.397 ns

FALL-PROPAGATION DELAY (AT 50 PERCENT OF THE FINAL VALUE (VDD = 1.2 V)) :-

(I/P) t3 = 1 us , (O/P) t4 = 1.00016 us

tpdf = t4-t3 = 0.00016 us = 0.16 ns

AVERAGE-DELAY (tpd) = (tpdr + tpdf)/2 = (0.397 + 0.16)/2 = 0.2785 ns.

PLOTS : - 3. TRANSIENT-ANALYSIS (PROPAGATION-DELAY)(BETWEEN Cin TO S<3>)

INFERENCE: - The circuit for the 4-BIT ALU was designed and the functionality was
also checked. The average power dissipated and propagation delay were also
calculated.