18BCB0072 and 18BCB0081

Time, Space and Power Complexity of ARM CORTEX M3

Team: Jatin Kumar (18BCB0072)

And Prateek Sinha (18BCB0081)

ARM-Programming-Examples-TM4C

Sample Program in Interrupt Implementation:

cstartup_M.c

#pragma language=extended
#pragma segment="CSTACK"

extern void __iar_program_start( void );

extern void NMI_Handler( void );

extern void HardFault_Handler( void );
extern void MemManage_Handler( void );
extern void BusFault_Handler( void );
extern void UsageFault_Handler( void );
extern void SVC_Handler( void );
extern void DebugMon_Handler( void );
extern void PendSV_Handler( void );
extern void SysTick_Handler( void );

extern void TIMER0A_Handler(void);

typedef void( *intfunc )( void );
typedef union { intfunc __fun; void * __ptr; } intvec_elem;

// The vector table is normally located at address 0.

18BCB0072 and 18BCB0081

// When debugging in RAM, it can be located in RAM, aligned to at least 2^6.

// If you need to define interrupt service routines,

#pragma location = ".intvec"

const intvec_elem __vector_table[] =
{
  { .__ptr = __sfe( "CSTACK" ) },
  __iar_program_start,

  NMI_Handler,
  HardFault_Handler,
  MemManage_Handler,
  BusFault_Handler,
  UsageFault_Handler,
  0,
  0,
  0,
  0,
  SVC_Handler,
  DebugMon_Handler,
  0,
  PendSV_Handler,
  SysTick_Handler,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
18BCB0072 and 18BCB0081

  TIMER0A_Handler
};

#pragma call_graph_root = "interrupt"

__weak void NMI_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void HardFault_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void MemManage_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void BusFault_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void UsageFault_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void SVC_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void DebugMon_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void PendSV_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void SysTick_Handler( void ) { while (1) {} }
#pragma call_graph_root = "interrupt"
__weak void TIMER0A_Handler( void ) { while (1) {} }

void __cmain( void );

__weak void __iar_init_core( void );
__weak void __iar_init_vfp( void );

#pragma required=__vector_table
void __iar_program_start( void )
{
  __iar_init_core();
  __iar_init_vfp();
  __cmain();
}

main.c

#include <lm4f120h5qr.h>

#define FLAG_NONE 0x00000000

#define FLAG_TOGGLE_LED 0x00000001
18BCB0072 and 18BCB0081

volatile int flags = FLAG_NONE;

void TIMER0A_Handler(void)
{
  flags = FLAG_TOGGLE_LED;
  TIMER0->ICR |= (1<<0);
}

int main()
{
  SYSCTL->RCGCGPIO |= (1<<5);
  GPIOF->AFSEL &= ~(1<<2);
  GPIOF->DIR = (1<<2);
  GPIOF->DEN = (1<<2);
  GPIOF->DATA |= (1<<2);
  

  
  //Enable and provide a clock to 16/32-bit general purpose timer module 0 in Run mode (enable timer0)
  SYSCTL->RCGCTIMER |= (1<<0); //0b0000 0001
  
  //Step1:Ensure the time is disabld (the TnEN bit in the GPTMCTL register is cleared) before making any
changes [pg.698]
  //disable timer0 by giving a value of 0 to bit 0
  TIMER0->CTL &= ~(1<<0);
  
  //Step2:Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000 [pg.688]
  //For a 16/32 bit timer, this value selects the 32 bit timer configuration
  //For a 32/64 bit wide timer, this value selects the 64 bit timer configuration
  TIMER0->CFG = 0x00000000;
  
  //Step3:Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR)
  //This value set to the GPTMTAMR register allows us to choose periodic mode
  TIMER0->TAMR |= (0x2<<0);
  
  //Step4: 0 - timer counts down: 1 - timer counts up, starting from 0x0
  //Setting TACDIR(bit 4) to 0 in order to make the timer count down
  TIMER0->TAMR &= ~(1<<4);
  
  //Step5: Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR)
  //Loads the start value into to the GPTMTnILR
  TIMER0->TAILR = 0x00F42400; //16,000,000 = 1 sec for this microcontroller
18BCB0072 and 18BCB0081

  
  //Step6: If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register
(GPTMIMR)
  TIMER0->IMR |= (1<<0); //Enabled Interrupt
  //NVIC->ISER[0] |= (1<<19); //Interrupts from registers directly
  NVIC_EnableIRQ(TIMER0A_IRQn); //from CMSIS Library
  
  //Step7: Set the TnEN bit in the GPTMCTL register to enable the timer and start counting
  //Enable timer0 by giving a vaule of 1 to bit 0, this will get the timer to start counting
  TIMER0->CTL |= (1<<0);
  
  //Step8: Clear status flag (GPTMICR) by writing a 1 to the appropriate bit
  //Wrinting a 1 to bit 0 of this register clears the TATORIS bit in the GPTMRIS register and the TATOMIS
bit in the GPTMMIS register
  //By giving TATORIS bit a value of 1, we say that Timer A has timed out. This interrupt is asserted when
a one-shot or
  //periodic mode timer reaches it's count limit
  while(1)
  {
    if(flags == FLAG_TOGGLE_LED)
    {
      GPIOF->DATA ^= (1<<2);
      flags = FLAG_NONE;
    }

  }
  
  return 0;
}

Time Complexity of main.c is 4 and of cstartup M.c is 21.

In the Cortex-M3 processor, you can mix 32-bit instructions with 16-bit instructions without switching
state, getting high code density and high performance with no extra complexity.