5 4 3 2 1

BD3 VGA CARD

M92XT/M96M DDR3 (64Mx16)
DDR3 64M*16
PCI-E x16
D

ATi DDR3 64M*16

D

CH-A PAGE10
M96M2
M92M2 - XT

.ru
VGA 200PIN
FCBGA DDR3 64M*16
C
CONNECTOR C

m
CRT 962pin
DDR3 64M*16
CH-B PAGE11
HDMI

ru
LVDS

Fo
PAGE 2, 4, 5, 6, 7, 8, 9

B
+5V B

+3.3V
er
VIN VDD_CORE
VGA CORE POWER OZ8111 PAGE 12
yb
VIN +1.8V/+1.5V
1.8V/1.5V POWER ISL6228 PAGE 13
GFXON
C

A
GFXRST# +1.5V A

GFXPG Quanta Computer Inc.

PAGE 3 +1.1V
1.1V POWER G9661 PAGE 14 PROJECT : BD3 VGA
Size Document Number Rev
B2A
BLOCK DIAGRAM
Date: Monday, December 22, 2008 Sheet 1 of 15
5 4 3 2 1
 5 4 3 2 1

U5A

STITCH CAPACITORS
VIN +1.8V

PEG_TXP0 AA38 Y33 C_PEG_RXP0 C228 0.1u/10V_4

[3] PEG_TXP0 PCIE_RX0P PCIE_TX0P PEG_RXP0 [3]
PEG_TXN0 Y37 Y32 C_PEG_RXN0 C227 0.1u/10V_4 C1 0.1u/50V_6
D [3] PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 [3] D

PEG_TXP1 Y35 W33 C_PEG_RXP1 C247 0.1u/10V_4 C62 1000p/50V_6

[3] PEG_TXP1 PCIE_RX1P PCIE_TX1P PEG_RXP1 [3]
PEG_TXN1 W36 W32 C_PEG_RXN1 C246 0.1u/10V_4
[3] PEG_TXN1 PCIE_RX1N PCIE_TX1N PEG_RXN1 [3]

PEG_TXP2 W38 U33 C_PEG_RXP2 C232 0.1u/10V_4 C85 0.1u/50V_6

[3] PEG_TXP2 PCIE_RX2P PCIE_TX2P PEG_RXP2 [3]
PEG_TXN2 V37 U32 C_PEG_RXN2 C231 0.1u/10V_4
[3] PEG_TXN2 PCIE_RX2N PCIE_TX2N PEG_RXN2 [3]
C83 1000p/50V_6
PEG_TXP3 V35 U30 C_PEG_RXP3 C261 0.1u/10V_4
[3] PEG_TXP3 PCIE_RX3P PCIE_TX3P PEG_RXP3 [3]
PEG_TXN3 U36 U29 C_PEG_RXN3 C260 0.1u/10V_4
[3] PEG_TXN3 PCIE_RX3N PCIE_TX3N PEG_RXN3 [3]
C207 0.1u/50V_6

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PEG_TXP4 U38 T33 C_PEG_RXP4 C230 0.1u/10V_4
[3] PEG_TXP4 PCIE_RX4P PCIE_TX4P PEG_RXP4 [3]
PEG_TXN4 T37 T32 C_PEG_RXN4 C229 0.1u/10V_4
[3] PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 [3]

PCI EXPRESS INTERFACE

C210 1000p/50V_6

PEG_TXP5 T35 T30 C_PEG_RXP5 C259 0.1u/10V_4

[3] PEG_TXP5 PCIE_RX5P PCIE_TX5P PEG_RXP5 [3]
PEG_TXN5 R36 T29 C_PEG_RXN5 C258 0.1u/10V_4
[3] PEG_TXN5 PCIE_RX5N PCIE_TX5N PEG_RXN5 [3] VDD_CORE
+1.8V

PEG_TXP6 R38 P33 C_PEG_RXP6 C226 0.1u/10V_4

[3] PEG_TXP6 PCIE_RX6P PCIE_TX6P PEG_RXP6 [3]
PEG_TXN6 P37 P32 C_PEG_RXN6 C225 0.1u/10V_4
C [3] PEG_TXN6 PCIE_RX6N PCIE_TX6N PEG_RXN6 [3] C

m
PEG_TXP7 P35 P30 C_PEG_RXP7 C257 0.1u/10V_4 C118 1000p/50V_6
[3] PEG_TXP7 PCIE_RX7P PCIE_TX7P PEG_RXP7 [3]
PEG_TXN7 N36 P29 C_PEG_RXN7 C256 0.1u/10V_4
[3] PEG_TXN7 PCIE_RX7N PCIE_TX7N PEG_RXN7 [3]

PEG_TXP8 N38 N33 C_PEG_RXP8 C218 0.1u/10V_4

[3] PEG_TXP8 PCIE_RX8P PCIE_TX8P PEG_RXP8 [3]
PEG_TXN8 M37 N32 C_PEG_RXN8 C217 0.1u/10V_4
[3] PEG_TXN8 PCIE_RX8N PCIE_TX8N PEG_RXN8 [3]

ru
PEG_TXP9 M35 N30 C_PEG_RXP9 C255 0.1u/10V_4
[3] PEG_TXP9 PCIE_RX9P PCIE_TX9P PEG_RXP9 [3]
PEG_TXN9 L36 N29 C_PEG_RXN9 C254 0.1u/10V_4
[3] PEG_TXN9 PCIE_RX9N PCIE_TX9N PEG_RXN9 [3]
VIN VDD_CORE
PEG_TXP10 L38 L33 C_PEG_RXP10 C224 0.1u/10V_4
[3] PEG_TXP10 PCIE_RX10P PCIE_TX10P PEG_RXP10 [3]
PEG_TXN10 K37 L32 C_PEG_RXN10 C223 0.1u/10V_4
[3] PEG_TXN10 PCIE_RX10N PCIE_TX10N PEG_RXN10 [3]

Fo
C109 0.1u/50V_6

PEG_TXP11 K35 L30 C_PEG_RXP11 C253 0.1u/10V_4

[3] PEG_TXP11 PCIE_RX11P PCIE_TX11P PEG_RXP11 [3]
PEG_TXN11 J36 L29 C_PEG_RXN11 C252 0.1u/10V_4 C103 1000p/50V_6
[3] PEG_TXN11 PCIE_RX11N PCIE_TX11N PEG_RXN11 [3]

PEG_TXP12 J38 K33 C_PEG_RXP12 C222 0.1u/10V_4

[3] PEG_TXP12 PCIE_RX12P PCIE_TX12P PEG_RXP12 [3]
B PEG_TXN12 H37 K32 C_PEG_RXN12 C221 0.1u/10V_4 B
[3] PEG_TXN12 PCIE_RX12N PCIE_TX12N PEG_RXN12 [3]

PEG_TXP13 H35 J33 C_PEG_RXP13 C251 0.1u/10V_4

[3] PEG_TXP13 PCIE_RX13P PCIE_TX13P PEG_RXP13 [3]
[3] PEG_TXN13

[3] PEG_TXP14
[3] PEG_TXN14
PEG_TXN13

PEG_TXP14
PEG_TXN14

PEG_TXP15
G36

G38
F37
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N
erPCIE_TX13N

PCIE_TX14P
PCIE_TX14N
J32

K30
K29
C_PEG_RXN13

C_PEG_RXP14
C_PEG_RXN14

C_PEG_RXP15
C250

C220
C219

C249
0.1u/10V_4

0.1u/10V_4
0.1u/10V_4

0.1u/10V_4
PEG_RXN13 [3]

PEG_RXP14 [3]
PEG_RXN14 [3]
EMI CAP.
+5V
[3] PEG_TXP15 F35 PCIE_RX15P PCIE_TX15P H33 PEG_RXP15 [3]
PEG_TXN15 C_PEG_RXN15 C248 0.1u/10V_4
yb
[3] PEG_TXN15 E37 PCIE_RX15N PCIE_TX15N H32 PEG_RXN15 [3]

C265
CLOCK *1000p/50V_6
MXM_REFCLKP AB35
[3] MXM_REFCLKP PCIE_REFCLKP
MXM_REFCLKN AA36
[3] MXM_REFCLKN PCIE_REFCLKN

CALIBRATION +1.1V
C

AJ21 NC#1
AK21 Y29 R101 2K/F_4
A NC#2 PCIE_CALRN A
T27
AH16 NC_PWRGOOD
Y30
+1.1V
PCIE_CALRP
GFXRST# AA30 R104
[3] GFXRST# PERSTB
1.27K/F_4 Quanta Computer Inc.
216-0729012-00 PROJECT : BD3 VGA
Size Document Number Rev
B2A
GFX(PCIE I/F)
Date: Monday, December 22, 2008 Sheet 2 of 15
5 4 3 2 1
 5 4 3 2 1

CN1
PEG_TXN15 2 1 PEG_RXN15
[2] PEG_TXN15 2 1 PEG_RXN15 [2]
PEG_TXP15 4 3 PEG_RXP15
[2] PEG_TXP15 4 3 PEG_RXP15 [2]
6 6 5 5
PEG_TXN14 8 7 PEG_RXN14
[2] PEG_TXN14 8 7 PEG_RXN14 [2]
PEG_TXP14 10 9 PEG_RXP14
[2] PEG_TXP14 10 9 PEG_RXP14 [2]
12 12 11 11
PEG_TXN13 14 13 PEG_RXN13
[2] PEG_TXN13 14 13 PEG_RXN13 [2]
PEG_TXP13 16 15 PEG_RXP13
[2] PEG_TXP13 16 15 PEG_RXP13 [2]
18 18 17 17
PEG_TXN12 20 19 PEG_RXN12
[2] PEG_TXN12 20 19 PEG_RXN12 [2]
PEG_TXP12 22 21 PEG_RXP12
[2] PEG_TXP12 22 21 PEG_RXP12 [2]
D
24 24 23 23 D
PEG_TXN11 26 25 PEG_RXN11
[2] PEG_TXN11 26 25 PEG_RXN11 [2]
PEG_TXP11 28 27 PEG_RXP11
[2] PEG_TXP11 28 27 PEG_RXP11 [2]
30 30 29 29
PEG_TXN10 32 31 PEG_RXN10
[2] PEG_TXN10 32 31 PEG_RXN10 [2]
PEG_TXP10 34 33 PEG_RXP10
[2] PEG_TXP10 34 33 PEG_RXP10 [2]
36 36 35 35
PEG_TXN9 38 37 PEG_RXN9
[2] PEG_TXN9 38 37 PEG_RXN9 [2]
PEG_TXP9 40 39 PEG_RXP9
[2] PEG_TXP9 40 39 PEG_RXP9 [2]
42 42 41 41
PEG_TXN8 44 43 PEG_RXN8
[2] PEG_TXN8 44 43 PEG_RXN8 [2]
PEG_TXP8 46 45 PEG_RXP8
[2] PEG_TXP8 46 45 PEG_RXP8 [2]
48 48 47 47
PEG_TXN7 50 49 PEG_RXN7
[2] PEG_TXN7 50 49 PEG_RXN7 [2]
PEG_TXP7 52 51 PEG_RXP7

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[2] PEG_TXP7 52 51 PEG_RXP7 [2]
54 54 53 53
PEG_TXN6 56 55 PEG_RXN6
[2] PEG_TXN6 56 55 PEG_RXN6 [2]
PEG_TXP6 58 57 PEG_RXP6
[2] PEG_TXP6 58 57 PEG_RXP6 [2]
60 60 59 59
PEG_TXN5 62 61 PEG_RXN5
[2] PEG_TXN5 62 61 PEG_RXN5 [2]
PEG_TXP5 64 63 PEG_RXP5
[2] PEG_TXP5 64 63 PEG_RXP5 [2]
66 66 65 65
PEG_TXN4 68 67 PEG_RXN4
[2] PEG_TXN4 68 67 PEG_RXN4 [2]
PEG_TXP4 70 69 PEG_RXP4
[2] PEG_TXP4 70 69 PEG_RXP4 [2]
72 72 71 71
PEG_TXN3 74 73 PEG_RXN3
[2] PEG_TXN3 74 73 PEG_RXN3 [2]
PEG_TXP3 76 75 PEG_RXP3

m
[2] PEG_TXP3 76 75 PEG_RXP3 [2]
78 78 77 77
PEG_TXN2 80 79 PEG_RXN2
[2] PEG_TXN2 80 79 PEG_RXN2 [2]
PEG_TXP2 82 81 PEG_RXP2
[2] PEG_TXP2 82 81 PEG_RXP2 [2]
C 84 84 83 83 C
PEG_TXN1 86 85 PEG_RXN1
[2] PEG_TXN1 86 85 PEG_RXN1 [2]
PEG_TXP1 88 87 PEG_RXP1
[2] PEG_TXP1 88 87 PEG_RXP1 [2]
90 90 89 89
PEG_TXN0 92 91 PEG_RXN0
[2] PEG_TXN0 92 91 PEG_RXN0 [2]

ru
PEG_TXP0 94 93 PEG_RXP0
[2] PEG_TXP0 94 93 PEG_RXP0 [2]
96 96 95 95
EXT_CRT_DDCCLK 98 97 MXM_REFCLKN
[4] EXT_CRT_DDCCLK 98 97 MXM_REFCLKN [2]
EXT_CRT_DDCDAT 100 99 MXM_REFCLKP
[4] EXT_CRT_DDCDAT 100 99 MXM_REFCLKP [2]
102 102 101 101
EXT_HDMI_DDCCLK 104 103 GFXRST# SYSFANON# GFXON
[8] EXT_HDMI_DDCCLK 104 103 GFXRST# [2]
EXT_HDMI_DDCDAT 106 105 SYSFANON#
[8] EXT_HDMI_DDCDAT 106 105 SYSFANON# [7]
108 107 GFXON C270 C271
108 107 GFXON [12]
EXT_LVDS_PNLCLK 110 109 GFXPG
[4] EXT_LVDS_PNLCLK 110 109 GFXPG [14]
EXT_LVDS_PNLDAT 112 111 VGA_MBDATA *0.1u/10V_4 *0.1u/10V_4

Fo
[4] EXT_LVDS_PNLDAT 112 111 VGA_MBDATA [7]
114 113 VGA_MBCLK
114 113 VGA_MBCLK [7]
EXT_VGA_RED 116 115 EXT_LVDS_BLON
[4] EXT_VGA_RED 116 115 EXT_LVDS_BLON [4]
118 117 EXT_DISP_ON
118 117 EXT_DISP_ON [8]
EXT_VGA_GRN 120 119 HPD_HDMI
[4] EXT_VGA_GRN 120 119 HPD_HDMI [8]
122 122 121 121
EXT_VGA_BLU 124 123 EXT_HSYNC
[4] EXT_VGA_BLU 124 123 EXT_HSYNC [4,7]
126 125 EXT_VSYNC
126 125 EXT_VSYNC [4,7]
EXT_LVDS_TXL#2 128 127
[8] EXT_LVDS_TXL#2 128 127
EXT_LVDS_TXL2 130 129 EXT_LVDS_TXU#2
[8] EXT_LVDS_TXL2 130 129 EXT_LVDS_TXU#2 [8]
132 131 EXT_LVDS_TXU2
132 131 EXT_LVDS_TXU2 [8]
EXT_LVDS_TXL#1 134 133
[8] EXT_LVDS_TXL#1 134 133
EXT_LVDS_TXL1 136 135 EXT_LVDS_TXU#1

B
[8] EXT_LVDS_TXL1

[8] EXT_LVDS_TXL#0
[8] EXT_LVDS_TXL0

[8] EXT_LVDS_TXLCK#
[8] EXT_LVDS_TXLCK
EXT_LVDS_TXL#0
EXT_LVDS_TXL0

EXT_LVDS_TXLCK#
EXT_LVDS_TXLCK

EXT_TV_C/R
138
140
142
144
146
148
150
152
136
138
140
142
144
146
148
150
135
137
139
141
143
145
147
149
137
139
141
143
145
147
149
151
EXT_LVDS_TXU1

EXT_LVDS_TXU#0
EXT_LVDS_TXU0

EXT_LVDS_TXUCK#
EXT_LVDS_TXUCK
er
EXT_LVDS_TXU#1 [8]
EXT_LVDS_TXU1 [8]

EXT_LVDS_TXU#0 [8]
EXT_LVDS_TXU0 [8]

EXT_LVDS_TXUCK# [8]
EXT_LVDS_TXUCK [8]
B

T23 152 151

154 153
yb
EXT_TV_Y/G 154 153
156 156 155 155
T53 158 157
EXT_TV_COMP 158 157
160 160 159 159
T54 162 161
EXT_HDMICLK- 162 161
[8] EXT_HDMICLK- 164 164 163 163
EXT_HDMICLK+ 166 165 +3V +5V
[8] EXT_HDMICLK+ 166 165 +5V
168 168 167 167
EXT_HDMITX2N 170 169
[8] EXT_HDMITX2N 170 169
EXT_HDMITX2P 172 171
[8] EXT_HDMITX2P 172 171
174 173 C269 C267 C268 C266
EXT_HDMITX1N 174 173
[8] EXT_HDMITX1N 176 175
C

EXT_HDMITX1P 176 175 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 10u/6.3V_6

[8] EXT_HDMITX1P 178 178 177 177
180 180 179 179
EXT_HDMITX0N 182 181 +3V
[8] EXT_HDMITX0N 182 181
EXT_HDMITX0P 184 183
[8] EXT_HDMITX0P 184 183
186 186 185 185
188 188 187 187
190 190 189 189
192 192 191 191
194 194 193 193
196 196 195 195 VIN
VIN 198 198 197 197
200 200 199 199
A A
FOXCONN-HOUSING

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
VGA Connector
Date: Monday, December 22, 2008 Sheet 3 of 15
5 4 3 2 1
 1

U5B
+1.8V (1.8V@70mA AVDD) AVDD

GPIO TXCAP_DPA3P
TXCAM_DPA3N
AU24
AV23
HDMICLK+ [8]
HDMICLK- [8]
L6 HCB1608KF-181T15_6

AT25 HDMITX0P [8]

+3V_D MUTI GFX TX0P_DPA2P C58 C54 C201
AR24
DPA TX0M_DPA2N HDMITX0N [8] HDMI 10u/6.3V_6 1u/6.3V_4 0.1u/10V_4
AU26 HDMITX1P [8]
TX1P_DPA1P
AV25 HDMITX1N [8]
TX1M_DPA1N
GPIO_16_SSIN R73 *10K/F_4 AR8 AT27
DVPCNTL_MVP_0 TX2P_DPA0P HDMITX2P [8]
AU8 AR26 HDMITX2N [8]
GPIO18_HPD3 R67 *10K/F_4 DVPCNTL_MVP_1 TX2M_DPA0N
AP8
DVPCNTL_0
(1.8V@45mA VDD1DI)
AW8 AR30 VDD1DI
GPIO5 R82 *10K/F_4 DVPCNTL_1 TXCBP_DPB3P T51
AR3 AT29
DVPCNTL_2 TXCBM_DPB3N T49
AR1
GPIO3_SMBDAT R96 *10K/F_4 DVPCLK L3 HCB1608KF-181T15_6
[7] RAM_STRAP0 AU1 AV31
DVPDATA_0 TX3P_DPB2P T52
[7] RAM_STRAP1 AU3 AU30
GPIO4_SMBCLK R92 *10K/F_4 DVPDATA_1 DPB TX3M_DPB2N T22
[7] RAM_STRAP2 AW3
DVPDATA_2
[7] RAM_STRAP3 AP6 AR32
DVPDATA_3 TX4P_DPB1P T20 C56 C184 C183
[7] RAM_STRAP4 AW5 AT31
DVPDATA_4 TX4M_DPB1N T21 10u/6.3V_6 1u/6.3V_4 0.1u/10V_4
AU5
T1 DVPDATA_5
AR6 AT33
DVPDATA_6 TX5P_DPB0P T18
AW6 AU32
EXT_LVDS_BLON DVPDATA_7 TX5M_DPB0N T19
AU6
THE PINS WITH TEST DVPDATA_8
AT7 AU14
POINTS DVPDATA_9 TXCCP_DPC3P T5
AV7 AV13
ARE REQUIRED TO BE DVPDATA_10 TXCCM_DPC3N T2
AN7
ACCESSIBLE DVPDATA_11
AV9 AT15
R90 FOR DEBUG AND DVPDATA_12 TX0P_DPC2P T4
AT9 AR14
BOUNDRY SCAN DVPDATA_13 TX0M_DPC2N T3
10K/F_4 AR10
PURPOSES USING TEST DVPDATA_14 DPC
POINT
AW10
DVPDATA_15 TX1P_DPC1P
AU16 (1.8V@1mA A2VDDQ)

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AU10 AV15 T8 A2VDDQ
VIAS IF UNUSED OR DVPDATA_16 TX1M_DPC1N T7
AP10
COMPONENT DVPDATA_17 L18 HCB1608KF-181T15_6
PADS AV11 AT17
DVPDATA_18 TX2P_DPC0P T9
AT11 AR16
DVPDATA_19 TX2M_DPC0N T6
ENSURE AR12
DVPDATA_20
DEBUG_ACCESS STRAP AW12 AU20
DVPDATA_21 TXCDP_DPD3P T11 C235 C236
IS ALSO ACCESSIBLE AU12 AT19
DVPDATA_22 TXCDM_DPD3N T10 1u/6.3V_4 0.1u/10V_4
SEE CONFIG STRAPPING AP12
DVPDATA_23
PAGE AT21
TX3P_DPD2P T13
AR20
TX3M_DPD2N T14
ACCESS TO ATI DEBUG
PORT DPD AU22
TX4P_DPD1P T16
IS MANDATORY ON AV21
INITIAL +3V_D TX4M_DPD1N T12
PROTOTYPE DESIGNS I2C AT23
TX5P_DPD0P T17

m
AR22
R95 10K/F_4 TX5M_DPD0N T15
AK26
R97 10K/F_4 AJ26
SCL
SDA
For AMD suggest.
AD39 EXT_VGA_RED
GENERAL PURPOSE I/O R EXT_VGA_RED [3]
AD37
RB
[7] GPIO0 AH20
GPIO_0 EXT_VGA_GRN
[7] GPIO1 AH18 AE36 EXT_VGA_GRN [3]
GPIO_1 G
[7] GPIO2 AN16 AD35
GPIO3_SMBDAT GPIO_2 GB
AH23
GPIO4_SMBCLK GPIO_3_SMBDATA EXT_VGA_BLU
AJ23 AF37 EXT_VGA_BLU [3]
GPIO_4_SMBCLK B

ru
GPIO5 AH17 AE38
GPIO_5_AC_BATT DAC1 BB
AJ17
T30 GPIO_6 R118 R116 R115
[3] EXT_LVDS_BLON AK17 AC36 EXT_HSYNC [3,7]
GPIO_7_BLON HSYNC
[7] SOUT_GPIO8 AJ13 AC38 EXT_VSYNC [3,7] 150/F_4 150/F_4 150/F_4
GPIO_8_ROMSO VSYNC
[7] SIN_GPIO9 AH15
GPIO_9_ROMSI
[7] SCLK_GPIO10 AJ16
GPIO_10_ROMSCK R114 FOR MXM DESIGN:
[7] GPIO11 AK16 AB34
GPIO_11 RSET AVDD 499/F_4 PLACE RGB 150 Ohm TERMINATION
[7] GPIO12 AL16
GPIO_12 RESISTORS CLOSE TO ASIC
[7] GPIO13 AM16 AD34
GPIO_13 AVDD
AM14 AE34
T28 GPIO_14_HPD2 AVSSQ VDD1DI
[12] VCORE1.2ID0 AM13
+3V_D GPIO_16_SSIN GPIO_15_PWRCNTL_0
AK14 AC33

Fo
GPIO_16_SSIN VDD1DI
[7] ALT#_GPIO17 AG30 AC34
A GPIO18_HPD3 GPIO_17_THERMAL_INT VSS1DI A
AN14
R86 10K_4 GPIO_18_HPD3
AM17
GPIO_19_CTF
[12] VCORE1.2ID1 AL13 AC30
GPIO_20_PWRCNTL_1 R2
AJ14 AC31
R85 T31 GPIO_21_BB_EN R2B
[7] SCS#_GPIO22 AK13
*10K/F_4 GPIO_22_ROMCSB
AN13 AD30
GPIO_23_CLKREQB G2
AM23 AD31
JTAG_TRSTB G2B
AN23
+3V_D T42 JTAG_TDI
AK23 AF30
T33 JTAG_TCK B2
AL24 AF31
R98 T29 JTAG_TMS B2B
AM24
R64 *10K/F_4 T46 JTAG_TDO
1K/F_4 AJ19
GENERICA
AK19 AC32
GENERICB C
AJ20 AD32
GENERICC Y

+1.8V

L2
(1.8V@120mA DPLL_PVDD)
HCB1608KF-181T15_6

C47 C49
+1.8VDPLL_PVDD

C190
R66
10K/F_4

[8] HPD_1
T36

+1.8V
er
AK20
AJ24
AH26
AH24

AK24
GENERICD
GENERICE_HPD4
GENERICF
GENERICG

HPD1
DAC2
COMP

H2SYNC
V2SYNC

VDD2DI
VSS2DI
AF32

AD29
AC29

AG31
AG32
+1.8V_VDD2DI
T34
V2SYNC

R105
[7]

0_4
+1.8V

+3V_D
(1.8V@40mA VDD2DI)

(3.3V@65mA A2VDD)

10u/6.3V_6 1u/6.3V_4 0.1u/10V_4 AG33 +3V_D_A2VDD R110 0_4 A2VDDQ (1.8V@1mA A2VDDQ)
yb
R76 A2VDD
PLACE VREFG DIVIDER AND CAP 499/F_4 AD33 +1.8V_A2VDDQ R120 0_4
A2VDDQ
AH13
CLOSE TO ASIC
R74 C110
VREFG
A2VSSQ
AF33 For AMD suggest.
249/F_4 0.1u/10V_4 R102
AA29 715/F_4
+1.1V R2SET
(1.1V@300mA DPLL_VDDC)
L16 HCB1608KF-181T15_6 +1.1VDPLL_VDDC DDC/AUX AM26
PLL/CLOCK DDC1CLK EXT_CRT_DDCCLK [3]
AN26
+1.8VDPLL_PVDD AM32
DPLL_PVDD
DDC1DATA EXT_CRT_DDCDAT [3] CRT
AN32 AM27
C

C206 C209 C180 DPLL_PVSS AUX1P T38

AL27
10u/6.3V_6 1u/6.3V_4 0.1u/10V_4 AUX1N T48
+1.1VDPLL_VDDC AN31 AM19
DPLL_VDDC DDC2CLK T35
AL19
DDC2DATA T39
XTALIN AV33 AN20
XTALOUT XTALIN AUX2P T44
AU34 AM20
XTALOUT AUX2N T41
R32 1M/F_4 AL30
DDCCLK_AUX3P
AM30
DDCDATA_AUX3N
M96 Only (NC on M92-M2)
2 1 AL29
DDCCLK_AUX4P
C42 Change to 27p 12/17 [7] D+ AF29
DPLUS DDCDATA_AUX4N
AM29
Y1 27MHZ AG29 THERMAL
[7] D- DMINUS
C42 C45 AN21
27p/50V_4 27p/50V_4 DDCCLK_AUX5P
AM21
DDCCLK_AUX5P [8] HDMI
T43
+1.8V_TSVDD
AK32
AJ32
TS_FDO
DDCDATA_AUX5N
AJ30
DDCDATA_AUX5N [8]
M96M-M2 P/N: AJ072900T04
+1.8V AJ33
TSVDD
TSVSS
DDC6CLK
DDC6DATA
AJ31
EXT_LVDS_PNLCLK
EXT_LVDS_PNLDAT
[3]
[3]
LVDS M92XT-M2 P/N: AJ072800T10
(1.8V@20mA TSVDD)
C45 Change to 27p 12/17 NC_DDCCLK_AUX7P
AK30
L4 HCB1608KF-181T15_6 +1.8V_TSVDD AK29 T40
NC_DDCDATA_AUX7N T37

C59 C55 C191

10u/6.3V_6 1u/6.3V_4 0.1u/10V_4 216-0729012-00
Quanta Computer Inc.
PROJECT : BD3 VGA
Size Document Number Rev
B2A
MAIN(LVDS,CRT,HDMI)
Date: Monday, December 22, 2008 Sheet 4 of 15
1
 5 4 3 2 1

+1.5V U5E
(1.5V@2.9A VDDR1) +1.8V
For DDR3, MVDDQ = 1.5V MEM I/O L15 AB39 A3
PCIE HCB1608KF-181T15_6 PCIE_VSS#1 GND#1
(1.8V@500mA PCIE_VDDR) E39
PCIE_VSS#2 GND#2
A37
AC7 AA31 PCIE_VDDR F34 AA16
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#3 GND#3
AD11 AA32 F39 AA18
VDDR1#2 PCIE_VDDR#2 PCIE_VSS#4 GND#4
AF7 AA33 G33 AA2
C97 C101 C89 C121 C148 C154 C165 C173 C95 C94 VDDR1#3 PCIE_VDDR#3 C194 C186 C174 C179 C188 C185 C177 C193 PCIE_VSS#5 GND#5
AG10 AA34 G34 AA21
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 VDDR1#4 PCIE_VDDR#4 0.1u/10V_4 0.1u/10V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 PCIE_VSS#6 GND#6
AJ7 V28 H31 AA23
VDDR1#5 PCIE_VDDR#5 PCIE_VSS#7 GND#7
AK8 W29 H34 AA26
VDDR1#6 PCIE_VDDR#6 PCIE_VSS#8 GND#8
AL9 W30 H39 AA28
VDDR1#7 PCIE_VDDR#7 PCIE_VSS#9 GND#9
G11 Y31 J31 AA6
VDDR1#8 PCIE_VDDR#8 PCIE_VSS#10 GND#10
G14 J34 AB12
VDDR1#9 PCIE_VSS#11 GND#11
G17 K31 AB15
VDDR1#10 +1.1V PCIE_VSS#12 GND#12
G20 G30 K34 AB17
VDDR1#11 PCIE_VDDC#1 PCIE_VSS#13 GND#13
D G23
VDDR1#12 PCIE_VDDC#2
G31 (1.1V@2A PCIE_VDDC) K39
PCIE_VSS#14 GND#14
AB20 D
G26 H29 L31 AB22
C105 C104 C88 C96 C92 C90 C91 VDDR1#13 PCIE_VDDC#3 PCIE_VSS#15 GND#15
G29 H30 L34 AB24
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDR1#14 PCIE_VDDC#4 PCIE_VSS#16 GND#16
H10 J29 M34 AB27
VDDR1#15 PCIE_VDDC#5 C176 C182 C175 C172 C167 C196 C171 C116 PCIE_VSS#17 GND#17
J7 J30 M39 AC11
VDDR1#16 PCIE_VDDC#6 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 PCIE_VSS#18 GND#18
J9 L28 N31 AC13
VDDR1#17 PCIE_VDDC#7 PCIE_VSS#19 GND#19
K11 M28 N34 AC16
VDDR1#18 PCIE_VDDC#8 PCIE_VSS#20 GND#20
K13 N28 P31 AC18
VDDR1#19 PCIE_VDDC#9 PCIE_VSS#21 GND#21
K8 R28 P34 AC2
VDDR1#20 PCIE_VDDC#10 PCIE_VSS#22 GND#22
L12 T28 P39 AC21
VDDR1#21 PCIE_VDDC#11 PCIE_VSS#23 GND#23
L16 U28 R34 AC23
VDDR1#22 PCIE_VDDC#12 PCIE_VSS#24 GND#24
L21
VDDR1#23 For M96/M92 PCIE_VDDC = 1.1V T31
PCIE_VSS#25 GND#25
AC26
C87 C107 C119 C157 C86 L23 T34 AC28
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 VDDR1#24 PCIE_VSS#26 GND#26
L26 AA15 T39 AC6
VDDR1#25 CORE VDDC#1 PCIE_VSS#27 GND#27
L7 AA17 U31 AD15
VDDR1#26 VDDC#2 PCIE_VSS#28 GND#28
M11 AA20 U34 AD17
VDDR1#27 VDDC#3 PCIE_VSS#29 GND#29
N11 AA22 V34 AD20
VDDR1#28 VDDC#4 PCIE_VSS#30 GND#30
P7 AA24 V39 AD22
VDDR1#29 VDDC#5 PCIE_VSS#31 GND#31
R11 AA27 W31 AD24
VDDR1#30 VDDC#6 PCIE_VSS#32 GND#32
U11 AB13 W34 AD27
VDDR1#31 VDDC#7 PCIE_VSS#33 GND#33
U7 AB16 Y34 AD9
VDDR1#32 VDDC#8 PCIE_VSS#34 GND#34

.ru
Y11 AB18 Y39 AE2
VDDR1#33 VDDC#9 VDD_CORE PCIE_VSS#35 GND#35
Y7
VDDR1#34 VDDC#10
AB21 (1.1V@18A VDDC FOR M96 25W) GND#36
AE6
+1.8V AB23 AF10
VDDC#11 GND#37
(1.8V@136mA VDD_CT) VDDC#12
AB26
GND#38
AF16
VDDC_CT AB28 AF18
VDDC#13 GND#39
AC12 AF21
L10 HCB1608KF-181T15_6 LEVEL
TRANSLATION
VDDC#14
VDDC#15
VDDC#16
AC15
AC17
C134
1u/6.3V_4
C136
1u/6.3V_4
C122
1u/6.3V_4
C141
1u/6.3V_4
C152
1u/6.3V_4
C130
1u/6.3V_4
C160
1u/6.3V_4
C126
1u/6.3V_4
C127
1u/6.3V_4
C149
1u/6.3V_4 F15
GND#101
GND GND#40
GND#41
GND#42
AG17
AG2

POWER
AF26 AC20 F17 AG20
C153 C156 C166 VDD_CT#1 VDDC#17 GND#102 GND#43
AF27 AC22 F19 AG22
10u/6.3V_6 1u/6.3V_4 0.1u/10V_4 VDD_CT#2 VDDC#18 GND#103 GND#44
AG26 AC24 F21 AG6
VDD_CT#3 VDDC#19 GND#104 GND#45
AG27 AC27 F23 AG9
VDD_CT#4 VDDC#20 GND#105 GND#46
AD13 F25 AH21
+3V_D VDDC#21 GND#106 GND#47
(3.3V@60mA VDDR3) VDDC#22
AD16 F27
GND#107 GND#48
AH29
I/O AD18 F29 AJ10
VDDC#23 GND#108 GND#49
AF23 AD21 F31 AJ11
VDDR3#1 VDDC#24 GND#109 GND#50
AF24 AD23 F33 AJ2

m
C VDDR3#2 VDDC#25 GND#110 GND#51 C
AG23 AD26 F7 AJ28
C142 C161 C155 C163 VDDR3#3 VDDC#26 C147 C133 C137 C128 C150 C159 C131 C138 C151 C135 GND#111 GND#52
AG24 AF17 F9 AJ6
10u/6.3V_6 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 +1.8V VDDR3#4 VDDC#27 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 GND#112 GND#53
(1.8V@170mA VDDR5) VDDC#28
AF20 G2
GND#113 GND#54
AK11
AF22 G6 AK31
VDDC#29 GND#114 GND#55
AF13 AG16 H9 AK7
VDDR5#1 VDDC#30 GND#115 GND#56
AF15 AG18 J2 AL11
VDDR5#2 VDDC#31 GND#116 GND#57
VDDR5 for DVPDATA[0..11] AG13
VDDR5#3 VDDC#32
AG21 J27
GND#117 GND#58
AL14
AG15 AH22 J6 AL17
+1.8V VDDR5#4 VDDC#33 C162 C117 C123 C158 C140 C143 GND#118 GND#59
M16 J8 AL2
VDDC#34 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 GND#119 GND#60
(1.8V@170mA VDDR4) VDDC#35
M18 K14
GND#120 GND#61
AL20
AD12 M23 K7 AL21
VDDR4#1 VDDC#36 GND#121 GND#62

ru
AF11 M26 L11 AL23
VDDR4#2 VDDC#37 GND#122 GND#63
VDDR4 for DVPDATA[12..23] AF12
VDDR4#3 VDDC#38
N15 L17
GND#123 GND#64
AL26
AG11 N17 L2 AL32
VDDR4#4 VDDC#39 GND#124 GND#65
N20 L22 AL6
VDDC#40 GND#125 GND#66
N22 L24 AL8
+1.5V VDDC#41 GND#126 GND#67
M96 ONLY (1.5V@2.9A VDDRHA) VDDC#42
N24 L6
GND#127 GND#68
AM11
MEM CLK N27 M17 AM31
L11 HCB1608KF-181T15_6 +VDDRHA VDDC#43 GND#128 GND#69
M20 R13 M22 AM9
VDDRHA VDDC#44 GND#129 GND#70
M21 R16 M24 AN11
C144 VSSRHA VDDC#45 GND#130 GND#71
R18 N16 AN2
1u/6.3V_4 VDDC#46 GND#131 GND#72
R21 N18 AN30
+VDDRHB VDDC#47 GND#132 GND#73
V12 R23 N2 AN6
VDDRHB VDDC#48 GND#133 GND#74
U12 R26 N21 AN8

Fo
L8 HCB1608KF-181T15_6 VSSRHB VDDC#49 GND#134 GND#75
T15 N23 AP11
VDDC#50 GND#135 GND#76
(1.5V@2.9A VDDRHB) VDDC#51
T17 N26
GND#136 GND#77
AP7
C113 T20 N6 AP9
1u/6.3V_4 VDDC#52 GND#137 GND#78
(1.8V@68mA PCIE_PVDD) VDDC#53
T22 R15
GND#138 GND#79
AR5
PLL T24 R17 AW34
L17 HCB1608KF-181T15_6 PCIE_PVDD VDDC#54 GND#139 GND#80
AB37 T27 R2 B11
PCIE_PVDD VDDC#55 GND#140 GND#81
U16 R20 B13
VDDC#56 GND#141 GND#82
H7 U18 R22 B15
C234 C233 C203 NC_MPV18#1 VDDC#57 GND#142 GND#83
H8 U21 R24 B17
10u/6.3V_6 1u/6.3V_4 0.1u/10V_4 NC_MPV18#2 VDDC#58 GND#143 GND#84
U23 R27 B19
VDD_CORE VDDC#59 GND#144 GND#85
U26 R6 B21
VDDC#60 GND#145 GND#86
(1.1V@35mA SPV10) AM10
NC_SPV18 VDDC#61
V15 T11
GND#146 GND#87
B23
B V17 T13 B25 B
L7 HCB1608KF-181T15_6 SPV10 VDDC#62 GND#147 GND#88
AN9 V20 T16 B27
SPV10 VDDC#63 GND#148 GND#89
(For M96/M92 SPV10 = VDDC) VDDC#64
V22 T18
GND#149 GND#90
B29
AN10 V24 T21 B31
C99 C100 C98 SPVSS VDDC#65 GND#150 GND#91
10u/6.3V_6

C145
1u/6.3V_4

VDD_CORE
0.1u/10V_4

(1.1V@144mA BBP)

C125
AA13
Y13
BACK BIAS

BBP#1
BBP#2
er VDDC#66
VDDC#67
VDDC#68
VDDC#69
VDDC#70
VDDC#71
VDDC#72
VDDC#73
VDDC#74

ISOLATED VDDCI#1
V27
Y16
Y18
Y21
Y23
Y26
Y28
AH27
AH28

M15
N13
(For M96/92, 1.1V@2A VDDCI)
+VGA_CORE_VDDCI
L9
BLM21PG221SN1D_8
VDD_CORE
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
GND#151
GND#152
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99
GND#100
B33
B7
B9
C1
C39
E35
E5
F11
F13

1u/6.3V_4 0.1u/10V_4 CORE I/O VDDCI#2 R12 V18

GND#162
VDDCI#3 GND#163
yb
T12 C114 C112 C129 V21
VDDCI#4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 GND#164
V23
GND#165
V26
GND#166
W2
GND#167
W6
216-0729012-00 GND#168
Y15
GND#169
Y17
GND#170
Y20
GND#171
Y22 A39
GND#172 VSS_MECH#1
Y24 AW1
GND#173 VSS_MECH#2
Y27 AW39
+3V +3V GND#174 VSS_MECH#3
U13
GND#175
V13
GND#176
C

R130 216-0729012-00
1

4.7K_4

Modified on 12/12 Fine-tune Power-on sequence 2 +3.3V(0.5A)

A AO3413 A
3

Q4
+1.8V +3V_D
3

R119 10K/F_4 2 Q3
PDTC143TT

C216 C215 C212 C208

1

1u/10V_4 10u/6.3V_6 1u/10V_4 0.1u/10V_4

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
POWER & Core GND
Date: Monday, December 22, 2008 Sheet 5 of 15
5 4 3 2 1
 5 4 3 2 1

U5H

DP C/D POWER DP A/B POWER

(1.8V@200mA DPE_VDD18) +1.8V AP20 AN24

L5 NC_DPC_VDD18#1 NC_DPA_VDD18#1
AP21 NC_DPC_VDD18#2 NC_DPA_VDD18#2 AP24
+1.8V_DPE_VDD18
+1.1V (1.1V@200mA DPA_VDD10) +1.1V
D HCB1608KF-181T15_6 L13 D
C57 C53 C197 AP13 AP31 +1.1V_DPA_VDD10
10u/6.3V_6 1u/6.3V_4 0.1u/10V_4 DPC_VDD10#1 DPA_VDD10#1
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
(1.1V@200mA DPC_VDD10) HCB1608KF-181T15_6
C189 C181 C178
AN17 AN27 10u/6.3V_6 1u/6.3V_4 0.1u/10V_4
DPC_VSSR#1 DPA_VSSR#1
AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
(1.1V@170mA DPE_VDD10) +1.1V AW16 AW26
L14 DPC_VSSR#5 DPA_VSSR#5
+1.1V_DPE_VDD10

HCB1608KF-181T15_6

.ru
AP22 NC_DPD_VDD18#1 NC_DPB_VDD18#1 AP25
C200 C198 C205 AP23 AP26
10u/6.3V_6 1u/6.3V_4 0.1u/10V_4 NC_DPD_VDD18#2 NC_DPB_VDD18#2
+1.1V +1.1V

AP14 DPD_VDD10#1 DPB_VDD10#1 AN33

AP15 DPD_VDD10#2 DPB_VDD10#2 AP33
(1.1V@200mA DPD_VDD10) (1.1V@200mA DPB_VDD10)

C AN19 DPD_VSSR#1 DPB_VSSR#1 AN29 C

m
AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32

R28
R25 150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR
DPCD_CALR DPAB_CALR

ru
(1.8V@20mA DPA_PVDD) +1.8V
150/F_4 L12
DP E/F POWER DP PLL POWER +1.8V_DPA_PVDD
AH34 DPE_VDD18#1 DPA_PVDD AU28
+1.8V_DPE_VDD18 AJ34 AV27 HCB1608KF-181T15_6
DPE_VDD18#2 DPA_PVSS C168 C170 C169
+1.8V 10u/6.3V_6 1u/6.3V_4 0.1u/10V_4

Fo
AL33 DPE_VDD10#1 DPB_PVDD AV29
+1.1V_DPE_VDD10 AM33 AR28 (1.8V@20mA DPB_PVDD)
DPE_VDD10#2 DPB_PVSS
+1.8V

AN34 DPE_VSSR#1 DPC_PVDD AU18 Add GND for DPA PLL power 12/17
AP39 DPE_VSSR#2 DPC_PVSS AV17 (1.8V@20mA DPC_PVDD)
B AR39 DPE_VSSR#3 B
AU37 DPE_VSSR#4
AW35 DPE_VSSR#5
DPD_PVDD AV19
er +1.8V_DPE_VDD18
AF34
AG34
DPF_VDD18#1
DPF_VDD18#2
DPD_PVSS

DPE_PVDD
DPE_PVSS
AR18

AM37
AN38

C48
(1.8V@20mA DPE_PVDD)
+1.8V_DPE_PVDD

C51 C202
L1

HCB1608KF-181T15_6
+1.8V

AK33 DPF_VDD10#1
+1.1V_DPE_VDD10 10u/6.3V_6 1u/6.3V_4 0.1u/10V_4
yb
AK34 DPF_VDD10#2
NC_DPF_PVDD AL38
NC_DPF_PVSS AM35

AF39 DPF_VSSR#1
AH39 DPF_VSSR#2
AK39 DPF_VSSR#3
AL34 DPF_VSSR#4
AM34 DPF_VSSR#5
C

A R117 150/F_4 DPEF_CALR AM39 A

DPEF_CALR

216-0729012-00
Quanta Computer Inc.
PROJECT : BD3 VGA
Size Document Number Rev
B2A
DP POWER
Date: Monday, December 22, 2008 Sheet 6 of 15
5 4 3 2 1
 1 2 3 4 5 6 7 8

PIN STRAPS +3V_D

CONFIGURATION STRAPS
[4] GPIO0
R91 *10K/F_4 Manufacturer Part Number Code ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
[4] GPIO1
R87 *10K/F_4 THEY MUST NOT CONFLICT DURING RESET
M25P05A 100
R80 *10K/F_4
[4] GPIO2
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK
R78 10K/F_4 101
[4] GPIO11 M25P10A
[4] GPIO12
R77 *10K/F_4 Numonyx TX_PWRS_ENB GPIO0 0 = 50% TX OUTPUT SWING 0
M25P20 101 1 = FULL TX OUTPUT SWING
R79 10K/F_4 ST
[4] GPIO13
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
R106 *10K/F_4 Microelectronics 101 0 = TX DE-EMPHASIS DISABLED
A [4] V2SYNC M25P40 1 = TX DE-EMPHASIS ENABLED
A

R37 10K/F_4
[3,4] EXT_HSYNC
101 BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0
R38 10K/F_4
M25P80 1 = PCIE DEVICE AS 5GT/S CAPABLE
[3,4] EXT_VSYNC
SOUT_GPIO8 R52 *10K/F_4 100 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1
Chingis Pm25LV512A 0 = DISABLE 1 = ENABLE
SIN_GPIO9 R45 *10K/F_4
PMC 101 GPIO_8_ROMSO GPIO8 SERIAL ROM OUTPUT FORM ROM 0
SCS#_GPIO22 R53 10K/F_4
Pm25LV010A
GPIO_9_ROMSI GPIO9 SERIAL ROM INPUT TO ROM 0

ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 101
NUMONYX M25P10A : 101
11
EXT_HSYNC EXT_VSYNC AUD[1] HSYNC AUD[1:0]
Discription AUD[0] VSYNC 00: NO AUDIO FUNCTION.

.ru
01: AUDIO FOR DISPLAYPORT AND HDMI IF

0 0 No Audio ADAPTER IS DETECTED.

10: AUDIO FOR DISPLAYPORT ONLY.
11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
0 1 Any one by dectec
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER WOULD USE THE SAMPLED ON 0
EEPROM 1 0 DP only DVPDATA_20 DURING RESET.
1 = DRIVER WOULD USE THE SAMPLED AT
U3
1 1 Both DP & HDMI RESET FROM DVPDATA_20 TO DETERMINE
WHETHER OR NOT A VIP SLAVE DEVICE.
[4] SIN_GPIO9 5 2 SOUT_GPIO8 [4]
D Q

[4] SCLK_GPIO10 6
C

m
[4] SCS#_GPIO22 1
S

+3V 7
HOLD
B R46 *10K_4 3 B
W
8 4
R44
10K_4 C76
VCC
M25P10-AVMN6P
VSS
DDR3 Memory Aperture size

ru
0.1u/10V_4 RAM_STRAP4 RAM_STRAP3 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
Vendor Size
DVPDATA_4 DVPDATA_3 DVPDATA_2 DVPDATA_1 DVPDATA_0

256M 0 0 0 1 0
Thermal Sensor Qimonda 512M
+3V_D +3V_D
0 0 1 0 0 +1.8V

1G 0 0 1 1 0

Fo
R17 *10K/F_4
[4] RAM_STRAP1
R121 R16 *10K/F_4
256M 0 1 0 0 0 [4] RAM_STRAP2
R135 R131 200_6 R19 *10K/F_4
[4] RAM_STRAP3
10K_4 10K_4 Hynix 512M
ADDRESS: 98H C264 0.1u/10V_4 0 1 0 1 0 [4] RAM_STRAP4
R18 *10K/F_4
VCC_TH

Need to pull-high +3VPCU in M/B side U11 R15 10K/F_4

D+
D+ [4]
1G 0 1 1 0 0 [4] RAM_STRAP0

[3] VGA_MBCLK 8 1
SCLK VCC
C262
[3] VGA_MBDATA 7
SDA DXP
2
RAM_STRAP0 SET GDDR3<High> OR DDR3<Low>.
6 3 2200p/50V_4
[4] ALT#_GPIO17 ALERT# DXN

C
[3] SYSFANON# 4
OVERT#

G784P81U
GND
5 D-
D- [4] er RAM_STRAP[1:4] SET VENDOR AND SIZE.

C
yb
C

D D

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
Straps & Thermal & HDCP
Date: Monday, December 22, 2008 Sheet 7 of 15
1 2 3 4 5 6 7 8
 5 4 3 2 1

LVDS Interface Hole

U5G

R100 *10K/F_4 H4 H-C236D118P2-8 H5 H-C236D118P2-8 H2 H-C236D118P2-8

D D

5
LVDS CONTROL AK27 R99 10K/F_4
VARY_BL
DIGON AJ27 EXT_DISP_ON [3] 7 4 7 4 7 4
8 3 8 3 8 3
9 2 9 2 9 2

1
TXCLK_UP_DPF3P AK35 EXT_LVDS_TXUCK [3]
TXCLK_UN_DPF3N AL36 EXT_LVDS_TXUCK# [3]

TXOUT_U0P_DPF2P AJ38 EXT_LVDS_TXU0 [3]

TXOUT_U0N_DPF2N AK37 EXT_LVDS_TXU#0 [3]
H3 H-C236D118P2-8 H1 H-C236D118P2-8

.ru
TXOUT_U1P_DPF1P AH35 EXT_LVDS_TXU1 [3]
TXOUT_U1N_DPF1N AJ36 EXT_LVDS_TXU#1 [3]

5
TXOUT_U2P_DPF0P AG38 EXT_LVDS_TXU2 [3] 7 4 7 4
TXOUT_U2N_DPF0N AH37 EXT_LVDS_TXU#2 [3] 8 3 8 3
9 2 9 2
TXOUT_U3P AF35
AG36

1
TXOUT_U3N

LVTMDP
C C

m
TXCLK_LP_DPE3P AP34 EXT_LVDS_TXLCK [3]
TXCLK_LN_DPE3N AR34 EXT_LVDS_TXLCK# [3]

TXOUT_L0P_DPE2P AW37 EXT_LVDS_TXL0 [3]

TXOUT_L0N_DPE2N AU35 EXT_LVDS_TXL#0 [3]

TXOUT_L1P_DPE1P AR37 EXT_LVDS_TXL1 [3]

ru
TXOUT_L1N_DPE1N AU39 EXT_LVDS_TXL#1 [3]
DDCDATA_AUX5N R93 0_4 EXT_HDMI_DDCDAT
TXOUT_L2P_DPE0P AP35 EXT_LVDS_TXL2 [3]
AR35 DDCCLK_AUX5P R94 0_4 EXT_HDMI_DDCCLK
TXOUT_L2N_DPE0N EXT_LVDS_TXL#2 [3]

TXOUT_L3P AN36
AP37 +3V_D +5V
TXOUT_L3N

Fo
R70 R54 R71 R55
216-0729012-00

2
*10K_4 *10K_4 *2K/F_4 *2K/F_4

B [4] DDCDATA_AUX5N 1 3 EXT_HDMI_DDCDAT [3] B

Q2
*RHU002N06T106
[4] HDMICLK+
[4] HDMICLK-
C238
C237
0.1u/10V_4
0.1u/10V_4
er EXT_HDMICLK+ [3]
EXT_HDMICLK- [3]
+3V

2
C240 0.1u/10V_4
[4] HDMITX2P EXT_HDMITX2P [3]
C239 0.1u/10V_4
[4] HDMITX2N EXT_HDMITX2N [3] [4] DDCCLK_AUX5P
1 3 EXT_HDMI_DDCCLK [3]
C242 0.1u/10V_4 EXT_HDMITX1P [3]
[4] HDMITX1P
C241 0.1u/10V_4 Q1
[4] HDMITX1N EXT_HDMITX1N [3]
*RHU002N06T106
yb
C244 0.1u/10V_4
[4] HDMITX0P EXT_HDMITX0P [3]
C243 0.1u/10V_4
[4] HDMITX0N EXT_HDMITX0N [3]
PLACE AC CAP +3V
CLOSE TO CONNECTOR R128 R129 R126 R127 R124 R125 R122 R123
499/F_4 499/F_4 499/F_4 499/F_4 499/F_4 499/F_4 499/F_4 499/F_4
R132

3
Q6 2 HPD_HDMI
HPD_HDMI [3]
C

MMBT3904
3

1
A 150K_4 A

[4] HPD_1
+5V 2

R134 Q5
R133 Quanta Computer Inc.
10K_4
RHU002N06T106
PROJECT : BD3 VGA
1

100K_4
Size Document Number Rev
HDMI Interface Date: Monday, December 22, 2008
LVDS, HDMI, HOLE
Sheet 8 of 15
B2A

5 4 3 2 1
 5 4 3 2 1

DDR3 Memory Interface

D D

DDR3 Memory Interface M92M Use Channel B Memory Interface Only

U5D
U5C

VMB_DQ0 C5 P8 VMB_MA0
VMA_DQ0 VMA_MA0 VMB_DQ1 DQB_0 MAB_0 VMB_MA1
C37 G24 C3 T9

MEMORY INTERFACE B
VMA_DQ1 DQA_0 MAA_0 VMA_MA1 VMB_DQ2 DQB_1 MAB_1 VMB_MA2
C35 J23 E3 P9

MEMORY INTERFACE A
VMA_DQ2 DQA_1 MAA_1 VMA_MA2 VMB_DQ3 DQB_2 MAB_2 VMB_MA3
A35 H24 E1 N7
VMA_DQ3 DQA_2 MAA_2 VMA_MA3 VMB_DQ4 DQB_3 MAB_3 VMB_MA4
E34 J24 F1 N8
VMA_DQ4 DQA_3 MAA_3 VMA_MA4 VMB_DQ5 DQB_4 MAB_4 VMB_MA5
G32 H26 F3 N9
VMA_DQ[63..0] VMA_DQ5 DQA_4 MAA_4 VMA_MA5 VMB_DQ6 DQB_5 MAB_5 VMB_MA6
[10] VMA_DQ[63..0] D33 J26 F5 U9
VMA_DQ6 DQA_5 MAA_5 VMA_MA6 VMB_DQ7 DQB_6 MAB_6 VMB_MA7
F32 H21 G4 U8
VMA_DM[7..0] VMA_DQ7 DQA_6 MAA_6 VMA_MA7 VMB_DQ8 DQB_7 MAB_7 VMB_MA8
[10] VMA_DM[7..0] E32 G21 H5 Y9
DQA_7 MAA_7 DQB_8 MAB_8

.ru
VMA_DQ8 D31 H19 VMA_MA8 VMB_DQ[63..0] VMB_DQ9 H6 W9 VMB_MA9
VMA_RDQS[7..0] DQA_8 MAA_8 [11] VMB_DQ[63..0] DQB_9 MAB_9
VMA_DQ9 F30 H20 VMA_MA9 VMB_DQ10 J4 AC8 VMB_MA10
[10] VMA_RDQS[7..0] DQA_9 MAA_9 VMB_DM[7..0] DQB_10 MAB_10
VMA_DQ10 C30 L13 VMA_MA10 VMB_DQ11 K6 AC9 VMB_MA11
VMA_WDQS[7..0] DQA_10 MAA_10 [11] VMB_DM[7..0] DQB_11 MAB_11
VMA_DQ11 A30 G16 VMA_MA11 VMB_DQ12 K5 AA7 VMB_MA12
[10] VMA_WDQS[7..0] DQA_11 MAA_11 VMB_RDQS[7..0] DQB_12 MAB_12
VMA_DQ12 F28 J16 VMA_MA12 VMB_DQ13 L4 AA8 VMB_BA2
DQA_12 MAA_12 [11] VMB_RDQS[7..0] DQB_13 MAB_13/BA2
VMA_DQ13 C28 H16 VMA_BA2 VMB_DQ14 M6 Y8 VMB_BA0
VMA_DQ14 DQA_13 MAA_13/BA2 VMA_BA0 VMB_WDQS[7..0] VMB_DQ15 DQB_14 MAB_14/BA0 VMB_BA1
A28 J17 [11] VMB_WDQS[7..0] M1 AA9
VMA_MA[12..0] VMA_DQ15 DQA_14 MAA_14/BA0 VMA_BA1 VMB_DQ16 DQB_15 MAB_15/BA1
[10] VMA_MA[12..0] E28 H17 M3
VMA_DQ16 DQA_15 MAA_15/BA1 VMB_DQ17 DQB_16 VMB_DM0
D27 M5 H3
VMA_DQ17 DQA_16 VMA_DM0 VMB_MA[12..0] VMB_DQ18 DQB_17 DQMB_0 VMB_DM1
F26 A32 [11] VMB_MA[12..0] N4 H1
VMA_BA0 VMA_DQ18 DQA_17 DQMA_0 VMA_DM1 VMB_DQ19 DQB_18 DQMB_1 VMB_DM2
[10] VMA_BA0 C26 C32 P6 T3
VMA_BA1 VMA_DQ19 DQA_18 DQMA_1 VMA_DM2 VMB_DQ20 DQB_19 DQMB_2 VMB_DM3
[10] VMA_BA1 A26 D23 P5 T5
VMA_BA2 VMA_DQ20 DQA_19 DQMA_2 VMA_DM3 VMB_BA0 VMB_DQ21 DQB_20 DQMB_3 VMB_DM4
[10] VMA_BA2 F24 E22 [11] VMB_BA0 R4 AE4
VMA_DQ21 DQA_20 DQMA_3 VMA_DM4 VMB_BA1 VMB_DQ22 DQB_21 DQMB_4 VMB_DM5
C24 C14 [11] VMB_BA1 T6 AF5
VMA_DQ22 DQA_21 DQMA_4 VMA_DM5 VMB_BA2 VMB_DQ23 DQB_22 DQMB_5 VMB_DM6
A24 A14 [11] VMB_BA2 T1 AK6
VMA_DQ23 DQA_22 DQMA_5 VMA_DM6 VMB_DQ24 DQB_23 DQMB_6 VMB_DM7

m
E24 E10 U4 AK5
VMA_DQ24 DQA_23 DQMA_6 VMA_DM7 VMB_DQ25 DQB_24 DQMB_7
C22 D9 V6
VMA_DQ25 DQA_24 DQMA_7 VMB_DQ26 DQB_25 VMB_RDQS0
A22 V1 F6
VMA_DQ26 DQA_25 VMA_RDQS0 VMB_DQ27 DQB_26 QSB_0/RDQSB_0 VMB_RDQS1
F22 C34 V3 K3
VMA_DQ27 DQA_26 QSA_0/RDQSA_0 VMA_RDQS1 VMB_DQ28 DQB_27 QSB_1/RDQSB_1 VMB_RDQS2
D21 D29 Y6 P3
VMA_DQ28 DQA_27 QSA_1/RDQSA_1 VMA_RDQS2 VMB_DQ29 DQB_28 QSB_2/RDQSB_2 VMB_RDQS3
C A20
DQA_28 QSA_2/RDQSA_2
D25 Y1
DQB_29 QSB_3/RDQSB_3
V5 QSB[7..0] C
VMA_DQ29 F20 E20 VMA_RDQS3 QSA[7..0] VMB_DQ30 Y3 AB5 VMB_RDQS4
VMA_DQ30 DQA_29 QSA_3/RDQSA_3 VMA_RDQS4 VMB_DQ31 DQB_30 QSB_4/RDQSB_4 VMB_RDQS5
D19 E16 Y5 AH1
VMA_DQ31 DQA_30 QSA_4/RDQSA_4 VMA_RDQS5 VMB_DQ32 DQB_31 QSB_5/RDQSB_5 VMB_RDQS6
E18 E12 AA4 AJ9
VMA_DQ32 DQA_31 QSA_5/RDQSA_5 VMA_RDQS6 VMB_DQ33 DQB_32 QSB_6/RDQSB_6 VMB_RDQS7
C18 J10 AB6 AM5
VMA_DQ33 DQA_32 QSA_6/RDQSA_6 VMA_RDQS7 VMB_DQ34 DQB_33 QSB_7/RDQSB_7
A18 D7 AB1
DQA_33 QSA_7/RDQSA_7 DQB_34

ru
VMA_DQ34 F18 VMB_DQ35 AB3 G7 VMB_WDQS0
VMA_DQ35 DQA_34 VMA_WDQS0 VMB_DQ36 DQB_35 QSB_0B/WDQSB_0 VMB_WDQS1
D17 A34 AD6 K1
VMA_DQ36 DQA_35 QSA_0B/WDQSA_0 VMA_WDQS1 VMB_DQ37 DQB_36 QSB_1B/WDQSB_1 VMB_WDQS2
A16 E30 AD1 P1
VMA_DQ37 DQA_36 QSA_1B/WDQSA_1 VMA_WDQS2 VMB_DQ38 DQB_37 QSB_2B/WDQSB_2 VMB_WDQS3
F16
DQA_37 QSA_2B/WDQSA_2
E26 AD3
DQB_38 QSB_3B/WDQSB_3
W4 QSB#[7..0]
VMA_DQ38 D15 C20 VMA_WDQS3 QSA#[7..0] VMB_DQ39 AD5 AC4 VMB_WDQS4
VMA_DQ39 DQA_38 QSA_3B/WDQSA_3 VMA_WDQS4 VMB_DQ40 DQB_39 QSB_4B/WDQSB_4 VMB_WDQS5
E14 C16 AF1 AH3
VMA_DQ40 DQA_39 QSA_4B/WDQSA_4 VMA_WDQS5 VMB_DQ41 DQB_40 QSB_5B/WDQSB_5 VMB_WDQS6
F14 C12 AF3 AJ8
VMA_DQ41 DQA_40 QSA_5B/WDQSA_5 VMA_WDQS6 VMB_DQ42 DQB_41 QSB_6B/WDQSB_6 VMB_WDQS7
D13 J11 AF6 AM3
VMA_DQ42 DQA_41 QSA_6B/WDQSA_6 VMA_WDQS7 VMB_DQ43 DQB_42 QSB_7B/WDQSB_7
F12 F8 AG4
VMA_DQ43 DQA_42 QSA_7B/WDQSA_7 VMB_DQ44 DQB_43 VMB_ODT0
A12 AH5 T7 VMB_ODT0 [11]
VMA_DQ44 DQA_43 VMA_ODT0 VMB_DQ45 DQB_44 ODTB0 VMB_ODT1
D11 J21 VMA_ODT0 [10] AH6 W7 VMB_ODT1 [11]
VMA_DQ45 DQA_44 ODTA0 VMA_ODT1 VMB_DQ46 DQB_45 ODTB1
F10 G19 VMA_ODT1 [10] AJ4

Fo
VMA_DQ46 DQA_45 ODTA1 VMB_DQ47 DQB_46 VMB_CLK0
A10 AK3 L9 VMB_CLK0 [11]
VMA_DQ47 DQA_46 VMA_CLK0 VMB_DQ48 DQB_47 CLKB0 VMB_CLK0#
C10 H27 VMA_CLK0 [10] AF8 L8 VMB_CLK0# [11]
VMA_DQ48 DQA_47 CLKA0 VMA_CLK0# VMB_DQ49 DQB_48 CLKB0B
VMA_DQ49
G13
DQA_48 CLKA0B
G27 VMA_CLK0# [10] PLACE MVREF DIVIDERS VMB_DQ50
AF9
DQB_49 VMB_CLK1
H13 AG8 AD8 VMB_CLK1 [11]
VMA_DQ50 DQA_49 VMA_CLK1 AND CAPS CLOSE TO ASIC VMB_DQ51 DQB_50 CLKB1 VMB_CLK1#
PLACE MVREF DIVIDERS VMA_DQ51
J13
DQA_50 CLKA1
J14
VMA_CLK1#
VMA_CLK1 [10]
VMB_DQ52
AG7
DQB_51 CLKB1B
AD7 VMB_CLK1# [11]
H11 H14 VMA_CLK1# [10] AK9
AND CAPS CLOSE TO ASIC VMA_DQ52 DQA_51 CLKA1B VMB_DQ53 DQB_52 VMB_RAS0#
G10 AL7 T10 VMB_RAS0# [11]
VMA_DQ53 DQA_52 VMA_RAS0# VMB_DQ54 DQB_53 RASB0B VMB_RAS1#
G8 K23 VMA_RAS0# [10] AM8 Y10 VMB_RAS1# [11]
VMA_DQ54 DQA_53 RASA0B VMA_RAS1# VMB_DQ55 DQB_54 RASB1B
K9 K19 VMA_RAS1# [10] AM7
VMA_DQ55 DQA_54 RASA1B VMB_DQ56 DQB_55 VMB_CAS0#
K10 AK1 W10 VMB_CAS0# [11]
VMA_DQ56 DQA_55 VMA_CAS0# VMB_DQ57 DQB_56 CASB0B VMB_CAS1#
G9 K20 VMA_CAS0# [10] AL4 AA10 VMB_CAS1# [11]
+1.5V VMA_DQ57 DQA_56 CASA0B VMA_CAS1# +1.5V VMB_DQ58 DQB_57 CASB1B
A8 K17 VMA_CAS1# [10] AM6
VMA_DQ58 DQA_57 CASA1B VMB_DQ59 DQB_58 VMB_CS0#
C8 AM1 P10 VMB_CS0# [11]
VMA_DQ59 DQA_58 VMA_CS0# VMB_DQ60 DQB_59 CSB0B_0
E8 K24 VMA_CS0# [10] AN4 L10
VMA_DQ60 DQA_59 CSA0B_0 VMB_DQ61 DQB_60 CSB0B_1
A6 K27 AP3
DQA_60 CSA0B_1 DQB_61

B
R84
100/F_4

R83
100/F_4
C124
MVREFDA

0.1u/10V_4
VMA_DQ61
VMA_DQ62
VMA_DQ63

T47
T24
T25
C6
E6
A5

L18
L20

L27
N12
AG12
DQA_61
DQA_62
DQA_63

MVREFDA
MVREFSA

NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2
CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B
M13
K16

K21
J20

K26
L15

AF28
er
VMA_CS1#

VMA_CKE0
VMA_CKE1

VMA_WE0#
VMA_WE1#

T32
VMA_CS1#

VMA_CKE0
VMA_CKE1

VMA_WE0#
VMA_WE1#
[10]

[10]
[10]

[10]
[10]
R60
100/F_4

R65
100/F_4
C115
MVREFDB

0.1u/10V_4
+3V_D

R107

R108
*5.11K/F_4

1K/F_4
VMB_DQ62
VMB_DQ63

TESTEN
AP1
AP5

Y12
AA12

AD28
DQB_62
DQB_63

MVREFDB
MVREFSB
CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B
AD10
AC10

U10
AA11

N10
AB11
VMB_CS1#

VMB_CKE0
VMB_CKE1

VMB_WE0#
VMB_WE1#
VMB_CS1#

VMB_CKE0
VMB_CKE1

VMB_WE0#
VMB_WE1#
[11]

[11]
[11]

[11]
[11]

+1.5V
B

R58 243/F_4 RSVD#1 T45 TESTEN R61 4.7K_4

M12 AG28
yb
T50 MEM_CALRP1 RSVD#2 TEST_MCLK
M27 AL31 AK10
T26 NC_MEM_CALRP0 RSVD#3 TEST_YCLK CLKTESTA
AH12 AL10 AH11
NC_MEM_CALRP2 CLKTESTB DRAM_RST MEM_RST# [10,11]
H23
+1.5V RSVD#5 +1.5V
J19
RSVD#6
T8 R62 R56 R57 C102
RSVD#9 4.7K_4 4.7K_4 *4.7K_4 0.01u/16V_4
W8
RSVD#11
R88 R68 216-0729012-00
100/F_4 100/F_4
216-0729012-00
MVREFSA MVREFSB
C

R89 C139 R69 C111

100/F_4 0.1u/10V_4 100/F_4 0.1u/10V_4

A A

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
MEMORY_Interface
Date: Monday, December 22, 2008 Sheet 9 of 15
5 4 3 2 1
 5 4 3 2 1

MFR P/N : IDGH1G-04A1F1C-16X

CHANNEL A: 512MB/1GB DDR3
[9] VMA_DQ[63..0]
[9] VMA_DM[7..0]
[9] VMA_WDQS[7..0] QCI P/N : AKD58GGT^00
[9] VMA_RDQS[7..0]
U10 U6 U9 U4

VREFC_VMA1 M8 E3 VMA_DQ19 VREFC_VMA2 M8 E3 VMA_DQ25 VREFC_VMA3 M8 E3 VMA_DQ37 VREFC_VMA4 M8 E3 VMA_DQ53

VREFD_VMA1 VREFCA DQL0 VMA_DQ20 VREFD_VMA2 VREFCA DQL0 VMA_DQ24 VREFD_VMA3 VREFCA DQL0 VMA_DQ34 VREFD_VMA4 VREFCA DQL0 VMA_DQ55
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMA_DQ18 VREFDQ DQL1 VMA_DQ29 VREFDQ DQL1 VMA_DQ38 VREFDQ DQL1 VMA_DQ48
F2 F2 F2 F2
DQL2 VMA_DQ22 VMA_MA0 DQL2 VMA_DQ26 VMA_MA0 DQL2 VMA_DQ33 VMA_MA0 DQL2 VMA_DQ54
[9] VMA_MA0 N3 F8 N3 F8 N3 F8 N3 F8
A0 DQL3 VMA_DQ16 VMA_MA1 A0 DQL3 VMA_DQ31 VMA_MA1 A0 DQL3 VMA_DQ39 VMA_MA1 A0 DQL3 VMA_DQ51
[9] VMA_MA1 P7 H3 P7 H3 P7 H3 P7 H3
A1 DQL4 VMA_DQ21 VMA_MA2 A1 DQL4 VMA_DQ27 VMA_MA2 A1 DQL4 VMA_DQ32 VMA_MA2 A1 DQL4 VMA_DQ50
[9] VMA_MA2 P3 H8 P3 H8 P3 H8 P3 H8
A2 DQL5 VMA_DQ17 VMA_MA3 A2 DQL5 VMA_DQ28 VMA_MA3 A2 DQL5 VMA_DQ36 VMA_MA3 A2 DQL5 VMA_DQ52
[9] VMA_MA3 N2 G2 N2 G2 N2 G2 N2 G2
A3 DQL6 VMA_DQ23 VMA_MA4 A3 DQL6 VMA_DQ30 VMA_MA4 A3 DQL6 VMA_DQ35 VMA_MA4 A3 DQL6 VMA_DQ49
[9] VMA_MA4 P8 H7 P8 H7 P8 H7 P8 H7
A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
[9] VMA_MA5 P2 P2 P2 P2
A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5
[9] VMA_MA6 R8 R8 R8 R8
D A6 VMA_DQ14 VMA_MA7 A6 VMA_DQ4 VMA_MA7 A6 VMA_DQ56 VMA_MA7 A6 VMA_DQ43 D
[9] VMA_MA7 R2 D7 R2 D7 R2 D7 R2 D7
A7 DQU0 VMA_DQ11 VMA_MA8 A7 DQU0 VMA_DQ3 VMA_MA8 A7 DQU0 VMA_DQ61 VMA_MA8 A7 DQU0 VMA_DQ44
[9] VMA_MA8 T8 C3 T8 C3 T8 C3 T8 C3
A8 DQU1 VMA_DQ13 VMA_MA9 A8 DQU1 VMA_DQ7 VMA_MA9 A8 DQU1 VMA_DQ59 VMA_MA9 A8 DQU1 VMA_DQ41
[9] VMA_MA9 R3 C8 R3 C8 R3 C8 R3 C8
A9 DQU2 VMA_DQ9 VMA_MA10 A9 DQU2 VMA_DQ1 VMA_MA10 A9 DQU2 VMA_DQ63 VMA_MA10 A9 DQU2 VMA_DQ45
[9] VMA_MA10 L7 C2 L7 C2 L7 C2 L7 C2
A10/AP DQU3 VMA_DQ15 VMA_MA11 A10/AP DQU3 VMA_DQ5 VMA_MA11 A10/AP DQU3 VMA_DQ57 VMA_MA11 A10/AP DQU3 VMA_DQ42
[9] VMA_MA11 R7 A7 R7 A7 R7 A7 R7 A7
A11 DQU4 VMA_DQ8 VMA_MA12 A11 DQU4 VMA_DQ0 VMA_MA12 A11 DQU4 VMA_DQ62 VMA_MA12 A11 DQU4 VMA_DQ47
[9] VMA_MA12 N7 A2 N7 A2 N7 A2 N7 A2
A12/BC DQU5 VMA_DQ12 A12/BC DQU5 VMA_DQ6 A12/BC DQU5 VMA_DQ58 A12/BC DQU5 VMA_DQ40
T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMA_DQ10 A13 DQU6 VMA_DQ2 A13 DQU6 VMA_DQ60 A13 DQU6 VMA_DQ46
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V A15 +1.5V A15 +1.5V A15 +1.5V

M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2

[9] VMA_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9
[9] VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7
[9] VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
VDD#K8 VDD#K8 VDD#K8 VDD#K8
N1 N1 N1 N1
VDD#N1 VDD#N1 VDD#N1 VDD#N1

.ru
J7 N9 VMA_CLK0 J7 N9 J7 N9 VMA_CLK1 J7 N9
[9] VMA_CLK0 CK VDD#N9 CK VDD#N9 [9] VMA_CLK1 CK VDD#N9 CK VDD#N9
K7 R1 VMA_CLK0# K7 R1 K7 R1 VMA_CLK1# K7 R1
[9] VMA_CLK0# CK VDD#R1 CK VDD#R1 [9] VMA_CLK1# CK VDD#R1 CK VDD#R1
K9 R9 VMA_CKE0 K9 R9 K9 R9 VMA_CKE1 K9 R9
[9] VMA_CKE0 CKE VDD#R9 CKE VDD#R9 [9] VMA_CKE1 CKE VDD#R9 CKE VDD#R9
+1.5V +1.5V +1.5V +1.5V

K1 A1 VMA_ODT0 K1 A1 K1 A1 VMA_ODT1 K1 A1
[9] VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 [9] VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
L2 A8 VMA_CS0# L2 A8 L2 A8 VMA_CS1# L2 A8
[9] VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 [9] VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
J3 C1 VMA_RAS0# J3 C1 J3 C1 VMA_RAS1# J3 C1
[9] VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 [9] VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 VMA_CAS0# K3 C9 K3 C9 VMA_CAS1# K3 C9
[9] VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [9] VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 VMA_WE0# L3 D2 L3 D2 VMA_WE1# L3 D2
[9] VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 [9] VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMA_RDQS2 VDDQ#F1 VMA_RDQS3 VDDQ#F1 VMA_RDQS4 VDDQ#F1 VMA_RDQS6 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMA_RDQS1 DQSL VDDQ#H2 VMA_RDQS0 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2 VMA_RDQS5 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9

m
VMA_DM2 E7 A9 VMA_DM3 E7 A9 VMA_DM4 E7 A9 VMA_DM6 E7 A9
VMA_DM1 DML VSS#A9 VMA_DM0 DML VSS#A9 VMA_DM7 DML VSS#A9 VMA_DM5 DML VSS#A9
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMA_WDQS2 VSS#G8 VMA_WDQS3 VSS#G8 VMA_WDQS4 VSS#G8 VMA_WDQS6 VSS#G8
C G3 J2 G3 J2 G3 J2 G3 J2 C
VMA_WDQS1 DQSL VSS#J2 VMA_WDQS0 DQSL VSS#J2 VMA_WDQS7 DQSL VSS#J2 VMA_WDQS5 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
VSS#M9 VSS#M9 VSS#M9 VSS#M9
P1 P1 P1 P1
VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
[9,11] MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9

ru
T1 T1 T1 T1
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R112 VSSQ#B9 R31 VSSQ#B9 R72 VSSQ#B9 R24 VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
243/F_4 D8 243/F_4 D8 243/F_4 D8 243/F_4 D8
VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1

Fo
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VRAM _DDR3 VRAM _DDR3 VRAM _DDR3 VRAM _DDR3

+1.5V +1.5V +1.5V +1.5V +1.5V +1.5V +1.5V +1.5V

R103 R111 R29 R36 R75 R59 R27 R23

4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4

B
R109
4.99K/F_4
VREFC_VMA1

C187
0.1u/10V_4

VMA_CLK0
R113
4.99K/F_4
VREFD_VMA1

C192
0.1u/10V_4
R30
4.99K/F_4

+1.5V
VREFC_VMA2

C43
0.1u/10V_4
er
R35
4.99K/F_4
VREFD_VMA2

C46
0.1u/10V_4
R81
4.99K/F_4

+1.5V
VREFC_VMA3

C120
0.1u/10V_4
R63
4.99K/F_4
VREFD_VMA3

C108
0.1u/10V_4
R26
4.99K/F_4
VREFC_VMA4

C35
0.1u/10V_4
R21
4.99K/F_4
VREFD_VMA4

C33
0.1u/10V_4
B
yb
R34
56.2/F_4
C36 C28 C30 C27 C32 C37 C93 C132 C199 C50 C214 C40 C211 C61 C195 C213
C44
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
VMA_CLK0_COMM

R33 0.01u/16V_4 +1.5V

56.2/F_4

VMA_CLK0#
VMA_CLK1 C19 C146 C29 C204 C164 C26 C31 C106
C

1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4

R20
56.2/F_4
+1.5V +1.5V
C34
VMA_CLK1_COMM

R22 0.01u/16V_4 C39 C60 C263 C52 C38 C25 C84 C245
56.2/F_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

VMA_CLK1#

A A

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
MEMORY 1 channel A
Date: Monday, December 22, 2008 Sheet 10 of 15
5 4 3 2 1
 5 4 3 2 1

MFR P/N : IDGH1G-04A1F1C-16X

CHANNEL B: 512MB/1GB DDR3
[9] VMB_DQ[63..0]
[9] VMB_DM[7..0]
[9] VMB_WDQS[7..0] QCI P/N : AKD58GGT^00
[9] VMB_RDQS[7..0]
U2 U8 U7 U1

VREFC_VMB1 M8 E3 VMB_DQ0 VREFC_VMB2 M8 E3 VMB_DQ31 VREFC_VMB3 M8 E3 VMB_DQ36 VREFC_VMB4 M8 E3 VMB_DQ52

VREFD_VMB1 VREFCA DQL0 VMB_DQ2 VREFD_VMB2 VREFCA DQL0 VMB_DQ27 VREFD_VMB3 VREFCA DQL0 VMB_DQ34 VREFD_VMB4 VREFCA DQL0 VMB_DQ53
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMB_DQ7 VREFDQ DQL1 VMB_DQ30 VREFDQ DQL1 VMB_DQ39 VREFDQ DQL1 VMB_DQ51
F2 F2 F2 F2
DQL2 VMB_DQ3 VMB_MA0 DQL2 VMB_DQ28 VMB_MA0 DQL2 VMB_DQ32 VMB_MA0 DQL2 VMB_DQ55
[9] VMB_MA0 N3 F8 N3 F8 N3 F8 N3 F8
A0 DQL3 VMB_DQ1 VMB_MA1 A0 DQL3 VMB_DQ24 VMB_MA1 A0 DQL3 VMB_DQ37 VMB_MA1 A0 DQL3 VMB_DQ50
[9] VMB_MA1 P7 H3 P7 H3 P7 H3 P7 H3
A1 DQL4 VMB_DQ5 VMB_MA2 A1 DQL4 VMB_DQ25 VMB_MA2 A1 DQL4 VMB_DQ35 VMB_MA2 A1 DQL4 VMB_DQ48
[9] VMB_MA2 P3 H8 P3 H8 P3 H8 P3 H8
A2 DQL5 VMB_DQ6 VMB_MA3 A2 DQL5 VMB_DQ29 VMB_MA3 A2 DQL5 VMB_DQ38 VMB_MA3 A2 DQL5 VMB_DQ54
[9] VMB_MA3 N2 G2 N2 G2 N2 G2 N2 G2
A3 DQL6 VMB_DQ4 VMB_MA4 A3 DQL6 VMB_DQ26 VMB_MA4 A3 DQL6 VMB_DQ33 VMB_MA4 A3 DQL6 VMB_DQ49
[9] VMB_MA4 P8 H7 P8 H7 P8 H7 P8 H7
A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7
[9] VMB_MA5 P2 P2 P2 P2
A5 VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5
[9] VMB_MA6 R8 R8 R8 R8
A6 VMB_DQ23 VMB_MA7 A6 VMB_DQ13 VMB_MA7 A6 VMB_DQ62 VMB_MA7 A6 VMB_DQ44
[9] VMB_MA7 R2 D7 R2 D7 R2 D7 R2 D7
D A7 DQU0 VMB_DQ18 VMB_MA8 A7 DQU0 VMB_DQ11 VMB_MA8 A7 DQU0 VMB_DQ60 VMB_MA8 A7 DQU0 VMB_DQ43 D
[9] VMB_MA8 T8 C3 T8 C3 T8 C3 T8 C3
A8 DQU1 VMB_DQ21 VMB_MA9 A8 DQU1 VMB_DQ12 VMB_MA9 A8 DQU1 VMB_DQ58 VMB_MA9 A8 DQU1 VMB_DQ45
[9] VMB_MA9 R3 C8 R3 C8 R3 C8 R3 C8
A9 DQU2 VMB_DQ22 VMB_MA10 A9 DQU2 VMB_DQ10 VMB_MA10 A9 DQU2 VMB_DQ56 VMB_MA10 A9 DQU2 VMB_DQ41
[9] VMB_MA10 L7 C2 L7 C2 L7 C2 L7 C2
A10/AP DQU3 VMB_DQ20 VMB_MA11 A10/AP DQU3 VMB_DQ15 VMB_MA11 A10/AP DQU3 VMB_DQ61 VMB_MA11 A10/AP DQU3 VMB_DQ46
[9] VMB_MA11 R7 A7 R7 A7 R7 A7 R7 A7
A11 DQU4 VMB_DQ17 VMB_MA12 A11 DQU4 VMB_DQ8 VMB_MA12 A11 DQU4 VMB_DQ57 VMB_MA12 A11 DQU4 VMB_DQ40
[9] VMB_MA12 N7 A2 N7 A2 N7 A2 N7 A2
A12/BC DQU5 VMB_DQ16 A12/BC DQU5 VMB_DQ9 A12/BC DQU5 VMB_DQ63 A12/BC DQU5 VMB_DQ47
T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMB_DQ19 A13 DQU6 VMB_DQ14 A13 DQU6 VMB_DQ59 A13 DQU6 VMB_DQ42
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V A15 +1.5V A15 +1.5V A15 +1.5V

M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

[9] VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
[9] VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
[9] VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
VDD#K8 VDD#K8 VDD#K8 VDD#K8
N1 N1 N1 N1
VDD#N1 VMB_CLK0 VDD#N1 VDD#N1 VMB_CLK1 VDD#N1
[9] VMB_CLK0 J7 N9 J7 N9 [9] VMB_CLK1 J7 N9 J7 N9
CK VDD#N9 CK VDD#N9 CK VDD#N9 CK VDD#N9

.ru
K7 R1 VMB_CLK0# K7 R1 K7 R1 VMB_CLK1# K7 R1
[9] VMB_CLK0# CK VDD#R1 CK VDD#R1 [9] VMB_CLK1# CK VDD#R1 CK VDD#R1
K9 R9 VMB_CKE0 K9 R9 K9 R9 VMB_CKE1 K9 R9
[9] VMB_CKE0 CKE VDD#R9 CKE VDD#R9 [9] VMB_CKE1 CKE VDD#R9 CKE VDD#R9
+1.5V +1.5V +1.5V +1.5V

K1 A1 VMB_ODT0 K1 A1 K1 A1 VMB_ODT1 K1 A1
[9] VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 [9] VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
L2 A8 VMB_CS0# L2 A8 L2 A8 VMB_CS1# L2 A8
[9] VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 [9] VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
J3 C1 VMB_RAS0# J3 C1 J3 C1 VMB_RAS1# J3 C1
[9] VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 [9] VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 VMB_CAS0# K3 C9 K3 C9 VMB_CAS1# K3 C9
[9] VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [9] VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 VMB_WE0# L3 D2 L3 D2 VMB_WE1# L3 D2
[9] VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 [9] VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMB_RDQS0 VDDQ#F1 VMB_RDQS3 VDDQ#F1 VMB_RDQS4 VDDQ#F1 VMB_RDQS6 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMB_RDQS2 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9

VMB_DM0 VMB_DM3 VMB_DM4 VMB_DM6

m
E7 A9 E7 A9 E7 A9 E7 A9
VMB_DM2 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM7 DML VSS#A9 VMB_DM5 DML VSS#A9
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMB_WDQS0 VSS#G8 VMB_WDQS3 VSS#G8 VMB_WDQS4 VSS#G8 VMB_WDQS6 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMB_WDQS2 DQSL VSS#J2 VMB_WDQS1 DQSL VSS#J2 VMB_WDQS7 DQSL VSS#J2 VMB_WDQS5 DQSL VSS#J2
C B7 J8 B7 J8 B7 J8 B7 J8 C
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
VSS#M9 VSS#M9 VSS#M9 VSS#M9
P1 P1 P1 P1
VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
[9,10] MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VSS#T1 VSS#T1 VSS#T1 VSS#T1

ru
VMB_ZQ1 L8 T9 VMB_ZQ2 L8 T9 VMB_ZQ3 L8 T9 VMB_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R14 VSSQ#B9 R39 VSSQ#B9 R49 VSSQ#B9 R7 VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
243/F_4 D8 243/F_4 D8 243/F_4 D8 243/F_4 D8
VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9

Fo
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VRAM _DDR3 VRAM _DDR3 VRAM _DDR3 VRAM _DDR3

+1.5V +1.5V +1.5V +1.5V +1.5V +1.5V +1.5V +1.5V

R12 R4 R41 R51 R48 R43 R9 R10

4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4

VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4

B
R13
4.99K/F_4 C23
0.1u/10V_4

VMB_CLK0
R3
4.99K/F_4 C4
0.1u/10V_4
R40
4.99K/F_4

+1.5V
C69
0.1u/10V_4
erR50
4.99K/F_4 C81
0.1u/10V_4
R47
4.99K/F_4

+1.5V
C77
0.1u/10V_4
R42
4.99K/F_4 C73
0.1u/10V_4
R8
4.99K/F_4 C16
0.1u/10V_4
R11
4.99K/F_4 C22
0.1u/10V_4
B
yb
R2
56.2/F_4
C6 C5 C7 C41 C75 C67 C24 C20 C8 C9 C10 C17 C15 C72 C14 C13
C2
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
VMB_CLK0_COMM

R1 0.01u/16V_4 +1.5V
56.2/F_4

VMB_CLK0#
VMB_CLK1 C66 C65 C80 C70 C78 C79 C21 C68
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
C

R5
56.2/F_4
+1.5V +1.5V
C12
VMB_CLK1_COMM

R6 0.01u/16V_4 C71 C74 C11 C18 C3 C63 C82 C64

56.2/F_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

VMB_CLK1#

A A

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
MEMORY 2 channel B
Date: Monday, December 22, 2008 Sheet 11 of 15
5 4 3 2 1
 1 2 3 4 5

1
V1.2GND PC51 PC50
0.1u/50V_6 1n/50V_6

2
R1
PR64
158K/F_6

V1.2GND
A A

R3
R4
PR63 PR62 PR24

R2
332K/F_4 750K/F_6 121K/F_6 PR66
PR60
100K/F_6 PC52 33K/F_6
0.1u/50V_6

3
PR61
0_6
2 2 V1.2GND
[4] VCORE1.2ID1
G1

G0
PR25
PQ14 PQ13 63.4K/F_6
2N7002E 2N7002E

.ru
1

1
V1.2GND V1.2GND
[4] VCORE1.2ID0
PR59
0_6 VIN-1.2V_CORE
V1.2GND V1.2GND PC31
PR58 1u/16V_6

VDDA
VIN
100K/F_6

+3V V1.2GND added on 10/21

m
V1.2GND VIN-1.2V_CORE

PC29

17

16

15

14

13
B V1.2GND 12/12 Modify 2200p/50V_4 B
modified on 10/24

AGND

VDDA

TEST

VREF

VSET
PR28 PR23 PC23 1n/50V_6
[3] GFXON

5
1K_4 100K/F_4
1 12 CSN 1 2 PC28 PC27 PC22
Main ON PR29 OCT CSN V1.2GND
0.1u/50V_6 10u/25V_1206

ru
10K_6 PC32 4 10u/25V_1206
PR68 0.01u/50V_6 V1.2GND
0_6 V1.2GND 2 1 2 11 CSP 2 1 V1.2GND PQ5 Change footprint 12/11

1
2
3
VIN CSP
AOL1414
PU2 PC24 22p/50V_4 PL3
OZ8111 0R47UH(PCMC063T-0R82MN) 11/06 Modify 18A
3 10 PHASE-1.2V
ON/SKIP LX VDD_CORE

1
Fo
PL4
PR67 4 9 UGATE-1.2V PR18 0R47UH(PCMC063T-0R82MN) PR19
PGD HDR
GNDP
VDDP

100K/F_6 LDR *2.2_4 51/F_6 + +

BST
PR27
0_6 PR22 PC25

2
PC21 100K/F_6 3.3n/50V_6
5

1
PC26 2 1
V1.2GND 0.22u/25V_6 *2200p/50V_4

5
[13] 1.8ON

2
+5V
PQ4
LGATE-1.2V 4 AOL1412 12/12 Modify PC19 PC18 PC20
330u/2V_7343 330u/2V_7343 10u//10V_8
PR21
PR26 22_6
er
1
2
3
VDDA
CSP
C PD1 0_6 V1.2GND C
RB500V PR20
PC30 CSN 1.91K/F_4
1u/16V_6 modified on 11/06 EMI solution
M96-92 XT DDR3 TZ12
8/30 Modify
yb
PR65 0_8

V1.2GND
VIN VDD_CORE

PR54
PR56 22_8
C

1M_6

3
3
VID[1:0] INPUTS OUTPUTS VOUT1
2
GFXON 2
VID1 VID0 G1 G0 OD1 OD2 OD3 PQ11
PR55 2N7002E

1
PQ12 1M_6

1
0 0 1.2V 0 0 2.75xR2/(R1+R2) 1.2V PR57 DTC144EU
100K_4
D D
0 1 1.1V 1 0 2.75x(R2//R3)/[(R2//R3)+R1] 1.1V

2
1 0 1.0V 0 1 2.75x(R2//R4)/[(R2//R4)+R1] 1.0V

1 1 0.9V 1 1 2.75x(R2//R3)/[(R2//R3//R4)+R1] 0.9V

Quanta Computer Inc.
MCP67 TABLE Set
PROJECT : BD3 VGA
Size Document Number Rev
B2A
VDD_CORE (OZ8111)
Date: Monday, December 22, 2008 Sheet 12 of 15
1 2 3 4 5
 1 2 3 4 5

+3V VIN +5V +3V

10/22 modify

PR3 0_6

2
EN1
[12] 1.8ON
PR9 PR12 PR11 PR10
EN2 100K_4 10/F_6 2.2_6 100K_4

A PR4 0_6 A

1
1u/10V_6
0.1u/50V_6
PC5 PC4 [14] HW PG_1.8V 6228_GND 6228_GND
HW PG_1.5V [14]
*0.1u/10V_4 *0.1u/10V_4
modified on 11/6
modified on 11/6
6228_GND PR39 PR38
22.1K/F_4 18.2K/F_4 6228_GND

6228_GND

1
modified on 11/6
modified on 11/6 PR36 PC46 PC43 PR35

PC44

PC45
16.9K/F_6 1000p/50V_6 1000p/50V_6 22.6K/F_6

2
PC42 PR33 PR32 PC41
1800p/50V_6 750/F_6 750/F_6 1800p/50V_6

.ru
modified on 10/24
PR37 34K/F_6 34K/F_6 PR34

1
PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
GND_T 29 6228_GND modified on 12/12
modified on 12/12 PR6 19.1K/F_6 16.5K/F_6 PR7
8 FB1 PGOOD2 28

PC6 9 27 PC7
PR5 19.1K/F_6 68n/50V_6 VO1 FB2 68n/50V_6 16.5K/F_6 PR8
10 26

m
OCSET1 PU3 VO2
VIN EN1 11 ISL6228 25 VIN
EN1 OCSET2
B PHASE1 12 24 EN2 B
PHASE1 EN2
UGATE1 13 23 PHASE2
UGATE1 PHASE2

5
6
7
8
PC40 2 1 14 22 UGATE2 PC35
BOOT1 UGATE2

LGATE1

LGATE2
2200p/50V_4 2200p/50V_4

PGND1

PGND2

BOOT2
PVCC1

PVCC2

ru
PC37 PR31 2.2_6 UGATE2 4
PC3 PC39 0.1u/50V_6 PC2 PC38 0.1u/50V_6
10u/25V_1206 0.1u/50V_6 PC36 10u/25V_1206
0.1u/50V_6 Change

15

16

17

18

19

20

21
LGATE1 footprint
PR30 2.2_6 PQ2 7A
2 1 AO4468 12/11

LGATE1

LGATE2

3
2
1
4

+1.5V
D1

D1
S2

G2

Fo
+5V +5V
PHASE2
PQ3 PL1
AO4932 1R5UH(PCMC063T-1R5MN)
PR1
S1/D2

2A Change PC33 PC34 *2.2_4 L=1.5uH

G1

5
6
7
8
1u/16V_6 1u/16V_6 + PC16
+1.8V
footprint 12/11
PC1
DCR=14mohm 0.1u/50V_6
5

PC15
LGATE2 4
OCP = 9A
*2200p/50V_4 10u/10V_8

PHASE1 UGATE1 PQ1

PL2 AO4710 PC14
4R7UH(PCMC063T-4R7MN)

L=4.7uH PR13
er 220u/2.5V_3528

3
2
1
C + *2.2_4 C

PC49
DCR=37mohm
10u/10V_8 added on 10/21
OCP = 4A PC8

PC48 PC13 *2200p/50V_4

yb
0.1u/50V_6 220u/2.5V_3528

added on 10/21 added for +1.5V discharging on oct.14

VIN +1.8V +1.5V

C

PR53 PR52
PR50 22_8 22_8
1M_6
3

3
3

2 2
1.8ON 2

PR2 PR51 PQ10 PQ9

1

0_6 PQ8 1M_6 DMN601K-7 DMN601K-7

1

D PR49 DTC144EU D
100K_4
2

6228_GND

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
1.8V/1.5V(ISL6228)
Date: Monday, December 22, 2008 Sheet 13 of 15
1 2 3 4 5
 1 2 3 4 5

+1.1V

A
10/30 Change to G9661 A

+3V

+5V PR15
100K_4
PC12 PU1
0.1u/50V_6 G9661

.ru
4 VPP PGOOD 1 GFXPG [3]
1.1_EN 0_6 PR14 2 6
VEN VO +1.1V

+1.5V 3 VIN 2A
8

ADJ
GND
9 GND NC 5
PR16
15K/F_6 PC17

7
10u/10V_8

0.8V

m
PC10 PC9 PC11
10u/16V_8 0.1u/50V_6 *0.1u/50V_6
PR17
B 34K/F_6 B

Vout =0.8(1+R1/R2)
=1.1V

ru
Fo
C
er C

VIN +1.1V
yb
10/14 modify
PR43 PR47
1M_6 22_8
+3V

3
3
C

PR46
37.4K/F_6 PR45
1.1_EN 2 1M_6 2

PR48 PQ7
*100K/F_6 PQ6 DMN601K-7

1
DTC144EU

1
PU4
5

PR44 0_6 1
[13] HW PG_1.8V
4 1.1_EN
PR42 0_6 2
[13] HW PG_1.5V NC7SZ08P5X
3

D D

HW PG_1.8V PR40 *0_6 1.1_EN

HW PG_1.5V PR41 *0_6

PC47 Quanta Computer Inc.
*0.1u/50V_6
PROJECT : BD3 VGA
Size Document Number Rev
B2A
+1.1V (OZ8116LN)
Date: Monday, December 22, 2008 Sheet 14 of 15
1 2 3 4 5
 5 4 3 2 1

Model REV DATE CHANGE LIST NOTE

1st release schematic
BD3 A1A PAGE2, Remove C80,C105,C106,C179
PAGE2, C1 change to 1000p
RE-FLASH PAGE5, C3201,C3794 change footprint
VGA PAGE7, Update DDR3 Memory strap table
PAGE10, Remove C3429,C3426,C3425,C3428,C3433,C3439,C3427,C3434,C3412,C3364
D PAGE10, U3039,U3038,U3013 data pin swap D

PAGE11, Remove C3357,C3139,C3142,C3358,C3141,C3840,C3196,C3219,C3870,C3873

PAGE11, U3036,U3012,U3010,U3034 data pin swap
PAGE13, PR5,PR6 P/N change to CS31003F949
PAGE13, PR7,PR8 P/N change to CS31153F929
PAGE13, PC7,PC6 P/N change to CH31206K916
Power
PAGE12, Update VID table
PAGE12, Add PR21

.ru
PAGE14, Change to G9661 for +1.1V circuit

PAGE4, Change C42,C45 to 29p/50V

B2A PAGE5, Change R119 to 10K 1%.
PAGE6, Add GND for DPA PLL power.

m
Power
PAGE12, Change PL3,PL4 footprint.
C
PAGE13, Change PL1,PL2 footprint. C

PAGE13, Remove JP1, JP2.

PAGE12, Change PR23 to 100K 1%.

ru
PAGE12, Change PC25 to 3.3nF.
PAGE13, Change PR6,PR5 to 19.1K 1%.
PAGE13, Change PR7,PR8 to 16.5K 1%.
PAGE13, Change PC6,PC7 to 68nF.

Fo
B
er B
yb
C

A A

Quanta Computer Inc.

PROJECT : BD3 VGA
Size Document Number Rev
B2A
Change list
Date: Monday, December 22, 2008 Sheet 15 of 15
5 4 3 2 1