enhanced Serial

Communication Interface
(eSCI)

D. Valli
Associate Professor
TIFAC CORE in Automotive Infotronics
E-mail: dvalli@vit.ac.in

1
Communication Interfaces

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 Electronic controls in Automotive
9Vehicle functions are divided into systems and sub-systems to
provide for passenger entertainment, comfort, and safety, as
well as to improve vehicle performance and enhance power
train control.
• Body Electronics:
Window, Mirror, Lighting & Door lock etc.,
• Safety: Air Bag, ABS
• Power train: Automatic transmission control
• Telematics & Infotainment: Navigation systems

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 Need of IVN
9Added wiring increases
vehicle weight,
weak performance, and
to adherence to reliability standards difficult.
9For an average well-tuned vehicle,
every extra 50 kilograms of wiring—or extra 100
watts of power—
increases fuel consumption by 0.2 liters for each 100
kilometers traveled.
9Eventually, the wiring harness became the single most
expensive and complicated component in vehicle
electrical systems
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 Need of IVN

9 Cost Efficient Cabling

9 Increased Reliability of the overall system –
9 Reduced number of connectors and
maintenance
9 functions can be added through software
changes.
9Enhanced and more efficient diagnostics from any
location
9 Communication speed – Critical Requirement

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 Automotive Buses

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 Automotive Buses

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 eSCI Features
9The eSCI allows asynchronous serial communications with peripheral
devices and other CPUs.

9The eSCI has special features which allow the eSCI to operate as a LIN
bus master, complying with the LIN 2.0 specification.

SCI Transmit (TXDx)

This pin serves as transmit data output of eSCI.
SCI Receive Pin (RXDx)
This pin serves as receive data input of the eSCI.

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 eSCI Features
9 Full-duplex operation
9 Standard mark/space non-return-to-zero (NRZ) format
9 Configurable baud rate
9 Programmable 8-bit or 9-bit data format
9Separately enabled transmitter and receiver
9 Programmable transmitter output parity
9 Two receiver wake-up methods:
— Idle line wake-up
— Address mark wake-up
9 Interrupt-driven operation
9 Receiver framing error detection
9 Hardware parity checking
9 Two-channel DMA interface
9 LIN master node support
9 Configurable CRC detection for LIN
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 eSCI Block Diagram

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 Memory Map/Register Description

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 eSCI Control Register 1(ESCIx_CR1)

SBRn SCI baud rate.

9600=1MHz/(16*x)

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 eSCI Control Register 1(ESCIx_CR1)

LOOPS Loop select

M Data format mode.

0 - 1 start bit, 8 data bits, 1 stop bit
1 - 1 start bit, 9 data bits, 1 stop bit
WAKE Wake-up condition.
0 Idle line wake-up
1 Address mark wake-up
PE Parity enable
PT Parity type.
0 Even parity
1 Odd parity

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 eSCI Control Register 1(ESCIx_CR1)

TIE Transmitter interrupt enable.

0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
TCIE Transmission complete interrupt enable.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
RIE Receiver full interrupt enable.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
ILIE Idle line interrupt enable.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled

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 eSCI Control Register 1(ESCIx_CR1)
TE Transmitter enable.
0 Transmitter disabled
1 Transmitter enabled
RE Receiver enable.
0 Receiver disabled
1 Receiver enabled
RWU Receiver wake-up. Standby state.
0 Normal operation.
1 RWU enables the wake-up function and inhibits further receiver
interrupt requests.
Normally, hardware wakes the receiver by automatically clearing RWU.
SBK Send break.
0 No break characters
1 Transmit break characters

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eSCI Control Register 2(ESCIx_CR2)

MDIS Module disable.

FBR Fast bit error detection
BSTP Bit error/physical bus error stop
IEBERR Enable bit error interrupt
RXDMA Activate RX DMA channel
TXDMA Activate TX DMA channel
BRK13 Break transmit character length

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eSCI Control Register 2(ESCIx_CR2)
BESM13 Bit error sample mode, bit 13.
0 Sample at RT clock 9
1 Sample at RT clock 13
SBSTP SCI bit error stop.
Stops the SCI when a bit error is asserted. This allows to stop driving
the LIN bus quickly after a bit error has been detected.
ORIE Overrun error interrupt enable.
NFIE Noise flag interrupt enable.
FEIE Frame error interrupt enable.
PFIE Parity flag interrupt enable.

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eSCI Data Register (ESCIx_DR)

eSCI Status Register (ESCIx_SR)

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eSCI Status Register (ESCIx_SR)

BERR Bit error.

RAF Receiver active flag.
0 No reception in progress.
1 Reception in progress.
RXRDY The eSCI has received LIN data.
TXRDY The LIN FSM can accept another write to ESCIx_LTR.
LWAKE Received LIN wake-up signal.
STO Slave time out.
PBERR Physical bus error.
CERR CRC error.
CKERR Checksum error.
FRC Frame complete.
LIN frame completely transmitted. All LIN data bytes received.
OVFL ESCIx_LRR overflow.
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Register Definition
eSCI Status Register (ESCIx_SR)

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Programming Steps: (Loop Back Mode)
(I) Initialization of system clock (lock the system clock by FMPLL)
1. Initialization of eSCI
2. Transmit Data
3. Read and Echo Back Data
(I) Initialization of system clock
a. Set System Clock
b. Wait Until PLL gets Lock

1. Initialization of eSCI
a. Enable the module of esCI
b. Initialize eSCI control.
c. Configure Pads

2. Transmit Data
a. Wait for Transmit Data Empty register Status Flag.
b. Clear Status Flag.
c. Load data to Data Register.

3. Reading the Echo back

a. Wait for Receive Data Full Register Status Flag to set
b. Clear Status Flag.
c. Read result from Data Register.

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Programming Steps: (Loop Back Mode)
(I) Initialization of system clock
a. Set System Clock
Set System Clock [Synthesizer Control Register (FMPLL_SYNCR)]

For example, required Fsys = 64 MHZ

Reference Clock = 8 MHz
Hence low value to RFD = 0
PREDIV = 0
Hence, 64 MHz = 8 MHz x ( MFD + 4)
-----------------------------
((0 + 1) x 1)

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a. Set System Clock
Set System Clock [Synthesizer Control Register (FMPLL_SYNCR)]

Hence,
MFD = ( 64MHz / 8MHz) – 4
= 4
Therefore,
MFD = 00100
RFD = 000
PREDIV = 000

FMPLL.SYNCR.R = 0x0200000;

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b. Wait Until PLL gets Lock

while(FMPLL.SYNSR.B.LOCK != 1);

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1. Initialization of eSCI
a. Enable the module of esCI

eSCI Control Register 2(ESCIx_CR2)

Module Disable
MDIS When 1 - Disable
0 - Enable

ESCI_A.CR2.R = 0x0000;

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b. Initialize esCI Control
eSCI Control Register 1(ESCIx_CR1)

• Baud Rate value = 64 M / (16 × 9600) ~= 417 SBR = 417(0x1A1)

• Word length = 8 bits M=0
• Parity is not enabled PE = 0
• Enable transmitter TE = 1
• Enable receiver RE = 1
• Enable Loop Back mode LOOPS = 1

ESCI_A.CR1.R = 0x01A1800C;

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c. Configure Pads
Pad Configuration Register (PCR)
The pin 89 is TXDA and the pin 90 is RXDA
Hence, these pins (pads) functionality can be configured by using SIU
(System Integration Unit)

3,4,5 - PA

SIU.PCR[90].R = 0x0400;
SIU.PCR[89].R = 0x0400;

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2. Transmit Data
a. Wait for Transmit Data Empty register Status Flag.

TDRE When
0 - No byte transferred to transmit shift register
1 - Byte transferred to transmit shift register; transmit data register empty

Hence, poll for 1.

while(ESCI_A.SR.B.TDRE == 0);

b. Clear the Status Flag.

To Clear, place TDRE=1.

ESCI_A.SR.B.TDRE = 1;

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c. Load Data to the data register
eSCI Data Register (ESCIx_DR)

ESCI_A.DR.B.D = txdata;

3. Reading the Echo back

a. Wait for Receive Data Full Register Status Flag to set
RDRF When
0 Data not available in eSCI data register
1 Received data available in eSCI data register
Hence, poll for 1.

while(ESCI_A.SR.B.RDRF == 0);

• Clear the Status Flag.

ESCI_A.SR.B.RDRF = 1;
To Clear, place RDRF=1.

c. Load Data from the data register eSCI Data Register (ESCIx_DR)

rxdata = ESCI_A.DR.B.D;

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Program:

# include “MPC5554.h”
uint8_t recdata[10];
uint8_t j; ESCI_A.DR.B.D = txdata;
const uint8_t transdata[ ] = { “HELLO” };
void main(void)
{
FMPLL.SYNCR.R = 0x0200000;
while(FMPLL.SYNSR.B.LOCK != 1);
ESCI_A.CR2.R = 0x0000;
ESCI_A.CR1.R = 0x01A1800C;
SIU.PCR[90].R = 0x0400;
SIU.PCR[89].R = 0x0400;
while(1) {
for( j=0; j<size of(transdata); j++) {
while(ESCI_A.SR.B.TDRE == 0);
ESCI_A.SR.B.TDRE = 1;
ESCI_A.DR.B.D = txdata;
while(ESCI_A.SR.B.RDRF == 0);
ESCI_A.SR.B.RDRF = 1;
rxdata[j] = ESCI_A.DR.B.D;
}
}
}

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Programming Steps: (In Transmitter Side)

(I) Initialization of system clock (lock the system clock by FMPLL)

1. Initialization of eSCI
2. Transmit Data
3. Read and Echo Back Data
(I) Initialization of system clock
a. Set System Clock
b. Wait Until PLL gets Lock

1. Initialization of eSCI
a. Enable the module of esCI
b. Initialize eSCI control.
c. Configure Pads

2. Transmit Data
a. Wait for Transmit Data Empty register Status Flag.
b. Clear Status Flag.
c. Load data to Data Register.

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Programming Steps: (Loop Back Mode)
(I) Initialization of system clock
a. Set System Clock
Set System Clock [Synthesizer Control Register (FMPLL_SYNCR)]

For example, required Fsys = 64 MHZ

Reference Clock = 8 MHz
Hence low value to RFD = 0
PREDIV = 0
Hence, 64 MHz = 8 MHz x ( MFD + 4)
-----------------------------
((0 + 1) x 1)

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a. Set System Clock
Set System Clock [Synthesizer Control Register (FMPLL_SYNCR)]

Hence,
MFD = ( 64MHz / 8MHz) – 4
= 4
Therefore,
MFD = 00100
RFD = 000
PREDIV = 000

FMPLL.SYNCR.R = 0x0200000;

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b. Wait Until PLL gets Lock

while(FMPLL.SYNSR.B.LOCK != 1);

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1. Initialization of eSCI
a. Enable the module of esCI

eSCI Control Register 2(ESCIx_CR2)

Module Disable
MDIS When 1 - Disable
0 - Enable

ESCI_A.CR2.R = 0x0000;

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b. Initialize esCI Control
eSCI Control Register 1(ESCIx_CR1)

• Baud Rate value = 64 M / (16 × 9600) ~= 417 SBR = 417(0x1A1)

• Word length = 8 bits M=0
• Parity is not enabled PE = 0
• Enable transmitter TE = 1
• Enable receiver RE = 1
• Disable Loop Back mode LOOPS = 0

ESCI_A.CR1.R = 0x01A1000C;

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c. Configure Pads
Pad Configuration Register (PCR)
The pin 89 is TXDA.
Hence, these pins (pads) functionality can be configured by using SIU
(System Integration Unit)

3,4,5 - PA

SIU.PCR[89].R = 0x0400;

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2. Transmit Data
a. Wait for Transmit Data Empty register Status Flag.

TDRE When
0 - No byte transferred to transmit shift register
1 - Byte transferred to transmit shift register; transmit data register empty

Hence, poll for 1. while(ESCI_A.SR.B.TDRE == 0);

b. Clear the Status Flag.

To Clear, place TDRE=1. ESCI_A.SR.B.TDRE = 1;

c. Load Data to the data register

eSCI Data Register (ESCIx_DR)

ESCI_A.DR.B.D = txdata;

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Program:

ESCI_A.DR.B.D = txdata;
# include “MPC5554.h”
uint8_t j;
const uint8_t transdata[ ] = { “HELLO” };
void main(void)
{
FMPLL.SYNCR.R = 0x0200000;
while(FMPLL.SYNSR.B.LOCK != 1);
ESCI_A.CR2.R = 0x0000;
ESCI_A.CR1.R = 0x01A1000C;
SIU.PCR[89].R = 0x0400;
while(1) {
for( j=0; j<size of(transdata); j++) {
while(ESCI_A.SR.B.TDRE == 0);
ESCI_A.SR.B.TDRE = 1;
ESCI_A.DR.B.D = txdata;
}
}
}

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Programming Steps: (Receiver Side)
(I) Initialization of system clock
a. Set System Clock
Set System Clock [Synthesizer Control Register (FMPLL_SYNCR)]

For example, required Fsys = 64 MHZ

Reference Clock = 8 MHz
Hence low value to RFD = 0
PREDIV = 0
Hence, 64 MHz = 8 MHz x ( MFD + 4)
-----------------------------
((0 + 1) x 1)

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a. Set System Clock
Set System Clock [Synthesizer Control Register (FMPLL_SYNCR)]

Hence,
MFD = ( 64MHz / 8MHz) – 4
= 4
Therefore,
MFD = 00100
RFD = 000
PREDIV = 000

FMPLL.SYNCR.R = 0x0200000;

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b. Wait Until PLL gets Lock

while(FMPLL.SYNSR.B.LOCK != 1);

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1. Initialization of eSCI
a. Enable the module of esCI

eSCI Control Register 2(ESCIx_CR2)

Module Disable
MDIS When 1 - Disable
0 - Enable

ESCI_A.CR2.R = 0x0000;

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b. Initialize esCI Control
eSCI Control Register 1(ESCIx_CR1)

• Baud Rate value = 64 M / (16 × 9600) ~= 417 SBR = 417(0x1A1)

• Word length = 8 bits M=0
• Parity is not enabled PE = 0
• Enable transmitter TE = 1
• Enable receiver RE = 1
• Enable Loop Back mode LOOPS = 0

ESCI_A.CR1.R = 0x01A1000C;

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c. Configure Pads
Pad Configuration Register (PCR)
The pin 89 is TXDA and the pin 90 is RXDA
Hence, these pins (pads) functionality can be configured by using SIU
(System Integration Unit)

3,4,5 - PA

SIU.PCR[90].R = 0x0400;

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2. Receive Data
a. Wait for Receive Data Full register Status Flag.

RDRF When
0 Data not available in eSCI data register
1 Received data available in eSCI data register

Hence, poll for 1. while(ESCI_A.SR.B.RDRF == 0);

b. Clear the Status Flag.

To Clear, place RDRF=1. ESCI_A.SR.B.RDRF = 1;

c. Load Data from the data register

eSCI Data Register (ESCIx_DR)

rxdata = ESCI_A.DR.B.D ;

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Program:

ESCI_A.DR.B.D = txdata;
# include “MPC5554.h”
uint8_t recdata[10];
uint8_t j;
void main(void)
{
FMPLL.SYNCR.R = 0x0200000;
while(FMPLL.SYNSR.B.LOCK != 1);
ESCI_A.CR2.R = 0x0000;
ESCI_A.CR1.R = 0x01A1000C;
SIU.PCR[90].R = 0x0400;
while(1) {
for( j=0; j<10; j++) {
while(ESCI_A.SR.B.RDRF == 0);
ESCI_A.SR.B.RDRF = 1;
rxdata[j] = ESCI_A.DR.B.D;
}
}
}

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Thank You

48