Motorola Power Controller: by Sasi Kumar C Development Engineer

- Motorola Power Controller
By
Sasi Kumar C
Development Engineer
TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Sponsored by Dept. of Science & Technology, Govt. of India
Overview

SPI – Serial Peripheral Interface
Why? Æ SPI
¾ Master and Slave Concept
¾ High Data Rate.
¾ Data synchronization
¾ Cost Effective (No Driver Support).
What? Æ SPI
SPI is a synchronous serial protocol proposed by Motorola to be used as

standard for interfacing peripheral chips to a microcontroller.

SPI:
Devices are classified into the master or slaves.
¾ The SPI protocol uses four wires to carry out the task of data
communication:
9 MOSI: master out slave in
9 MISO: master in slave out
9 SCK: serial clock
9 SS: slave select
¾ An SPI data transfer is initiated by the master device.
¾ A master is responsible for generating the SCK signal to synchronize the

data transfer.
¾ The SPI protocol is mainly used to interface with MCU’s, shift registers,
LED/LCD drivers, phase locked loop chips, memory components with SPI
interface, or A/D or D/A converter chips.

DSPI - Overview
Deserial Serial Peripheral Interface provides a synchronous serial communication

between MPC5554 and an external peripheral device.
The DSPI supports pin count reduction through serialization and deserialization of
eTPU channels, eMIOS channels, and memory-mapped registers.
There are four identical DSPI modules (DSPI_A, DSPI_B, DSPI_C, and DSPI_D)
The DSPI has three configurations:
¾ Serial peripheral interface (SPI) configuration where the DSPI operates as an SPI
¾ Deserial serial interface (DSI) configuration where the DSPI serializes eTPU and
eMIOS output channels and deserializes the received data by placing it on the
eTPU and eMIOS input channels and as inputs to the external interrupt request
submodule of the SIU.
¾ Combined serial interface (CSI) configuration where the DSPI operates in both SPI
and DSI configurations interleaving DSI frames with SPI frames, giving priority to
SPI frames.
DSPI – Block Diagram

Modes of Operation
The DSPI has Four Modes of operation. They are
9 Master Mode
9 Slave Mode
9 Module Disable Mode
9 Debug mode
Master Mode
¾ Master mode allows the DSPI to initiate and control serial communication.
¾ In this mode the SCK, PCSn and SOUT signals are controlled by the DSPI and
configured as outputs.
Slave Mode
¾ Slave mode allows the DSPI to communicate with SPI/DSI bus masters.
¾ In this mode the DSPI responds to externally controlled serial transfers. The DSPI
cannot initiate serial transfers in slave mode.
¾ In slave mode, the SCK signal and the PCS0/SS signal are configured as inputs.

Module Disable Mode
¾ The module disable mode is used for MCU power management.
Debug Mode
¾ Debug mode is used for system development and debugging.
¾ If the device enters debug mode, the DSPI behavior is unaffected.
Signal Properties

DSPI – DSI Configuration
The DSI configuration supports pin count reduction by serializing parallel input signals
or register bits and shifting them out in an SPI-like protocol.
The received serial frames are converted to a parallel form (deserialized) and placed
on the parallel output signals or in a register.
Up to 16 ETPU (or a combination of eTPU and eMIOS ) channels can be serialized onto 3
wires (half-duplex master transmit) or 4 wires for master/slave operation.
Data is taken from the eTPU, eMIOS, or ASDR and transmitted serially.
Data from a received SPI frame is routed through to the eTPU, eMIOS channels, or to the
SIU interrupts.

Serialization and De Serialization

Serialized and De serialized Sources and Destinations

Internal Muxing/SIU support for serial and parallel chaining

DSPI – CSI Configuration
The Combined Serial Interface (CSI) mode allows the DSPI to operate in both SPI and DSI
configuration.
In master mode, the CSI configuration of the DSPI is used to support SPI and DSI functions
on a frame by frame basis.
CSI configuration allows interleaving of DSI data frames from the parallel input signals (from
the eTPU or eMIOS) with SPI commands and data from the TX FIFO.
The data returned from the bus slave is either used to drive the parallel output signals (to
the eTPU or eMIOS) or is stored in the RX FIFO.

CSI Serialization
CSI DeSerialization

DSPI – SPI Configuration
When DSPI operates as a basic SPI
SPI supports Full – Duplex Synchronous Serial communication
¾ Data transfers serially using shift registers. SPI frames can be 4 to 16 bits long. It
supports two module specific modes – Master , Slave.
¾ Master Mode initiates and controls the transfer according to command field
¾ Slave Mode only responds to the Master mode
The SPI signals on the MPC55xx family are as follows:

• SCK for serial clock, which is always driven by the master
• SOUT is the data out signal
• SIN is the serial data in signal
• PCS or peripheral chip select, used to enable the slave device

DSPI – SPI Configuration: Features
• Buffered transmit and receive operation using the TX and RX FIFO

• Programmable transfer attributes on a per-frame basis
— Eight clock and transfer attribute registers
— Serial clock with programmable polarity and phase
— Programmable delays
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
• Two DMA conditions for SPI queues residing in RAM or Flash
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
• Six interrupt conditions
– End of queue reached (EOQF)
– TX FIFO is not full (TFFF)
– Transfer of current frame complete (TCF)
– RX FIFO is not empty (RFDF)
– FIFO overrun (attempt to transmit with an empty TX FIFO or serial frame
received while RX FIFO is full) (RFOF)
– FIFO under flow

SPI – Registers:
Module Configuration Register (MCR)

Module Configuration Register (MCR)

DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
The MPC5553/MPC5554 DSPI modules each contain eight clock and transfer attribute
registers (DSPIx_CTARn) which are used to define different transfer attribute configurations.
Like • Frame size
• Baud rate and transfer delay values
• Clock phase
• Clock polarity
• MSB/LSB first


DSPIx_CTARn




DSPI Status Register (DSPIx_SR)



DSPI PUSH TX FIFO REGISTER (DSPIx_PUSHR)
DSPI POP RX FIFO REGISTER (DSPIx_POPR)

DSPIx_PUSHR
DSPIx_POPR

Communication Method:
Two methods of communication is possible

1. Loading data directly to register
2. Using eDMA
Method 2:

Method 1: Programming
Step 1:
To select Hardware pins ( Inputs to DPSI )
SIU_DISR

To select DSPI_C
SIN - Pin 108

SCK - Pin 109
SS - Pin 110

Programming:
Step 1:
To select Hardware pins ( Inputs to DPSI )
Hence,
SIU.DISR.R = 0x00000000;

Programming:
Step 2:
To set Time Base
Core with MCU with

SPI SPI
By using FMPLL
For 1 MHz MFD = 00000 = 0

Hence, PREDIV = 000 = 1
RFD = 100 = 4
FMPLL_SYNCR.R = 0x00200000;
while (FMPLL.SYNSR.B.LOCK != 1) {};

Programming:
Step 3:
Setting Baud Rate and Frame size using CTAR register
When DBR = 0 Normal SCK with 50/50

1 Twice SCK
When,
DBR = 0 When
BR = 0000
8 bit per frame
Hence,
DSPI_C.CTAR[0].R = 0x38000000;
Programming:
Step 4:
Configure pad as in input and output
Pin 107 – PCSB[2]_SOUTC_GPIO[107]

Pin 108 – PCSB[3]_SIN_C_GPIO[108]
Pin 109 – PCSB[4]_SCKC_GPIO[109]
Pin 110 – PCSB[5]_PCSC[0]_GPIO[110]
Hence,
SIU.PCR[107].R = 0x0A00;
SIU.PCR[109].R = 0x0A00;
SIU.PCR[110].R = 0x0A00;
SIU.PCR[108].R = 0x0900;

Programming:
Step 5:
Load value to Push register
When ,
CONT = 0 Slave select

Become inactive after transfers
CONT = 1 Slave select
Always remains active.
EOQ = 1 Indicates Last data

= 0 Not a Last data
PCS0 = 1 Peripheral Chip Select
Hence,
DSPI_C.PUSHR.R = 0x08010067;
where, TXDATA = 0067;
67 indicates 8 bit data in a frame.

Programming:
Step 6: For Reception
Wait for RFDF flag to set in the Status Register (DSPI_C.SR.R)
When
RFDF = 0 RX FIFO empty
1 Not Empty
Poll RFDF still become 1
Step 7:
Load Value from POP Register(DSPI_C.POPR.R)
Step 8:
Clear RFDF
Hence,
while(DPSI_C.SR.B.RFDF != 1);
receive = DSPI_C.POPR.;
DSPI_C.SR.R = 00020000;
CAN System

Programming Procedure ( NODE to NODE )
NODE-A NODE-B NODE-C
CAN BUS
NODE-D NODE-E NODE-F

NODE-B
NODE-A
AIR CONDITIONER
BUZZER
WHEEL
LCD DISPLAY
VIBRATION SENSOR
LED DISPLAY
MAGNETIC PICKUP SENSOR
NODE-C
TYRE PRESSURE SENSOR

ULTRASONIC SENSOR
RAIN SENSOR
LDR
INCLINOMETER

NODE-D
FUEL LEVEL SENSOR

TEMPERATURE SENSOR
DOOR LOCK SENSOR
NODE-E NODE-F
HEAD LIGHT STEERING

WIPER ACCELERATOR
BEAM LEVEL CONTROLLER AIR BAG
POWER WINDOW

CAN Programming Overview

Flex CAN – Overview
¾ MPC5554 contains three Control Area Network.

Features:
• Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Data length of 0 to 8 bytes
— Programmable bit rate up to 1 Mb/sec
• 64 flexible message buffers of 0 to 8 bytes data length
• It Supports standard and extended messages
• Includes 1024 bytes of RAM used for MB storage
• Programmable clock source, either system clock or oscillator clock
• Listen-only mode capability, Programmable loop-back mode supporting self-test operation
• Three programmable mask registers
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• Time stamp based on 16-bit free-running timer
• Short latency time due to an arbitration scheme for high-priority messages

Modes of Operation
1. Normal Mode:
The module operates receiving and/or transmitting message frames, errors are
handled normally and all the CAN protocol functions are enabled.
2. Freeze Mode:
In freeze mode no transmission or reception of frames is done, and

synchronization with the CAN bus is lost. (HLT / FRZ)
3. Listen Mode:
FlexCAN operates in a CAN error passive mode, freezing all error counters and
receiving messages without sending acknowledgments.
4. Loop Back Mode:
FlexCAN performs an internal loop back that can be used for self test operation.
5. Module Disable Mode:
Module shuts down clock, Buffer Management Sub Module.

Message Buffer:
The message buffer structure
used by the FlexCAN2 module is
represented by

Message Buffer code for RX buffer Message Buffer code for RX buffer

Register Description
Module Configuration Register
(CANx_MCR)

Register Description
Module Configuration Register
(CANx_MCR)

Control Register (CANx_CR)



Global Acceptance Mask (CANx_RXGMASK)

Interrupt Flags High and Low Register (CANx_IFRH & CANx_IFRL)

Programming:
Step 1:
To Enable Module and
Buffer.
MDIS 1 – Enable
0 – Disable
Buffer MAXMB 1 – Init Enable

0 – Init Disable
Hence,
CAN_A.MCR.R = 0x0000003F;

Programming:
Step 2:
To Set Bit Time
CLK_SRC 0 – Oscillator Clock

1 – System Clock
Ftq = Fclk / Prescalar

Prescalar = PRESDIV + 1
Bit time = Ftq / No. of Time Quanta
No. of Time Quanta = 1+TS1+TS2
TS1 = PROPSEG + PSEG1 + 2
TS2 = PSEG2 + 1
For 100KHz Bit Time,
If CLK_SRC = 0,
PRESDIV = 00000100 = 4,
Ftq = 8 MHz / 5 = 1.6 MHz
Therefore, 100 KHz Bit Time = 1.6 MHz / No. of Time Quanta
Hence, No. of Time Quanta = 16
So, PSEG1 = PSEG2 = 3 Hence,
PROPSEG = 6
HENCE, TS1 = 11, TS2 = 4
CAN_A.CR.R = 0x04DB0006;

Programming:
Step 3: (Optional)
To In activate all Message
Buffer
Hence,
for (i=0; i<64; i++) {

CAN_A.BUF[i].CS.B.CODE = 0;
}
Step 4:
To In activate TX for Message Buffer 0
Hence,
CAN_A.BUF[0].CS.B.CODE = 8;

Programming:
Step 5:
Configure Pad
CANTXA – Open Drain – Pin 83
CANRXA – Pin 84
Hence,
SIU.PCR[83].R = 0x0620;
SIU.PCR[84].R = 0x0500;
Step 6: (In Transmitting Side)
Select Standard / Extended ID
Standard – 0
Extended – 1
Hence, CAN_A.BUF[0].CS.B.IDE = 0;

Programming:
Step 7:
Transmit ID
ID = 555
Step 8:
Set RTR as Data Frame
Remote Frame = 1 Hence,
CAN_A.BUF[0].CS.B.RTR = 0;
Data Frame = 0
Step 9:
Specify the Length of the Tx’ng Data
For example, If const uint8_t TxData[] = {"Hello"};
Hence,
CAN_A.BUF[0].CS.B.LENGTH = sizeof(TxData) – 1 ;

Programming:
Step 10:
Transmit Data
for (i=0; i<sizeof(TxData); i++) {

CAN_A.BUF[0].DATA.B[i] = TxData[i];
}
Step 11: ( Optional for std ID)
Set a method for arbitration loss.
In Tx SRR = 1, In Rx SRR = 0 (indicates Arbitration Loss)
Hence,
CAN_A.BUF[0].CS.B.SRR = 1;
Step 12:
Activate Message Buffer.
Hence,
CAN_A.BUF[0].CS.B.CODE = 0xC;

Programming:
Step 13:
Transmit Data

}
Step 14: ( Optional for std ID)
Set a method for arbitration loss.
In Tx SRR = 1, In Rx SRR = 0 (indicates Arbitration Loss)
Hence,
Step 15:
Activate Message Buffer.
Hence,
CAN_A.BUF[0].CS.B.CODE = 0xC;

Transmitting Side
Initialization
SIU.PCR[83].R = 0x0620;
SIU.PCR[84].R = 0x0500;
Transmitting
const uint8_t TxData[] = {"Hello"};
CAN_A.BUF[0].CS.B.IDE = 0;
CAN_A.BUF[0].ID.B.STD_ID = 555;
CAN_A.BUF[0].CS.B.RTR = 0;
CAN_A.BUF[0].CS.B.LENGTH = sizeof(TxData) -1 ;
}
CAN_A.BUF[0].CS.B.CODE =0xC;

Receiving Side
Initialization
CAN_A.BUF[0].CS.B.IDE = 0;
CAN_A.BUF[0].ID.B.STD_ID = 555;
CAN_C.RXGMASK.R = 0x1FFFFFFF;
SIU.PCR[83].R = 0x0620;
SIU.PCR[84].R = 0x0500;
Receiving
while (CAN_A.IFRL.B.BUF00I == 0) {};
RxCODE = CAN_A.BUF[0].CS.B.CODE;
RxID = CAN_A.BUF[0].ID.B.STD_ID;
RxLENGTH = CAN_A.BUF[0].CS.B.LENGTH;
for (j=0; j<RxLENGTH; j++) {
RxDATA[j] = CAN_A.BUF[0].DATA.B[j];
}
CAN_A.IFRL.B.BUF00I = 1;

Arbitration
The arbitration process is triggered in the following events:
• During the CRC field of the CAN frame
• During the error delimiter field of the CAN frame
• During Intermission.
• When MBM is in idle or bus off state and the CPU writes to the C/S word of any
MB
• Upon leaving freeze mode
All MBs programmed as transmit buffers will be scanned to find the lowest ID1 or the
lowest MB number, depending on the LBUF bit in the CANx_CR.


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- Motorola Power Controller

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

¾ Master and Slave Concept

¾ High Data Rate.

¾ Cost Effective (No Driver Support).

SPI is a synchronous serial protocol proposed by Motorola to be used as

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

¾ A master is responsible for generating the SCK signal to synchronize the

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

 Deserial Serial Peripheral Interface provides a synchronous serial communication

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

The SPI signals on the MPC55xx family are as follows:

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

• Buffered transmit and receive operation using the TX and RX FIFO

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

DSPI POP RX FIFO REGISTER (DSPIx_POPR)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Two methods of communication is possible

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

SIN - Pin 108

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Core with MCU with

For 1 MHz MFD = 00000 = 0

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

When DBR = 0 Normal SCK with 50/50

Pin 107 – PCSB[2]_SOUTC_GPIO[107]

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

CONT = 0 Slave select

EOQ = 1 Indicates Last data

PCS0 = 1 Peripheral Chip Select

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Poll RFDF still become 1

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

NODE-A NODE-B NODE-C

NODE-D NODE-E NODE-F

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TYRE PRESSURE SENSOR

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

FUEL LEVEL SENSOR

Deserial Serial Peripheral Interface provides a synchronous serial communication