A B C D E

1 1

LCFC Confidential
APL G 320 M/B DG424/DG524 Schematics Document
Intel Apollolake M-Processor with DDRIIIL + NV(AMD LV2-R17M-M1-70) GPU
2 2

2017-02-28
REV:1.0

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 1 of 58
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 A B C D E

LCFC confidential
File Name : Cairo 4D&5D
AMD LV2-R17M-M1-70
Board Number : NM-B301
PN : DA600013C00 AMD: Level2 Memory BUS (DDR3L) DDR3L-SO-DIMM
Package: S3 Page 17
PCI-Express Single Channel
Page 19~24 PCIe Port 1~4
4x Gen3 UP TO 8G USB 3.0 Conn
1.35V DDR3L 1600 MT/s
1
VRAM: 512/256*16 (platform support up to 1866MT/s)
1

GDDR5*4: 4GB/2GB USB 3.0 Port1

Page 25~29
USB 3.0 1x Page 31
USB 2.0 Port0
USB 2.0 1x
HDMI
HDMI Conn. USB 2.0 Conn
Page 34 USB 2.0 1x
eDP Conn
USB 2.0 Port3 Page 31
Int. Camera
USB 2.0 Port6
Apollolake-M
eDP x2 Lane USB3.0 x1 USB3.0 Redriver Type-C IC
USB2.0 x1 Parade PS8713 Realtek RTS5449 Type-C Conn
Int. MIC Conn. BGA-1296 Page 29 Page 29

Page 28 31mm*24mm

TDP 6W
USB 2.0 1x Touch Screen
SATA Gen3 Page 28
SATA HDD Reserve
Page 42 SATA Port0
USB2.0 1x
2 2

SATA ODD SATA Gen1 NGFF Card

Page 42 SATA Port1 PCIe 1x WLAN&BT
PCIe Port5
Page 39 USB 2.0 Port7

LAN Realtek USB 2.0 1x Int. Camera

RJ45 Conn. PCIe 1x
Page 37
RTL8111GUL Page 28 USB 2.0 Port4
Page 36 PCIe Port4

HD Audio
SD/MMC Conn.
Page 35
FSPI BUS EC SPI ROM
Codec & C/R SPI Port 8MB
Page 8
USB2.0 x1
SPK Conn.
Page 34
HD Audio Page 4~16
Realtek RTS5119
LPC BUS
HP&Mic Combo Conn.
Page 34
I2C
Page 34 USB2.0 Port5
3 3
EC TPM
ITE IT8986E/BX-LQFP Z32H320TC
Page 44 Page 38 Reserve

Touch Pad Thermal Sensor

Page 45 Int.KBD NCT7718W
Page 45 Page 38 Reserve

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 2 of 58
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 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

PCIE PORT LIST
SIGNAL
STATE SLP_S0# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS/VTT Clock Port Device BIOS Device ID Map CLK REQ
+5VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON 0
+3VS
+3VALW_SOC +1.8VS S0IX(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON OFF 1 dGPU PCIe1(Func0):Root Port#3 CLKREQ0
V20B+ +3VALW +1.24VALW +1.35V +1.05VS 2
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 3
+1.8VALW VTT
+3VL +5VALW 4 LAN PCIe0(Func0):Root Port#1 CLKREQ1
+CPU_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
State +5VL 5 WLAN PCIe0(Func1):Root Port#2 CLKREQ2
1 +VNN 1
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
BOM Structure Table
USB Port Table BOM Structure BTO Item
S0 O O O O O XHCI Port Port device EMC@ For EMC part
EMC_NS@ For EMC un-stuff part
S3 O O O O X 0 Type C EMC_15@ EMC 15" part
USB 3.0
EMC_14@ EMC 14" part
1 USB3.0
S5 S4/AC Only EMC_USB@ EMC USB TVS part
O O O X X 0 Type C( USB 2.0) CD@ Cost Down part

S5 S4 1 USB3.0 (2.0)
O X X X X RF@ For RF part
Battery only 2 Touch Screen RF_NS@ For RF un-stuff part
S5 S4 RF_PXNS@ For RF GPU un-stuff part
3 USB2.0
AC & Battery X X X X X USB 2.0
4 Finger Print 14@ For 14" part
don't exist
5 15@ For 15" part
CARD READER
6 CAMERA 8111GUL@ 8111GUL LAN SKU part@
2 2
7 8111H@ 8111H LAN SKU part@
BT
SMBUS Control Table
PX@ Discrete GPU SKU part
SOURCE VGA BATT IT8986HE SODIMM
WLAN
WiMAX
Thermal
Sensor
PCH TP
Module Charger PMIC DDI PORT LIST TOPAZ@ TOPAZ dGPU SKU part
EXO@ R16M-M1-30 dGPU SKU part
Port Device UMA@ UMA SKU ID part
EC_SMB_CK0 EC DDI0 NC
EC_SMB_DA0 +3VL X X V X X X X X X V DDI1 HDMI TMSEN@ Thermal Sensor part
eDP eDP TMSEN_PX@ dGPU Thermal Sensor part
EC_SMB_CK1 EC TMSEN_UMA@ UMA Thermal Sensor part
X V V X X X X X V X
EC_SMB_DA1 +3VL +3VL
TPM@ TPM part
EC_SMB_CK2 EC NUVOTON@ NOVOTON TPM part
V V X X X X X X
EC_SMB_DA2 +3VS +3VGS X +3VS V NATIONZ@ NATIONZ TPM part

PCH_SMB_CLK PCH TS@ Touch Screen part

PCH_SMB_DATA +3VALW_SOC X X X V V X V X X X
+3VS +3VS +3VALW_PCH FP@ Finger Print part
KBL@ KB Backlight part
3 3
UART@ UART debug part
EC SM Bus0 address EC SM Bus1 address EC SM Bus2 address PCH SM Bus address RTCRST@ Clear RTCRST# function part
Device Address Device Address Device Address Device Address
PMIC 0x68 Smart Battery 0x16 Thermal Sensor 0x98(reserve) DDR SO-DIMM 0xA0 ME@ ME part
Charger 0x12 Wlan Rsvd @ un-stuff part
HDMI@ HDMI Logo part

I2C4 Bus address (Touch Pad) N3350_B0@ Apollolake N3350 B0 stepping QS CPU part
N3450_B0@ Apollolake N3450 B0 stepping QS CPU part
Device Address N4200_B0@ Apollolake N4200 B0 stepping QS CPU part
Slave 0x15 N3350_B1@ Apollolake N3350 B1 stepping MP CPU part
Descriptor 0x0001 N3450_B1@ Apollolake N3450 B1 stepping MP CPU part
N4200_B1@ Apollolake N4200 B1 stepping MP CPU part
M2GX4@ Micron 2GB(256x16x4) VRAM X76 SKU
S2GX4@ Samsung 2GB(256x16x4) VRAM X76 SKU
H2GX4@ Hynix 2GB(256x16x4) VRAM X76 SKU
M2G@ Micron 2GB VRAM
S2G@ Samsung 2GB VRAM
4
H2G@ Hynix 2GB VRAM 4

PCB@ PCB part

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 3 of 58
A B C D E
 5 4 3 2 1

DDRA_DQ[63:0] 17

DDRA_MA[15:0] 17

DDRA_DQS[7:0] 17

DDRA_DQS#[7:0] 17

UC1A APL_SOC UC1B APL_SOC

DDRA_DQ0 AY62 AR39 DDRA_DQ32 DDRA_DQS0 BB63 AR35 DDRA_CAVREF

DDRA_DQ1 AY61 MEM_CH0_DQ0 MEM_CH0_DQ32 AV37 DDRA_DQ33 DDRA_DQS#0 BC62 MEM_CH0_DQSP0 MEM_CH0_VREFCA AT34 DDRA_DQVREF
DDRA_DQ2 BE62 MEM_CH0_DQ1 MEM_CH0_DQ33 AW37 DDRA_DQ34 MEM_CH0_DQSN0 MEM_CH0_VREFDQ
D DDRA_DQ3 MEM_CH0_DQ2 MEM_CH0_DQ34 DDRA_DQ35 DDRA_DQS1 DDRA_BA0# D

Group 0
BG62 AR37 AT59 BJ48

Group 4
DDRA_DQ4 MEM_CH0_DQ3 MEM_CH0_DQ35 DDRA_DQ36 DDRA_DQS#1 MEM_CH0_DQSP1 MEM_CH0_BA0 DDRA_BA1# DDRA_BA0# 17
BD63 AT37 AT58 BG49 DDRA_BA1# 17
DDRA_DQ5 AW62 MEM_CH0_DQ4 MEM_CH0_DQ36 AT41 DDRA_DQ37 MEM_CH0_DQSN1 MEM_CH0_BA1 BH57 DDRA_BA2#
DDRA_DQ6 MEM_CH0_DQ5 MEM_CH0_DQ37 DDRA_DQ38 DDRA_DQS2 MEM_CH0_BA2 DDRA_BA2# 17
AW63 AR41 BB59
DDRA_DQ7 BD62 MEM_CH0_DQ6 MEM_CH0_DQ38 AW35 DDRA_DQ39 DDRA_DQS#2 BB58 MEM_CH0_DQSP2 AW43 DDRA_ODT0
MEM_CH0_DQ7 MEM_CH0_DQ39 MEM_CH0_DQSN2 MEM_CH0_ODT0 DDRA_ODT1 DDRA_ODT0 17
AW41 DDRA_ODT1 17
DDRA_DQ8 AV59 BJ44 DDRA_DQ40 DDRA_DQS3 BD52 MEM_CH0_ODT1
DDRA_DQ9 AU63 MEM_CH0_DQ8 MEM_CH0_DQ40 BG39 DDRA_DQ41 DDRA_DQS#3 BB52 MEM_CH0_DQSP3 BH47 DDRA_CAS#
DDRA_DQ10 MEM_CH0_DQ9 MEM_CH0_DQ41 DDRA_DQ42 MEM_CH0_DQSN3 MEM_CH0_CAS_N DDRA_WE# DDRA_CAS# 17
AU62 BG40 BG48 DDRA_WE# 17
DDRA_DQ11 MEM_CH0_DQ10 MEM_CH0_DQ42 DDRA_DQ43 DDRA_DQS4 MEM_CH0_WE_N DDRA_RAS#

Group 1
AV58 BJ40 AV39 BG47

Group 5
DDRA_DQ12 MEM_CH0_DQ11 MEM_CH0_DQ43 DDRA_DQ44 DDRA_DQS#4 MEM_CH0_DQSP4 MEM_CH0_RAS_N DDRA_RAS# 17
AV57 BG43 AW39
DDRA_DQ13 AT55 MEM_CH0_DQ12 MEM_CH0_DQ44 BG44 DDRA_DQ45 MEM_CH0_DQSN4 AT43
DDRA_DQ14 AT54 MEM_CH0_DQ13 MEM_CH0_DQ45 BH45 DDRA_DQ46 DDRA_DQS5 BJ42 NCTF1 BB41
DDRA_DQ15 AY59 MEM_CH0_DQ14 MEM_CH0_DQ46 BH41 DDRA_DQ47 DDRA_DQS#5 BG42 MEM_CH0_DQSP5 NCTF2
MEM_CH0_DQ15 MEM_CH0_DQ47 MEM_CH0_DQSN5 BA41 DDRA_CS1#
DDRA_DQ16 DDRA_DQ48 DDRA_DQS6 MEM_CH0_CS1_N DDRA_CS0# DDRA_CS1# 17
AY57 BA34 BB35 AR43 DDRA_CS0# 17
DDRA_DQ17 BB57 MEM_CH0_DQ16 MEM_CH0_DQ48 BE34 DDRA_DQ49 DDRA_DQS#6 BD35 MEM_CH0_DQSP6 MEM_CH0_CS0_N
DDRA_DQ18 BD59 MEM_CH0_DQ17 MEM_CH0_DQ49 BD34 DDRA_DQ50 MEM_CH0_DQSN6 BB48 DDRA_CLK1
DDRA_DQ19 MEM_CH0_DQ18 MEM_CH0_DQ50 DDRA_DQ51 DDRA_DQS7 MEM_CH0_CLKP1 DDRA_CLK1# DDRA_CLK1 17
Group 2
BF59 BD37 BG36 BD48

Group 6
DDRA_DQ20 MEM_CH0_DQ19 MEM_CH0_DQ51 DDRA_DQ52 DDRA_DQS#7 MEM_CH0_DQSP7 MEM_CH0_CLKN1 DDRA_CLK1# 17
AV54 BB37 BH35
DDRA_DQ21 AY55 MEM_CH0_DQ20 MEM_CH0_DQ52 BE39 DDRA_DQ53 MEM_CH0_DQSN7 BD45 DDRA_CLK0
DDRA_DQ22 MEM_CH0_DQ21 MEM_CH0_DQ53 DDRA_DQ54 MEM_CH0_CLKP0 DDRA_CLK0# DDRA_CLK0 17
AV52 BD39 BE45 DDRA_CLK0# 17
DDRA_DQ23 BD58 MEM_CH0_DQ22 MEM_CH0_DQ54 BB34 DDRA_DQ55 DDRA_MA0 BG50 MEM_CH0_CLKN0
MEM_CH0_DQ23 MEM_CH0_DQ55 DDRA_MA1 BG51 MEM_CH0_MA0 BH61 DDRA_CKE0
DDRA_DQ24 DDRA_DQ56 DDRA_MA2 MEM_CH0_MA1 MEM_CH0_CKE0 DDRA_CKE1 DDRA_CKE0 17
BE56 BJ38 BH51 BH60 DDRA_CKE1 17
DDRA_DQ25 BD54 MEM_CH0_DQ24 MEM_CH0_DQ56 BG34 DDRA_DQ57 DDRA_MA3 BD41 MEM_CH0_MA2 MEM_CH0_CKE1
DDRA_DQ26 BF58 MEM_CH0_DQ25 MEM_CH0_DQ57 BG33 DDRA_DQ58 DDRA_MA4 BE41 MEM_CH0_MA3 BH58
DDRA_DQ27 MEM_CH0_DQ26 MEM_CH0_DQ58 DDRA_DQ59 DDRA_MA5 MEM_CH0_MA4 NCTF3
Group 3

BE50 BH33 BJ52 BJ58

Group 7

DDRA_DQ29 BB50 MEM_CH0_DQ27 MEM_CH0_DQ59 BG38 DDRA_DQ60 DDRA_MA6 BG53 MEM_CH0_MA5 NCTF4
DDRA_DQ28 BD50 MEM_CH0_DQ29 MEM_CH0_DQ60 BH37 DDRA_DQ61 DDRA_MA7 BG55 MEM_CH0_MA6 AR30 DDRB_DRAMRST# 1 TP53 @
DDRA_DQ30 BA50 MEM_CH0_DQ28 MEM_CH0_DQ61 BG37 DDRA_DQ62 DDRA_MA8 BH53 MEM_CH0_MA7 MEM_CH1_RESET_N AR34 DDRA_DRAMRST#
DDRA_DQ31 BB54 MEM_CH0_DQ30 MEM_CH0_DQ62 BJ34 DDRA_DQ63 DDRA_MA9 BG52 MEM_CH0_MA8 MEM_CH0_RESET_N
MEM_CH0_DQ31 MEM_CH0_DQ63 DDRA_MA10 BH49 MEM_CH0_MA9 BD47
DDRA_MA11 BH55 MEM_CH0_MA10 MEM_CH0_DQSP8 BB47
1 OF 23 DDRA_MA12 BG54 MEM_CH0_MA11 MEM_CH0_DQSN8
APOLLOLAKE_FCBGA1296 DDRA_MA13 BG46 MEM_CH0_MA12 BA45
REV = 0.7 DDRA_MA14 BG56 MEM_CH0_MA13 MEM_CH0_CB7 BD43
DDRA_MA15 BG57 MEM_CH0_MA14 MEM_CH0_CB6 AV47
C @ C
MEM_CH0_MA15 MEM_CH0_CB5 AV48
MEM_CH0_CB4 AW45
MEM_CH0_CB3 BB43
MEM_CH0_CB2 AW47
MEM_CH0_CB1 AW48
MEM_CH0_CB0

2 OF 23
APOLLOLAKE_FCBGA1296
REV = 0.7
@

Follow CRB(v1.2): unstuff RC289, CC160, RC290, RC292, CC161, RC291 03/12 Follow CRB(PDG w/o 1k damping resister)
Double confirm with Intel FAE, follow CRB will have low risk
DDRA_CAVREF RC9321 1 @ 2 0_0402_5% DDRA_CAVREF_R RC289 1 @ 2 0_0402_5% DDR_CA 17

1
CC160
0.022U_0201_6.3V6-K +1.35V
2 @
1

1
RC290
24.9_0402_1% RC268
@ 1K_0402_1%
2

2
DDRA_DQVREF RC9320 1 @ 2 0_0402_5% DDRA_DQVREF_R RC292 1 @ 2 0_0402_5% DDR_DQ 17 DDRA_DRAMRST# DDRA_DRAMRST#_R
RC270 1 2 1K_0402_1% DDRA_DRAMRST#_R 17
1
B B
CC161
0.022U_0201_6.3V6-K
2 @
1

RC291
24.9_0402_1%
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2014/01/21 SOC (DDR3L CHA)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 4 of 58
5 4 3 2 1
 5 4 3 2 1

UC1C APL_SOC UC1D APL_SOC

D D
BJ26 BF6 BG28 AT30
BG30 MEM_CH1_DQ0 MEM_CH1_DQ32 BD10 BH29 MEM_CH1_DQSP0 MEM_CH1_VREFDQ AR29
BH31 MEM_CH1_DQ1 MEM_CH1_DQ33 BE14 MEM_CH1_DQSN0 MEM_CH1_VREFCA
BG31 MEM_CH1_DQ2 MEM_CH1_DQ34 BB10 BD29 BH6

Group 0

Group 4
BH27 MEM_CH1_DQ3 MEM_CH1_DQ35 BA14 BB29 MEM_CH1_DQSP1 MEM_CH1_BA0 BG8
BG27 MEM_CH1_DQ4 MEM_CH1_DQ36 BB14 MEM_CH1_DQSN1 MEM_CH1_BA1 BH15
BG26 MEM_CH1_DQ5 MEM_CH1_DQ37 BD14 BJ22 MEM_CH1_BA2
BJ30 MEM_CH1_DQ6 MEM_CH1_DQ38 BE8 BG22 MEM_CH1_DQSP2 BJ6
MEM_CH1_DQ7 MEM_CH1_DQ39 MEM_CH1_DQSN2 MEM_CH1_RAS_N BH4
BA30 AV12 AV25 MEM_CH1_CAS_N BH7
BB30 MEM_CH1_DQ8 MEM_CH1_DQ40 BD6 AW25 MEM_CH1_DQSP3 MEM_CH1_WE_N
BE30 MEM_CH1_DQ9 MEM_CH1_DQ41 BD5 MEM_CH1_DQSN3 AW16
BD30 MEM_CH1_DQ10 MEM_CH1_DQ42 BB7 BB12 MEM_CH1_ODT0 AV16

Group 1

Group 5
BE25 MEM_CH1_DQ11 MEM_CH1_DQ43 AV10 BD12 MEM_CH1_DQSP4 MEM_CH1_ODT1
BB27 MEM_CH1_DQ12 MEM_CH1_DQ44 AY9 MEM_CH1_DQSN4 BB21
BD25 MEM_CH1_DQ13 MEM_CH1_DQ45 AY7 BB5 MEM_CH1_CLKP1 BD21
BD27 MEM_CH1_DQ14 MEM_CH1_DQ46 BF5 BB6 MEM_CH1_DQSP5 MEM_CH1_CLKN1
MEM_CH1_DQ15 MEM_CH1_DQ47 MEM_CH1_DQSN5 BD19
BG24 AU2 AT5 MEM_CH1_CLKP0 BE19
BJ20 MEM_CH1_DQ16 MEM_CH1_DQ48 AT10 AT6 MEM_CH1_DQSP6 MEM_CH1_CLKN0
BH23 MEM_CH1_DQ17 MEM_CH1_DQ49 AT9 MEM_CH1_DQSN6 BG18
BJ24 MEM_CH1_DQ18 MEM_CH1_DQ50 AU1 BC2 MEM_CH1_CKE0 BG17
Group 2

BG20 MEM_CH1_DQ19 Group 6 MEM_CH1_DQ51 AY5 BB1 MEM_CH1_DQSP7 MEM_CH1_CKE1

BG21 MEM_CH1_DQ20 MEM_CH1_DQ52 AV5 MEM_CH1_DQSN7 BH17
BH19 MEM_CH1_DQ21 MEM_CH1_DQ53 AV6 NCTF5 BJ16
BG25 MEM_CH1_DQ22 MEM_CH1_DQ54 AV7 BG9 NCTF6
MEM_CH1_DQ23 MEM_CH1_DQ55 BG10 MEM_CH1_MA0 BD17
AT27 AY2 BH9 MEM_CH1_MA1 MEM_CH1_CS0_N AW17
AW29 MEM_CH1_DQ24 MEM_CH1_DQ56 BD2 BD16 MEM_CH1_MA2 MEM_CH1_CS1_N
AR27 MEM_CH1_DQ25 MEM_CH1_DQ57 BD1 BB16 MEM_CH1_MA3 AV17
AT23 MEM_CH1_DQ26 MEM_CH1_DQ58 BE2 BG11 MEM_CH1_MA4 NCTF7 BB17
Group 3

Group 7

AV27 MEM_CH1_DQ27 MEM_CH1_DQ59 AW1 BJ12 MEM_CH1_MA5 NCTF8

AR25 MEM_CH1_DQ28 MEM_CH1_DQ60 AW2 BG14 MEM_CH1_MA6 BE23
AR23 MEM_CH1_DQ29 MEM_CH1_DQ61 AY3 BG12 MEM_CH1_MA7 MEM_CH1_DQSN8 BD23
AW27 MEM_CH1_DQ30 MEM_CH1_DQ62 BG2 BH11 MEM_CH1_MA8 MEM_CH1_DQSP8
MEM_CH1_DQ31 MEM_CH1_DQ63 BG7 MEM_CH1_MA9 BB23
BH13 MEM_CH1_MA10 MEM_CH1_CB7 BA23
C C
3 OF 23 BG13 MEM_CH1_MA11 MEM_CH1_CB6 AW19
APOLLOLAKE_FCBGA1296 BH3 MEM_CH1_MA12 MEM_CH1_CB5 BA19
REV = 0.7 BG15 MEM_CH1_MA13 MEM_CH1_CB4 AW21
BG16 MEM_CH1_MA14 MEM_CH1_CB3 AW23
@ MEM_CH1_MA15 MEM_CH1_CB2 AT21
MEM_CH1_CB1 AR21
MEM_CH1_CB0

4 OF 23
APOLLOLAKE_FCBGA1296
REV = 0.7
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2014/01/21 SOC (DDR3L CHB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 5 of 58
5 4 3 2 1
 5 4 3 2 1

1 DDI0_RCOMP_P

RC1 eDP RCOMP is used for DDI0/DDI1 ports of HDMI/DP UC1E APL_SOC
@ 402_0402_1% as well as the eDP interface. DDI0_RCOMP is not used
B49 AK3
2

DDI0_RCOMP_N C49 DDI0_DDC_SCL DDI0_TXP_0 AK2 +1.8V_PU

DDI0_DDC_SDA DDI0_TXN_0
DDPB_CLK A54 AM3
EDP_RCOMP_P 32 DDPB_CLK DDPB_DATA DDI1_DDC_SCL DDI0_TXP_1 EDP_HPD#
C54 AM2 RC9359 1 2 100K_0402_5%
32 DDPB_DATA DDI1_DDC_SDA DDI0_TXN_1
1

AH3
RC2 CPU_EDP_AUX AH10 DDI0_TXP_2 AH2
28 CPU_EDP_AUX EDP_AUXP DDI0_TXN_2
402_0402_1% CPU_EDP_AUX# AH9
28 CPU_EDP_AUX# EDP_AUXN AL2
D EDP_RCOMP_N AG5 DDI0_TXP_3 AL1 D
EDP_HPD
2

EDP_RCOMP_N EDP_RCOMP_P AG6 EDP_RCOMP_N DDI0_TXN_3

EDP_RCOMP_P AG1 DDI0_RCOMP_P EDP_HPD#
CPU_EDP_TX0+ DDI0_RCOMP_P DDI0_RCOMP_N EDP_HPD# 10
AG7 AG2
28 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TXP_0 DDI0_RCOMP_N
AG9
28 CPU_EDP_TX0- EDP_TXN_0
eDP AM16
+1.8V_PU CPU_EDP_TX1+ AG12 DDI0_AUXP AM15
28 CPU_EDP_TX1+ CPU_EDP_TX1- EDP_TXP_1 DDI0_AUXN
28 CPU_EDP_TX1- AG10
EDP_TXN_1
RPC22

3
AC6 AK16 D QC1B D
3 2 DDPB_CLK AC5 EDP_TXP_2 DDI1_AUXP AK15 2 5
4 1 DDPB_DATA EDP_TXN_2 DDI1_AUXN G CPU_EDP_HPD 28 G
AC7 AF2 HDMI_TX2+ L2N7002KDW1T1G_SOT363-6
EDP_TXP_3 DDI1_TXP_0 HDMI_TX2+ 32
AC9 AF3 HDMI_TX2-
HDMI_TX2- 32 HDMI D2 S L2N7002KDW1T1G_SOT363-6 S

4
10K_0404_4P2R_5% EDP_TXN_3 DDI1_TXN_0

1
QC1A RC3
AD3 HDMI_TX1+
DDI1_TXP_1 HDMI_TX1+ 32
AD2 HDMI_TX1-
HDMI_TX1- 32 HDMI D1 100K_0402_5%
DDI1_TXN_1
DDI PORT LIST AC1 HDMI_TX0+
HDMI_TX0+ 32

2
DDI1_TXP_2 HDMI_TX0-
DDI1_TXN_2
AC2 HDMI_TX0- 32 HDMI D0
Port Device HPD Net HPD Pin AB2 HDMI_CLK-
DDI1_TXN_3 HDMI_CLK+ HDMI_CLK- 32
AB3 HDMI_CLK+ 32 HDMI CLK
DDI0 DP TO VGA VGA_HPD# C50 DDI1_TXP_3
EDP_HPD# RC9388 1 @ 2 0_0402_5% CPU_EDP_HPD
DDI1 HDMI HDMI_HPD# A50 5 OF 23
APOLLOLAKE_FCBGA1296
EDP eDP EDP_HPD# P48 REV = 0.7
@

+3VS +3VS
+3VALW +3VALW
UC1F APL_SOC
C C

4
3

4
3
AP12 AK7
MDSI_A_DP_0 MDSI_C_DP_0 RPC3
AP10 AK6 RPC2
MDSI_A_DN_0 MDSI_C_DN_0 10K_0404_4P2R_5%
10K_0404_4P2R_5%
AR2 AM5
AR1 MDSI_A_DP_1 MDSI_C_DP_1 AM6 @

1
2

1
2
MDSI_A_DN_1 MDSI_C_DN_1 PCH_ENVDD
PCH_EDP_PWM 28
AP15 AM12
AP13 MDSI_A_DP_2 MDSI_C_DP_2 AM10
MDSI_A_DN_2 MDSI_C_DN_2

3
AP6 AK13
AP5 MDSI_A_DP_3 MDSI_C_DP_3 AM13

D2

D2
MDSI_A_DN_3 MDSI_C_DN_3 5 5
AP2 AM9 G2 G2
AP3 MDSI_A_CLKP MDSI_C_CLKP AM7

S2

S2
MDSI_A_CLKN MDSI_C_CLKN

6
QC2B QC3B

4
B51 C47 PCH_LCD_VDDEN_Q PJT138K_SOT363-6 @ PJT138K_SOT363-6

D1

D1
C51 MIPI_I2C_SDA PNL0_VDDEN B47 PCH_ENBKL PCH_BKLT_CTRL_Q 2 PCH_LCD_VDDEN_Q 2
MIPI_I2C_SCL PNL0_BKLTEN C46 PCH_BKLT_CTRL_Q G1 G1
PNL0_BKLTCTL

S1

S1
32 HDMI_HPD# A50 C52
C50 GPIO_199 PNL1_VDDEN B53 QC2A QC3A

1
GPIO_200 PNL1_BKLTEN C53 PJT138K_SOT363-6 @ PJT138K_SOT363-6 GPIO Name I/O Voltage Default Term Buffer Type
PNL1_BKLTCTL PNL0_VDDEN 1.8V 20K PD CMOS
M45 PNL0_BKLTEN 1.8V 20K PD CMOS
M43 MDSI_A_TE PNL0_BKLTCTL 1.8V 20K PD CMOS
MDSI_C_TE
PJT138K[Vgs(th)<1.5V] PJT138K[Vgs(th)<1.5V]
6 OF 23
APOLLOLAKE_FCBGA1296
REV = 0.7 PCH_LCD_VDDEN_Q RC83 1 @ 2 0_0402_5% PCH_ENVDD
PCH_ENVDD 28
@ PCH_LCD_VDDEN_Q VOH min is 1.35V,
SY6288C20 VIH min is 1.35V, do NOT use level shift
(Follow BMWC1)
B PCH_ENBKL B
PCH_ENBKL 28
PCH_ENBKL can direct connect to EC for costdown

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2014/01/21 SOC (DDI,EDP,HDMI,MDSI)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 6 of 58
5 4 3 2 1
 5 4 3 2 1

UC1H APL_SOC

T55 V57
T54 SDIO_D3 EMMC_D7 V55
P57 SDIO_D2 EMMC_D6 Y49
T52 SDIO_D1 EMMC_D5 V52
SDIO_D0 EMMC_D4 V51
T57 EMMC_D3 T59
P58 SDIO_CMD EMMC_D2 T58
P51 SDIO_CLK EMMC_D1 V58
D SDIO_PWR_DWN_N EMMC_D0 D
V54
AB58 EMMC_RCLK Y51
AB54 SDCARD_CLK EMMC_CMD Y58
AB55 SDCARD_CD_N EMMC_CLK
AC52 SDCARD_LVL_WP
SDCARD_CMD
AB51
AC51 SDCARD_D3
AC48 SDCARD_D2
AC49 SDCARD_D1
SDCARD_D0

8 OF 23
APOLLOLAKE_FCBGA1296
REV = 0.7
@

C C

UC1G APL_SOC

P17 M23
M17 MCSI_DP_0 MCSI_RX_DATA0_P P23
MCSI_DN_0 MCSI_RX_DATA0_N
P21 L23
R21 MCSI_DP_1 MCSI_RX_CLK0_P J23
MCSI_DN_1 MCSI_RX_CLK0_N
L17 J21
J17 MCSI_DP_2 MCSI_RX_DATA1_P H21
MCSI_DN_2 MCSI_RX_DATA1_N
F17 M25
E17 MCSI_DP_3 MCSI_RX_DATA2_P L25
MCSI_DN_3 MCSI_RX_DATA2_N

M19 F25
L19 MCSI_CLKP_0 MCSI_RX_CLK1_P E25
MCSI_CLKN_0 MCSI_RX_CLK1_N
H19 H25
F19 MCSI_CLKP_2 MCSI_RX_DATA3_P J25
MCSI_CLKN_2 MCSI_RX_DATA3_N

L37 R35
P34 GP_CAMERASB0 GP_CAMERASB6 L34
J34 GP_CAMERASB1 GP_CAMERASB7 M34
H30 GP_CAMERASB2 GP_CAMERASB8 M35
M37 GP_CAMERASB3 GP_CAMERASB9 R34
F30 GP_CAMERASB4 GP_CAMERASB10 E30
GP_CAMERASB5 GP_CAMERASB11
B B

7 OF 23
APOLLOLAKE_FCBGA1296
REV = 0.7
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2014/01/21 SOC (eMMC,SD,MCSI)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 7 of 58
5 4 3 2 1
 5 4 3 2 1

PCIE Configuration
Port Config Device BIOS Device ID Map
UC1I APL_SOC P0
P1
CC169 1 2 0.1U_0201_6.3V6-K PCIE_PTX_DRX_P5 L2 T2 PCIE_PTX_GRX_P2 CC173 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_GRX_P2 20 X4 dGPU PCIe1(Func0):Root Port#3
39 PCIE_PTX_C_DRX_P5
39 PCIE_PTX_C_DRX_N5 CC170 1 2 0.1U_0201_6.3V6-K PCIE_PTX_DRX_N5 L1 PCIE_P5_USB3_P2_TXP
PCIE_P5_USB3_P2_TXN
PCIE_P2_TXP
PCIE_P2_TXN
T3 PCIE_PTX_GRX_N2 CC174 1 2PX@
0.1U_0201_6.3V6-K
PCIE_PTX_C_GRX_N2 20
P2
WLAN PCIE_PRX_DTX_P5 K7 M5 PCIE_PRX_GTX_P2 PX@
P3
39 PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 PCIE_P5_USB3_P2_RXP PCIE_P2_RXP PCIE_PRX_GTX_N2 PCIE_PRX_GTX_P2 20
M7 M6
39 PCIE_PRX_DTX_N5 PCIE_P5_USB3_P2_RXN PCIE_P2_RXN PCIE_PRX_GTX_N2 20 P4 X1 LAN PCIe0(Func0):Root Port#1
36 PCIE_PTX_C_DRX_P4 CC171 1 2 0.1U_0201_6.3V6-K PCIE_PTX_DRX_P4
PCIE_PTX_DRX_N4
N2
PCIE_P4_USB3_P3_TXP PCIE_P1_TXP
R1 PCIE_PTX_GRX_P1
PCIE_PTX_GRX_N1
CC175 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_GRX_P1 20 P5 X1 WLAN PCIe0(Func1):Root Port#2
36 PCIE_PTX_C_DRX_N4 CC172 1 2 0.1U_0201_6.3V6-K M2 R2 CC176 1 2PX@
0.1U_0201_6.3V6-K
PCIE_P4_USB3_P3_TXN PCIE_P1_TXN PCIE_PTX_C_GRX_N1 20
LAN PCIE_PRX_DTX_P4 H5 T10 PCIE_PRX_GTX_P1
PX@
+1.8VALW
36 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 H6 PCIE_P4_USB3_P3_RXP PCIE_P1_RXP T12 PCIE_PRX_GTX_N1 PCIE_PRX_GTX_P1 20 dGPU
D
36 PCIE_PRX_DTX_N4 PCIE_P4_USB3_P3_RXN PCIE_P1_RXN PCIE_PRX_GTX_N1 20 D

PCIE_PTX_GRX_P3 PCIE_PTX_GRX_P0 RPC27

20 PCIE_PTX_C_GRX_P3 CC180 1 2 0.1U_0201_6.3V6-K P3 V3 CC177 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_GRX_P0 20
CC179 1 2PX@
0.1U_0201_6.3V6-K PCIE_PTX_GRX_N3 P2 PCIE_P3_USB3_P4_TXP PCIE_P0_TXP V2 PCIE_PTX_GRX_N0 CC178 1 2PX@
0.1U_0201_6.3V6-K PCIE_WAKE3# 5 4
20 PCIE_PTX_C_GRX_N3 PCIE_P3_USB3_P4_TXN PCIE_P0_TXN PCIE_PTX_C_GRX_N0 20 PCIE_WAKE2#
PX@ PX@ 6 3
PCIE_PRX_GTX_P3 P12 P7 PCIE_PRX_GTX_P0 PCIE_WAKE1# 7 2
20 PCIE_PRX_GTX_P3 PCIE_PRX_GTX_N3 PCIE_P3_USB3_P4_RXP PCIE_P0_RXP PCIE_PRX_GTX_N0 PCIE_PRX_GTX_P0 20 PCIE_WAKE0#
P10 P6 8 1
dGPU 20 PCIE_PRX_GTX_N3 PCIE_P3_USB3_P4_RXN PCIE_P0_RXN PCIE_PRX_GTX_N0 20
10K_0804_8P4R_5%
PCIE_RCOMP_DP F6 N62 PCIE_WAKE3#
PCIE2_USB3_SATA3_RCOMP_P PCIE_WAKE3_N
PCIE_RCOMP_DN F5 P61 PCIE_WAKE2#
PCIE_RCOMP_DP PCIE2_USB3_SATA3_RCOMP_N PCIE_WAKE2_N
P62 PCIE_WAKE1#
2

PCIE_WAKE1_N
RC11 R62 PCIE_WAKE0#
PCIE_WAKE0_N
402_0402_1%

9 OF 23 SPI ROM PCH_SPI_CLK_R RC9310 2 1 33_0402_5% PCH_SPI_CLK

1

PCIE_RCOMP_DN APOLLOLAKE_FCBGA1296 RC9380 1 @ 2 0_0402_5%

44 EC_SPI_CLK_R
REV = 0.7
Intel recommends to add a VSS shield at least 4Mmils PCH_SPI_CS0#_R RC9311 1 @ 2 0_0402_5% PCH_SPI_CS0#
@
wide to shield between PCIE2_USB3_SATA3_RCOMP_P /
44 EC_SPI_CS0#_R RC9381 1 @ 2 0_0402_5%
PCIE2_USB3_SATA3_RCOMP_N trace and adjacent I/O.
PCH_SPI_D0_R RC9312 1 @ 2 0_0402_5% PCH_SPI_D0

44 EC_SPI_D0_R RC9382 1 @ 2 0_0402_5%

UC1M APL_SOC
PCH_SPI_D1_R RC9313 1 @ 2 0_0402_5% PCH_SPI_D1

44 EC_SPI_D1_R RC9383 1 @ 2 0_0402_5%

PCH_SPI_D0_R A58 AP62 LPSS_I2C7_SDA 1
PCH_SPI_D1_R FST_SPI_MOSI_IO0 LPSS_I2C7_SDA LPSS_I2C7_SCL TP55 @
B58 AP61 1 Near place RC9310&RC9380; RC9311&RC9381; RC9312&RC9382; RC9313&RC9383
V1P8 SPI BUS PCH_SPI_D2_R B60 FST_SPI_MISO_IO1 LPSS_I2C7_SCL TP56 @
PCH_SPI_D3_R B61 FST_SPI_IO2 AL63 PCH_SPI_D2_R RC9314 1 @ 2 0_0402_5% PCH_SPI_D2
FST_SPI_IO3 LPSS_I2C6_SDA AK61
C57 LPSS_I2C6_SCL PCH_SPI_D3_R RC9315 1 @ 2 0_0402_5% PCH_SPI_D3
FST_SPI_CS1_N AP49
PCH_SPI_CS0#_R B57 LPSS_I2C5_SDA AP51
FST_SPI_CS0_N LPSS_I2C5_SCL Place RC9380, RC9381, RC9382, RC9383 near SPI ROM for minimum SPI Stub
PCH_SPI_CLK_R C56 AP52 TP_I2C_SDA4
FST_SPI_CLK LPSS_I2C4_SDA AP54 TP_I2C_SCL4
LPSS_I2C4_SCL
E62 AM62
Ball Name Signal Name I/O Voltage Default Term Buffer Type
16 GPIO_123 SIO_SPI_2_TXD LPSS_I2C3_SDA
C C62 AL62 C
D59 SIO_SPI_2_RXD LPSS_I2C3_SCL FST_SPI_CS0_B PCH_SPI_CS0# 1.8V 20K PU CMOS
16 GPIO_121 SIO_SPI_2_FS2
E56 AP59
16 GPIO_120
D61 SIO_SPI_2_FS1 LPSS_I2C2_SDA AP58 FST_SPI_MOSI_IO0 PCH_SPI_D0 1.8V 20K PD CMOS
16 SIO_SPI_2_FS0 SIO_SPI_2_FS0 LPSS_I2C2_SCL
F62 +1.8VALW
16 GPIO_118 SIO_SPI_2_CLK AN62 FST_SPI_MISO_IO1 PCH_SPI_D1 1.8V 20K PU CMOS
LPSS_I2C1_SDA AM61 RC14 1 @ 2 0_0402_5% +VCC_SPI
H58 LPSS_I2C1_SCL FST_SPI_IO2 PCH_SPI_D2 1.8V 20K PU CMOS
16 GPIO_117 SIO_SPI_1_TXD
H57 AR62
F61 SIO_SPI_1_RXD LPSS_I2C0_SDA AR63 FST_SPI_IO3 PCH_SPI_D3 1.8V 20K PU CMOS
16 GPIO_113 SIO_SPI_1_FS1 LPSS_I2C0_SCL
K55
16 GPIO_112
F58 SIO_SPI_1_FS0 +VCC_SPI FST_SPI_CLK PCH_SPI_CLK 1.8V 20K PD CMOS
16 GPIO_111 SIO_SPI_1_CLK
RC13 1 @ 2 100K_0402_5% PCH_SPI_CS0#
+VCC_SPI
16 GPIO_110 J52
H54 SIO_SPI_0_TXD RC9316 1 2 3.3K_0402_5% PCH_SPI_D2
H52 SIO_SPI_0_RXD RC9317 1 2 3.3K_0402_5% PCH_SPI_D3 UC2
16 GPIO_106 SIO_SPI_0_FS1 PCH_SPI_CS0# 50mA
16 GPIO_105 F52 1 8
F54 SIO_SPI_0_FS0 PCH_SPI_D1 2 /CS VCC 7 PCH_SPI_D3
16 GPIO_104 Follow CRB: set WP# and HOLD# PU
SIO_SPI_0_CLK PCH_SPI_D2 3 DO(IO1) /HOLDor/RESET(IO3) 6 PCH_SPI_CLK
/WP(IO2) CLK PCH_SPI_D0 1
4 5
13 OF 23 GND DI(IO0) CC181
APOLLOLAKE_FCBGA1296 W25Q64FWSSIQ_SO8 0.1U_0201_6.3V6-K
REV = 0.7 2
@ 1.8V SPI ROM

+3VS
+3VALW +3VS

0_0402_5% 2 @ 1 R9417 +1.8VS

+3VALW
+1.8VALW R9413 2 10_0402_5%

1
2
@

3
4
B 0_0402_5% 2 @ 1 R9416 RP17 B
+3VS
RP16 2.2K_0404_4P2R_5%

5
.1U_0402_10V6-K .1U_0402_10V6-K 2.2K_0404_4P2R_5%

4
3
1

2
1 2 C5008 1 2 C5009 Q167B
@

2
1
R4731 R4732
G1

1K_0402_5% 1K_0402_5% @ @
TP_I2C_SDA4 1 S1 D1 6 TP_I2C_SDA4_M @ 3 4 TP_I2C_SDA4_R

S
U32

D
2

1 8 L2N7002KDW1T1G_SOT363-6
VCCA VCCB
TP_I2C_SDA4 2 7 TP_I2C_SDA4_R Q166A 0_0402_5% 2 1 R9423
A1 B1 TP_I2C_SDA4_R 45 PJT138K_SOT363-6

2
TP_I2C_SCL4 3 6 TP_I2C_SCL4_R

G
A2 B2 TP_I2C_SCL4_R 45
G2 5

Q167A
4 5 R4735 2 @ 1
GND OE +1.8VALW
10K_0402_5%
TP_I2C_SCL4 4 S2 D2 3 TP_I2C_SCL4_M @ 6 1 TP_I2C_SCL4_R
10U_0603_6.3V6M
.1U_0402_10V6-K

S
D
@
TXS0102DQER_X2SON8_1X1P4 2 1 Follow BMWC1: PJT138K[Vgs(th)=1.5V] L2N7002KDW1T1G_SOT363-6
C5010 C5011 SCH CKL request MOSFET output capacitance less than 10pF
@ @ Q166B 0_0402_5% 2 1 R9424
1 2 PJT138K_SOT363-6

The I2C signals are open drain, and it has internal pull-up.
A 1 kΩ ± 5% for external pull-up resistor is recommended.
Reserve Touch Pad I2C LS(MOS and IC) Lewis 2016/10/21

+3VALW

+1.8VALW
2

A A
RC9370
10K_0402_5%
2
G

PCIE_WAKE1# 3 1 PCIE_WAKE# 36,39,44

S

QC12
PJQ1900_DFN3L Title
PJQ1900[Vgs(th)<1.0V], 01/15
Security Classification LC Future Center Secret Data
Issued Date 2013/03/26 Deciphered Date 2014/01/21 SOC (PCIE&GPIO&SPI)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
10 PMC_WAKE# RC9343 1 @ 2 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 8 of 58

5 4 3 2 1
 5 4 3 2 1

+1.8VALW
R9415 1 @ 2 10_0402_5% XDP_TRST#
UC1R APL_SOC UC1P APL_SOC

PCIE_REF_CLK_RCOMP
use 10ohm pull up to +1.8VALW for LTB BSSB enable
RC39 1 2 60.4_0402_1% E21 AM58 A18 H43
PMU_RCOMP
PCIE_REF_CLK_RCOMP NCTF39
NCTF40
AM59 lewis 2016/10/21 reserve C19 RSVD1
RSVD2
RSVD4
RSVD3
AG52
RC40 1 2 200_0402_1% AG59 AB49
PMU_RCOMP NCTF41 R25 1 XDP_TRST# C24 A60
USB_SSIC_RCOMP NCTF42 @ TP29 XDP_TMS JTAG_TRST_N NCTF9
RC41 1 2 137_0402_1% AB15 C13 @ TP28 1 C23
USB_SSIC_RCOMP NCTF43 B13 1 XDP_TDO A22 JTAG_TMS J43
Follow PDG; RC41 is 135 +/-0.5% in CRB
USB2_RCOMP NCTF44 @ TP27 XDP_TDI JTAG_TDO RSVD10
RC42 1 2 113_0402_1% Y15 AB13 @ TP26 1 C22 AG54
USB2_RCOMP NCTF45 AC13 1 XDP_TCLK B23 JTAG_TDI RSVD5
NCTF46 @ TP25 JTAG_TCK
RC43 1 2 150_0402_1% MCSI_DPHY1.1_RCOMP H27 P27 1 XDP_PREQ# C20 A61
MCSI_DPHY1.1_RCOMP NCTF47 @ TP31 XDP_PRDY# JTAG_PREQ_N NCTF10
1 C21 BJ2
GPIO_RCOMP SYS_PWROK_R @ TP30 JTAG_PRDY_N NCTF11
RC44 2 1 200_0402_1% E34 AG49 B19 BG1
D GPIO_RCOMP 3.3V SOC_PWROK JTAG_PMODE NCTF12 B15 D
MCSI_DPHY1.2_RCOMP GPIO_88 strap to LOW, SUSPWRDNACK set to 3.3V Mode
SUSPWRDNACK_R NCTF13
RC45 1 2 150_0402_1% F27 J29 SUSPWRDNACK RC9331 1 @ 2 0_0402_5% AC63 C15
MCSI_DPHY1.2_RCOMP NCTF48 SUSPWRDNACK 3.3V NCTF14 D8
RC46 2 1 200_0402_1% EMMC_RCOMP V59 B21 PCH_JTAGX 1 RTC_RST# AC55 NCTF15 E8
EMMC_RCOMP JTAGX TP54 @ 44 RTC_RST# RTC_TEST# RTC_RST_N 3.3V NCTF16
AH49 F8
MDSI_RCOMP 44 RTC_TEST# RTC_TEST_N 3.3V NCTF17
RC47 1 2 150_0402_1% AP7 A3 C9
MDSI_RCOMP NCTF49 P25 EC_RSMRST#_R AC57 NCTF18 E10
Spacing: 10mils; length: 1000mils NCTF50 C2 RSM_RST_N 3.3V NCTF19 H10
D2 NCTF51 M39 H_PROCHOT# E47 NCTF20 A14
NCTF38 NCTF52 P39 PROCHOT_N NCTF21 C14
NCTF53 R39 CC155 2 1 0.1u_0201_10V6K BVCCRTC_EXTPAD AG51 NCTF22
RC48 2 1 105_0402_1% M0_RCOMPPD AV30 NCTF54 R37 VCC_RTC_EXTPAD C1
MEM_CH1_RCOMP NCTF55 Follow CRB use 10V cap, need confirm if can use 6.3V RTC_X2 AC58 RSVD6 F1
RC49 2 1 105_0402_1% M1_RCOMPPD AV34 RTC_X1 AC59 RTC_X2 3.3V RSVD7 B4
MEM_CH0_RCOMP RTC_X1 3.3V RSVD8 A4
RTC_INTRUDER AC54 RSVD9
18 OF 23 INTRUDER 3.3V
APOLLOLAKE_FCBGA1296
REV = 0.7 16 OF 23
@ APOLLOLAKE_FCBGA1296
REV = 0.7

RCOMP RESISTOR REQUIREMENT @

INTERFACE PIN NAME LOCATION VALUE(ohm)

CSI1.1 MCSI_DPHY1.1_RCOMP RC43 150 +/-1%
CSI 1.2 (DPHY/CPHY) MCSI_DPHY1.2_RCOMP RC45 150 +/-1%
+1.8VALW
USB2 and 3.3V mode GPIO USB2_RCOMP RC42 113 +/-1%
PCIe Refclk PCIE_REF_CLK_RCOMP RC39 60.4 +/-1% 44 H_PROCHOT#
H_PROCHOT# RC55 1 2 1K_0402_5%
modPHY (PCIE, USB3, SATA) PCIE2_USB3_SATA3_RCOMP_P/N RC11 402 +/-1%
+1.8VALW
MDSI MDSI_RCOMP RC47 150 +/-1%
C C
SSIC USB_SSIC_RCOMP RC41 137 +/-1% 44 SUSPWRDNACK SUSPWRDNACK RC272 2 @ 1 20K_0402_5%
EMMC, Legacy and GPIO EMMC_RCOMP RC46 PDG v0.9 request SUSPWRDNACK PU to +1.8VALW(CRB w/o PU)--Remove this requirement in PDG v1.0;
signals including 1.8V mode GPIO_RCOMP RC44 200 +/-1%
SUSPWRDNACK is +3.3V Level set by GPIO_88(PD)
SD Card, PMU, LPC, SMBUS. PMU_RCOMP RC40 PDG&CRB request H_PROCHOT# 1Kohm PU to +1.8VALW
eDP EDP_RCOMP_P/N RC2 402 +/-1%
DDI DDI0_RCOMP_P/N RC1 402 +/-1%
MEM_CH0_RCOMP/ RC49 105 +/-1%
Memory MEM_CH1_RCOMP RC48

+1.8VALW

RTCRST#/SRTCRST#
VCCRTC

1
RTC_X1

RTC_X2

RC9350
RTC_TEST# RC59 1 2 20K_0402_1% 20K_0402_5%
RC56 1 2 10M_0402_5%
@

2
RTC_RST# RC58 1 2 20K_0402_1%

YC1 EC_RSMRST#_R RC9346 1 @ 2 0_0402_5%

1 2 EC_RSMRST# 44
1U_0402_6.3V6K

1U_0402_6.3V6K

Need change to 0201 size later 1 1

0.1U_0201_6.3V6-K
1
CC29

1 32.768KHZ_9PF_X1A0001410002 1 JCMOS1

100K_0402_5%
1
CC28

SHORT PADS 2
CC26 CC27 @

RC25
CC182
2

9P_0402_50V8-B 9P_0402_50V8-B 2 2
2 2
1

EMC@

2
B B

32.768kHz CRYSTAL--EPSON SJ10000IX00 JCMOS1 RTCRST# EMC request 03/09

1. Space 15MIL Place under Bottom Big Door Space 15Mil
2. No trace under crystal VCCRTC Follow Intel schematics check list to add PU for EC_RSMRST#(Reserve)
3. Place on oppsosit side of MCP for temp influence
4. EDS request X'TAL ESR=50Kohm; +/-20ppm; X1,X2 pin capacitance=15pF
RTC_INTRUDER RC50 1 2 100K_0402_5%
Follow CRB v1.5 to change RC50 from 330Kohm to 100K ohm 05/06
SYS_PWROK_R RC9345 1 @ 2 0_0402_5% SYS_PWROK 44

2
CC188
0.1U_0201_6.3V6-K
EMC@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 SOC (RTC&RCOMP&JTAG)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 9 of 58
5 4 3 2 1
 5 4 3 2 1

+3VALW_SOC UC1N APL_SOC

PMC_PLTRST# RC21 2 @ 1 10K_0402_5% R9327 1 @ 2 0_0402_5%

PMC_WAKE# AG55 EMMC_PWR_EN_N H41 SOC_UART_TXD 39
8 PMC_WAKE# PMC_SUSCLK PMU_WAKE_N 3.3V LPSS_UART2_TXD GPIO_47 16
AE62 J41 SOC_UART_RXD 39
PMC_RSTBTN# RC22 1 2 10K_0402_5% PMU_SUSCLK 3.3V LPSS_UART2_RXD L41
PM_SLP_S4#_R LPSS_UART2_RTS_N EC_SMI#_Q GPIO_48 16
AK54 M41
PM_SLP_S3#_R AC62 PMU_SLP_S4_N 3.3V LPSS_UART2_CTS_N
PMC_WAKE# RC9344 1 2 1K_0402_5% @ TP36 1 PMC_SLP_S0IX# AD61 PMU_SLP_S3_N 3.3V
PMU_SLP_S0_N 3.3V B43
PMC_RSTBTN# LPSS_UART1_TXD GPIO_43 16
AD62 C43
PMC_PLTRST# & PMC_RSTBTN# is 3.3V level set by GPIO_88(PD) PBTN_OUT#_R AK55 PMU_RSTBTN_N 3.3V LPSS_UART1_RXD A42
PMC_PLTRST# PMU_PWRBTN_N 3.3V LPSS_UART1_RTS_N GPIO_44 16
AG57 C42
RC27 1 2 20K_0402_1% PMC_BATLOW# AH51 PMU_PLTRST_N 3.3V LPSS_UART1_CTS_N
+3VALW_SOC PMC_ACIN PMU_BATLOW_N 3.3V
PMC_BATLOW# is 3.3V level set by GPIO_88(PD) AK49
RC93511 @ 2 0_0402_5% PMIC_THERMTRIP#_R J47 PMU_AC_PRESENT 3.3V B45
D 44 PMIC_THERMTRIP# PMIC_STDBY PMIC_THERMTRIP_N LPSS_UART0_TXD GPIO_39 16 D
@ TP38 1 J45 C45
+1.24VALW 1 GPIO_213 M47 PMIC_STDBY GPIO_224 LPSS_UART0_RXD A46
follow CRB reserve PU for PMIC_RESET# @ TP39
GPIO_213 LPSS_UART0_RTS_N GPIO_40 16
SKL_XCLK_BIASREF F48 C44
PMIC_RESET# is 1P8V voltage, need double check PMIC_RESET_N GPIO_223 LPSS_UART0_CTS_N
@ TP40 1 PMIC_PWRGOOD H48
SKL_XCLK_BIASREF RC9291 1 @ 2 2.71K_0402_0.5% R30 PMIC_PWRGOOD NCTF
1 SUS_STAT# AG58 NCTF65 H50
@ TP37 SUS_STAT_N 3.3V PMC_SPI_TXD J50
+1.8VALW 1 PMIC_I2C_SDA F47 PMC_SPI_RXD M48
@ TP45 PMIC_I2C_SDA PMC_SPI_FS2
@ TP46 1 PMIC_I2C_SCL H45 P48 EDP_HPD# 6
PMIC_THERMTRIP#_R RC9390 1 2 1K_0402_5% PMIC_I2C_SCL PMC_SPI_FS1 L48
1 GPIO_214 L47 PMC_SPI_FS0 E52
@ TP43
1 GPIO_215 P47 GPIO_214 PMC_SPI_CLK
@ TP44
PMC_PLTRST# RC9301 2 @ 1 100K_0402_5% GPIO_215
14 OF 23
PMC_SUSCLK RC24 1 @ 2 10K_0402_5% APOLLOLAKE_FCBGA1296
REV = 0.7
@ GPIO functionality only. It should not be
+1.8VALW
connected with the on-board AC present logic
because APL does not support this
+3VALW +3VS functionality.

2
RC63
3
4

2.2K_0402_5%

2
RPC6 @ QC11

G
10K_0404_4P2R_5% Connect SUSCLK to NGFF Conn.

1
+1.8VALW +3VALW
Connect SUSCLK to EC in CRB
2
1

PLT_RST# PMC_ACIN 3 1 AC_PRESENT

@ PLT_RST# 20,36,38,39,44

D
PJQ1900_DFN3L

2
@
3

RC61 RC62 RC64

2.2K_0402_5% 10K_0402_5% 10K_0402_5% Change LBSS138[Vgs(th)<1.5V] to PJQ1900[Vgs(th)<0.9V]
D2

2
5 @ @ @

G
G2 RC60

1
C 100K_0402_5% D QC10 C
S2

2
ACIN# 44
6

QC6B @ PMC_SUSCLK 3 1 G
SUSCLK 39
4

D
@ PJT138K_SOT363-6
D1

PMC_PLTRST# 2 @ S L2N7002KWT1G_SOT323-3

3
G1 QC14
@
PJQ1900_DFN3L
S1

QC6A
1

@ PJT138K_SOT363-6 RC9298 1 @ 2 0_0402_5%

PMC_SUSCLK is 3.3V level set by GPIO_88(PD) PMC_ACIN RC9340 1 @ 2 0_0402_5% AC_PRESENT

PJT138[Vgs(th)<1.5V] Change LBSS138[Vgs(th)<1.5V] to PJQ1900[Vgs(th)<0.9V] AC_PRESENT 44

+1.8VALW +1.8VALW

PMC_PLTRST# RC9349 1 @ 2 0_0402_5% PLT_RST# +1.8VALW +3VL_EC

3
4

3
4
RC9299 RPC9
RPC18
10K_0402_5% 10K_0404_4P2R_5% 10K_0404_4P2R_5%
@
@

2
1
@

2
1
EC_SMI#_Q

L2N7002KDW1T1G_SOT363-6

3
PM_SLP_S3#_R RC9332 1 @ 2 0_0402_5% D QC213B
PM_SLP_S3# 44,54
5
PBTN_OUT#_R RC9322 1 @ 2 0_0402_5% PM_SLP_S4#_R RC9333 1 @ 2 0_0402_5% G
PBTN_OUT# 44 PM_SLP_S4# 44

L2N7002KDW1T1G_SOT363-6
PBTN_OUT# is 3.3V level set by GPIO_88(PD), and /w internal 20Kohm PU PM_SLP_S3# & PM_SLP_S4# is 3.3V level set by GPIO_88(PD) S

4
B B
@

6
D QC213A
2 EC_SMI#
G

1
@

Change LBSS138DW[Vgs(th)<1.5V] to L2N7002KDW[Vgs(th)<2.0V]

+1.8VALW

2
RC9334
10K_0402_5%

1
EC_SMI#_Q RC9319 1 @ 2 0_0402_5% EC_SMI#
EC_SMI# 44

If EC_SMI#_Q default term is PU, EC is OD for EC_SMI#, can use 0ohm short

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 SOC (PMU&UART)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 10 of 58
5 4 3 2 1
 5 4 3 2 1

+3VALW_SOC

UC1J APL_SOC
UC1L APL_SOC
PCH_SMB_ALERT# RC65 1 2 1K_0402_5%
USB30_TX_P1 K3 B7 PCH_SMB_ALERT# with 20K PU default term
31 USB30_TX_P1 USB30_TX_N1 USB3_P1_TXP PCIE_CLKOUT3P B5 CPU_SVID_DAT USB20_P7
31 USB30_TX_N1 K2 C18 V5 USB20_P7 39
USB3_P1_TXN PCIE_CLKOUT3N CPU_SVID_CLK SVID0_DATA1.05V USB2_DP7 USB20_N7
USB (3.0) USB30_RX_P1 F2 A7 CLK_PCIE_WLAN CPU_SVID_ALRT#_R
C17
B17 SVID0_CLK 1.05V USB2_DN7
V6 USB20_N7 39 BT +1.8VALW
31 USB30_RX_P1 USB30_RX_N1 USB3_P1_RXP PCIE_CLKOUT2P B8 CLK_PCIE_WLAN# CLK_PCIE_WLAN 39 SVID0_ALERT_B1.05V USB20_P6
G2 AC12
31 USB30_RX_N1 USB3_P1_RXN PCIE_CLKOUT2N CLK_PCIE_WLAN# 39 USB2_DP6 AC10 USB20_N6 USB20_P6
USB20_N6
28
28
CAMERA USB_VBUSSNS RC299 2 @ 1 10K_0402_5%
C10 CLK_PCIE_LAN PCH_SMB_DATA T61 USB2_DN6 RC9393 1 2 0_0402_5%
USB30_TX_P0 PCIE_CLKOUT1P A10 CLK_PCIE_LAN# CLK_PCIE_LAN 36 PCH_SMB_CLK SMB_DATA 3.3V USB20_P5
J1 T62 AB6
29 USB30_TX_P0
29 USB30_TX_N0
USB30_TX_N0 J2 USB3_P0_TXP PCIE_CLKOUT1N CLK_PCIE_LAN# 36 PCH_SMB_ALERT# R63 SMB_CLK 3.3V USB2_DP5 AB7 USB20_N5 USB20_P5
USB20_N5
34
34
CARD READER
USB3_P0_TXN C11 CLK_PCIE_GPU SMB_ALERT_N3.3V USB2_DN5
Type C USB30_RX_P0 K9 PCIE_CLKOUT0P B11 CLK_PCIE_GPU# CLK_PCIE_GPU 20
Y9 USB20_P4 +1.8VALW
29 USB30_RX_P0
29 USB30_RX_N0
USB30_RX_N0 K10 USB3_P0_RXP PCIE_CLKOUT0N CLK_PCIE_GPU# 20 USB_VBUSSNS AC16 USB2_DP4 Y10 USB20_N4 USB20_P4
USB20_N4
45
45
Finger Print
USB3_P0_RXN USB2_VBUS_SNS USB2_DN4
AJ62 PCIE_CLKREQ_3# USB_OTG_ID AC15 V9 USB20_P3
SATA_PTX_DRX_P1 PCIE_CLKREQ3_N USB2_OTG_ID USB2_DP3 USB20_N3 USB20_P3 31 USB_OTG_ID
42 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1
W1
W2 SATA_P1_USB3_P5_TXP AH61 WLAN_CLKREQ#_Q USB_OC1# C55 USB2_DN3
V7 USB20_N3 31 USB2.0 RC9394 2
RC9360 1
@
@
1 10K_0402_5%
2 0_0402_5%
42 SATA_PTX_DRX_N1 SATA_P1_USB3_P5_TXN PCIE_CLKREQ2_N 31 USB_OC1# USB2_OC1_N USB20_P2
D Y13 D
ODD SATA_PRX_DTX_P1 T5 AH62 LAN_CLKREQ#_Q USB_OC0# B55 USB2_DP2 V13 USB20_N2 USB20_P2 28
42 SATA_PRX_DTX_P1
42 SATA_PRX_DTX_N1
SATA_PRX_DTX_N1 T6 SATA_P1_USB3_P5_RXP PCIE_CLKREQ1_N USB2_OC0_N USB2_DN2 USB20_N2 28 Touch Screen
SATA_P1_USB3_P5_RXN AK62 GPU_CLKREQ#_Q V16 USB20_P1 +1.8VALW
PCIE_CLKREQ0_N USB2_DP1 USB20_N1 USB20_P1 31 RPC11
V15
42 SATA_PTX_DRX_P0
SATA_PTX_DRX_P0 Y3 USB2_DN1 USB20_N1 31 USB 2.0( for stand USB 3.0 port)
USB_OC1# 2 3
SATA_PTX_DRX_N0 Y2 SATA_P0_TXP AH13 V12 USB20_P0 USB_OC0# 1 4
42 SATA_PTX_DRX_N0 SATA_P0_TXN USB_SSIC_0_TX_P AH12 USB2_DP0 USB20_N0 USB20_P0 29
V10
HDD 42 SATA_PRX_DTX_P0
SATA_PRX_DTX_P0 T9 USB_SSIC_0_TX_N USB2_DN0 USB20_N0 29 Type C USB 2.0 10K_0404_4P2R_5%
SATA_PRX_DTX_N0 T7 SATA_P0_RXP AG16
42 SATA_PRX_DTX_N0 SATA_P0_RXN USB_SSIC_0_RX_P AG15 12 OF 23 +3VALW_SOC
USB_SSIC_0_RX_N APOLLOLAKE_FCBGA1296
REV = 0.7
10 OF 23 LPC_CLKRUN#_R RC9387 2 @ 1 10K_0402_5%
@
APOLLOLAKE_FCBGA1296
REV = 0.7
@
CLOCK REQUEST
USB2_OC0_N：Used by t he c ontr oll er t o di sabl e I / Oi n case of +1.8VALW

UC1K APL_SOC
LPC_CLKRUN#_R RC9409 1 2 0_0402_5% LPC_CLKRUN#_EC LPC_CLKRUN#_EC 44 overcurrent - USB port 0 (OTG port) 5
RPC12
4 WLAN_CLKREQ#_Q
6 3 PCIE_CLKREQ_3#

M52 AB62 SERIRQ_R RC9368 1 2 20_0402_5%

USB2_OC1_N：Used by t he c ontr oll er t o di sabl e I / Oi n case of 7
8
2
1 LAN_CLKREQ#_Q
M54 AVS_DMIC_DATA_2
AVS_DMIC_DATA_1
3.3V LPC_SERIRQ V61 LPC_FRAME#_R
3.3V LPC_FRAME_N V62 LPC_CLKRUN#_R
RC9369 1
RC9386 1 @
2 20_0402_5%
2 20_0402_5%
SERIRQ 38,44
LPC_FRAME# 38,44
overcurrent - USB host ports [7:1] 10K_0804_8P4R_5%
3.3V LPC_CLKRUN_N LPC_CLKRUN# 38
P52
M55 AVS_DMIC_CLK_B1 AA62 CLK_PCI_TPM_R RC70 1 TPM@ 2 20_0402_5%
16 GPIO_82 AVS_DMIC_CLK_AB2 3.3V LPC_CLKOUT1 AB61 CLK_PCI_EC_R CLK_PCI_TPM 38
P54 RC71 1 2 20_0402_5%
AVS_DMIC_CLK_A1 3.3V LPC_CLKOUT0 CLK_PCI_EC 44
USB OCP
W63 LPC_AD3_R RC9364 1 2 20_0402_5% LPC_AD3 38,44 +3VALW
M61 3.3V LPC_AD3 W62 LPC_AD2_R RC9365 1 2 20_0402_5%
AVS_I2S3_WS_SYNC 3.3V LPC_AD2 Y62 LPC_AD1_R LPC_AD2 38,44
16 GPIO_92 L63 RC9366 1 2 20_0402_5% LPC_AD1 38,44
L62 AVS_I2S3_SDO 3.3V LPC_AD1 Y61 LPC_AD0_R RC9367 1 2 20_0402_5%
AVS_I2S3_SDI 3.3V LPC_AD0 LPC_AD0 38,44

2
M62
AVS_I2S3_BCLK RC9407
P29 XTAL19_OUT 10K_0402_5%
M57 OSCOUT R27 XTAL19_IN @
M58 AVS_I2S2_WS_SYNC OSCIN
16 GPIO_88

1
K59 AVS_I2S2_SDO USB_OC0#
RC69 1 2 33_0402_5% HDA_RST_AUDIO#_R K58 AVS_I2S2_SDI AF62
34 HDA_RST_AUDIO# AVS_I2S2_MCLK OSC_CLK_OUT_4 Remove level shift, due to LAN chip page already have level shift
H59
AVS_I2S2_BCLK

3
AE60 D QC225B
C OSC_CLK_OUT_3 5 C
J62 AG63 G
K62 AVS_I2S1_WS_SYNC OSC_CLK_OUT_2
16 GPIO_78 L2N7002KDW1T1G_SOT363-6
K61 AVS_I2S1_SDO AF61 S

4
AVS_I2S1_SDI OSC_CLK_OUT_1

6
G62 D QC225A LAN_CLKREQ#_Q RC75 1 @ 2 0_0402_5%
AVS_I2S1_MCLK @ TYPE_C_OCP# LAN_CLKREQ# 36
H63 AG62 2 TYPE_C_OCP# 29
AVS_I2S1_BCLK OSC_CLK_OUT_0 G
L2N7002KDW1T1G_SOT363-6
Both RTL8111GUL&RTL8111H CLKREQ# are OD,Can pull high to 1.8V
11 OF 23 S

1
APOLLOLAKE_FCBGA1296
@
REV = 0.7
@

+3VS
USB_OC0# RC9405 1 @ 2 0_0402_5% TYPE_C_OCP#

2
Reserve TYPE_C_OCP# to CPU USB_OC0# Lewis RC76
10K_0402_5%
XTAL19_IN

Reserve LS for USB OCP Lewis 2016/10/13

XTAL19_OUT

1
WLAN_CLKREQ#_Q

SMBus

3
RC79 1 2 200K_0402_5% D QC17B
5
G
YC2
L2N7002KDW1T1G_SOT363-6
S

6
1 4 D QC17A
OSC1 NC2 +3VALW_SOC +3VS +3VS 2 WLAN_CLKREQ# 39
2 3 G
NC1 OSC2
1 1 L2N7002KDW1T1G_SOT363-6
S

1
CC30 19.2MHZ_12PF_7V19200001 CC31

1
2

1
2
15P_0201_50V8-J 15P_0201_50V8-J
2 2 RPC13 RPC14
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

4
3

4
3
2
19.2MHz CRYSTAL--TXC SJ10000LN00

G
B
GPU do NOT use CLKREQ#, Set level shifter as NC B

1. Space 15MIL GPU_CLKREQ# control by BOM structure(Follow CG412)

PCH_SMB_CLK 6 1 +3VS
2. No trace under crystal

S
SMB_CLK_S3 17,39

D
3. Place on oppsosit side of MCP for temp influence
4. EDS request X'TAL Max ESR=80ohm; +/-30ppm; Typical CL=12pF; Max PD=100uW QC22A
L2N7002KDW1T1G_SOT363-6

2
G
RC77
10K_0402_5%
GPU_CLKREQ#_Q
PCH_SMB_DATA 3 4 @

S
SMB_DATA_S3 17,39

1
D

3
D QC18B
QC22B 5
L2N7002KDW1T1G_SOT363-6 G
Change LBSS138DW[Vgs(th)<1.5V] to L2N7002KDW[Vgs(th)<2.0V] L2N7002KDW1T1G_SOT363-6
S @

6
D QC18A
2
GPIO_78 strap to LOW, SMBUS set to 3.3V Mode G
GPU_CLKREQ# 21
L2N7002KDW1T1G_SOT363-6
S @
SVID

1
+3VS
+1.05VS

2
RC78
Follow HW check list to reserve 10K_0402_5%
1

1
0.1uF for +1.05VS, 01/15 CC191
0.1U_0201_6.3V6-K RC297 RC298 @

1
68_0402_5% GPU_CLKREQ#
169_0402_1%
2@
PDG: RC298 is 170ohm± 5 % +1.8VALW

2
CRB: RC298 is 169ohm± 1 %
GPU_CLKREQ#_Q RC9330 2 UMA@ 1 10K_0402_5%
CPU_SVID_CLK
CPU_SVID_ALRT#_R RC296 1 CPU_SVID_CLK 56,57 GPU_CLKREQ#_Q
2 220_0402_5% CPU_SVID_ALRT# 56,57 RC9329 1 PX@ 2 2K_0402_5%
CPU_SVID_DAT
CPU_SVID_DAT 56,57

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2014/01/21 SOC (USB&SATA&CLK&SVID&LPC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 11 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS +3VALW +3VS

UC1Q APL_SOC

3
4
RC956
RPC16
10K_0402_5%
M16 L30 10K_0404_4P2R_5%
NCTF23 GPIO_219 PCH_JTAG_TDO 16
L16 M30 PX@ PX@
F16 NCTF24 GPIO_218 M29 PCH_JTAG_TMS 16
PCH_JTAG_TDI 16

2
1
E16 NCTF25 GPIO_217 P30
J16 NCTF26 GPIO_216 PCH_JTAG_TCK 16 PXS_PWREN
NCTF27 PXS_PWREN 24,55 PXS_RST# 20
H16 AP57
H12 NCTF28 NCTF35
F12 NCTF29 E41
NCTF30 PWM3 GPIO_37 16

3
M12 F41 GPIO_36 16 QC19

1
M10 NCTF31 PWM2 C41 D

D2
NCTF32 PWM1 GPIO_35 16

2
F14 B41 PXS_PWREN#_SOC 2 5
D NCTF33 PWM0 GPIO_34 16 G2 D
H14 +1.8VALW +3VS G RC9290 RC9288
NCTF34 C63 LBSS138LT1G_SOT-23-3 100K_0402_5%
S 100K_0402_5%

S2
3
NCTF36 E63 @
PX@

6
NCTF37 QC211B

1
PJT138K_SOT363-6

D1
@

3
4
17 OF 23 PXS_RST#_SOC 2 PX@
RPC30 G1
APOLLOLAKE_FCBGA1296
10K_0404_4P2R_5%
REV = 0.7

S1
2
@
RC9287 QC211A

2
1

1
@ 10K_0402_5% PJT138K_SOT363-6

1
TP_INT# Q164 D PX@

L2N7002KDW1T1G_SOT363-6
RC170 1 @ 2 0_0402_5% 2

1
44 VGA_GATE# G

3
D QC226B 1
TP_INT# IS Output,pull up @ touch pad conn side

L2N7002KDW1T1G_SOT363-6
5 CC137 PX@ S L2N7002KWT1G_SOT323-3

3
G .1U_0402_10V6-K
CRB direct connect to GPIO_18 @

6
S D QC226A 2
Lewis 2016/10/13

4
2 PCH_TP_INT# 45
G

1
TP_INT# RC9408 1 @ 2 0_0402_5% PCH_TP_INT#
Ball Name Signal Name I/O Voltage Default Term Buffer Type
GPIO_15 PXS_PWREN#_SOC 1.8V 20K PD CMOS
UC1O APL_SOC GPIO_13 PXS_RST#_SOC 1.8V 20K PD CMOS

AK57 J39 TP_INT# +1.8VALW +3VL_EC

34 PCH_BEEP PCH_BT_OFF# ISH_GPIO_9 GPIO_18
AM52 C25 +1.8VALW +3VL_EC
AM55 ISH_GPIO_8 GPIO_24 B25 SATA_GP1
AM57 ISH_GPIO_7 GPIO_23 A26 SATA_GP0
C C

3
4
AM49 ISH_GPIO_6 GPIO_22 C26
ISH_GPIO_5 GPIO_21 RPC21

3
4
AM51 B27
HDA_SDOUT_AUDIO_R ISH_GPIO_4 GPIO_20 10K_0404_4P2R_5% RPC20
34 HDA_SDOUT_AUDIO RC324 1 2 33_0402_5% AM54 C33
AK51 ISH_GPIO_3 GPIO_19 A30 KBRST#_Q 10K_0404_4P2R_5%
34 HDA_SDIN0 HDA_SYNC_AUDIO_R ISH_GPIO_2 GPIO_9
34 HDA_SYNC_AUDIO RC325 1 2 33_0402_5% AK58 C35 @

2
1
RC326 1 2 33_0402_5% HDA_BITCLK_AUDIO_R AM48 ISH_GPIO_1 GPIO_17 C36 EC_SCI#_Q @
34 HDA_BITCLK_AUDIO

2
1
ISH_GPIO_0 GPIO_16 F39 PXS_PWREN#_SOC KBRST#_Q
F34 GPIO_15 C38
16 GPIO_33 GPIO_33 GPIO_14 PXS_RST#_SOC

L2N7002KDW1T1G_SOT363-6
F35 C30
H34 GPIO_32 GPIO_13 E39 EC_WAKE_SCI#_R Follow CRB: EC_WAKE_SCI# connect to EC

3
C37 GPIO_31 GPIO_12 C34 EC_SCI#_Q Follow CRB: SOC GPIO_11 is 1.8V Voltage D QC217B
GPIO_30 GPIO_11

3
H35 L39 5 D QC215B
+1.8VALW B37 GPIO_29 GPIO_10 A38 G 5
C29 GPIO_28 GPIO_0 B29 G
SATA_LED# GPIO_27 GPIO_8

L2N7002KDW1T1G_SOT363-6
RC9352 1 @ 2 10K_0402_5% C31 H39 S L2N7002KDW1T1G_SOT363-6

4
1 SATA_DEVLSP1 C27 GPIO_26 GPIO_7 B31 VR_VGA_PWRGD_Q S
@ TP48 @

4
GPIO_25 GPIO_6

6
A34 D QC217A
@

6
GPIO_5 B35 BOARD_ID3 2 D QC215A
GPIO_4 BOARD_ID2 EC_SCI# 44
B39 G 2
Sighting Alert(DOC#560733) GPIO_3 C39 BOARD_ID1 G
KBRST# 44
1206618869: HD Audio SDI I/O Pin Issue GPIO_2 B33 BOARD_ID0 S L2N7002KDW1T1G_SOT363-6

1
GPIO_1
Follow Intel request to remove for QS CPU @
S

1
HDA_SYNC_AUDIO_R 1 2 249_0402_1% SDATA_IN @
RC331 @ SDATA_IN 34 15 OF 23
APOLLOLAKE_FCBGA1296 Change LBSS138DW[Vgs(th)<1.5V] to L2N7002KDW[Vgs(th)<2.0V]
REV = 0.7 Change LBSS138DW[Vgs(th)<1.5V] to L2N7002KDW[Vgs(th)<2.0V]
@
1

+1.8VALW +1.8VALW +1.8VALW

Reserve for MS-Windows RS1
RC332
1K_0402_1%

2
2

@ RC9336 RC9338
2

RC9391 1K_0402_5% 1K_0402_5%

1K_0402_5%

1
@
1

EC_SCI#_Q RC9335 1 @ 2 0_0402_5% EC_SCI# KBRST#_Q RC9337 1 @ 2 0_0402_5% KBRST#

B EC_WAKE_SCI#_R RC9392 1 @ 2 0_0402_5% B
EC_WAKE_SCI# 44
If EC_SCI#_Q default term is PU, EC is OD for EC_SCI#, can use 0ohm short If KBRST#_Q default term is PU, EC is OD for KBRST#, can use 0ohm short

+1.8VALW +3VS

+1.8VALW +3VALW
BOARD ID +1.8VALW
4
3

RPC15 +1.8VALW
RPC28
3
4

10K_0404_4P2R_5%
RPC29 SATA_GP0 4 1
10K_0404_4P2R_5% SATA_GP1
@ 3 2
1
2

BT_OFF# 39,44
PX@
2
1

2
VR_VGA_PWRGD_Q 10K_0404_4P2R_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
@ PX@ 15@ @ @

RC28

RC30

RC32

RC34
3

L2N7002KDW1T1G_SOT363-6
D2

1
3

G2 D QC220B
5
S2

G
6

QC23B BOARD_ID0
4

BOARD_ID1
L2N7002KDW1T1G_SOT363-6

@ PJT138K_SOT363-6 S
D1

PCH_BT_OFF# 2 PX@ BOARD_ID2

6

G1 D QC220A BOARD_ID3
2
S1

VR_VGA_PWRGD 20,55
G

2
QC23A

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
1

@ PJT138K_SOT363-6 S UMA@ 14@ @ @

RC29

RC31

RC33

RC35
1

PX@
BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 Description

1
0 UMA SKU
A A

VR_VGA_PWRGD_Q
1 GPU SKU
RC9342 1 UMA@ 2 2K_0402_5% Reserve Reserve
VR_VGA_PWRGD RC9363 1 @ 2 100K_0402_5%
0 14" Panel
Maybe can delete this connection, after checking /w BIOS
1 15" Panel

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 P12-SOC (GPIO&HDA)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 12 of 58
5 4 3 2 1
 5 4 3 2 1

+3VALW_USB_G3 +1.24VALW +VDD2_1P24_MPHY

+3VALW_SOC +3VALW_USB_G3 UC1V APL_SOC

4 x 0402_1uF; 1 x 0603_22uF RC102 1 @ 2 0_0603_5% IccMax=0.52A 3 x 0402_1uF; 1 x 0603_22uF

RC100 1 @ 2 0_0603_5% IccMax=0.15A AJ25 D4
+1.24VA_USB2_G3 AK25 VCC_3P3V_A3 NCTF56 T51
VCC_3P3V_A4 NCTF57 L14
NCTF58 1 1 1 1
1 1 1 1 1 E3 CC91 CC92 CC93
CC86 CC87 CC88 CC89 AG20 NCTF59 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K CC94
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K CC90 +VNN VCC_1P24V_1P35V_A4 +VDD2_1P24_GLML CD@ 22U_0603_6.3V6-M
CD@ 22U_0603_6.3V6-M AM37 2 2 2 2
2 2 2 2 2 AJ37 VCC_1P24V_1P35V_A12 AM20
AJ39 VNN1 VCC_1P24V_1P35V_A10
VNN2
Place near UC1.AE20, AE18, AE22, AG22
AJ41 Follow CRB(DOC#559031) V1.0 connect
AJ42 VNN3 AM28
D AJ46 VNN4 VCC_1P24V_1P35V_A11 UC1.AM28 to +VDD2_1P24_GLML D
Place near UC1.AC41, AA42, Y44, V44, V46 VNN5 Note:Place CAPs Back of CPU Note:Place CAP Near CPU
AK37 Note:Place CAP Edge of CPU
Place near UC1.AK25, AJ25 AK39 VNN6 +CPU_CORE
VNN7
Note:Place CAPs Back of CPU Note:Place CAPs Edge of CPU Note:Place CAP Near CPU AK41
VNN8
+1.24VALW +VDD2_1P24_GLML
AK42 AA28
AK44 VNN9 VCC_VCGI1 AA30
+1.24VALW +1.24VA_USB2_G3 +VNN AK46 VNN10 VCC_VCGI2 AA32 RC105 1 @ 2 0_0603_5% IccMax=0.52A 4 x 0402_1uF; 1 x 0603_22uF
VNN11 VCC_VCGI3 AC28
AM44 VCC_VCGI4 AC30
RC101 1 @ 2 0_0603_5%
1 x 0402_1uF IccMax=3.3A 3 x 0402_1uF VNN16 VCC_VCGI5 AC32
VCC_VCGI6 1 1 1 1 1
AE28 CC99 CC100 CC101 CC131 CC189
AJ44 VCC_VCGI7 AE30 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6-M 1U_0402_6.3V6K
IccMax=0.13A 1
CC70
1
CC71
1
CC72
1 RSVD22 VCC_VCGI8 AE32 CD@ CD@
1
CC80 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K CC184 +3VALW_USB_G3 VCC_VCGI9 AG28 2 2 2 2 2
1U_0402_6.3V6K CD@ 0.1U_0201_6.3V6-K AA42 VCC_VCGI10 AG30
2 2 2 2 Y44 VCC_3P3V_A1 VCC_VCGI11 AG32
VCC_3P3V_A7 VCC_VCGI12
Place near UC1.AM20, AK20, AM37 Place near UC1.AM28
2 V46 AJ28
V44 VCC_3P3V_A6 VCC_VCGI13 AJ30
Follow CRB add 0.1uF CAP VCC_3P3V_A5 VCC_VCGI14
AC41 AJ32 Note:Place CAPs Back of CPU Note:Place CAP Near CPU
+VDD2_1P24_AUD_ISH_PLL VCC_3P3V_A2 VCC_VCGI15 AK28 Note:Place CAP Edge of CPU
VCC_VCGI16 AK30
Place near UC1.AM44, AK46, AK41, AK39, AJ42, AJ41, AJ39, AK42, AK44, AJ46, AJ37, AK37 VCC_VCGI17
Place near UC1.AG20 AJ20
VCC_1P24V_1P35V_A6 VCC_VCGI18
AK32 +1.24VALW +VDD2_1P24_DSI_CSI
AJ22 AM30
VCC_1P24V_1P35V_A7 VCC_VCGI19 E29
Note:Place CAP Back of CPU Note:Place CAPs Back of CPU +VDD2_1P24_MPHY VCC_VCGI20 IccMax=0.26A 2 x 0402_1uF; 1 x 0603_22uF
AE18 E37 RC104 1 @ 2 0_0603_5%
AE20 VCC_1P24V_1P35V_A1 VCC_VCGI21 U28
AE22 VCC_1P24V_1P35V_A2 VCC_VCGI23 U30
VCC_1P24V_1P35V_A3 VCC_VCGI24
+1.24VALW +VDD2_1P24_AUD_ISH_PLL AG22
VCC_1P24V_1P35V_A5 VCC_VCGI25
U32 1 1 1
V28 CC97 CC98
VCC_VCGI26 V30 1U_0402_6.3V6K 1U_0402_6.3V6K CC130
RC103 1 @ 2 0_0603_5% IccMax=0.39A 2 x 0402_1uF; 1 x 0603_22uF +VDD2_1P24_GLML BJ61 VCC_VCGI27 V32 CD@ 22U_0603_6.3V6-M
RSVD11 VCC_VCGI28 Y28 2 2 2
C VCC_VCGI29 Y30 C
AK20 VCC_VCGI30 Y32
1 1 1 VCC_1P24V_1P35V_A8 VCC_VCGI31
CC95 CC96 CC132 E50
1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6-M VCC_VCGI22
Place near UC1.AA18, AA20
CD@ AC20 Note:Place CAP Back of CPU Note:Place CAP Near CPU
2 2 2 +VDD2_1P24_DSI_CSI AC22 RSVD12 R19 +CPU_CORE
RSVD13 NCTF60 Note:Place CAP Edge of CPU
VCCRTC

AA18 AA44 IccMax=21A 12 x 0402_1uF

AA20 VCC_1P24V_A1 VCCRTC_3P3V
Place near UC1.AJ20, AJ22, AK22 +VDD2_1P24_AUD_ISH_PLL VCC_1P24V_A2 +VNN
Note:Place CAPs Back of CPU Note:Place CAP Near CPU 1 1 1 1 1 1
Note:Place CAP Edge of CPU AM23 CC50 CC52
AK22 VNN12 AM25 1U_0402_6.3V6K CC51 1U_0402_6.3V6K CC53 CC54 CC55
VCC_1P24V_1P35V_A9 VNN13 AM41 CD@ CD@
+VCCRAM_1P05_IO_3PHASEIO +VCCRAM_1P05_IO_3PHASEIO 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
+1.05VS VNN14 AM42 2 2 2 2 2 2
AA22 VNN15
AC23 VCC_1P05V1
RC107 1 @ 2 0_0603_5% IccMax=0.9A 4 x 0402_1uF; 1 x 0603_22uF V18 VCC_1P05V3 BJ62
VCC_1P05V7 RSVD14 Note:Place CAPs Back of CPU
Y18 V49
Y20 VCC_1P05V8 RSVD15
+VCCRAM_1P05_FUSE VCC_1P05V9
1 1 1 1 1
CC104 CC105 CC106 CC107 1 1 1 1 1 1
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K CC108 P16 CC60
CD@ CD@ +VCCRAM_1P05_FHV1 VCC_1P05V4 CC56 CC57 CC58 CC59 1U_0402_6.3V6K CC61
22U_0603_6.3V6-M
2 2 2 2 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K CD@ 1U_0402_6.3V6K
T15 2 2 2 2 2 2
+VCCRAM_1P05_FHV0 VCC_1P05V6
Place near UC1.AA22, Y20, V18, Y18, AA23, AC23 CRB set CC107 un-mount
T13 Note:Place CAPs Back of CPU
+VCCRAM_1P05_IO_3PHASEIO VCC_1P05V5

Note:Place CAPs Back of CPU Note:Place CAPs Edge of CPU Note:Place CAP Near CPU AA23
VCC_1P05V2
VCCRTC
B +1.05VS +VNN B
+VCCRAM_1P05_FHV1 1 x 0201_0.1uF; 1 x 0603_22uF
1 x 0402_1uF; 1 x 0402_1uF(@) 22 OF 23
RC106 1 @ 2 0_0603_5% +VCCRAM_1P05_FVH_FUSE RC293 1 @ 2 0_0603_5% APOLLOLAKE_FCBGA1296 IccMax=1.5A 2 x 0402_1uF; 2 x 0603_22uF
REV = 0.7
+VCCRAM_1P05_FHV0
@ 1 1
1 1 1 1 1 1 CC185 CC79
CC102 CC103 RC294 1 @ 2 0_0603_5% CC81 CC82 CC84 CC85 0.1U_0201_6.3V6-K 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6-M 22U_0603_6.3V6-M
+VCCRAM_1P05_FUSE 2@ 2
CD@ CD@
2 2@ 2 2 2 2
RC295 1 @ 2 0_0603_5%
Additional CAPs Follow WW10 change from 22uF to 1uF
Place near UC1.AM42, AM25, AM23, AM41
Additional CAPs Note:Place CAP Back of CPU Note:Place CAP Near CPU

Note:Place CAP Back of CPU Note:Place CAPs Edge of CPU Note:Place CAPs near CPU
Follow CRB: P16, T15, T13 are different power trace.
Maybe can merge them to one net +VNN

1
CC190
0.1U_0201_6.3V6-K
2@

A A

For SVID over moat.

Place near over moat area.

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (Power)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 13 of 58
5 4 3 2 1
 5 4 3 2 1

+1.05VA_SOC_G3
+VDD1_1P8
+1.05VS +1.05VA_SOC_G3
UC1W APL_SOC

RC9362 1 @ 2 0_0805_5% IccMAX=1.8A 4 x 0402_1uF; 2 x 0603_22uF

E6 AE42
NCTF61 VCC_1P8V_A5 AE44
VCC_1P8V_A6 AA46
1 1 1 1 1 1 VCC_1P8V_A1
CC118 CC119 CC120 CC121 CC123 CC124 AA25 AC42
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6-M 22U_0603_6.3V6-M AC25 VCC_1P05V10 VCC_1P8V_A2 AC44
CD@ CD@ AE25 VCC_1P05V11 VCC_1P8V_A3 AC46
D 2 2 2 2 2 2 U22 VCC_1P05V12 VCC_1P8V_A4 AE46 D
U23 VCC_1P05V13 VCC_1P8V_A7 AG25
V22 VCC_1P05V14 VCC_1P8V_A8
V23 VCC_1P05V15
V25 VCC_1P05V16
Place near UC1.AE25, AC25, AA25, U23, V22, V23, V25, Y23, Y25, U25, U20, U22
Y23 VCC_1P05V17 R17
U20 VCC_1P05V18 NCTF64
U25 VCC_1P05V19
Y25 VCC_1P05V20 +CPU_CORE
Note:Place CAPs Back of CPU Note:Place CAPs Edge of CPU Note:Place CAPs near CPU VCC_1P05V21
F29
AM32 VCC_VCGI32 E35
AN32 RSVD16 VCC_VCGI33 AK34
+CPU_CORE +VNN D1 RSVD17 VCC_VCGI34
BG63 RSVD18 +CPU_CORE
V48 RSVD19
RC80 2 1 100_0402_1% CPU_VCC_SENSE RC82 2 1 100_0402_1% VNN_VCC_SENSE RSVD20 E45
VCC_VCGI35 AC37
CPU_VSS_SENSE R43 VCC_VCGI36 AE36
CPU_VSS_SENSE 56 CPU_VSS_SENSE CPU_VCC_SENSE VCC_VCGI_SENSE_N VCC_VCGI37
RC81 2 1 100_0402_1% R41 AE37
CLOSED PU3401 56 CPU_VCC_SENSE VCC_VCGI_SENSE_P VCC_VCGI38 AG36
VNN_VCC_SENSE AG48 VCC_VCGI39 E43
57 VNN_VCC_SENSE VNN_SENSE VCC_VCGI40 E48
CLOSED PU3301 VCC_VCGI41 R45
AN18 VCC_VCGI42 R47
AN20 VDDQ1 VCC_VCGI43 U36
AN22 VDDQ2 VCC_VCGI63 U37
+1.35V +CPU_CORE AN23 VDDQ3 VCC_VCGI44 U39
AN41 VDDQ4 VCC_VCGI45 U41
IccMAX=2.8A 2 x 0402_1uF +1.35V AN42 VDDQ5 VCC_VCGI46 U42
AN44 VDDQ6 VCC_VCGI47 U44
1 VDDQ7 VCC_VCGI48
CC192 AN46 U46
0.1U_0201_6.3V6-K AR17 VDDQ8 VCC_VCGI49 U47
1 1 VDDQ9 VCC_VCGI50
CC186 CC187 AR47 U48
1U_0402_6.3V6K 1U_0402_6.3V6K 2 EMC@ AT13 VDDQ10 VCC_VCGI51 V36
CD@ AT17 VDDQ11 VCC_VCGI52 V37
2 2 AT47 VDDQ12 VCC_VCGI53 V39
AT51 VDDQ13 VCC_VCGI54 V41
C C
EMC request: AV14 VDDQ14 VCC_VCGI55 Y36
Place near UC1.AN46, AN44, AN42, AN41, AN23, AN22, VDDQ15 VCC_VCGI56
AN20, AN18, AV14, AT51, AR17, AR47, AT13, AT17, AV50 Place near CPU_VCC_SENSE under +CPU_COR moat 03/10 AV50 Y37
VDDQ16 VCC_VCGI57 Y39
VCC_VCGI58 Y41
F23 VCC_VCGI59 AC36
Note:Place CAPs Back of CPU NCTF62 VCC_VCGI60
E23 AA36
NCTF63 VCC_VCGI61 AA37
VCC_VCGI64 AA39
BJ3 VCC_VCGI62
RSVD21

+1.8VALW +VDD1_1P8 23 OF 23
APOLLOLAKE_FCBGA1296
REV = 0.7
RC108 1 @ 2 0_0805_5% IccMax=0.4A 4 x 0402_1uF; 1 x 0603_22uF
@

1 1 1 1 1
CC125 CC126 CC127 CC128 CC129
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6-M
CD@
2 2 2 2 2

Place near UC1.AE44, AC46, AC44, AA46, AE42, AG25, AE46, AC42
Note:Place CAPs Back of CPU Note:Place CAP Edge of CPU Note:Place CAP Near CPU

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 14 of 58
5 4 3 2 1
 5 4 3 2 1

UC1S APL_SOC
UC1T APL_SOC UC1U APL_SOC

AM36 A12
AG42 VSS107 VSS1 A16 AR19 BB19 D6 P45
AG44 VSS70 VSS2 A20 AR32 VSS133 VSS201 BB25 E12 VSS262 VSS328 P5
AG46 VSS71 VSS3 A24 AR45 VSS134 VSS202 BB3 E14 VSS263 VSS329 P55
AH15 VSS72 VSS4 A28 AT12 VSS135 VSS203 BB39 E19 VSS264 VSS330 P59
AH16 VSS73 VSS5 A32 AT16 VSS136 VSS204 BB45 E27 VSS265 VSS331 P9
AH48 VSS74 VSS6 A36 AT19 VSS137 VSS205 BB61 E4 VSS266 VSS332 R23
D
AH5 VSS75 VSS7 A40 AT2 VSS138 VSS206 BC32 E54 VSS267 VSS333 R32 D
AH52 VSS76 VSS8 A44 AT25 VSS139 VSS207 BD3 F10 VSS268 VSS334 T49
AH54 VSS77 VSS9 A48 AT29 VSS140 VSS208 BD32 F21 VSS269 VSS335 U1
AH55 VSS78 VSS10 A52 AT3 VSS141 VSS209 BD56 F3 VSS270 VSS336 U10
AH57 VSS79 VSS12 A56 AT35 VSS142 VSS210 BD61 F32 VSS271 VSS337 U11
AH58 VSS80 VSS13 A62 AT39 VSS143 VSS211 BD8 F37 VSS272 VSS338 U13
AH59 VSS81 VSS14 A9 AT45 VSS144 VSS212 BE1 F43 VSS273 VSS339 U14
AH6 VSS82 VSS15 AA1 AT48 VSS145 VSS213 BE10 F45 VSS274 VSS340 U16
AH7 VSS83 VSS16 AA2 AT52 VSS146 VSS214 BE12 F50 VSS275 VSS341 U17
AJ1 VSS84 VSS17 AA27 AT57 VSS147 VSS215 BE16 F56 VSS276 VSS342 U18
AJ18 VSS85 VSS18 AA34 AT61 VSS148 VSS216 BE17 F59 VSS277 VSS343 U2
AJ2 VSS86 VSS19 AA41 AT62 VSS149 VSS217 BE21 F63 VSS278 VSS344 U27
AJ23 VSS87 VSS20 AA63 AT7 VSS150 VSS218 BE27 G1 VSS279 VSS345 U34
AJ27 VSS88 VSS21 AB10 AU32 VSS151 VSS219 BE29 G32 VSS280 VSS346 U5
AJ34 VSS89 VSS22 AB12 AV19 VSS152 VSS220 BE35 H17 VSS281 VSS347 U50
AJ36 VSS90 VSS23 AB16 AV2 VSS153 VSS221 BE37 H23 VSS282 VSS348 U51
AJ63 VSS91 VSS24 AB48 AV21 VSS154 VSS222 BE43 H29 VSS283 VSS349 U53
AK10 VSS92 VSS25 AB5 AV23 VSS155 VSS223 BE47 H3 VSS284 VSS350 U54
AK12 VSS93 VSS26 AB52 AV29 VSS156 VSS224 BE48 H37 VSS285 VSS351 U56
AK18 VSS94 VSS27 AB57 AV3 VSS157 VSS225 BE52 H47 VSS286 VSS352 U57
AK23 VSS95 VSS28 AB59 AV32 VSS158 VSS226 BE54 H61 VSS287 VSS353 U59
AK27 VSS96 VSS29 AB9 AV35 VSS159 VSS227 BE63 H7 VSS288 VSS354 U62
AK48 VSS97 VSS30 AC27 AV41 VSS160 VSS228 BF3 J12 VSS289 VSS355 U63
AK5 VSS98 VSS32 AC34 AV43 VSS161 VSS229 BF32 J14 VSS290 VSS356 U7
AK52 VSS99 VSS33 AC39 AV45 VSS162 VSS230 BF61 J19 VSS291 VSS357 U8
AK59 VSS100 VSS34 AE1 AV55 VSS163 VSS231 BG19 J27 VSS292 VSS358 V20
AK9 VSS101 VSS35 AE10 AV61 VSS164 VSS232 BG23 J30 VSS293 VSS359 V27
AM18 VSS102 VSS36 AE11 AV62 VSS165 VSS233 BG29 J32 VSS294 VSS360 V34
AM22 VSS103 VSS37 AE13 AV9 VSS166 VSS234 BG32 J35 VSS295 VSS361 V42
AM27 VSS104 VSS38 AE14 AW14 VSS167 VSS235 BG35 J37 VSS296 VSS362 Y12
AM34 VSS105 VSS39 AE16 AW30 VSS168 VSS236 BG41 J48 VSS297 VSS363 Y16
AM39 VSS106 VSS40 AE17 AW34 VSS169 VSS237 BG45 J63 VSS298 VSS364 Y22
AM46 VSS108 VSS41 AE2 AW50 VSS170 VSS238 BH1 K32 VSS299 VSS365 Y27
AN1 VSS109 VSS42 AE23 AY10 VSS171 VSS239 BH2 K5 VSS300 VSS366 Y34
AN10 VSS110 VSS43 AE27 AY32 VSS172 VSS240 BH21 K54 VSS301 VSS367 AP9
AN11 VSS111 VSS44 AE34 AY54 VSS173 VSS241 BH25 K57 VSS302 VSS368 AP55
AN13 VSS112 VSS45 AE39 AY58 VSS174 VSS242 BH39 K6 VSS303 VSS369 AN63
AN14 VSS113 VSS46 AE4 AY6 VSS175 VSS243 BH43 L21 VSS304 VSS370 AN7
C C
AN16 VSS114 VSS47 AE41 B2 VSS176 VSS244 BH62 L27 VSS305 VSS371 AN8
AN17 VSS115 VSS48 AE47 B3 VSS177 VSS245 BH63 L29 VSS306 VSS372 AN54
AN2 VSS116 VSS49 AE48 VNN_VSS_SENSE_R RC9302 1 @ 2 0_0402_5% VNN_VSS_SENSE B62 VSS178 VSS246 BJ10 L35 VSS307 VSS373 AN56
AN25 VSS117 VSS50 AE5 VNN_VSS_SENSE 57 VSS179 VSS247 VSS308 VSS374
RC9303 1 2 0_0402_5% B9 BJ14 L43 AN57
AN27 VSS118 VSS51 AE50 @ BA1 VSS180 VSS248 BJ18 L45 VSS309 VSS375 AN59
AN28 VSS119 VSS52 AE51 BA12 VSS181 VSS249 BJ28 L50 VSS310 VSS376 Y42
Place RC9302 & RC9303 as Tri-Pad
AN30 VSS120 VSS53 AE53 BA16 VSS182 VSS250 BJ32 M14 VSS311 VSS377 Y46
AN34 VSS121 VSS54 AE54 BA17 VSS183 VSS251 BJ36 M21 VSS312 VSS378 Y48
AN36 VSS122 VSS55 AE56 BA2 VSS184 VSS252 BJ4 M27 VSS313 VSS379 Y5
AN37 VSS123 VSS56 AE57 BA21 VSS185 VSS253 BJ46 M3 VSS314 VSS380 Y52
AN39 VSS124 VSS57 AE59 BA25 VSS186 VSS254 BJ50 M32 VSS315 VSS381 Y54
AN47 VSS125 VSS58 AE63 BA27 VSS187 VSS255 BJ54 M50 VSS316 VSS382 Y55
AN48 VSS126 VSS59 AE7 BA29 VSS188 VSS256 BJ56 M59 VSS317 VSS383 Y57
AN5 VSS127 VSS60 AE8 BA32 VSS189 VSS257 BJ60 M9 VSS318 VSS384 Y59
AN50 VSS128 VSS61 AG13 BA35 VSS190 VSS258 BJ8 N1 VSS319 VSS385 Y6
AN51 VSS129 VSS62 AG18 BA37 VSS191 VSS259 C12 N32 VSS320 VSS386 Y7
AN53 VSS130 VSS63 AG23 BA39 VSS192 VSS260 C16 N63 VSS321 VSS387 C28
B63 VSS131 VSS64 AG27 BA43 VSS193 VSS261 P13 VSS322 VSS388 C32
A5 VSS132 VSS65 AG34 BA47 VSS194 P19 VSS323 VSS389 C40
AC18 VSS11 VSS66 AG37 BA48 VSS195 P35 VSS324 VSS390 C48
VSS31 VSS67 AG39 BA52 VSS196 P37 VSS325 VSS391 D32
VSS68 AG41 BA62 VSS197 VSS326 VSS392 D58
VSS69 BA63 VSS198 VSS393 P41
AK36 VSS199 R29 VSS394 P43
19 OF23 VSS200 VSS327 VSS395
APOLLOLAKE_FCBGA1296
REV = 0.7 20 OF 23 21 OF 23
@ APOLLOLAKE_FCBGA1296 APOLLOLAKE_FCBGA1296
REV = 0.7 REV = 0.7
@ @

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 15 of 58
5 4 3 2 1
 5 4 3 2 1

Hardware STRAPS
(Follow up CRB)
+1.8VALW +1.8VALW Internal Schematics
GPIO# Purpose Termination Setting Pin usage Remark
GPIO_33 RSVD 20K PD Floating N/A Follow CRB(DOC#: 561386); EDS(v2.1) P54
Ensure this strap always PD for normal
GPIO_34 RSVD 20K PD Floating platform operation EDS(v2.1) P47
1

1
RC314 RC315 RC316 RC317 RC321 RC319 RC322 RC226 RC234 RC228 RC236 RC230 RC231 RC232 Ensure this strap always PD for normal
4.7K_0402_1% 4.7K_0402_1% 10K_0402_5% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 10K_0402_5% 4.7K_0402_1% 10K_0402_5% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% GPIO_35 RSVD 20K PD Floating platform operation EDS(v2.1) P47
Ensure this strap always PD for normal
2

2
D D
@ @ @ @ @ @ @ @ @ @ @ @ @ @ Follow CRB, need check /w intel GPIO_36 RSVD 20K PD Floating EDS(v2.1) P47
platform operation
GPIO_34 SIO_SPI_2_FS0
GPIO_34 12 SIO_SPI_2_FS0 8
GPIO_35
GPIO_35 12
GPIO_47
GPIO_47 10
GPIO_37 RSVD 20K PD Floating N/A Follow CRB(DOC#: 561386); EDS(v1.5) P57
GPIO_36 GPIO_48
GPIO_36 12 GPIO_48 10 Enable CSE ROM 1 = Enable bypass This strap tells CSE (TXE3.0) to bypass ROM
GPIO_39
GPIO_39 10
GPIO_78
GPIO_78 11
GPIO_39 Bypass 20K PD Floating 0 = Disable bypass (default)* EDS(v2.1) P47
GPIO_40 GPIO_82
GPIO_40 10 GPIO_82 11 RTC Clock Timer 1 = Enable bypass Only be used when an external oscillator is used to
GPIO_43
GPIO_43 10
GPIO_88
GPIO_88 11
GPIO_40 Bypass 20K PD Floating 0 = Disable bypass (default)* supply a 32.768kHz clock to RTC_X1. EDS(v2.1) P47
GPIO_44 GPIO_92
GPIO_44 10 GPIO_92 11 Ensure this strap always PD for normal
GPIO_43 RSVD 20K PU 4.7K PD platform operation EDS(v2.1) P47
1

1
RC9297 RC9295 RC9293 RC9294 RC318 RC320 RC323 RC233 RC227 RC235 RC300 RC237 RC9296 RC239
4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 4.7K_0402_1% 10K_0402_5% 1K_0402_5% 10K_0402_5% 4.7K_0402_1% 10K_0402_5% Allow SPI as a boot 1 = Enable(Default)*
GPIO_44 source 20K PU Floating 0 = Disable EDS(v2.1) P47
2

2
@ @ @ @ @ @ @ @ @ @ @ 1 = Force Recovery strap for corrupted FW image
Enable CSE ROM Bypass

GPIO_47 Force DNX FW Load 20K PD Floating

SMBUS Power Mode

CRB add PD junmper on GPIO43

0 = Do not force(Default)* EDS(v2.1) P47

PMU Power Mode

Ensure this strap is PD when RSM_RST_N
GPIO_48 RSVD 20K PD Floating de-asserts for normal platform operation EDS(v2.1) P47
SMBus 1.8V/3.3V 1 = Buffers set to 1.8V mode(Default) Follow CRB to strap this pin LOW. SMBus signals are
GPIO_78 20K PU 1K PD

SMBus
mode select 0 = Buffers set to 3.3V mode* 3.3V mode. EDS(v2.1) P47
Ensure this strap always PD for normal
GPIO_82 RSVD 20K PD Floating platform operation EDS(v2.1) P47
PMU 1.8V/3.3V 1 = Buffers set to 1.8V mode(Default) Follow CRB to strap this pin LOW. PMU signals are
GPIO_88 mode select 20K PD 4.7K PD 0 = Buffers set to 3.3V mode* 3.3V mode. EDS(v2.1) P48
1 = Enable Should strap this pin LOW. Functionality is handled
GPIO_92 SMBus No Re-Boot 20K PD Floating 0 = Disable(Default)* by the PMC. EDS(v2.1) P48
Hardware STRAPS Ensure this strap is PD when RSM_RST_N
C
GPIO_104 RSVD 20K PD Floating de-asserts for normal platform operation EDS(v2.1) P48 C

+1.8VALW
(Follow up CRB) +1.8VALW
Ensure this strap is PD when RSM_RST_N
GPIO_105 RSVD 20K PD Floating de-asserts for normal platform operation EDS(v2.1) P48
Ensure this strap is PD when RSM_RST_N
GPIO_106 RSVD 20K PU Floating de-asserts for normal platform operation EDS(v2.1) P48
LPC 1.8V/3.3V 1 = Buffers set to 1.8V mode(Default) Follow CRB to strap this pin LOW. LPC signals are
GPIO_110 mode select 20K PU 4.7K PD 0 = Buffers set to 3.3V mode* 3.3V mode. EDS(v3.1)) P48
1

1
RC312 RC240 RC241 RC242 RC243 RC244 RC245 RC246 RC247 RC248 RC249 RC250 RC251 RC9323
4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 10K_0402_5% 1K_0402_5% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 100K_0402_5% 1 = Leave these regions unmapped by the System Agent Pull LOW for designs that boot from SPI and HIGH
GPIO_111 RSVD 20K PU 4.7K PD 0 = Map these regions to the boot SPI otherwise. EDS(v2.1) P48
2

2
@ @ @ @ @ @ @ @ @ @ @ @ @ @ Ensure this strap is PD when RSM_RST_N
GPIO_112 RSVD 20K PD Floating de-asserts for normal platform operation EDS(v2.1) P48
GPIO_104 GPIO_33
GPIO_104 8 GPIO_33 12
GPIO_105 GPIO_117 Ensure this strap is PD when RSM_RST_N
GPIO_105 8 GPIO_117 8 GPIO_113 RSVD 20K PD Floating de-asserts for normal platform operation EDS(v2.1) P48
GPIO_106 GPIO_123
GPIO_106 8 GPIO_123 8
GPIO_111 GPIO_112 Ensure this strap is PD when RSM_RST_N
GPIO_111 8 GPIO_112 8 GPIO_117 RSVD 20K PD Floating de-asserts for normal platform operation EDS(v2.1) P48
GPIO_118 GPIO_113
GPIO_118 8 GPIO_113 8
GPIO_110 GPIO_120 Flash Descriptor 1 = Override This strap enables the platform to override security
GPIO_110 8 GPIO_120 8 GPIO_118 Override 20K PD 4.7KPD 0 = No Override (Normal Operation)* features in the SPI. EDS(v2.1) P48
GPIO_37 GPIO_121
GPIO_37 12 GPIO_121 8
1 = Enable This strap enables platform to change different SPI
GPIO_120 Top swap override 20K PD Floating
1

1
0 = Disable (default)* ROM location. ESD(v2.1) P48
RC313 RC252 RC253 RC254 RC9292 RC256 RC257 RC303 RC259 RC260 RC261 RC262 RC263 RC9324
10K_0402_5% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 1K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 4.7K_0402_1% 4.7K_0402_1% 10K_0402_5% 10K_0402_5% 100K_0402_5%
Ensure this strap is PD when RSM_RST_N
GPIO_121 RSVD 20K PD Floating de-asserts for normal platform operation EDS(v2.1) P48
2

2
@ @ @ @ @ @ @ @ @ @ @ @
Ensure this strap is PU when RSM_RST_N
Flash Descriptor Override

GPIO_123 RSVD 20K PU Floating de-asserts for normal platform operation EDS(v2.1) P48
LPC Power Mode

Boot BIOS Strap

B B

ME_PROTECT Circuit
Change to P-MOS Diodes DMG1013UW-7 09/02 +1.8VALW

+1.8VALW

1
2

RC9403 RC304 RC307 RC309 RC311

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2.2K_0402_5%

2
@ @ @ @
1

PCH_JTAG_TDO 12

PCH_JTAG_TMS 12
3

S
QC223
2

ME3 PCH_JTAG_TDI 12
G
2
SHORT PADS EC_ME_PROTECT 44
PCH_JTAG_TCK 12
1

D
DMG1013UW-7_SOT-323-3
1

1
RC9404
100K_0402_5% RC305 RC306 RC308 RC310
GPIO_118
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2

2
@ @ @ @

EC_ME_PROTECT GPIO_118 TXE Flash Descriptor Override

A A
Low High Override

High Low No Override (Normal Operation)

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 SOC (STRAPS & OTHERS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 16 of 58

5 4 3 2 1
 5 4 3 2 1

+1.35V +1.35V
DDR Mapping table
DDRA_DQ0---DQ0 3A@1.35V DDRA_DQ[0..63] 4
DDRA_DQ1---DQ1 For RF request: keep 0402 and set to mount
DDRA_DQ2---DQ7 JDDR1
DDR_DQ DDRA_DQS[0..7] 4
DDRA_DQ3---DQ6 DDRA_DQS0 ---DQS0 1
VREF_DQ VSS1
2
3 4 DDRA_DQ6
DDRA_DQ4---DQ3 DDRA_DQS0#---DQS#0 DDRA_DQ0 VSS2 DQ4 DDRA_DQ5 DDRA_DQS#[0..7] 4

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
5 6
DDRA_DQ5---DQ5

0.1U_0201_6.3V6-K
DDRA_DQ1 7 DQ0 DQ5 8
DDRA_DQ6---DQ4 1 DQ1 VSS3 DDRA_DQS#0 1 1 1 DDRA_MA[0..15] 4

CD4

CD5

CD6
9 10

CD105
DDRA_DQ7---DQ2 DDRA_DM0 11 VSS4 DQS#0 12 DDRA_DQS0
13 DM0 DQS0 14

EMC@
2 DDRA_DQ7 VSS5 VSS6 DDRA_DQ3 2 2 2
DDRA_DQ8 ---DQ11 15 16

RF@

RF@

RF@
DDRA_DQ4 17 DQ2 DQ6 18 DDRA_DQ2
DDRA_DQ9 ---DQ8 DQ3 DQ7
DDRA_DQ10---DQ9 19 20
DDRA_DQ9 VSS7 VSS8 DDRA_DQ13
DDRA_DQ11---DQ10 DDRA_DQS1 ---DQS1 21
DQ8 DQ12
22
DDRA_DQ10 23 24 DDRA_DQ14
DDRA_DQ12---DQ14 DDRA_DQS1#---DQS#1 DQ9 DQ13
D 25 26 D
DDRA_DQ13---DQ12 DDRA_DQS#1 27 VSS9 VSS10 28 DDRA_DM1
DDRA_DQ14---DQ13 DDRA_DQS1 29 DQS#1 DM1 30
DDRA_DQ15---DQ15 31 DQS1 RESET# 32
DDRA_DRAMRST#_R 4
DDRA_DQ11 33 VSS11 VSS12 34 DDRA_DQ12

0.1U_0201_6.3V6-K
DDRA_DQ8 DQ10 DQ14 DDRA_DQ15
DDRA_DQ16---DQ21 35
DQ11 DQ15
36 1
DDRA_DQ17---DQ20 37 38

CD115
DDRA_DQ20 39 VSS13 VSS14 40 DDRA_DQ17
DDRA_DQ18---DQ18 DDRA_DQ22 DQ16 DQ20 DDRA_DQ16
DDRA_DQS2 ---DQS2 41 42

EMC@
DDRA_DQ19---DQ19 DQ17 DQ21 2 OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
DDRA_DQ20---DQ16 DDRA_DQS2#---DQS#2 43 44
DDRA_DQS#2 45 VSS15 VSS16 46 DDRA_DM2
DDRA_DQ21---DQ23 DDRA_DQS2 47 DQS#2 DM2 48
DDRA_DQ22---DQ17 49 DQS2 VSS17 50 DDRA_DQ23
DDRA_DQ23---DQ22 DDRA_DQ18 51 VSS18 DQ22 52 DDRA_DQ21
DDRA_DQ19 DQ18 DQ23 Layout Note:
53 54 EMC request 03/09
DDRA_DQ24---DQ24 55 DQ19 VSS19 56 DDRA_DQ31 Place near DIMM
DDRA_DQ24 57 VSS20 DQ28 58 DDRA_DQ25
DDRA_DQ25---DQ29 DDRA_DQ26 DQ24 DQ29
DDRA_DQ26---DQ25 59 60
DQ25 VSS21 DDRA_DQS#3
DDRA_DQ27---DQ31 DDRA_DQS3 ---DQS3 61
VSS22 DQS#3
62
DDRA_DM3 63 64 DDRA_DQS3
DDRA_DQ28---DQ27 DDRA_DQS3#---DQS#3 DM3 DQS3
65 66
DDRA_DQ29---DQ26 DDRA_DQ29 67 VSS23 VSS24 68 DDRA_DQ30
DDRA_DQ30---DQ30 DDRA_DQ28 69 DQ26 DQ30 70 DDRA_DQ27 +1.35V
DDRA_DQ31---DQ28 71 DQ27 DQ31 72
8 x 0603_10uF; 8 x 0201_0.1uF
VSS25 VSS26
DDRA_DQ32---DQ63 CD19

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_DQ33---DQ56 1

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

330U_D2_2V_Y
DDRA_CKE0 73 74 DDRA_CKE1 CD7 1 CD8 1 CD9 1 CD10 CD11 CD12 CD13 CD14
DDRA_DQ34---DQ61 4 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 4 1 1 1 1 1 1 1 1 1 1 1 1 1
+
DDRA_DQS4 ---DQS7 75 76

CD80

CD81

CD82

CD83

CD84

CD85

CD86

CD87
DDRA_DQ35---DQ62 VDD1 VDD2 DDRA_MA15
DDRA_DQ36---DQ57 DDRA_DQS4#---DQS#7 77 78
DDRA_BA2# 79 NC1 A15 80 DDRA_MA14
DDRA_DQ37---DQ58 4 DDRA_BA2#
81 BA2 A14 82 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 2

CD@

CD@

CD@

CD@
DDRA_DQ38---DQ59 DDRA_MA12 83 VDD3 VDD4 84 DDRA_MA11
DDRA_DQ39---DQ60 DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 VDD5 VDD6 DDRA_MA6
DDRA_DQ40---DQ40 89
A8 A6
90
DDRA_MA5 91 92 DDRA_MA4
DDRA_DQ41---DQ47 A5 A4 Follow CRB Follow CRB
DDRA_DQ42---DQ43 93 94
DDRA_MA3 VDD7 VDD8 DDRA_MA2
DDRA_DQ43---DQ42 DDRA_DQS5 ---DQS5 95
A3 A2
96
DDRA_MA1 97 98 DDRA_MA0
DDRA_DQ44---DQ44 DDRA_DQS5#---DQS#5 A1 A0
99 100
DDRA_DQ45---DQ45 DDRA_CLK0 VDD9 VDD10 DDRA_CLK1
DDRA_DQ46---DQ41 4 DDRA_CLK0 DDRA_CLK0#
101
CK0 CK1
102
DDRA_CLK1# DDRA_CLK1 4
Follow PDG&CRB: use 3.65Kohm +/-1% voltage divider
4 DDRA_CLK0# 103 104 +1.35V
DDRA_DQ47---DQ46 105 CK0# CK1# 106
DDRA_CLK1# 4
DDRA_MA10 107 VDD11 VDD12 108 DDRA_BA1# +1.35V
C
DDRA_DQ48---DQ51 DDRA_BA0# 109 A10/AP BA1 110 DDRA_RAS# DDRA_BA1# 4 6 x 0201_0.1uF C
4 DDRA_BA0# BA0 RAS# DDRA_RAS# 4

1
DDRA_DQ49---DQ55 111 112
DDRA_WE# 113 VDD13 VDD14 114 DDRA_CS0# RD158
DDRA_DQ50---DQ54 4 DDRA_WE# DDRA_CAS# WE# S0# DDRA_ODT0 DDRA_CS0# 4
DDRA_DQ51---DQ49 DDRA_DQS6 ---DQS6 4 DDRA_CAS# 115 116 3.65K_0402_1%

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
CAS# ODT0 DDRA_ODT0 4
DDRA_DQ52---DQ52 DDRA_DQS6#---DQS#6 117 118 1 1 1 1 1 1
DDRA_MA13 119 VDD15 VDD16 120 DDRA_ODT1

CD88

CD89

CD90

CD91

CD92

CD93
DDRA_DQ53---DQ53 DDRA_ODT1 4

2
DDRA_CS1# 121 A13 ODT1 122 RD152 2 @ 1 0_0402_5% DDR_CA
DDRA_DQ54---DQ48 4 DDRA_CS1# S1# NC2 DDR_CA 4
123 124

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
DDRA_DQ55---DQ50 VDD17 VDD18

1
125 126 DDR_CA 2 2 2 2 2 2
127 NCTEST VREF_CA 128 RD159
DDRA_DQ62 VSS27 VSS28 DDRA_DQ56
DDRA_DQ56---DQ36 129 130 3.65K_0402_1%

0.1U_0201_6.3V6-K
DDRA_DQ57 131 DQ32 DQ36 132 DDRA_DQ61
DDRA_DQ57---DQ33 DQ33 DQ37 1
133 134

CD106
DDRA_DQ58---DQ34

2
DDRA_DQS#7 VSS29 VSS30 DDRA_DM4
DDRA_DQ59---DQ38 DDRA_DQS7 ---DQS4 135
DQS#4 DM4
136
DDRA_DQS7 137 138

EMC@
DDRA_DQS7#---DQS#4
DDRA_DQ60---DQ39
DDRA_DQ61---DQ37 139 DQS4 VSS31 140 DDRA_DQ59 2 For EMC
DDRA_DQ58 141 VSS32 DQ38 142 DDRA_DQ60 +1.35V
DDRA_DQ62---DQ32 DDRA_DQ63 143 DQ34 DQ39 144 +1.35V
DDRA_DQ63---DQ35 145 DQ35 VSS33 146 DDRA_DQ44 3 x 0201_0.1uF; 5 x 0201_330pF
DDRA_DQ40 147 VSS34 DQ44 148 DDRA_DQ45
DDRA_DQ46 149 DQ40 DQ45 150

0.1U_0201_25V6-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K
DQ41 VSS35 DDRA_DQS#5

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K
151 152 EMC request 1 1 1 1 1 1 1 1
VSS36 DQS#5

1
DDRA_DM5 153 154 DDRA_DQS5

CD107

CD108

CD109
Follow CRB DM5 DQS5

CD110

CD111

CD112

CD113

CD114
155 156 RD160
+3VS DDRA_DQ43 157 VSS37 VSS38 158 DDRA_DQ47

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
DDRA_DQ42 DQ42 DQ46 DDRA_DQ41 3.65K_0402_1% 2 2 2 2 2 2 2 2
159 160
161 DQ43 DQ47 162

2
DDRA_DQ54 163 VSS39 VSS40 164 DDRA_DQ52 RD153 2 @ 1 0_0402_5% DDR_DQ
DDRA_DQ51 DQ48 DQ52 DDRA_DQ53 DDR_DQ 4
165 166
DQ49 DQ53

1
167 168
VSS41 VSS42
1

DDRA_DQS#6 169 170 DDRA_DM6 RD161

DDRA_DQS6 DQS#6 DM6
RD154
10K_0402_5%
RD155
10K_0402_5%
171
173 DQS6 VSS43
172
174 DDRA_DQ50 3.65K_0402_1% For EMC
DDRA_DQ55 175 VSS44 DQ54 176 DDRA_DQ49

2
DDRA_DQ48 177 DQ50 DQ55 178
2

@ @ 179 DQ51 VSS45 180 DDRA_DQ39

SA0 DDRA_DQ33 181 VSS46 DQ60 182 DDRA_DQ34
SA1 DDRA_DQ36 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRA_DQS#4 VTT
DDRA_DM7 187 VSS48 DQS#7 188 DDRA_DQS4
DM7 DQS7 3 x 0603_10uF; 4 x 0201_0.1uF; 1 x 330pF
2

189 190
RD156 RD157 DDRA_DQ37 191 VSS49 VSS50 192 DDRA_DQ35
DDRA_DQ38 DQ58 DQ62 DDRA_DQ32

33P_0402_50V8J
0_0402_5% 0_0402_5% 193 194

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
@ @ 195 DQ59 DQ63 196
VSS51 VSS52 1 1 1 1 1 1 1 1

CD70
SA0 197 198

CD94

CD95

CD96

CD97

CD98

CD99

CD100
B
2 x 0.1uF_0201 VTT B
1

199 SA0 EVENT# 200

+3VS VDDSPD SDA SMB_DATA_S3 11,39
SA1 201 202
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

SA1 SCL SMB_CLK_S3 11,39 2 2 2 2 2 2 2 2

203 204

RF@
CD@

CD@

CD@
2.2U_0603_6.3V6K

VTT1 VTT2
1 1 1 0.65A@0.75V
205 206
CD27

CD78

CD79

G1 G2
Maybe can change RD156&RD157 as 0ohm R-short LCN_DAN06-K4406-0102 For RF request: keep 0402 and set to mount
2 2 2
CD@

@ ME@

Follow CRB

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 DDRIII SO-DIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 17 of 58
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

0.65A@0.75V

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 18 of 58

5 4 3 2 1
 5 4 3 2 1

Power-Up/Down Sequence
"Topaz" has the following requirements with regards to power-supply sequencing to VRAM ID config
avoid damaging the ASIC:
D
VRAM ID PU resistor PD resistor D
Memory Type
All the ASIC supplies must reach their respective nominal voltages within 20 ms PS_3[3:1] RV63 RV70
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µ s. Hynix
It is recommended that the 3.3-V rail ramp up first. 100 4.53K 4.99K
H5GC4H24AJR-R0C
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 µ s
before VDDC, VDDCI, and VMEMIO start to ramp up. 256Mx16 Micron
The power rails that are shared with other components on the system should be 111 4.75K NC
EDW4032BABG-70-F
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU. Samsung
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/µ s). 110 3.4K 10K
For power down, reversing the ramp-up sequence is recommended. K4G41325FE-HC28

000 NC 4.75K

0 ~ 20ms 010 4.53K 2K

VDDR3(+3VGS)
0 ~ 20ms 001 8.45K 2K
C C

VDD_CT(+1.8VGS)

PCIE_VDDC(+0.95VGS)
10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE) 100ms min.

100us min.
PERSTb(GPU_RST#)

REFCLK(CLK_PCIE_VGA)

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 19 of 58
5 4 3 2 1
 5 4 3 2 1

UV1A

PCIE_PTX_C_GRX_P0 AF30 AH30 PCIE_PRX_C_GTX_P0 CV1 1 PCIE_PRX_GTX_P0

2 0.1U_0201_6.3V6-K
8 PCIE_PTX_C_GRX_P0 PCIE_RX0P PCIE_TX0P PCIE_PRX_GTX_P0 8
PCIE_PTX_C_GRX_N0 AE31 AG31 PCIE_PRX_C_GTX_N0 CV2 1 2PX@ PCIE_PRX_GTX_N0
0.1U_0201_6.3V6-K
8 PCIE_PTX_C_GRX_N0 PCIE_RX0N PCIE_TX0N PCIE_PRX_GTX_N0 8
PX@
D D
PCIE_PTX_C_GRX_P1 AE29 AG29 PCIE_PRX_C_GTX_P1 CV3 1 PCIE_PRX_GTX_P1
2 0.1U_0201_6.3V6-K
8 PCIE_PTX_C_GRX_P1 PCIE_PTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_PRX_C_GTX_N1 PCIE_PRX_GTX_N1 PCIE_PRX_GTX_P1 8
8 PCIE_PTX_C_GRX_N1 AD28 AF28 CV4 1 2PX@
0.1U_0201_6.3V6-K
PCIE_RX1N PCIE_TX1N PCIE_PRX_GTX_N1 8
PX@
PCIE_PTX_C_GRX_P2 AD30 AF27 PCIE_PRX_C_GTX_P2 CV5 1 PCIE_PRX_GTX_P2
2 0.1U_0201_6.3V6-K
8 PCIE_PTX_C_GRX_P2 PCIE_PTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_PRX_C_GTX_N2 CV6 1 2PX@ PCIE_PRX_GTX_N2
0.1U_0201_6.3V6-K PCIE_PRX_GTX_P2 8
8 PCIE_PTX_C_GRX_N2 PCIE_RX2N PCIE_TX2N PCIE_PRX_GTX_N2 8
PX@
PCIE_PTX_C_GRX_P3 AC29 AD27 PCIE_PRX_C_GTX_P3 CV7 1 PCIE_PRX_GTX_P3
2 0.1U_0201_6.3V6-K
8 PCIE_PTX_C_GRX_P3 PCIE_RX3P PCIE_TX3P PCIE_PRX_GTX_P3 8
PCIE_PTX_C_GRX_N3 AB28 AD26 PCIE_PRX_C_GTX_N3 CV8 1 2PX@ PCIE_PRX_GTX_N3
0.1U_0201_6.3V6-K
8 PCIE_PTX_C_GRX_N3 PCIE_RX3N PCIE_TX3N PCIE_PRX_GTX_N3 8
PX@

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N
C C

V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27 with BOM strcture control, CV1--CV8 change to 0.22uf for CZ
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30
NC#P30 NC#T24
T24 change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
N31 T23
NC#N31 NC#T23

N29
NC#N29 NC#P27
P27 11/4 change to PC sample SA000074V10
M28 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
B NC#L31 NC#P23 B

L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26

CLOCK
CLK_PCIE_GPU AK30
11 CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP
AK32
11 CLK_PCIE_GPU# PCIE_REFCLKN
+0.95VGS
CALIBRATION
Y22 RV3 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX

GPU_RST# DV3
AL27
21 GPU_RST# PERSTB GPU_RST# 2
1 VGA_PWROK
VGA_PWROK 55
1

@ VR_VGA_PWRGD 3
12,55 VR_VGA_PWRGD
RV7 1 @ 2 0_0402_5% RV6
100K_0402_5% LBAT54AWT1G SOT323
+3VGS PX@ PX@
2
5

A A
UV2
VCC

1
12 PXS_RST# IN1 GPU_RST#
4
2 OUT
GND

10,36,38,39,44 PLT_RST# IN2 Security Classification LC Future Center Secret Data Title

MC74VHC1G08DFT2G_SC70-5 Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_PCIE

3

PX@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 20 of 58
5 4 3 2 1
 5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
UV1B 1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE

AF2
NC#AF2 AF4 RECOMMENDED
NC#AF4 MLPS Bit Strap Name Description
SETTINGS
N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
L9 DBG_DATA16 NC#AG3 AG5 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
AE9 DBG_DATA15 NC#AG5 PS_0[3] ROM_CONFIG[2] X
DPA
Y11 DBG_DATA14 AH3 001 = 256MB
AE8 DBG_DATA13 NC#AH3 AH1
AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
AC10 DBG_DATA11 AK3
AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
AC8 DBG_DATA9 NC#AK1 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3 1 = PCIe GEN3 is supported.
AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 1= GEN3 is supported X
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5 0 = The CLKREQB power management capability is disabled
AB2 DBG_DATA3 NC#AM5 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
DPB
Y8 DBG_DATA2 AJ7
D
Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
D

+3VGS DBG_DATA0 NC#AH6

AK8 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
NC#AK8 AL7 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 NC#AL7
0 = Tx deemphasis disabled.
W6 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
V6 NC#W6
1 2 GPU_GPIO0 NC#V6 V4
10K_0402_5% @ RV9 PS_2[1] N/A Reserved. 0
10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 AC6 NC#V4 U5
10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 AC5 NC#AC6 NC#U5 PS_2[2] N/A Reserved. 0
10K_0402_5% 1 @ 2 RV14 GPU_GPIO10 NC#AC5 W3 VGA_VSSI_SEN 1 TV10 PAD @
10K_0402_5% 1 @ 2 RV25 GPU_GPIO11 AA5 NC#W3 V2 0 = Disable the external BIOS ROM device.
10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 AA6 NC#AA5 NC#V2 1 = Enable the external BIOS ROM device. X
DPC PS_2[3] STRAP_BIOS_ROM_EN 0= Disable
10K_0402_5% 1 @ 2 RV34 GPU_GPIO13 +1.8VGS NC#AA6 Y4
10K_0402_5% 1 @ 2 RV81 GPU_GPIO22 NC#Y4 W5 0 = VGA controller capacity enabled.
1 2 GPU_VID1 NC#W5 1 = The device will not be recognized as the system’ s V GA
10K_0402_5% @ RV97 PS_2[4] STRAP_BIF_VGA_DIS 1
10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 controller.
1 2 GPU_VID5 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2
10K_0402_5% @ RV99 10K_0402_5% TV11 16.2K_0402_1% PS_2[5] N/A Reserved 1
10K_0402_5% 1 @ 2 RV106 GPU_VID2 RV95 1 2 TOPAZ@ @ PAD BP_1 U3 NC#W1 NC#Y2
10K_0402_5% Y6 NC#U3 J8 Board configuration related strapping, such as for memory ID
Reserve for Topaz
10K_0402_5% 1 @ 2 RV1011 GPU_GPIO17 TV12 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 PS_3[1] BOARD_CONFIG[0] 100 = Hynix 1G 000 = Hynix 2G X
@ PAD NC#AA1 PS_3[2] BOARD_CONFIG[1] 111 = Micron 1G 010 = Micron 2G
5.11K_0402_1% 1 @ 2 RV1039 TESTEN PS_3[3] BOARD_CONFIG[2] 110 = Samsung 1G 001 = Samsung 2G

Determines the maximum number of digital display audio endpoints

Reserve I2C that will be presented to the OS and user.(Combine with PS_0[5])
111 = No usable endpoints.
R1 AUD_PORT_CONN_ 110 = One usable endpoint.
R3 SCL PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
SDA 100 = Three usable endpoints. 11
AM26 DIECRACKMON RV120 1 2 TOPAZ@ PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
NC_R AK26 10K_0402_5% PINSTRAP[2] 010 = Five usable endpoints.
GPU_GPIO0 U6 GENERAL PURPOSE I/ONC_AVSSN#AK26 001 = Six usable endpoints.
+VGA_CORE U10 GPIO_0 AL25 000 = All endpoints are usable.
+VGA_CORE T10 NC_GPIO_1 NC_G AJ25
VGA_SMB_DATA U8 NC_GPIO_2 NC_AVSSN#AJ25
RB751V-40_SOD323-2 VGA_SMB_CLK U7 SMBDATA AH24
1 2 GPU_GPIO5 T9 SMBCLK NC_B AG25
DV1 @ +1.8VGS +1.8VGS
+VGA_CORE 44 VGA_AC_DET GPU_VID5 T8 GPIO_5_AC_BATT NC_AVSSN#AG25
T7 GPIO_6 DAC1 AH26
+VGA_CORE GPU_VR_HOT# GPU_GPIO8 NC_GPIO_7 NC_HSYNC

1
RV104 1 2 PX@ P10 AJ27 RV22 1 2 4.7K_0402_5%
0_0402_5% GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC TOPAZ@ RV71 RV74
GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 8.45K_0402_1%
GPU_GPIO11 N6 GPIO_10_ROMSCK AD22 PX@ @
GPU_GPIO12 NC_GPIO_11 NC_RSET Pull down for none OBFF design
@ PAD TV3 1 N5

2
GPU_GPIO13 N3 NC_GPIO_12 AG24 PS_0 PS_1
+VGA_CORE Y9 NC_GPIO_13 NC_AVDD AE22
GPU_SVD GPU_VID3 NC_GPIO_14 NC_AVSSQ

1
0_0402_5% 1 EXO@ 2 RV103 N1 1 1
C 10K_0402_5% 1 @ 2 RV67 GPU_GPIO16 M4 GPIO_15_PWRCNTL_0 AE23 RV77 CV15 RV80 CV16 C
0_0402_5% 1 @ 2 RV107 GPU_GPIO17 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% .01U_0402_16V7-K 4.75K_0402_1% .01U_0402_16V7-K
44,55 GPU_VR_HOT# +VGA_CORE GPIO_17_THERMAL_INT NC_VSS1DI
W10 PX@ @ PX@ @
10K_0402_5% 1 PX@ 2 RV68 GPIO_19_CTF M2 NC_GPIO_18 2 2
FutureASIC/SEYMOUR/PARK

2
GPU_SVC 0_0402_5% 1 EXO@ 2 RV105 GPU_VID4 P8 GPIO_19_CTF AM12 CEC_1 1 TV5
GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD @
GPU_GPIO22 N8 GPIO_21
GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R
RV110 1 TOPAZ@ 2 0_0402_5% +1.8VGS +1.8VGS
GPU_VR_HOT# 0_0402_5% 1 2 RV1012 GPU_VID1 AM10 GPIO_29 NC_SVI2#AK12 AL11 GPU_SVT_R GPU_SVD 55
@ RV109 1 TOPAZ@ 2 0_0402_5%
1 2 RV124 GPU_CLKREQ#_R N7 GPIO_30 NC_SVI2#AL11 AJ11 GPU_SVC_R GPU_SVT 55
0_0402_5% @ RV111 1 TOPAZ@ 2 0_0402_5%
11 GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC 55

1
JTAG_TRSTB L6 RV60 RV63
JTAG_TDI L5 JTAG_TRSTB
+3VGS 10K_0402_5% 8.45K_0402_1%
JTAG_TCK L3 JTAG_TDI @ @
@ PAD JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 PAD @

2
10K_0402_5% 1 @ 2 RV72 JTAG_TRSTB TV7 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 PAD @ PS_2 PS_3
10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
JTAG_TMS TESTEN

1
10K_0402_5% 1 @ 2 RV78 1K_0402_5% AF24 1 1
NC#AF24 AG13 RV69 CV18 RV70 CV19
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
AB13 NC_SWAPLOCKB PX@ @ @ @
+VGA_CORE NC_GENERICA 2 2
W8

2
470_0402_5% 1 PX@ 2 RV1040 GPU_CLKREQ# W9 NC_GENERICB
W7 NC_GENERICC AC19 PS_0
AD10 NC_GENERICD PS_0
2016/09/02: Pull-down GPU_CLKREQ# at GPU side NC_GENERICE_HPD4 PS_1
AJ9 AD19
AL9 NC#AJ9 PS_1
DBG_CNTL0 PS_2 Bit BOM
AE17 MLPS
PS_2
PX_EN
AC14
NC_HPD1 PS_3 5 4 3 2 1 R _ p u ( ) R _ p d ( ) C(nF)
@ PAD TV6 1 AB16 AE20
PX_EN PS_3
CV25 PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
4.7K_0402_5% 1 @ 2 RV54
2 1 XTALIN AE19 PS_1[5:1] 1 1 0 0 1 RV74=8.45K RV80=2K CV16=NC
@ PAD TV15 1 NC_DBG_VREFG AC16 TS_A
NC_DBG_VREFG
10P_0201_25V8G PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV18=NC
PX@ PS_3[5:1] 1 1 X X X RV63=X76 RV70=X76 CV19=NC
DDC/AUX
2

AE6
PLL/CLOCK NC_DDC1CLK AE5 with BOM strcture control,
27MHZ_10PF_7V27000050

YV1 R_pu (Ω ) R_pd (Ω ) Bits [3:1]

GND1

OSC1

PX@ NC_DDC1DATA
RV63,RV70 change to different value to
1

AD2 +VGA_CORE NC 4750 000

RV46 NC_AUX1P AD4
1
adjust VRAM config
NC_AUX1N
1M_0402_5% RV24 with BOM strcture control, 8450 2000 001
GND2
OSC2

PX@ AC11 100_0402_5% when config PEG3

NC_DDC2CLK AC13 TOPAZ@ 4530 2000 010
RV74 change to 8.45K,
2

NC_DDC2DATA
RV80 change to 2K
2

XTALIN AM28 AD13 6980 4990 011

3

XTALOUT AK28 XTALIN NC_AUX2P AD11

XTALOUT NC_AUX2N 4530 4990 100
B XO_IN VGA_VSS_SEN_R Capacitor Value (nF) Bits [5:4] B
10K_0402_5% 1 PX@ 2 RV45 AC22 AD20 RV125 1 TOPAZ@ 2 0_0402_5%
1 XO_IN2 XO_IN NC#AD20 VGA_CORE_SEN_R VGA_VSS_SEN 55
10K_0402_5% PX@ 2 RV50 AB22 AC20 RV126 1 TOPAZ@ 2 0_0402_5% 680 00 3240 5620 101
CV32 XO_IN2 NC#AC20 VGA_CORE_SEN 55
2 1 XTALOUT AE16 82 01 3400 10000 110
NC#AE16 AD16
NC#AD16 10 10 4750 NC 111
10P_0201_25V8G
1

SEYMOUR/FutureASIC AC1
PX@ 1 GPU_DPLUS T4 NC_DDCVGACLK AC3
@ PAD TV13 RV23 NC 11 Note: 0402 1% resistors are required.
@ PAD TV14 1 GPU_DMINUS T2 DPLUS THERMAL NC_DDCVGADATA 100_0402_5%
no symbol for 8pf cap, PLM has PN,change the PN DMINUS TOPAZ@
+3VGS +VDDIO_GPU
2

RV41 1 @ 2 GPIO_28_FDO R5
+3VGS GPIO28_FDO
10K_0402_5% +1.8VGS LV3 1 2 PX@ +TSVDD AD17 SVC SVD Output Voltage (V) RV234 1 2 EXO@
BLM15PD121SN1D_2P AC17 TSVDD +1.8VGS 0_0402_5%
TSVSS 1
+VGA_CORE 0 0 1.1 CV638
2

(1.8V@20mA TSVDD) RV203 1 2 TOPAZ@ .01U_0402_16V7-K

RV42 1 0 1 1.0 0_0402_5% @
10K_0402_5% CV21 @ 2
EXO@ 1U_0402_6.3V6K For Topaz, RV23/RV24 stuff 100ohm 1 0 0.9
PX@ For EXO, RV23/RV24 stuff 0hm
1

2
2 1 1 0.8
RV205 RV204 RV209
10K_0402_5% 10K_0402_5% 10K_0402_5%
Connect GPIO_28 to 10K pull @ PX@ @
down to enable MLPS.

1
GPU_SVD
GPU_SVC
GPU_SVT
RV242 2 @ 1 0_0402_5% WRST# 44

2
RV206 RV207 RV210
10K_0402_5% 10K_0402_5% 10K_0402_5%
PX@ @ @

1
1

C QV13
GPU_RST# @ 1 2 DV2 RV128 1 @ 2 2 MMBT3904WH_SOT323-3 Internal VGA Thermal Sensor
20 GPU_RST# B
2.2K_0402_5% @
0.1U_0201_6.3V6-K

SDM10U45LP-7_DFN1006-2-2 @ E
3
1

+3VGS
1
RV131 +3VGS
GPIO_19_CTF 1 @ 2 RV132 100K_0402_5%
47K_0402_5% @
1

2
CV215

A A
2

RV43 RV44
2

47K_0402_5% 47K_0402_5%
G

PX@ PX@
2

VGA_SMB_CLK QV4A 1 6 PX@

S

EC_SMB_CK2 38,44
D

2N7002KDWH_SOT363-6
G

VGA_SMB_DATA QV4B 4 3 PX@

S

EC_SMB_DA2 38,44
D

2N7002KDWH_SOT363-6

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_Main_MSIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

UV1F
+VGA_CORE

D D
AB11
NC_VARY_BL AB12
NC_DIGON

AL15
NC_UPHYAB_TMDPA_TX0N AK14
NC_UPHYAB_TMDPA_TX0P
AH16
NC_UPHYAB_TMDPA_TX1N AJ15
NC_UPHYAB_TMDPA_TX1P
AL17
NC_UPHYAB_TMDPA_TX2N AK16
NC_UPHYAB_TMDPA_TX2P
AH18
NC_UPHYAB_TMDPA_TX3N AJ17
NC_UPHYAB_TMDPA_TX3P
AL19
NC_TXOUT_L3P AK18
NC_TXOUT_L3N
C C
TMDP

AH20
NC_UPHYAB_TMDPB_TX0N AJ19
NC_UPHYAB_TMDPB_TX0P
AL21
NC_UPHYAB_TMDPB_TX1N AK20
NC_UPHYAB_TMDPB_TX1P
AH22
NC_UPHYAB_TMDPB_TX2N AJ21
NC_UPHYAB_TMDPB_TX2P
AL23
NC_UPHYAB_TMDPB_TX3N AK22
NC_UPHYAB_TMDPB_TX3P
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

@
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_TMDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

+1.8VGS (1.8V@425mA DP_VDDR)

RV48 1 2 0_0603_5% +DP_VDDR
UV1G UV1E

PX@

PX@
PX@
NC/DP POWER

10U_0603_6.3V6M

1U_0402_6.3V6K
DP POWER
1 1
AG15 AE11 AA27 A3
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
D D
AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
2 2 AG17 NC_DP_VDDR#AF16 NC#AE13 AF13 AC24 GND_3 GND_67 AA16

CV39

CV40
AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
AE27 GND_8 GND_72 AD6
+0.95VGS AF32 GND_9 GND_73 AD8
(0.95V@560mA DP_VDDC) GND_10 GND_74
AG27 AE7
RV47 1 2 0_0603_5% +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
AG21 NC_DP_VDDC#AG20 NC#AF6 AF7 K28 GND_12 GND_76 AH10
NC_DP_VDDC#AG21 NC#AF7 GND_13 GND_77

PX@

PX@
PX@ AF22 AF8 K32 AH28

0.1U_0201_6.3V6-K
AG22 NC_DP_VDDC#AF22 NC#AF8 AF9 L27 GND_14 GND_78 B10

1U_0402_6.3V6K
AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
1 1 DP_VDDC#AD14 GND_16 GND_80
N25 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
2 2 AG14 AE1 P32 GND_19 GND_83 B20

CV38

CV37
AH14 NC_DP_VSSR_1 NC#AE1 AE3 R27 GND_20 GND_84 B22
AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
C
AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32 C
AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28
AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
DP_VSSR_13 GND_96 F18
GND_97 F2
GND_98 F20
RV49 1 @ 2 AF17 AE10 M6 GND_99 F22
150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
N16 GND_33 GND_101 F26
N18 GND_34 GND_102 F6
@ N21 GND_35 GND
GND_103 F8
P6 GND_36 GND_104 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
B B
U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
Y10 GND_54
Y15 GND_55
Y17 GND_56
Y20 GND_57
R11 GND_58 A32
T11 GND_59 VSS_MECH_1 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
N11 GND_62
V11 GND_63
GND_64

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_DP Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

+1.35VGS
For DDR3/GDDR5, 1500mA@1.5V

CV48

CV51

CV52

CV53

CV54

CV55

CV56

CV217
10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.01U_0201_10V6K
0.1U_0201_6.3V6-K
1 1 1 1 1 1 1 1 1 UV1D +1.8VGS
CV501 (1.8V@100mA PCIE_PVDD)
33P_0402_50V8J AM30
PCIE_PVDD

PCIE
RF_PX@ MEM I/O

CV46

CV47
2 2 2 2 2 2 2 2 2 H13 AB23
VDDR1_1 NC#AB23

1U_0402_6.3V6K

10U_0603_6.3V6M
PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
H16 AC23 1 1
H19 VDDR1_2 NC#AC23 AD24
RF VDDR1_3 NC#AD24
J10 AE24
J23 VDDR1_4 NC#AE24 AE25
J24 VDDR1_5 NC#AE25 AE26 2 2
VDDR1_6 NC#AE26

PX@

PX@
J9 AF25
K10 VDDR1_7 NC#AF25 AG26
+1.8VGS +VDD_CT K23 VDDR1_8 NC#AG26 +0.95VGS
(1.8V@13mA VDD_CT) VDDR1_9
K24 (0.95V@2500mA PCIE_VDDC)
LV7 1 2 0_0402_5% K9 VDDR1_10 L23
L11 VDDR1_11 PCIE_VDDC_1 L24

CV144
L12 VDDR1_12 PCIE_VDDC_2 L25

CV64

CV65

CV66

CV67

CV68

CV69

CV71
PX@

1U_0402_6.3V6K
L13 VDDR1_13 PCIE_VDDC_3 L26
1 VDDR1_14 PCIE_VDDC_4

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
L20 M22 1 1 1 1 1 1 1 1
L21 VDDR1_15 PCIE_VDDC_5 N22 CV502
L22 VDDR1_16 PCIE_VDDC_6 N23 33P_0402_50V8J
D D
2 VDDR1_17 PCIE_VDDC_7

PX@
N24 RF_PX@
PCIE_VDDC_8 R22 2 2 2 2 2 2 2 2
PCIE_VDDC_9

PX@

PX@

PX@

PX@

PX@

PX@

PX@
T22 RF
LEVE L PCIE_VDDC_10 U22
TRANSLAT IO N PCIE_VDDC_11 V22
AA20 PCIE_VDDC_12 +VGA_CORE
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15
+3VGS AB21 VDD_CT_3 CORE VDDC_1 N15
(3.3V@25mA VDDR3) VDD_CT_4 VDDC_2 N17

CV73

CV74

CV75

CV76

CV77

CV84
CV141

CV143

CV146

CV148

CV150

CV152

CV159

CV133

CV137

CV151
VDDC_3

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
LV8 1 2 0_0402_5% +VDDR3 R13
I/O VDDC_4 R16

CV149
VDDC_5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122) PX@ AA17 R18
VDDR3_1 VDDC_6

1U_0402_6.3V6K
as DFC suggest, footprint with 1 AA18 Y21
AB17 VDDR3_2 VDDC_7 T12
MURAT_BLM15PD121SN1D_2P AB18 VDDR3_3 VDDC_8 T15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDDR3_4 VDDC_9

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
T17
2 VDDC_10

PX@
V12 T20
Y12 NC_VDDR4_1 VDDC_11 U13
+1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 U18
(1.8V@130mA MPLL_PVDD) VDDC_14 V21
1 2 PX@ +MPLL_PVDD VDDC_15 V15
LV4
BLM15AG221SN1 VDDC_16 V17

CV139

CV153

CV156

CV160

CV134

CV135
VDDC_17 V20
CV26

CV34

CV27

VDDC_18

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
POWE R
Y13
CV24

1 1 1 1 1 1 1
1U_0402_6.3V6K

VDDC_19
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0201_6.3V6-K

1 1 1 Y16 CV503
VDDC_20 Y18 33P_0402_50V8J
1 VDDC_21 AA12 RF_PX@
VDDC_22 M11 2 2 2 2 2 2 2
2 2 2 VDDC_23

PX@

PX@

PX@

PX@

PX@

PX@
N12
2 VDDC_24
PX@

PX@

PX@

U11
VDDC_25
@

RF
For EMC
PLL
+0.95VGS
(0.95V@1400mA BIF_VDDC)
+1.8VGS R21
BIF_VDDC_1 U21
(1.8V@75mA SPLL_PVDD) BIF_VDDC_2
+SPLL_PVDD +MPLL_PVDD 1
LV5 1 2 PX@ L8 CV41
BLM15PD121SN1D_2P MPLL_PVDD +VGA_CORE 1U_0402_6.3V6K
PX@
CV29

CV30

ISOLATE D
(GDDR3/DDR3 8.8A@1.12V VDDCI) 2
CV28

CORE I/O
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0201_6.3V6-K

1 1 M13
+SPLL_PVDD H7 VDDCI_1 M15
1 SPLL_PVDD VDDCI_2 M16

CV218

CV219

CV158

CV132

CV136

CV138

CV220
+0.95VGS VDDCI_3 M17
2 2 VDDCI_4

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
(0.95V@100mA SPLL_VDDC) M18

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDCI_5

10U_0603_6.3V6M

10U_0603_6.3V6M
2 M20
+SPLL_VDDC VDDCI_6 1 1 1 1 1 1 1 1
@

PX@

PX@

LV6 1 2 PX@ H8 M21 CV504

BLM15PD121SN1D_2P SPLL_VDDC VDDCI_7 N20 33P_0402_50V8J
For EMC J7 VDDCI_8 RF_PX@
C SPLL_PVSS 2 2 2 2 2 2 2 2 C
CV35

CV36
0.1U_0201_6.3V6-K

PX@

PX@

PX@

PX@

PX@

PX@

PX@
1U_0402_6.3V6K

1 1 1 RF
CV33 @
0.1U_0201_6.3V6-K
@
2 2 2
PX@

PX@

For EMC

MOS. AO3402 VGS MAX is 12V +1.8VALW TO +1.8VGS +1.05VS to +0.95VGS

+1.8VALW QV2 +1.8VGS Can change to low cost and small Can change to low cost and +1.05VS
AO3402_SOT-23-3 QV3 +0.95VGS
PX@
size MOS. AO3402 small size MOS.Rdson<22mohm AON6414AL_DFN8-5
+1.8VGS /0.5A Rdson<65mohm Reserve for GPU support +0.95VS /2A PX@
1 3
D S 1
CV518

CV519

CV241

CV243

CV242
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

2
1
G

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

5 3

CV521
1 1 1 1 1

1
0.1U_0201_6.3V6-K
RV1001

CV240

CV238

CV239
2

+5VALW 470_0603_5% 1 1 RV1002

PXS_PWREN#_H

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M
@ 1 @ 2 RV245 CV520 1 1 1 470_0603_5%

4
1 PX@ 2 RV1015 2 2 2 2 2 15K_0402_5% 0.1U_0201_6.3V6-K @
2
@

PX@

PX@

V20B+ 20K_0402_5% @

2
2 2
@

PXS_PWREN#_H
1

2 2 2

@
1 @ 2 RV202 D QV20 V20B+ 130K_0402_5% 1 PX@ 2 RV1006
PXS_PWREN#

1
PX@

PX@

PX@
120K_0402_5% 2 D QV21
G 1 2 2 PXS_PWREN#
+5VALW 120K_0402_5% @ RV1016
1

1
1 G
1

QV31 D RV123 1 S 2N7002KW_SOT323-3 RV1004 CV221

3

PXS_PWREN# 2 150K_0402_5% CV237 @ QV23 1 D 1M_0402_5% 0.1U_0201_25V6-K S 2N7002KW_SOT323-3

3
G PXS_PWREN# 2
@ 0.1U_0201_25V6-K PX@ PX@ @
PX@ G 2
2

2
2N7002KW_SOT323-3 S 2
3

PX@ 2N7002KW_SOT323-3 S
3

PX@
RV127 is 1% , will change to 5%
change MOS from 7408 to 6414 for Rds on consider

+3VGS +3.3VS TO +3VGS

+3VALW
+3.3VGS /25mA
+3VS RV1014 1 PX@ 2 0_0603_5% LP2301ALT1G_SOT23-3
B B
S

RV1013 1 @ 2 0_0603_5% QV6 3 1 PX@

CV513

CV511
10U_0603_6.3V6M

1
1U_0402_6.3V6K
G

1 1
2

RV1007
470_0603_5%
+5VALW @
2 2
PX@

PX@

1 PXS_PWREN#
RV1009 PX@ 2 RV1010 2 PX@ 1
20K_0402_5% 15K_0402_5%
1
1

CV517 D QV28
PXS_PWREN#
1

QV27 D 0.1U_0201_6.3V6-K 2
PXS_PWREN 2 G
PX@
12,55 PXS_PWREN G 2
S 2N7002KW_SOT323-3
3

2N7002KW_SOT323-3 S @
3

PX@

+1.35V TO +1.35VGS +1.35V +1.35VGS

+1.35VGS/6.5A Rdson<10.5mohm CV214 CV210 CV211

0.1U_0201_6.3V6-K

CV208 CV209
Vgs=17.85V(AC); 4.00V(DC) 1
1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
330U_D2_2V_Y

AON6414AL_DFN8-5 +VGA_CORE
1 1 1 1 1
RdsonR150mohm/125 ℃ ; 10oh m/25 ℃ + RV91
CV637

1 470_0603_5%
2 @
1

2 2 @ 2 2 2 2
@

5 3
PX@

PX@

PX@

PX@

1 2

RV166
1000P_0201_25V7K

1000P_0201_25V7K

1 1 D QV10 470_0603_5%
2 PXS_PWREN#
QV9 PX@ @
CV542

CV543
4

G
2

@ 2 @ 2 S L2N7002KWT1G_SOT323-3
3

PXS_PWREN#_H @
1

1 @ 2 RV1046 D
PXS_PWREN# 2
47K_0402_5% QV19
G 2N7002KW_SOT323-3
@
V20B+ RV92 1 PX@ 2 120K_0402_5% RV1047 1 PX@ 2 220K_0402_5% S
3
1

1 CV213
1

QV11 D RV118
PXS_PWREN# 2 1M_0402_5% 0.1U_0201_25V6-K
G PX@
PX@ 2
2

A L2N7002KWT1G_SOT323-3 S A
3

PX@

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date : Thursday, March 09, 2017 Sheet 24 of 60

5 4 3 2 1
 5 4 3 2 1

UV1C
DQA0_[31..0]
DQA0_[31..0] 26 GDDR5/DDR3 GDDR5/DDR3
DQA0_0 K27 K17 MAA0_0
DQA1_[31..0] DQA0_1 J29 DQA0_0 MAA0_0/MAA_0 J20 MAA0_1
DQA1_[31..0] 27 DQA0_2 H30 DQA0_1 MAA0_1/MAA_1 H23 MAA0_2
DQA0_3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA0_3
DQA0_4 G29 DQA0_3 MAA0_3/MAA_3 G24 MAA0_4
DQA0_5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA0_5
DQA0_6 F32 DQA0_5 MAA0_5/MAA_5 J19 MAA0_6
D DQA0_6 MAA0_6/MAA_6 D
DQA0_7 F30 K19 MAA0_7
DQA0_8 C30 DQA0_7 MAA0_7/MAA_7 G20 MAA0_8
MAA0_[8..0] DQA0_9 F27 DQA0_8 MAA0_8/MAA_13 L17
MAA0_[8..0] 26 DQA0_10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_11 C28 DQA0_10 J14 MAA1_0
MAA1_[8..0] DQA0_12 E27 DQA0_11 MAA1_0/MAA_8 K14 MAA1_1
MAA1_[8..0] 27 DQA0_13 G26 DQA0_12 MAA1_1/MAA_9 J11 MAA1_2
DQA0_14 D26 DQA0_13 MAA1_2/MAA_10 J13 MAA1_3
DQA0_15 F25 DQA0_14 MAA1_3/MAA_11 H11 MAA1_4
DQA0_16 A25 DQA0_15 MAA1_4/MAA_12 G11 MAA1_5
DQA0_17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 MAA1_6
DQA0_18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 MAA1_7
DQA0_19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 MAA1_8
DQA0_20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
DQA0_21 F23 DQA0_20 MAA1_9/RSVD
DQA0_22 D22 DQA0_21 E32 WCKA0_0
DQA0_23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 WCKA0#_0 WCKA0_0 26
DQA0_24 DQA0_23 WCKA0B_0/DQMA0_1 WCKA0_1 WCKA0#_0 26
E21 A21
DQA0_25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 WCKA0#_1 WCKA0_1 26
DQA0_26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 WCKA1_0 WCKA0#_1 26
DQA0_27 DQA0_26 WCKA1_0/DQMA1_0 WCKA1#_0 WCKA1_0 27
A19 D12
DQA0_28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 WCKA1_1 WCKA1#_0 27
DQA0_29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 WCKA1#_1 WCKA1_1 27
DQA0_30 A17 DQA0_29 WCKA1B_1/DQMA1_3 WCKA1#_1 27
DQA0_31 C17 DQA0_30 H28 EDCA0_0
DQA1_0 E17 DQA0_31 EDCA0_0/QSA0_0 C27 EDCA0_1 EDCA0_0 26
DQA1_1 D16 DQA1_0 EDCA0_1/QSA0_1 A23 EDCA0_2 EDCA0_1 26
C DQA1_1 EDCA0_2/QSA0_2 EDCA0_2 26 C
+1.35VGS DQA1_2 F15 E19 EDCA0_3
DQA1_3 A15 DQA1_2 EDCA0_3/QSA0_3 E15 EDCA1_0 EDCA0_3 26
DQA1_4 D14 DQA1_3 EDCA1_0/QSA1_0 D10 EDCA1_1 EDCA1_0 27
DQA1_4 EDCA1_1/QSA1_1 EDCA1_1 27
1

DQA1_5 F13 D6 EDCA1_2

DQA1_6 A13 DQA1_5 EDCA1_2/QSA1_2 G5 EDCA1_3 EDCA1_2 27
RV61
DQA1_7 C13 DQA1_6 EDCA1_3/QSA1_3 EDCA1_3 27
40.2_0402_1%
PX@ DQA1_8 E11 DQA1_7 H27 DDBIA0_0
DQA1_9 DQA1_8 DDBIA0_0/QSA0_0B DDBIA0_1 DDBIA0_0 26
A11 A27
DDBIA0_1 26
2

MVREFD_A DQA1_10 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 DDBIA0_2

DQA1_11 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 DDBIA0_3 DDBIA0_2 26
DQA1_11 DDBIA0_3/QSA0_3B DDBIA0_3 26
1

DQA1_12 A9 C15 DDBIA1_0

1 DQA1_13 DQA1_12 DDBIA1_0/QSA1_0B DDBIA1_1 DDBIA1_0 27
RV65 CV154 C9 E9
DQA1_14 DQA1_13 DDBIA1_1/QSA1_1B DDBIA1_2 DDBIA1_1 27
100_0402_1% 1U_0402_6.3V6K F9 C5
DQA1_15 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 DDBIA1_3 DDBIA1_2 27
PX@ PX@
2 DQA1_16 E7 DQA1_15 DDBIA1_3/QSA1_3B DDBIA1_3 27
2

DQA1_17 A7 DQA1_16 L18 ADBIA0

DQA1_18 C7 DQA1_17 ADBIA0/ODTA0 K16 ADBIA0 26
ADBIA1
DQA1_19 F7 DQA1_18 ADBIA1/ODTA1 ADBIA1 27
DQA1_20 A5 DQA1_19 H26 CLKA0
DQA1_21 E5 DQA1_20 CLKA0 H25 CLKA0 26
CLKA#0
DQA1_22 C3 DQA1_21 CLKA0B CLKA#0 26
DQA1_23 E1 DQA1_22 G9 CLKA1
DQA1_24 G7 DQA1_23 CLKA1 H9 CLKA1 27
CLKA#1
DQA1_25 G6 DQA1_24 CLKA1B CLKA#1 27
+1.35VGS
DQA1_26 G1 DQA1_25 G22 RASA#0
DQA1_27 G3 DQA1_26 RASA0B G17 RASA#0 26
RASA#1
DQA1_27 RASA1B RASA#1 27
1

DQA1_28 J6
B DQA1_28 B
RV62 DQA1_29 J1 G19 CASA#0
DQA1_30 DQA1_29 CASA0B CASA#0 26
40.2_0402_1% J3 G16 CASA#1
DQA1_31 J5 DQA1_30 CASA1B CASA#1 27
PX@
DQA1_31 H22 CSA0#_0
2

MVREFS_A MVREFD_A K26 CSA0B_0 J22 CSA0#_0 26

MVREFS_A J26 MVREFDA CSA0B_1
MVREFSA
1

G13 CSA1#_0
1 CSA1B_0 CSA1#_0 27
RV66 CV157 J25 K13
100_0402_1% 1U_0402_6.3V6K RV55 1 PX@ 2 MEM_CALRP0 K25 NC#J25 CSA1B_1
PX@ PX@ 120_0402_1% MEM_CALRP0 K20 CKEA0
2 CKEA0 CKEA0 26
J17 CKEA1
CKEA1 27
2

CKEA1
G25 WEA#0
WEA0B WEA#0 26
DRAMRST L10 H10 WEA#1
DRAM_RST WEA1B WEA#1 27
PAD @ TV8 1 CLKTESTA K8
PAD @ TV9 1 CLKTESTB L7 CLKTESTA
CLKTESTB

A DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@ A

DRAM_RST 26,27
10_0402_5% 51.1_0402_1%
1

RV58 1
4.99K_0402_1% CV147
PX@ 120P_0402_50V8-J Title
PX@ Security Classification LC Future Center Secret Data
2

2
Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_MEM IF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

Lower 32 bits
DQA0_[31..0] 25
MF=0 No Mirror MF=1 Mirror
MAA0_[8..0] 25
UV5 UV6

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

+1.35VGS A4 DQA0_30 A4 DQA0_7

EDCA0_3 C2 DQ24 DQ0 A2 DQA0_28 EDCA0_0 C2 DQ24 DQ0 A2 DQA0_5
25 EDCA0_3 EDC0 EDC3 DQ25 DQ1 DQA0_31 25 EDCA0_0 EDC0 EDC3 DQ25 DQ1 DQA0_6
C13 B4 C13 B4
EDCA0_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_29 EDCA0_2 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_4
D D
25 EDCA0_1 EDC2 EDC1 DQ27 DQ3 25 EDCA0_2 EDC2 EDC1 DQ27 DQ3
1

R2 E4 DQA0_27 R2 E4 DQA0_3
1 EDC3 EDC0 DQ28 DQ4 DQA0_26 EDC3 EDC0 DQ28 DQ4 DQA0_2
RV1018 CV522 E2 E2 +1.35VGS
2.37K_0402_1% 1U_0402_6.3V6K DQ29 DQ5 F4 DQA0_24 DQ29 DQ5 F4 DQA0_1
@ @ DDBIA0_3 D2 DQ30 DQ6 F2 DQA0_25 DDBIA0_0 D2 DQ30 DQ6 F2 DQA0_0
2 25 DDBIA0_3 DBI0# DBI3# DQ31 DQ7 25 DDBIA0_0 DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
+1.35VGS +1.35VGS
2

DDBIA0_1 P13 DBI1# DBI2# DQ16 DQ8 A13 DDBIA0_2 P13 DBI1# DBI2# DQ16 DQ8 A13 CLKA0 60.4_0402_1% 1 PX@ 2 RV1031
VREFD1_A0 25 DDBIA0_1 DBI2# DBI1# DQ17 DQ9 25 DDBIA0_2 DBI2# DBI1# DQ17 DQ9
+1.35VGS P2 B11 +1.35VGS P2 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13 CLKA#0 60.4_0402_1% 1 PX@ 2 RV1036
DQ19 DQ11 DQ19 DQ11
1

1 CLKA0 J12 E11 CLKA0 J12 E11

25 CLKA0 CK DQ20 DQ12 CK DQ20 DQ12
RV1019 CV361 CLKA#0 J11 E13 CLKA#0 J11 E13
25 CLKA#0 CK# DQ21 DQ13 CK# DQ21 DQ13
5.49K_0402_1% 1U_0402_6.3V6K CKEA0 J3 F11 CKEA0 J3 F11
25 CKEA0 CKE# DQ22 DQ14 CKE# DQ22 DQ14
@ @ F13 F13
2 DQ23 DQ15 U11 DQA0_14 DQ23 DQ15 U11 DQA0_16
2

MAA0_2 H11 DQ8 DQ16 U13 DQA0_12 MAA0_4 H11 DQ8 DQ16 U13 DQA0_18
MAA0_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_15 MAA0_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_17
MAA0_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA0_13 MAA0_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA0_19
MAA0_3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA0_10 MAA0_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA0_22
BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_9 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_20
DQ13 DQ21 M11 DQA0_8 DQ13 DQ21 M11 DQA0_23
MAA0_7 K4 DQ14 DQ22 M13 DQA0_11 MAA0_0 K4 DQ14 DQ22 M13 DQA0_21
MAA0_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MAA0_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4
+1.35VGS MAA0_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MAA0_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2
MAA0_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MAA0_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4
MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2
A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
DQ4 DQ28 DQ4 DQ28
1

1 A5 N2 A5 N2
RV1020 CV524 U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
2.37K_0402_1% 1U_0402_6.3V6K VPP/NC2 DQ6 DQ30 M2 VPP/NC2 DQ6 DQ30 M2
@ @ DQ7 DQ31 DQ7 DQ31
2 J1 +1.35VGS J1 +1.35VGS
+1.35VGS
2

J10 MF J10 MF
VREFD2_A0 1 PX@ 2 RV1017 J13 SEN B1 1 PX@ 2 RV1024 J13 SEN B1
120_0402_1% ZQ VDDQ1 D1 120_0402_1% ZQ VDDQ1 D1
VDDQ2 VDDQ2
1

1 F1 F1
C
RV1021 CV523 ADBIA0 J4 VDDQ3 M1 ADBIA0 J4 VDDQ3 M1 C
25 ADBIA0 ABI# VDDQ4 ABI# VDDQ4
5.49K_0402_1% 1U_0402_6.3V6K RASA#0 G3 P1 CASA#0 G3 P1
25 RASA#0 CSA0#_0 RAS# CAS# VDDQ5 RAS# CAS# VDDQ5
@ @ G12 T1 WEA#0 G12 T1
2 25 CSA0#_0 CS# WE# VDDQ6 CS# WE# VDDQ6
CASA#0 L3 G2 RASA#0 L3 G2
25 CASA#0
2

WEA#0 L12 CAS# RAS# VDDQ7 L2 CSA0#_0 L12 CAS# RAS# VDDQ7 L2
25 WEA#0 WE# CS# VDDQ8 WE# CS# VDDQ8
B3 B3
VDDQ9 D3 VDDQ9 D3
VDDQ10 F3 VDDQ10 F3
WCKA0#_1 D5 VDDQ11 H3 WCKA0#_0 D5 VDDQ11 H3
25 WCKA0#_1 WCKA0_1 WCK01# WCK23# VDDQ12 WCKA0_0 WCK01# WCK23# VDDQ12
D4 K3 D4 K3
25 WCKA0_1 WCK01 WCK23 VDDQ13 WCK01 WCK23 VDDQ13
M3 M3 UV6 SIDE
WCKA0#_0 P5 VDDQ14 P3 WCKA0#_1 P5 VDDQ14 P3 +1.35VGS
+1.35VGS 25 WCKA0#_0 WCKA0_0 WCK23# WCK01# VDDQ15 WCKA0_1 WCK23# WCK01# VDDQ15
P4 T3 P4 T3
25 WCKA0_0 WCK23 WCK01 VDDQ16 WCK23 WCK01 VDDQ16
E5 E5
VDDQ17 N5 VDDQ17 N5
VDDQ18 VDDQ18

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
VREFD2_A0 A10 VREFD1_A0 A10

PX@

PX@
E10 E10

CD@

CD@

CD@

CD@

CD@
VREFD1 VDDQ19 VREFD1 VDDQ19
1

VREFD1_A0 U10 N10 VREFD2_A0 U10 N10

1 VREFC_A0 J14 VREFD2 VDDQ20 VREFC_A0 J14 VREFD2 VDDQ20 1 1 1 1 1 1 1 1
RV1023 CV526 B12 B12 CV562
2.37K_0402_1% 1U_0402_6.3V6K VREFC VDDQ21 D12 VREFC VDDQ21 D12 33P_0402_50V8J
PX@ @ VDDQ22 F12 VDDQ22 F12 RF_PX@
2 VDDQ23 H12 VDDQ23 H12 2 2 2 2 2 2 2 2

CV561

CV553

CV566

CV555

CV567

CV554

CV629
2

DRAM_RST J2 VDDQ24 K12 DRAM_RST J2 VDDQ24 K12

VREFC_A0 25,27 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
M12 M12
VDDQ26 P12 VDDQ26 P12
VDDQ27 VDDQ27
1

1 T12 T12
RV1022 CV525 VDDQ28 G13 VDDQ28 G13
5.49K_0402_1% 1U_0402_6.3V6K H1 VDDQ29 L13 H1 VDDQ29 L13 +1.35VGS
VSS1 VDDQ30 VSS1 VDDQ30 UV6 SIDE
PX@ PX@ K1 B14 K1 B14
2 B5 VSS2 VDDQ31 D14 B5 VSS2 VDDQ31 D14
2

G5 VSS3 VDDQ32 F14 G5 VSS3 VDDQ32 F14

VSS4 VDDQ33 VSS4 VDDQ33

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@

PX@

PX@

PX@
L5 M14 L5 M14

CD@

CD@

CD@
T5 VSS5 VDDQ34 P14 T5 VSS5 VDDQ34 P14
VSS6 VDDQ35 VSS6 VDDQ35 1 1 1 1 1 1 1 1
B10 T14 B10 T14
D10 VSS7 VDDQ36 D10 VSS7 VDDQ36
G10 VSS8 G10 VSS8
B B
L10 VSS9 A1 L10 VSS9 A1 2 2 2 2 2 2 2 2

CV565

CV556

CV559

CV558

CV560

CV557

CV563

CV564
P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1
+1.35VGS T10 VSS11 VSSQ2 E1 T10 VSS11 VSSQ2 E1
UV5 SIDE VSS12 VSSQ3 VSS12 VSSQ3
H14 N1 H14 N1
K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
VSS14 VSSQ5 U1 VSS14 VSSQ5 U1
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

VSSQ6 VSSQ6
PX@

PX@

PX@

PX@

H2 H2
CD@

CD@

CD@

+1.35VGS G1 VSSQ7 K2 +1.35VGS G1 VSSQ7 K2

1 1 1 1 1 1 1 1 VDD1 VSSQ8 VDD1 VSSQ8 UV6 SIDE
CV505 L1 A3 L1 A3 +1.35VGS
33P_0402_50V8J G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3
RF_PX@ L4 VDD3 VSSQ10 E3 L4 VDD3 VSSQ10 E3
2 2 2 2 2 2 2 2 C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
CV85

CV86

CV87

CV88
CV552

CV155

CV628

VDD5 VSSQ12 VDD5 VSSQ12

PX@

PX@

PX@

PX@
R5 R3 R5 R3

CD@

CD@

CD@

CD@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C10 VDD6 VSSQ13 U3 C10 VDD6 VSSQ13 U3
VDD7 VSSQ14 VDD7 VSSQ14 1 1 1 1 1 1 1 1
R10 C4 R10 C4
D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5 2 2 2 2 2 2 2 2

CV573

CV572

CV571

CV575

CV574

CV568

CV569

CV570
+1.35VGS P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10
UV5 SIDE VDD12 VSSQ19 VDD12 VSSQ19
G14 M10 G14 M10
L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

VSSQ22 VSSQ22
PX@

PX@

PX@

A12 A12
CD@

CD@

CD@

CD@

CD@

VSSQ23 C12 VSSQ23 C12 +1.35VGS

1 1 1 1 1 1 1 1 VSSQ24 VSSQ24
E12 E12
VSSQ25 N12 VSSQ25 N12
VSSQ26 R12 VSSQ26 R12
2 2 2 2 2 2 2 2 VSSQ27 VSSQ27

PX@
170-BALL U12 170-BALL U12

CD@
CV551

CV533

CV537

CV535

CV538

CV534

CV549

CV550

10U_0603_6.3V6M

10U_0603_6.3V6M
VSSQ28 H13 VSSQ28 H13
VSSQ29 VSSQ29 1 1
SGRAM GDDR5 K13 SGRAM GDDR5 K13
VSSQ30 A14 VSSQ30 A14
VSSQ31 C14 VSSQ31 C14
VSSQ32 E14 VSSQ32 E14 2 2

CV577

CV576
VSSQ33 N14 VSSQ33 N14
A
+1.35VGS VSSQ34 R14 VSSQ34 R14 A
UV5 SIDE VSSQ35 VSSQ35
U14 U14
VSSQ36 VSSQ36
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
PX@

PX@

PX@

PX@

PX@

@ @
CD@

CD@

CD@

CD@

CD@
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 Security Classification LC Future Center Secret Data Title

CV78

CV79

CV80

CV81

CV82

CV83
CV548

CV545

CV546

CV547

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_VRAM_A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

Upper 32 bits
DQA1_[31..0] 25

MAA1_[8..0] 25 MF=1 Mirror MF=0 No Mirror

UV7 UV8

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

+1.35VGS A4 DQA1_19 A4 DQA1_7

EDCA1_2 C2 DQ24 DQ0 A2 DQA1_18 EDCA1_0 C2 DQ24 DQ0 A2 DQA1_4
25 EDCA1_2 EDC0 EDC3 DQ25 DQ1 DQA1_16 25 EDCA1_0 EDC0 EDC3 DQ25 DQ1 DQA1_6
C13 B4 C13 B4
EDCA1_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_17 EDCA1_3 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_5
D D
25 EDCA1_1 EDC2 EDC1 DQ27 DQ3 25 EDCA1_3 EDC2 EDC1 DQ27 DQ3
1

R2 E4 DQA1_23 R2 E4 DQA1_3
1 EDC3 EDC0 DQ28 DQ4 DQA1_21 EDC3 EDC0 DQ28 DQ4 DQA1_2
RV1025 CV528 E2 E2
2.37K_0402_1% 1U_0402_6.3V6K DQ29 DQ5 F4 DQA1_22 DQ29 DQ5 F4 DQA1_0 +1.35VGS
@ @ DDBIA1_2 D2 DQ30 DQ6 F2 DQA1_20 DDBIA1_0 D2 DQ30 DQ6 F2 DQA1_1
2 25 DDBIA1_2 DBI0# DBI3# DQ31 DQ7 25 DDBIA1_0 DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
+1.35VGS +1.35VGS
2

DDBIA1_1 P13 DBI1# DBI2# DQ16 DQ8 A13 DDBIA1_3 P13 DBI1# DBI2# DQ16 DQ8 A13
VREFD2_A1 25 DDBIA1_1 DBI2# DBI1# DQ17 DQ9 25 DDBIA1_3 DBI2# DBI1# DQ17 DQ9
+1.35VGS P2 B11 +1.35VGS P2 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13 CLKA1 60.4_0402_1% 1 PX@ 2 RV1037
DQ19 DQ11 DQ19 DQ11
1

1 CLKA1 J12 E11 CLKA1 J12 E11

25 CLKA1 CK DQ20 DQ12 CK DQ20 DQ12
RV1026 CV527 CLKA#1 J11 E13 CLKA#1 J11 E13 CLKA#1 60.4_0402_1% 1 PX@ 2 RV1038
25 CLKA#1 CK# DQ21 DQ13 CK# DQ21 DQ13
5.49K_0402_1% 1U_0402_6.3V6K CKEA1 J3 F11 CKEA1 J3 F11
25 CKEA1 CKE# DQ22 DQ14 CKE# DQ22 DQ14
@ @ F13 F13
2 DQ23 DQ15 U11 DQA1_11 DQ23 DQ15 U11 DQA1_30
2

MAA1_4 H11 DQ8 DQ16 U13 DQA1_13 MAA1_2 H11 DQ8 DQ16 U13 DQA1_28
MAA1_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_10 MAA1_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_29
MAA1_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA1_12 MAA1_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA1_31
MAA1_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA1_9 MAA1_3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA1_26
BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_15 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_27
DQ13 DQ21 M11 DQA1_8 DQ13 DQ21 M11 DQA1_24
MAA1_0 K4 DQ14 DQ22 M13 DQA1_14 MAA1_7 K4 DQ14 DQ22 M13 DQA1_25
MAA1_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MAA1_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4
+1.35VGS MAA1_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MAA1_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2
MAA1_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MAA1_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4
MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2
A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
DQ4 DQ28 DQ4 DQ28
1

1 A5 N2 A5 N2
RV1028 CV530 U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
2.37K_0402_1% 1U_0402_6.3V6K VPP/NC2 DQ6 DQ30 M2 VPP/NC2 DQ6 DQ30 M2
@ @ DQ7 DQ31 DQ7 DQ31
2 J1 +1.35VGS J1 +1.35VGS
+1.35VGS
2

J10 MF J10 MF
VREFD1_A1 1 PX@ 2 RV1032 J13 SEN B1 1 PX@ 2 RV1035 J13 SEN B1
120_0402_1% ZQ VDDQ1 D1 120_0402_1% ZQ VDDQ1 D1
VDDQ2 VDDQ2
1

1 F1 F1
C
RV1027 CV529 ADBIA1 J4 VDDQ3 M1 ADBIA1 J4 VDDQ3 M1 C
25 ADBIA1 ABI# VDDQ4 ABI# VDDQ4
5.49K_0402_1% 1U_0402_6.3V6K CASA#1 G3 P1 RASA#1 G3 P1
25 CASA#1 RAS# CAS# VDDQ5 CSA1#_0 RAS# CAS# VDDQ5
@ @ WEA#1 G12 T1 G12 T1
2 25 WEA#1 CS# WE# VDDQ6 CS# WE# VDDQ6
RASA#1 L3 G2 CASA#1 L3 G2
25 RASA#1
2

CSA1#_0 L12 CAS# RAS# VDDQ7 L2 WEA#1 L12 CAS# RAS# VDDQ7 L2
25 CSA1#_0 WE# CS# VDDQ8 WE# CS# VDDQ8
B3 B3
VDDQ9 D3 VDDQ9 D3
VDDQ10 F3 VDDQ10 F3
WCKA1#_1 D5 VDDQ11 H3 WCKA1#_0 D5 VDDQ11 H3
25 WCKA1#_1 WCKA1_1 WCK01# WCK23# VDDQ12 WCKA1_0 WCK01# WCK23# VDDQ12
D4 K3 D4 K3
25 WCKA1_1 WCK01 WCK23 VDDQ13 WCK01 WCK23 VDDQ13
M3 M3
WCKA1#_0 P5 VDDQ14 P3 WCKA1#_1 P5 VDDQ14 P3
+1.35VGS 25 WCKA1#_0 WCKA1_0 WCK23# WCK01# VDDQ15 WCKA1_1 WCK23# WCK01# VDDQ15 UV8 SIDE
P4 T3 P4 T3 +1.35VGS
25 WCKA1_0 WCK23 WCK01 VDDQ16 WCK23 WCK01 VDDQ16
E5 E5
VDDQ17 N5 VDDQ17 N5
VREFD2_A1 A10 VDDQ18 E10 VREFD1_A1 A10 VDDQ18 E10
VREFD1 VDDQ19 VREFD1 VDDQ19

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1

VREFD1_A1 U10 VREFD2_A1 U10

PX@

PX@

PX@
N10 N10

CD@

CD@

CD@

CD@
1 VREFC_A1 J14 VREFD2 VDDQ20 VREFC_A1 J14 VREFD2 VDDQ20
RV1029 CV532 B12 B12 1 1 1 1 1 1 1 1
2.37K_0402_1% 1U_0402_6.3V6K VREFC VDDQ21 D12 VREFC VDDQ21 D12 CV613
PX@ @ VDDQ22 F12 VDDQ22 F12 33P_0402_50V8J
2 VDDQ23 H12 VDDQ23 H12 RF_PX@
2

DRAM_RST J2 VDDQ24 K12 DRAM_RST J2 VDDQ24 K12 2 2 2 2 2 2 2 2

CV611

CV603

CV617

CV605

CV616

CV604

CV631
VREFC_A1 25,26 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
M12 M12
VDDQ26 P12 VDDQ26 P12
VDDQ27 VDDQ27
1

1 T12 T12
RV1030 CV531 VDDQ28 G13 VDDQ28 G13
5.49K_0402_1% 1U_0402_6.3V6K H1 VDDQ29 L13 H1 VDDQ29 L13
PX@ PX@ K1 VSS1 VDDQ30 B14 K1 VSS1 VDDQ30 B14 +1.35VGS
2 VSS2 VDDQ31 VSS2 VDDQ31 UV8 SIDE
B5 D14 B5 D14
2

G5 VSS3 VDDQ32 F14 G5 VSS3 VDDQ32 F14

L5 VSS4 VDDQ33 M14 L5 VSS4 VDDQ33 M14
VSS5 VDDQ34 VSS5 VDDQ34

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@

PX@

PX@
T5 P14 T5 P14

CD@

CD@

CD@

CD@
B10 VSS6 VDDQ35 T14 B10 VSS6 VDDQ35 T14
VSS7 VDDQ36 VSS7 VDDQ36 1 1 1 1 1 1 1 1
D10 D10
G10 VSS8 G10 VSS8
B B
L10 VSS9 A1 L10 VSS9 A1
P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1 2 2 2 2 2 2 2 2

CV614

CV606

CV610

CV608

CV609

CV607

CV612

CV615
+1.35VGS T10 VSS11 VSSQ2 E1 T10 VSS11 VSSQ2 E1
UV7 SIDE VSS12 VSSQ3 VSS12 VSSQ3
H14 N1 H14 N1
K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
VSS14 VSSQ5 U1 VSS14 VSSQ5 U1
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

VSSQ6 VSSQ6
PX@

PX@

PX@

H2 H2
CD@

CD@

CD@

CD@

+1.35VGS G1 VSSQ7 K2 +1.35VGS G1 VSSQ7 K2

1 1 1 1 1 1 1 1 VDD1 VSSQ8 VDD1 VSSQ8
CV596 L1 A3 L1 A3
33P_0402_50V8J G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3 +1.35VGS
VDD3 VSSQ10 VDD3 VSSQ10 UV8 SIDE
RF_PX@ L4 E3 L4 E3
2 2 2 2 2 2 2 2 C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
CV586

CV579

CV601

CV580

CV602

CV578

CV630

R5 VDD5 VSSQ12 R3 R5 VDD5 VSSQ12 R3

VDD6 VSSQ13 VDD6 VSSQ13

PX@

PX@

PX@

PX@
C10 U3 C10 U3

CD@

CD@

CD@

CD@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
R10 VDD7 VSSQ14 C4 R10 VDD7 VSSQ14 C4
VDD8 VSSQ15 VDD8 VSSQ15 1 1 1 1 1 1 1 1
D11 R4 D11 R4
G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5
+1.35VGS P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10 2 2 2 2 2 2 2 2
UV7 SIDE

CV623

CV621

CV622

CV625

CV624

CV618

CV619

CV620
G14 VDD12 VSSQ19 M10 G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

VSSQ22 VSSQ22
PX@

PX@

PX@

PX@

A12 A12
CD@

CD@

CD@

CD@

VSSQ23 C12 VSSQ23 C12

1 1 1 1 1 1 1 1 VSSQ24 VSSQ24
E12 E12 +1.35VGS
VSSQ25 N12 VSSQ25 N12
VSSQ26 R12 VSSQ26 R12
2 2 2 2 2 2 2 2 170-BALL VSSQ27 U12 170-BALL VSSQ27 U12
CV600

CV581

CV585

CV582

CV584

CV583

CV598

CV599

VSSQ28 VSSQ28

PX@
H13 H13

CD@

10U_0603_6.3V6M

10U_0603_6.3V6M
SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
VSSQ30 VSSQ30 1 1
A14 A14
VSSQ31 C14 VSSQ31 C14
VSSQ32 E14 VSSQ32 E14
VSSQ33 N14 VSSQ33 N14 2 2

CV627

CV626
A
+1.35VGS VSSQ34 R14 VSSQ34 R14 A
UV7 SIDE VSSQ35 VSSQ35
U14 U14
VSSQ36 VSSQ36
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
PX@

PX@

PX@

PX@

PX@

@ @
CD@

CD@

CD@

CD@

CD@
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 Security Classification LC Future Center Secret Data Title

CV597

CV595

CV591

CV592

CV590

CV593

CV594

CV587

CV588

CV589

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_VRAM_B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

B+ to +LEDVDD POWER CMOS CAMERA

LCD POWER CIRCUIT
+LCDVDD_CON +3VS Need Short +3VS_CMOS_R
+3VS +LEDVDD J1 @
U9 V20B+ 1 2
5 1 R4712 1 @ 2 0_0805_5% W=60mils 2A 80 mil 2A 80 mil
1 2
IN OUT R263 1 @ 2 0_0805_5% JUMP_43X39
1U_0402_6.3V6K

0.1U_0201_6.3V6-K
1 2 +3VS_CMOS
GND

33P_0402_50V8J

4.7U_0805_25V6-K

0.1U_0201_25V6-K
4.7U_0402_6.3V6M
C1

CD@
C25
PCH_ENVDD 4 3
EN OCB 1 1 1 1 1 C23 LP2301ALT1G_SOT23-3 W=40mils

C122

C4953
2 W=40 mils

C2
Q7 3 1 @ 1 2 0_0603_5%

D
R3 @

10U_0603_6.3V6M
0.1U_0201_6.3V6-K

0.01U_0201_6.3V7-K

0.1U_0201_6.3V6-K
SY6288C20AAC_SOT23-5 EMC@
2 2 2 2 2

EMC_NS@

RF@
D D

G
1 1 1 1

2
C5 C6 C3
PCH_ENVDD C4964
6 PCH_ENVDD
1

C23 0.1u for G HSW panel blink issue @ @

@2 2 2 2

CD@
R35
100K_0402_5%
R5 1 @ 2 0_0402_5%
44 CMOS_ON#
For RF request: keep 0402
2

0.1U_0201_6.3V6-K
1
1
C9 C10
APL SoC output enable Voh min is 1.8V-0.45V=1.35V +3VS 0.01U_0201_6.3V7-K
2 @ @
2
For EMI
Close to R5

2
INVT_PWM

100K_0402_1%
R19 1 @ 2 0_0402_5%
6 PCH_EDP_PWM

R8
1

R20

1
100K_0402_5%
@ @
EDP_AUX#
2

EDP_AUX
JEDP1
+LEDVDD 1
+3VS 2 1
2

100K_0402_1%
3
4 3
4
2

CPU_EDP_TX0+ EDP_TX0+

R9
C19 2 1 0.1U_0201_6.3V6-K 5
6 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 5
R10 C16 2 1 0.1U_0201_6.3V6-K 6
6 CPU_EDP_TX0- 6
4.7K_0402_5% 7

1
@ CPU_EDP_TX1+ C17 2 1 0.1U_0201_6.3V6-K EDP_TX1+ 8 7
C 6 CPU_EDP_TX1+ CPU_EDP_TX1- EDP_TX1- 8 C
@ C18 2 1 0.1U_0201_6.3V6-K 9
6 CPU_EDP_TX1-
1

10 9
R12 1 @ 2 0_0402_5% DISPOFF# CPU_EDP_AUX C20 2 1 0.1U_0201_6.3V6-K EDP_AUX 11 10
44 BKOFF# 6 CPU_EDP_AUX CPU_EDP_AUX# C21 EDP_AUX# 11
2 1 0.1U_0201_6.3V6-K 12
6 CPU_EDP_AUX# 12
13
R14 1 @ 2 0_0402_5% ENBKL DISPOFF# 14 13
6 PCH_ENBKL ENBKL 44 AUX do NOT reserve pull high and pull low for eDP panel 15 14
15
1

INVT_PWM 16
R16 L12 EMC_NS@ 17 16
100K_0402_5% USB20_N6 1 2 USB20_N6_R +3VS 18 17
1 2 19 18
6 CPU_EDP_HPD 19
R21 1 @ 2 20
2

USB20_P6 4 3 USB20_P6_R 0_0402_5% 21 20

4 3 +LCDVDD_CON 21

470P_0201_50V7-K
22
EXC24CH900U_4P
W=60mils 23 22
1 +3VS 23

C22

EMC_NS@
34 DMIC_DATA 24
25 24
34 DMIC_CLK 25
26
DMIC_CLK DISPOFF# INVT_PWM 2 27 26
USB20_P6 R182 1 @ 2 0_0402_5% USB20_P6_R 28 27
11 USB20_P6 USB20_N6 USB20_N6_R 28

470P_0201_50V7-K

470P_0201_50V7-K
100P_0201_25V8J

R183 1 @ 2 0_0402_5% 29
11 USB20_N6 29
C11

1 1 1 +3VS_CMOS 30
30
EMC@

C12

C13
EMC_NS@

EMC_NS@
1 31
C1320 32 G1
.047U_0201_6.3V6K
W=40mils G2
2 2 2 EMC_NS@ DRAPH_FC5AF301-3181H
2
ME@

EMC

B B

Touch Screen
Touch Screen

USB20_P2_CONN
+5VS +5VS_TS
L15 USB20_N2_CONN
USB20_P2 1 2 USB20_P2_CONN
1 2
3

+5VS_TS R26 1 TS@ 2 0_0402_5%

1 JTS1 ME@
USB20_N2 4 3 USB20_N2_CONN C4998 1
4 3 1
1

D46 0.1u_0201_10V6K 2 7
EXC24CH900U_4P TS@ R28 2 TS@ 1 0_0402_5% TS_RS 3 2 GND1
1

2 44 EC_TS_ON 3
EMC_NS@ 4 8
R23 1 TS@ 2 0_0402_5% USB20_N2_CONN 5 4 GND2
11 USB20_N2 USB20_P2_CONN 5
D45 R24 1 TS@ 2 0_0402_5% 6
11 USB20_P2 6
AZC199-02S.R7G_SOT23-3
2

EMC_NS@ CVILU_CI1806M2HR0-NH
For EMI AZ5725-01F.R7GR_DFN1006P2X2
2

A A
EMC_NS@
1

For ESD

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/CMOS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 28 of 58

5 4 3 2 1
 5 4 3 2 1

+3VS
+3VALW Equalizer control and program for channel A
3.3V tolerant. Internally pulled down at ~150K
RW31 1 @ 2 0_0402_5% USB30_TX_P0 R4713 1 @ 2 0_0201_5% USB30_TX_P0_R @ CW36 1 2 0.1U_0201_6.3V6-K USB30_TX_P0_M [A_EQ1, A_EQ0] ==
USB_EQ1_A RW19 1 @ 2 4.7K_0402_5% LL: program EQ for channel loss up to 9.5dB(default)
+3VS USB30_TX_N0 R4714 1 @ 2 0_0201_5% USB30_TX_N0_R @ CW37 1 2 0.1U_0201_6.3V6-K USB30_TX_N0_M LH: program EQ for channel loss up to 13dB
RW32 1 @ 2 0_0402_5% USB_EQ0_A RW20 1 @ 2 4.7K_0402_5% HL: program EQ for channel loss up to 4.5dB
USB30_RX_P0 R4716 1 @ 2 0_0201_5% USB30_RX_P0_R @ CW38 1 2 0.1U_0201_6.3V6-K USB30_RX_P0_M HH: program EQ for channel loss up to 7.5dB
U3 USB30_RX_N0 R4715 1 @ 2 0_0201_5% USB30_RX_N0_R @ CW39 1 2 0.1U_0201_6.3V6-K USB30_RX_N0_M +3VS
1 1
1 Programmable output de-emphasis level setting for channel A
CW32 CW33 13 VDD1
3.3V tolerant. Internally pulled down at ~150K
.1U_0402_10V6-K VDD2 USB_DE0_A RW21 1 @ 2 4.7K_0402_5%
.1U_0402_10V6-K [A_DE1, A_DE0] ==
2 2 LL: 3.5dB de-emphasis (default)
@ @ USB_EQ1_A USB_EQ1_B USB_DE1_A
15 4 RW22 1 @ 2 4.7K_0402_5% LH: No de-emphasis
USB_DE0_A 16 A_EQ1_SDA_CTL B_EQ1_I2C_ADDR1 3 USB_DE0_B HL: 2.7dB de-emphasis
USB_EQ0_A 17 A_DE0_SCL_CTL B_DE0_I2C_ADDR0 2 USB_EQ0_B HH: 5dB de-emphasis
USB_DE1_A 18 A_EQ0_NC B_EQ0_NC 6 USB_DE1_B
A_DE1_NC B_DE1_NC +3VS Equalizer control and program for channel B
CW30 1 @2 0.1U_0201_6.3V6-K USB30_TX_P0_C 19 12 USB30_TX_P0_U 3.3V tolerant. Internally pulled down at ~150K
11 USB30_TX_P0 A_INp A_OUTp
CW31 1 2 0.1U_0201_6.3V6-K USB30_TX_N0_C 20 11 USB30_TX_N0_U [B_EQ1, B_EQ0] ==
11 USB30_TX_N0 A_INn A_OUTn USB_EQ1_B
D @ RW23 1 @ 2 4.7K_0402_5% LL: program EQ for channel loss up to 9.5dB(default) D
LH: program EQ for channel loss up to 13dB
USB30_RX_P0_U 9 22 USB30_RX_P0_C CW34 1 @2 0.1U_0201_6.3V6-K USB_EQ0_B RW24 1 @ 2 4.7K_0402_5% HL: program EQ for channel loss up to 4.5dB
USB30_RX_N0_U B_INp B_OUTp USB30_RX_N0_C USB30_RX_P0 11
8 23 CW35 1 2 0.1U_0201_6.3V6-K HH: program EQ for channel loss up to 7.5dB
B_INn B_OUTn USB30_RX_N0 11
@
@ +3VS
TP52 1 USB_PD# 5 Programmable output de-emphasis level setting for channel B
REXT 7 PD# 10 3.3V tolerant. Internally pulled down at ~150K
TEST 14 REXT GND1 21 USB_DE0_B RW25 1 @ 2 4.7K_0402_5% [B_DE1, B_DE0] ==
24 TEST GND2 25 LL: 3.5dB de-emphasis (default)
I2C_EN GPAD
1

USB_DE1_B RW26 1 @ 2 4.7K_0402_5% LH: No de-emphasis

RW30 PS8713BTQFN24GTR2A_TQFN24_4X4 HL: 2.7dB de-emphasis
4.99K_0402_1% @ HH: 5dB de-emphasis
@ +3VS
LFPS swing adjust.
2

3.3V tolerant. Internally pulled down at ~150KΩ

8/31 Follow Vendor suggestion change from 3.9K to 4.99K wei TEST==
TEST RW27 1 @ 2 4.7K_0402_5% L: Normal LFPS swing(default)
H:Turn down LFPS swing

+3VALW
+3V_MUX +5VALW +5V_MUX
R133 1 @ 2 0_0402_5% R173 1 @ 2 0_0402_5% +5VALW VBUS_P0
VBUS_P0
+3VS +5VS
R134 1 @ 2 0_0402_5% R174 1 @ 2 0_0402_5%
1
1
+
3A
C1333
C213 150U_B2_6.3VM_R35M
47U_0805_6.3V6-M @ @
2 2
U26
U6
TYPE_C_OCP# 2 2
16 6 1

25
26
27
28
VBUS_EN 15 OCP_DET CC1271 CC1272 IN OUT JP1 ME@
VBUS_EN @ 220P_0201_25V7-K @ 220P_0201_25V7-K R9426 1 @ 2 3.3K_0402_1% 5 2

GND5
GND6
GND7
GND8
1 1 ISET GND
VMON 17 12 CC1 A5 VBUS_EN 4 3 TYPE_C_OCP# 24 1
C VMON CC1 EN/ENB OCB TYPE_C_OCP# 11 Power_GND_B12 GND_A1 C
14 CC2 B5
CC2 @ C_RX1_P_C 23 2 C_TX1_P_C
SY6861B1ABC_SOT23-6 SSRXp1_B11 SSTXp1_A2
11 MUX_TX2_N C2076 1@ 2 0.1U_0201_6.3V6-K C_TX2_N B3 C_RX1_N_C 22 3 C_TX1_N_C
C_TX2_1P/2N 10 MUX_TX2_P C2075 1@ 2 0.1U_0201_6.3V6-K C_TX2_P B2 SSRXn1_B10 SSTXn1_A3
C_TX2_1N/2P 21 4
USB30_RX_N0_U C2068 1@ 2 0.1U_0201_6.3V6-K USB30_RX_N0_M 4 24 C_RX2_N A10 VBUS_B9 VBUS_A4
USB30_RX_P0_U C2067 1@ 2 0.1U_0201_6.3V6-K USB30_RX_P0_M 5 SSRX_1P/2N
SSRX_1N/2P
10Gbps 2:1 MUX
C_RX2_1P/2N 1
C_RX2_1N/2P
C_RX2_P A11 ILIM (A)=6800/R9426 (Ω ) 20
SBU2_B8 CC1_A5
5 CC1
USB30_TX_N0_U C2065 1@ 2 0.1U_0201_6.3V6-K USB30_TX_N0_M 6 8 MUX_TX1_N C2073 1@ 2 0.1U_0201_6.3V6-K C_TX1_N A3 C_DM 19 6 C_DP
USB30_TX_P0_U C2066 1@ 2 0.1U_0201_6.3V6-K USB30_TX_P0_M 7 SSTX_1P/2N C_TX1_1P/2N 9 MUX_TX1_P C2074 1@ 2 0.1U_0201_6.3V6-K C_TX1_P A2 Dn2_B7 Dp1_A6
SSTX_1N/2P C_TX1_1N/2P C_DP 18 7 C_DM
2 C_RX1_N B10 Dp2_B6 Dn1_A7
C_RX1_1P/2N 3 C_RX1_P B11 CC2 17 8
C_RX1_1N/2P CC2_B5 SBU1_A8
+5V_MUX 16 9
13 VBUS_B4 VBUS_A9
VCON_IN C_TX2_N_C 15 10 C_RX2_N_C
23 Realtek +3V_MUX VBUS_P0 SSTXn2_B3 SSRXn2_A10
NC VBUS_P0 C_TX2_P_C C_RX2_P_C

10U_0805_10V6K
M1 21 19 14 11

0.1u_0201_10V6K
22 RP_SEL_M1 5V_IN SSTXp2_B2 SSRXp2_A11
M0
RP_SEL_M0 RTS5449 2 2
20 13 12
C2063

C2077
LDO_3V3 GND_B1 GND_A12

1
0.1u_0201_10V6K

GND12
GND11
GND10
4.7U_0402_6.3V6M

GND9
1 2
18 25 @ 1 @ 1 R3155
C2064
CC1273

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K
REXT E-PAD 200K_0402_1%

AZ5425-01F_DFN1006P2E2
@
2

1
D38 1 1 1 HIGHS_UB11246-15A0C-1H

32
31
30
29
1

1
R3150 RTS5449-GR_QFN24_4X4 @ 2 @ 1

C918

C919

C922

C921

C920

C1334
1
VMON

EMC@
6.2K_0402_1% @
@ Close Pin13 @ @ @ @ @ @

2
2 2 2
1

2
Close Pin19 R3149
10K_0402_1% 09/02 Update Type-C Conn. DC021608291 wei

2
@

1
+3V_MUX +3V_MUX
Rp configuration
2

Rp:1.5A (now)
R3139 R3142
10K_0402_5% @ 10K_0402_5%
B @ M1 M0 Note B

Rp:900mA 0 1 R3144/R3142 mount

1

M1 M0 R943 1 @ 2 0_0402_5% R3135 1 @ 2 0_0402_5%

Rp:1.5A 1 0 R3139/R3143 mount
2

L23 EMC_NS@ L31 EMC_NS@

R3144 R4674 Rp:3.0A 1 1 R3139/R3142 mount 1 2 C_DP C_RX1_N 4 3 C_RX1_N_C
11 USB20_P0 1 2 4 3 C_DP
@ 10K_0402_5% @ 10K_0402_5% CC1

4 3 C_DM C_RX1_P 1 2 C_RX1_P_C CC2 C_DM

11 USB20_N0
1

4 3 1 2
EXC24CH900U_4P EXC24CH900U_4P
R3137 1 @

2
2 0_0402_5%
R91 1 @ 2 0_0402_5% D50 D51
AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3
+3V_MUX R3136 1 @ 2 0_0402_5% EMC_NS@ EMC_NS@
For C_VBUS @
R944 2 1 0_0402_5%
power switch enable pin L32 EMC_NS@
2

L24 EMC_NS@ C_TX1_P 4 3 C_TX1_P_C

R3146 C_TX2_N 3 4 C_TX2_N_C 4 3
@ 10K_0402_5% 3 4
1 2
C_TX2_P 2 1 C_TX2_P_C 1 2
Power switch enable pin Note
1

2 1 EXC24CH900U_4P

1
VBUS_EN EXC24CH900U_4P C_TX1_N R3138 1 @ 2 0_0402_5% C_TX1_N_C
Low Active R3146 mount
@
2

R3107 2 1 0_0402_5%
R3141 High Active R3141 mount
@ 10K_0402_5%
R100 2 @ 1 0_0402_5%
1

L25 EMC_NS@
C_RX2_P 3 4 C_RX2_P_C D36 EMC_NS@ D20 EMC_NS@
3 4 C_TX2_P_C 9 10 C_TX2_P_C C_TX1_P_C C_TX1_P_C
1 1 9 10 1 1
C_RX2_N 2 1 C_RX2_N_C C_TX2_N_C 8 2 C_TX2_N_C C_TX1_N_C 8 2 C_TX1_N_C
9 2 9 2
+3V_MUX 2 1
For C_VBUS C_RX1_N_C 7 C_RX1_N_C C_RX2_N_C 7 C_RX2_N_C
EXC24CH900U_4P 7 4 4 7 4 4
power switch OCP pin
@
2

R101 2 1 0_0402_5% C_RX1_P_C 6 5 C_RX1_P_C C_RX2_P_C 6 5 C_RX2_P_C

6 5 6 5
R3147
@ 10K_0402_5% 3 3 3 3

Note 8 8
Power switch OCP pin
1

A TYPE_C_OCP# AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 A

Low Active R3147 mount For ESD
High Active R3140 mount
2

R3140
@ 10K_0402_5%
1

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 3D Camera
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 29 of 58
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 BLANK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 30 of 58
5 4 3 2 1
 5 4 3 2 1

+USB_VCCA
USB3.0 Port X 1
C55 1 2

+
220U_6.3V_M

C1117 1 2
@ 47U_0805_6.3V6-M

C125 1 2
@ 1U_0402_10V6K
+5VALW +USB_VCCA C127 1 2
U2 @ 1U_0402_10V6K
D D
5 1
IN OUT JUSB1 ME@
1
C128 2
1U_0402_6.3V6K GND USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
USB_OC1# 11 USB30_TX_P1 StdA_SSTX+
44 USB_ON# 4 3 1
2 ENB OCB USB_OC1# 11 USB30_TX_N1 C124 1 2 0.1u_0201_10V6K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
11 USB30_TX_N1 USB20_P1 1 2 0_0402_5% USB20_P1_R 3 StdA_SSTX-
SY6288D20AAC_SOT23-5 1 R97 @
11 USB20_P1 D+
C140 7
1000P_0201_50V7-K USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
11 USB20_N1 USB30_RX_P1 USB30_RX_R_P1 D- GND_2
Low Active 2A EMC_NS@ R94 1 @ 2 0_0402_5% 6 11
2 11 USB30_RX_P1 StdA_SSRX+ GND_3
4 12
USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
11 USB30_RX_N1 StdA_SSRX- GND_5

ALLTO_C190AG-10939-L

09/05 Update USBConn. P/N DC021609011 wei

L13 EMC@
USB30_RX_N1 1 2 USB30_RX_R_N1
1 2

USB30_RX_P1 4 3 USB30_RX_R_P1
4 3
EXC24CH900U_4P USB20_P1_R
+USB_VCCA
USB20_N1_R D12 EMC@
L16 EMC@ USB30_RX_R_N1 9 10 1USB30_RX_R_N1
1
USB30_TX_C_N1 1 2 USB30_TX_R_N1

AZ5725-01F.R7GR_DFN1006P2X2

2
1 2 D11 USB30_RX_R_P1 8 2 USB30_RX_R_P1
9 2
D13

1
USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 7 4USB30_TX_R_N1
4 3 4
EMC@
EXC24CH900U_4P USB30_TX_R_P1 6 6 5 USB30_TX_R_P1
5

2
C 3 3 C
EMC@

2
L8 EMC@ 8
USB20_P1 1 2 USB20_P1_R
1 2 AZ1045-04F_DFN2510P10E-10-9

1
USB20_N1 4 3 USB20_N1_R
4 3
EXC24CH900U_4P
EMC
EMC

+USB_VCCA

USB20_N3_R

USB20_P3_R
1 1
C4995 C4996
470P_0402_50V7K 1U_0603_25V6M

2
2 2
@ Close to Connector
D48
B @ B
L1 AZC199-02S.R7G_SOT23-3
JUSB3 USB20_P3 1 2 USB20_P3_R EMC@
1 1 2
USB20_N3 R4690 1 @ 2 0_0402_5% USB20_N3_R 2 VBUS
11 USB20_N3 USB20_P3 USB20_P3_R D- USB20_N3 USB20_N3_R
R4691 1 @ 2 0_0402_5% 3 4 3
11 USB20_P3 D+ 4 3
4 5
GND GND1 6 EXC24CH900U_4P
GND2 7
GND3 8
GND4

1
ALLTO_C147L3-40439-L
ME@

FOR ESD
Update footprint symbol lewis

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3.0&USB2.0 CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 31 of 58
5 4 3 2 1
 5 4 3 2 1

+5VS_HDMI
+5VALW

LBAT54AWT1G_SOT323-3
RP11
D8

1
HDMICLK_R 4 1

2
L2 EMC@ HDMIDAT_R 3 2
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2 EMC_NS@ R4661 R4660
1 2 @
C26 10P_0201_25V8G 0_0402_5% 0_0402_5% 2.2K_0404_4P2R_5%
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2 EMC_NS@ @ @

1
4 3 C27 10P_0201_25V8G
EXC24CH900U_4P +5VS_HDMI

L3 EMC@
D HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 EMC_NS@ +1.8V_PU D
1 2 C28 10P_0201_25V8G

3
4
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 EMC_NS@
4 3 C29 10P_0201_25V8G
RP10
EXC24CH900U_4P

5
2.2K_0404_4P2R_5%

G
2
L4 EMC@ Q163B

2
1
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2 EMC_NS@ @

G1
1 2 C30 10P_0201_25V8G
DDPB_CLK 1 S1 D1 6 HDMICLK_R_Q HDMICLK_R_Q 3 4 HDMICLK_R

S
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 EMC_NS@ 6 DDPB_CLK

D
4 3 C31 10P_0201_25V8G L2N7002KDW1T1G_SOT363-6
EXC24CH900U_4P
Q157A R4662 1 @ 2 0_0402_5%
L5 EMC@ PJT138K_SOT363-6

2
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 EMC_NS@

G
1 2

G2 5
C32 10P_0201_25V8G Q163A
@
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2 EMC_NS@
4 3 C33 10P_0201_25V8G DDPB_DATA 4 S2 D2 3 HDMIDAT_R_Q HDMIDAT_R_Q 6 1 HDMIDAT_R

S
6 DDPB_DATA
EXC24CH900U_4P

D
Follow BMWC1: PJT138K[Vgs(th)=1.5V] L2N7002KDW1T1G_SOT363-6
EMC EMC request stuff caps 03/09 SCH CKL request MOSFET output capacitance less than 10pF
Q157B R4663 1 @ 2 0_0402_5%
PJT138K_SOT363-6
+5VS_HDMI
+1.8V_PU

2
+5VS +5VS_HDMI_F +5VS_HDMI
D4 D5
Follow PDG & CRB use 470ohm

1
2 @ F1
C RP12 R4657 1 1 2 C
HDMI_CLK-_C 2 3 100K_0402_5% @ LBAT54SWT1G_SOT323-3 3
HDMI_CLK+_C 1 4 SCH CKL request Diode Cap less than 10pF RB491D_SOT23-3 0.5A_6V_1206L050YRHF

1
2
470_0404_4P2R_1% HDMI_HPD#
6 HDMI_HPD#
RP13 LP2301ALT1G_SOT23-3 1
HDMI_TX0-_C

1
2 3 C34
HDMI_TX0+_C 1 4 Q162 1 3 Q22 0.1u_0201_10V6K

S
C
470_0404_4P2R_1% B 2 R4656 1 2 150K_0402_5% HDMI_DET 2
RP14 LMBT3904WT1G_SOT323-3

G
2
2
HDMI_TX1-_C 2 3
HDMI_TX1+_C
E
1 4 R41
Follow AMD Circuit 100K_0402_5%
46 SUSP
3

470_0404_4P2R_1%
RP15 JHDMI1 ME@

1
HDMI_TX2-_C 2 3
HDMI_TX2+_C 1 4 18 15 HDMICLK_R
+5V_Power SCL 16 HDMIDAT_R
Change to 0404 RP 04/29 470_0404_4P2R_1% SDA
HDMI_TX0+ C38 2 1 0.1u_0201_10V6K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
6 HDMI_TX0+ TMDS_Data0+
1

Q13 D HDMI_TX0- C37 2 1 0.1u_0201_10V6K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 13

6 HDMI_TX0- HDMI_TX1+ HDMI_TX1+_C HDMI_TX1+_CON TMDS_Data0- CEC
2 C40 2 1 0.1u_0201_10V6K R48 2 @ 1 0_0402_5% 4 17
+3VS 6 HDMI_TX1+ HDMI_TX1- HDMI_TX1-_C HDMI_TX1-_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
G C39 2 1 0.1u_0201_10V6K R47 2 @ 1 0_0402_5% 6 19
6 HDMI_TX1- HDMI_TX2+ HDMI_TX2+_C HDMI_TX2+_CON TMDS_Data1- Hot_Plug_Detect
C42 2 1 0.1u_0201_10V6K R50 2 @ 1 0_0402_5% 1
6 HDMI_TX2+ HDMI_TX2- HDMI_TX2-_C HDMI_TX2-_CON TMDS_Data2+
S L2N7002KWT1G_SOT323-3 C41 2 1 0.1u_0201_10V6K R49 2 @ 1 0_0402_5% 3
6 HDMI_TX2-
3

TMDS_Data2-
R42 1 @ 2 8 14
5 TMDS_Data0_Shield Utility
100K_0402_5% 2 TMDS_Data1_Shield
TMDS_Data2_Shield
20
B 11 GND1 21 B
HDMI_CLK+ C36 2 1 0.1u_0201_10V6K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
6 HDMI_CLK+ HDMI_CLK- HDMI_CLK-_C R43 2 HDMI_CLK-_CON TMDS_Clock+ GND3
C35 2 1 0.1u_0201_10V6K @ 1 0_0402_5% 12 23
6 HDMI_CLK- TMDS_Clock- GND4

8/16 Update HDMIConn. P/N DC021608081 wei

D6 D7 ALLTO_C128S9-K1935-L
HDMI_CLK+_CON 1 1 HDMI_CLK+_CON HDMI_TX1-_CON HDMI_TX1-_CON
10 9 1 1 10 9
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON HDMI_TX0+_CON HDMI_TX2-_CON HDMI_TX2-_CON Intel PDG & CRB Suggestion Circuit
4 4 7 7 4 4 7 7
+1.8V_PU
HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

3 3 3 3

2
8 8
R3405
1K_0402_1%
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@

1
EMC HDMI_HPD# @

Follow CG711

1
D3 D Q12
HDMI_DET 1 1 HDMI_DET HDMI_DET
10 9 2
G
HDMICLK_R 2 2 9 8 HDMICLK_R
L2N7002KWT1G_SOT323-3 S
A HDMIDAT_R 4 4 7 7 HDMIDAT_R 3
Vgs<=2.0V A
@
+5VS_HDMI 5 5 6 6 +5VS_HDMI Intel PDG suggest use N-MOSFET Vgs<=1.5V
3 3

Security Classification LC Future Center Secret Data Title

AZ1045-04F_DFN2510P10E-10-9 Issued Date 2013/08/15 Deciphered Date 2013/08/15 HDMI_CONN
EMC_NS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
EMC AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 32 of 58
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 33 of 58
5 4 3 2 1
 5 4 3 2 1

DVDD_IO +1.8VS +1.8V_AUDIO

+3VALW
RA225 1 @ 2 0_0402_5%
RA213 1 @ 2 0_0402_5% Digital power for HDA link
+1.8VALW 8/29 Add +1.8VS Circuit for Audio wei
+1.8VS
2
RA216 1 @ 2 0_0402_5% RA226 1 @ 2 0_0402_5%
CA2
+1.8VALW 0.1U_0201_6.3V6-K UA1
RA227 1 @ 2 0_0402_5% Close to1 Pin7
DMIC_DATA RA19 1 @ DMIC_DATA_R
2 0_0402_5% 1 30
28 DMIC_DATA DMIC_CLK DMIC_CLK_R HD-GPIO0/DMIC-DATA CR-GPIO SD_CD#
RA18 1 @ 2 0_0402_5% 2 31
28 DMIC_CLK HDA_SDOUT_AUDIO 3 HD-GPIO1/DMIC-CLK CR-SD-CD 32 SD_WP SD_CD# 35
12 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO HD-SDATA-OUT CR-SD-WP SD_D1_R SD_WP 35
4 33
D 12 HDA_BITCLK_AUDIO HD-BCLK CR-SD-DAT[1] SD_D0_R SD_D1_R 35 D
CA1 1 2 2.2U_0402_6.3V6M 5 34
Analog power for mixers, & IO ports Power supply for full-bridge left/Right channel HDA_SDIN0 RA16 1 2 33_0402_5% SDATA_IN 6 HD-LDO3-CAP CR-SD-DAT[0] 35 SD_CLK_R SD_D0_R 35
+5VS +5VA +5VS +5VD 12 HDA_SDIN0 HD-SDATA-IN CR-SD-CLK SD_CLK_R 35
DVDD_IO 7 36 +5VA
EMC_NS@ HDA_SYNC_AUDIO 8 HD-DVDD-IO HD-AVDD1 37 LDO1_CAP CA43 1 2 2.2U_0402_6.3V6M CA48 1 2 1U_0402_6.3V6K
12 HDA_SYNC_AUDIO HD-SYNC HD-LDO1-CAP
LA25 1 2 BLM15PD600SN1D_2P +3VS RA205 1 2 100K_0402_1% PC_BEEP 9 38 CA44 1 2 1U_0402_6.3V6K
RA7 1 @ 2 0_0603_5% PLUG_IN RA204 1 2 200K_0402_1% JSENSE 10 HD-PCBEEP HD-VREF 39 MICBIASB
RA10 1 EMC@ 2 0_0603_5% RING2_CONN 11 HD-JD1(HP/LINE1) HD-MIC2-VREFO 40 LINE1_VREF_L +1.8V_AUDIO
RING3_CONN 12 HD-MIC2-L(RING) HD-LINE1-VREFO-L 41 HPOUT_L
VDD_STB HD-MIC2-R(SLEEVE) HD-HPOUT-L HPOUT_R
0.1U_0201_6.3V6-K

1U_0402_6.3V6K

2 2 13 42
HD-3V5V-STB HD-HPOUT-R +1.8V_AUDIO

CA178
10U_0805_10V6K

CA18 0.1U_0201_6.3V6-K

CA19 0.1U_0201_6.3V6-K
1 2 2 1 RA38 2 2.2K_0402_5% CA41 1 2 2.2U_0402_6.3V6M 14 43 CA47 1 2 1U_0402_6.3V6K
CA42 CA20 LINE1_R 15 HD-MIC2-CAP HD-CPVEE 44
MICBIASB 1 RA37 2 2.2K_0402_5% LINE1_L 16 HD-LINE1-R HD-CBN 45 4.7U_0603_6.3V6K 2 1 CA4
1 1 17 HD-LINE1-L HD-CPVDD 46
2 1 1 18 HD-LINE2-R HD-CBP 47 HD_LDO2 CC167 1 2 10U_0402_6.3V6M @
SD_CMD_R 19 HD-LINE2-L HD-LDO2-CAP 48
35 SD_CMD_R SD_D3_R CR-SD-CMD HD-AVDD2
20 49 +5VD
35 SD_D3_R SD_D2_R 21 CR-SD-DAT[3] HD-PVDD1 50 SPK_L+ Analog power for DACs, ADCs
35 SD_D2_R CR-SD-DAT[2] HD-SPKOUT-LP SPK_L-
CW1 1 2 1U_0402_6.3V6K 22 51 2
23 CR-SDREG HD-SPKOUT-LN 52 SPK_R- +3VS
CW2 1 2 1U_0402_6.3V6K 24 CR-TEST1 HD-SPKOUT-RN 53 SPK_R+ CC257
RW11 1 2 6.2K_0402_1% RREF 25 CR-V18-CAP HD-SPKOUT-RP 54 +5VD
CR-RREF HD-PVDD2 10U_0402_6.3V6M
+3VALW USB20_N5 RW12 1 @ 2 0_0402_5% USB20_N5_R 26 55 SPKR_MUTE# 1
11 USB20_N5 USB20_P5 RW13 1 @ 2 0_0402_5% USB20_P5_R 27 CR-DM HD-PDB 56 Digital power for digital I/O circuit
+3VS +3VS_CARD 11 USB20_P5 28 CR-DP HD-DVDD
+3VS_CARD CR-3V3-IN
CARD_3V3 29
CR-SD-3V3 57
Power for card reader controller 1 1
GNDPAD 2 2

0.1U_0201_6.3V6-K

1U_0402_6.3V6K
RA220 1 @ 2 0_0402_5% CW18 CW19 RTS5199-CG_QFN56_7X7 CA180 CA179
4.7U_0402_6.3V6M 0.1u_0201_10V6K
1 1
2 2
RA219 1 @ 2 0_0402_5%
SDATA_IN
1U_0402_6.3V6K

1 12 SDATA_IN
C2062

C 2 C
DA4
EC_MUTE# 1 2 @ SPKR_MUTE#
44 EC_MUTE#

1
LRB751V-40T1G_SOD323-2 LINE1_L CA45 1 2 1U_0402_6.3V6K
RA35 1 @ 2 0_0402_5% RA43
10K_0402_5% LINE1_VREF_L RA41 1 2 4.7K_0402_5%
Power for combo jack depop circuit at system HPOUT_L RA21 1 2 51_0402_1% A_HP_OUTL_R

2
HPOUT_R A_HP_OUTR_R
+3VL shutdown mode RA20 1 2 51_0402_1%

DA1 LINE1_VREF_L RA42 1 2 4.7K_0402_5%

RA203 1 @ 2 0_0402_5% VDD_STB 2
44 BEEP#
1PC_BEEP1 1 @ 2 CA40 1 2 PC_BEEP LINE1_R CA46 1 2 1U_0402_6.3V6K
3 RA211 0_0402_5% 0.1U_0201_6.3V6-K
12 PCH_BEEP

1
To solve the background noise while combojack connecting to an
active speaker and system entry into S3/S4/S5 without analog power. LBAT54CWT1G_SOT323-3 RA14
10K_0402_5%
11/8 SIT Vendor suggestion form 47 ohm change to 51om wei

2
RA217 1 @ 2 0_0402_5% @1 TC203
11 HDA_RST_AUDIO#

When HD-Audio interfaces are not implemented on the platform the signal pins may be
left unconnected JSPK1 ME@
From APL PDG RA223 1 CD@ 2 15_0402_5% SPK_R+ RA222 1 2 0_0603_5% SPK_R+_CONN 1
RA224 1 CD@ 2 15_0402_5% SPK_R- RA221 1 2 0_0603_5% SPK_R-_CONN 2 1
RA1 1 2 0_0402_5% RA32 1 CD@ 2 15_0402_5% SPK_L+ RA30 1 2 0_0603_5% SPK_L+_CONN 3 2
EMC_NS@ RA33 1 CD@ 2 15_0402_5% SPK_L- RA34 1 2 0_0603_5% SPK_L-_CONN 4 3
RA4 1 2 0_0402_5% 4
EMC_NS@ 5
GND1

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K
LW2 6

CA29

CA30
CA183

CA184
220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K
USB20_N5 USB20_N5_R GND2

CA31

CA32

CA181

CA182
1 2 2 2 2 2
B
RA9 1 @ 2 0_0402_5% 1 2 ACES_88231-04001
B
1 1 1 1
RA12 1 2 0_0402_5% USB20_P5 4 3 USB20_P5_R vendor request change bead to 0603 0ohm lewis/2016/12/26
4 3 1 1 1 1

EMC@

EMC@

EMC@

EMC@
EMC_NS@
EXC24CH900U_4P 2 2 2 2
EMC_NS@
FOR EMI CD@ CD@ CD@ CD@

GND GNDA
8/16 Update Audio Jack P/N SP011509163 wei

Audio Jack JHP1 ME@

RING2_CONN 3
R3124 1 @ 2 C232 1 2 A_HP_OUTL_R 1 G/M
0_0402_5% @ 470P_0201_50V7-K L
RING3_CONN PLUG_IN 5
RING2_CONN 5
A_HP_OUTL_R DMIC_CLK HDA_SYNC_AUDIO 6
A_HP_OUTR_R EMC_NS@ HDA_SDOUT_AUDIO 6
PLUG_IN DMIC_DATA RA27 1 2 27_0402_5% HDA_BITCLK_AUDIO R3123 1 @ 2 C184 1 2 A_HP_OUTR_R 2
HDA_SDIN0 0_0402_5% @ 470P_0201_50V7-K R
RING3_CONN 4
CA38

CA39
100P_0201_25V8J

100P_0201_25V8J

M/G
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

CA23

CA24

CA25

CA26
EMC_NS@

EMC_NS@

1 1
7
22P_0201_258J

22P_0201_258J

33P_0201_50V8-J

33P_0201_50V8-J

MS
1

EMC_NS@

EMC_NS@

EMC_NS@

1 1 1 1
47P_0201_25V8-J

DA5 DA6 DA7 DA8 DA9 SINGA_2SJ3095-140111F

EMC_NS@

1
1

100P_0201_25V8J

100P_0201_25V8J
C185 2 2
1 1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
2 2 2 2 C182 C183
A 2 EMC@ EMC@ A
2 2
2

For EMI
2

8/16 Update Audio Jack P/N DC021608101 wei

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Codec & CR_RTS5199

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 34 of 58
5 4 3 2 1
 5 4 3 2 1

CARD_3V3

SD / MMC

0.1u_0201_10V6K
4.7U_0402_6.3V6M
1 1
D SD_D0_R RW3 1 @ 2 0_0402_5% SD_D0 CW9 CW17 D
34 SD_D0_R
CW5 1 2 5.6P_0402_50V8-D @
2 2
EMC@

JREAD1 ME@
SD_D1_R RW4 1 @ 2 0_0402_5% SD_D1 SD_D3 1
34 SD_D1_R SD_CMD CD/DAT3
CW6 1 2 5.6P_0402_50V8-D 2
3 CMD
4 VSS1
EMC@
SD_CLK 5 VDD
6 CLK
SD_D2_R RW5 1 @ 2 0_0402_5% SD_D2 SD_D0 7 VSS2
34 SD_D2_R Close to Connector SD_D1 DAT0
CW7 1 2 5.6P_0402_50V8-D 8
SD_D2 9 DAT1
DAT2
EMC@
SD_CD#_R 10 12
SD_D3_R RW6 1 @ 2 0_0402_5% SD_D3 SD_WP_R 11 CARDDETECT SH1 13
34 SD_D3_R WRITEPROTECT SH2
CW8 1 2 5.6P_0402_50V8-D 14
SH3 15
SH4
EMC@
T-SOL_5-251301001000-6_NR
SD_CMD_R SD_CMD
Close to Connector
RW7 1 @ 2 0_0402_5%
C 34 SD_CMD_R C
CW11 1 2 5.6P_0402_50V8-D

EMC@ CARD_3V3

8/16 Update Conn. P/N SP07000WG00 wei

1
SD_CLK_R RW8 1 @ 2 0_0402_5% SD_CLK
34 SD_CLK_R
CW12 1 2 5.6P_0402_50V8-D DW1

AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
EMC@
SD_WP RW88 1 @ 2 0_0402_5% SD_WP_R
34 SD_WP

2
2
SD_CD# RW89 1 @ 2 0_0402_5% SD_CD#_R
34 SD_CD#
FOR ESD

B
FOR ESD Close to Connector B

SD_CD#_R SD_WP_R

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
1

1
DW4 DW2

1
2

2
EMC_NS@ EMC_NS@

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cardreader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 35 of 58
5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms＜s pec＜ 10 0m s +3VALW_LAN +LAN_VDDREG
Need short
JL1 1 2 @ width : 40 mils RL1 1 @ 2 0_0603_5%
1 2
JUMP_43X79
D 1 1 D
+3VALW LP2301ALT1G_SOT23-3 CL1 CL2

4.7U_0402_6.3V6M

4.7U_0603_6.3V6K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1 1 1 1 4.7U_0603_6.3V6K 0.1U_0201_6.3V6-K
3 1 @

D
Q14 CL4 CL5 CL6 CL7 @

1
2 2

0.01U_0201_10V6K
@

CD@

CD@
RL2 1 1
100K_0402_5% CL8 CL9 2 2 2 2

G
2
@ 0.1U_0201_6.3V6-K
@ @

2
2 2
RL3 1 @ 2
44 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

+3VALW_LAN +1.8VALW

2
+3VALW_LAN

2
RL4

G
10K_0402_5%
2

@ PJQ1900[Vgs(th)<1.0V], 01/15
RL5

1
10K_0402_5% LAN_CLKREQ#_R 1 3
LAN_CLKREQ# 11
@

S
8106E@ QL1 @
1

UL1
PJQ1900_DFN3L
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
8,39,44 PCIE_WAKE#
C
39,44 LAN_WAKE# RL6 1 @ 2 0_0402_5% RL18 1 @ 2 0_0402_5% C
33
32 +3VALW_LAN GND 16 CLK_PCIE_LAN#
AVDD33 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 11
RL8 1 2 31 RSET 15
APL SOC CLKREQ are 1.8VALW power plane
+LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N4 CLK_PCIE_LAN 11
2.49K_0402_1% 30 14
29 LAN_XTALO AVDD10_1 HSIN 13 PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4 8
28 LAN_XTALI CKXTAL2 HSIP 12 LAN_CLKREQ#_R PCIE_PTX_C_DRX_P4 8
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# 1
RL12 @ 2 LAN_DISABLE# 26 LED0 NC_4 10 LAN_MDI3-
GPO NC_3 LAN_MDI3+ LAN_MDI3- 37
0_0402_5% TL4 @ 1 25 9
LED1 NC_2 LAN_MDI3+ 37
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 NC_6 AVDD10_0 7 LAN_MDI2-
+LAN_VDD10 DVDD33 NC_1 LAN_MDI2+ LAN_MDI2- 37
1K_0402_1% 22 6
PCIE_WAKE#_R 21 NC_5 NC_0 5 LAN_MDI1- LAN_MDI2+ 37
20 LANWAKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 37
ISOLATE#
LAN_MDI1+ 37
2

PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10

10,20,38,39,44 PLT_RST# PCIE_PRX_C_DTX_N4 PERSTB NC_7 LAN_MDI0-
8 PCIE_PRX_DTX_N4 CL10 2 1 0.1U_0201_6.3V6-K 18 2
LAN_PWR_ON# 1 0.1U_0201_6.3V6-K PCIE_PRX_C_DTX_P4 17 HSON MDIN0 LAN_MDI0+ LAN_MDI0- 37
ISOLATE# RL10 1 @ 2
8 PCIE_PRX_DTX_P4 CL11 2 1
HSOP MDIP0 LAN_MDI0+ 37
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17

15K_0402_5% RTL8106E-CG_QFN32_4X4
@
2

B B

For RTL8111GUL SWR mode)

LAN_XTALI
For RTL8111H /RTL 8107E (LDO mode) RL19 stuf f
YL1 LAN_XTALO 8107E@ +LAN_VDD10
RL19 1 2 0_0805_5%
1 4
OSC1 GND2
2 3 +LAN_REGOUT LL1 1 2
GND1 OSC2 2.2UH_NLC252018T-2R2J-N_5%
1 1 @ 1 1 1 1 1 1 1 1
Layout Note: LL1 must be CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
CL12 25MHZ_10PF_7V25000014 CL13 4.7U_0603_6.3V6K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 1U_0402_6.3V6K 0.1U_0201_6.3V6-K
10P_0201_25V8G 10P_0201_25V8G
within 200mil to Pin24, @
2 2 CL15,CL16 must be within 2 2 2 2 2 2 2 2
@
200mil to LL1
25MHz Crystal--TXC SJ10000G500 +LAN_REGOUT: Width =60mil
Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
Follow common pool change 25MHz X'tal from EPSON to TXC. 03/01

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8106E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 36 of 58
5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC300004X00

D TL1 D
24 1 MCT
DL1 MCT1 TCT1
LAN_MDI1- 1 10 LAN_MDI1- LAN_MDI0+ 23 2 LAN_MDO0+
LINE1IN LINE1OUT 36 LAN_MDI0+ MX1+ TD1+
LAN_MDI1+ 2 9 LAN_MDI1+ LAN_MDI0- 22 3 LAN_MDO0-
LINE2IN LINE2OUT 36 LAN_MDI0- MX1- TD1-

1
3 8 21 4 MCT RL17
GND1 GND2 MCT2 TCT2 20_0603_5%

1
LAN_MDI0- 4 7 LAN_MDI0- LAN_MDI1+ 20 5 LAN_MDO1+
LINE3IN LINE3OUT 36 LAN_MDI1+ MX2+ TD2+ EMC@ DL3

1
2
LAN_MDI0+ 5 6 LAN_MDI0+ LAN_MDI1- 19 6 LAN_MDO1-
LINE4IN LINE4OUT 36 LAN_MDI1- MX2- TD2- BS4200N-C-LV_SMB-F2

2
11 13 18 7 MCT EMC@
GND3 GND5 MCT3 TCT3

2
12 LAN_MDI2+ 17 8 LAN_MDO2+
GND4 36 LAN_MDI2+ MX3+ TD3+ EMC
AZ3133-08F.R7G_DFN3020P10E10 LAN_MDI2- 16 9 LAN_MDO2-
36 LAN_MDI2- MX3- TD3-
EMC_NS@
15 10 MCT
MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL25
36 LAN_MDI3+ MX4+ TD4+ CL32 1000P_1206_2KV7-K
DL2 LAN_MDI3- 13 12 LAN_MDO3- 0.022U_0603_50V7K EMC_NS@
C 1 36 LAN_MDI3- MX4- TD4- 2 2 C
LAN_MDI2+ 1 10 LAN_MDI2+ CL24
LINE1IN LINE1OUT 0.01U_0201_25V6-K EMC@
LAN_MDI2- 2 9 LAN_MDI2- EMC@ TST1284A
LINE2IN LINE2OUT 2 EMC
3 8 EMC
GND1 GND2
LAN_MDI3+ 4 7 LAN_MDI3+
LINE3IN LINE3OUT
LAN_MDI3- 5 6 LAN_MDI3- CHASSIS1_GND
LINE4IN LINE4OUT
11

12
GND3 GND5
13
change TL1 PN SP050008C00 to SP050009G00;
GND4
AZ3133-08F.R7G_DFN3020P10E10
EMC_NS@
TL1 is SP050008C00 footprint
Place Close to TL1
JRJ1 ME@
12
GND_4
11
GND_3
B 10 B
LAN_MDO0+ 1 GND_2
TX_DA+ 9
EMC LAN_MDO0- 2 GND_1
TX_DA-
LAN_MDO1+ 3
RL14 1 @ 2 0_0603_5% RX_DB+ CHASSIS1_GND
LAN_MDO2+ 4
RL15 1 @ 2 0_0603_5% BI_DC+
LAN_MDO2- 5
RL16 1 @ 2 0_0603_5% BI_DC-
LAN_MDO1- 6
RX_DB-
LAN_MDO3+ 7
BI_DD+
Reserve for EMI go rural solution LAN_MDO3- 8
CHASSIS1_GND BI_DD-

ALLTO_C10235-10839-L

8/16 Update RJ45 P/N DC021608091 wei

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 37 of 58
5 4 3 2 1
 5 4 3 2 1

THERMAL SENSOR
R175 1 2 0_0402_5% REMOTE1+
TMSEN_PX@ Near GPU&VRAM Near CPU Core
Close to U1 REMOTE1+ REMOTE2+
REMOTE+_R R176 1 2 0_0402_5% REMOTE2+
REMOTE+_R TMSEN_UMA@

1
1 REMOTE-_R
C44 R177 1 2 0_0402_5% REMOTE2-

C
2200P_0402_25V7-K TMSEN_UMA@ 1 Q15 1 Q16
TMSEN@ C45 2 B LMBT3904WT1G_SOT323-3 C46 2 B LMBT3904WT1G_SOT323-3
2 REMOTE-_R R178 1 2 0_0402_5% REMOTE1- 100P_0201_25V8J 100P_0201_25V8J
TMSEN_PX@ @ @
2 2

E
TMSEN_PX@ TMSEN_UMA@
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

3
Set Thermal Sensor as a BOM Structure Trace width/space:10/10 mil
Trace length:R8" REMOTE1- REMOTE2-
D D

Near CPU
+3VALW +3VALW

SMSC thermal sensor

placed near DIMM

1
R17 R25
+3VS 13.7K_0402_1% 13.7K_0402_1%
U1 PX@
1 8 EC_SMB_CK2
EC_SMB_CK2 21,44

2
VDD SCL NTC_V1 NTC_V2
REMOTE+_R 2 7 EC_SMB_DA2
1 EC_SMB_DA2 21,44

1
C47 D+ SDA
0.1U_0201_6.3V6-K REMOTE-_R 3 6 PH2 PH3
TMSEN@ D- ALERT# 100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC
2 R51 2 @ 1 4 5 PX@
+3VS T_CRIT# GND
10K_0402_5%

2
NCT7718W_MSOP8 TMSEN@
Address 1001_101xb

2
R184 R185 R191 R192
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
+5VLP +5VLP PX@
+5VLP @ @

1
HW thermal sensor

2
1 R252 R253 EC_AGND EC_AGND
C4 21.5K_0402_1% 21.5K_0402_1%
0.1U_0201_6.3V6-K @ @
@

1
2 @
U4
C 1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1 C
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
44,53,54 EC_ON OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

Over temperature threshold:

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

FAN Conn TPM

+3VS
+3VS_TPM
1A
RTPM11 TPM@ 2 0_0603_5%
+5VS
B JFAN1 1 1 B
CTPM3
1 +5VS_FAN R52 2 @ 1 CTPM1 0.1U_0201_6.3V6-K
1 2 0_0603_5% 10U_0603_6.3V6M TPM@
2 EC_FAN_SPEED 44 2 2
3 @
3 EC_FAN_PWM 44
4 1 1
4 5 C50 C49
GND1 6 0.1U_0201_6.3V6-K 10U_0805_10V6K
GND2 @
ACES_85205-04001 2 2 +3VS_TPM
ME@ UTPM1 TPM@
1 24
2 NC_1 VDD3 10
3 NC_2 VDD1 NATIONZ@
RTPM14 1 2 0_0402_5% 7 NC_3 28 RTPM2 1 2 4.7K_0402_5%
NATIONZ@ PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
SERIRQ LPC_AD0_TPM SERIRQ 11,44
6 26 RTPM6 1 TPM@ 2 0_0402_5%
9 NC_4 LAD0 23 LPC_AD1_TPM 1 TPM@ 2 0_0402_5% LPC_AD0 11,44
RTPM7
NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 11,44
22 RTPM8 1 TPM@ 2 0_0402_5%
Update FAN conn. footprint to SP020008X0J 4
11 GND_1
LFRAME#
LAD2
20
17
LPC_AD2_TPM
LPC_AD3_TPM
RTPM9
RTPM10
1 TPM@ 2 0_0402_5%
1 TPM@ 2 0_0402_5%
LPC_FRAME# 11,44
LPC_AD2 11,44
+3VALW
SP020012200 main source is SP020008X0J 18 GND_2
GND_3
LAD3
25
LPC_AD3 11,44
+3VS_TPM
Lewis 2016/10/14 RTPM12 1 2 0_0402_5% 5
8 NC_5
GND_4
LCLK
21
19
CLK_PCI_TPM 11
NUVOTON@ NUVOTON@
12 NC_6 VDD2 15 LPC_CLKRUN#_TPM RTPM13 1 2 0_0402_5%
Add for NUVOTON TPM NC_8 CLK_RUN# LPC_CLKRUN# 11
13 RTPM11 1 2 0_0402_5%
14 NC_9 16 NATIONZ@
NC_10 LRESET# PLT_RST# 10,20,36,39,44

Z32H320TC_TSSOP28

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN/TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 38 of 58
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VS Need short +3VS_WLAN
J2 @
1 2
1 2
JUMP_43X79 1
C53
0.1U_0201_6.3V6-K
@ +3VS_WLAN
2

1 1

JWLAN1 ME@
1 2
3 GND1 3.3VAUX1 4
11 USB20_P7 5 USB_D+ 3.3VAUX2 6 1 @ T2
11 USB20_N7 USB_D- LED1#
7 8
9 GND2 PCM_CLK/I2S_SCK 10
11 SDIO_CLK PCM_SYNC/I2S_WS 12
13 SDIO_CMD PCM_IN/I2S_SD_IN 14
15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ T3
17 SDIO_DATA1 LED#2 18
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22 UART_RX_DEBUG_R R256 1 @ 2 0_0402_5% UART_RX_DEBUG
23 SDIO_WAKE# UART_RXD
SDIO_RESET#

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 UART_TX_DEBUG_R R257 1 @ 2 0_0402_5% UART_TX_DEBUG

35 GND3 UART_TXD 34
8 PCIE_PTX_C_DRX_P5 PETP0 UART_CTS
37 36
8 PCIE_PTX_C_DRX_N5 39 PETN0 UART_RTS 38 EC_TX_RSVD 1 2 0_0402_5%
R62 @
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
8 PCIE_PRX_DTX_P5 PERP0 VENDOR_DEFINED2
43 42
8 PCIE_PRX_DTX_N5 45 PERN0 VENDOR_DEFINED3 44 1 2 0_0402_5%
R88 @
GND5 COEX3 EC_RX 44
47 46
11 CLK_PCIE_WLAN 49 REFCLKP0 COEX2 48
11 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R55 1 @ 2 0_0402_5%
WLAN_CLKREQ# GND6 SUSCLK PLT_RST# SUSCLK 10
53 52
11 WLAN_CLKREQ# PCIE_WAKE#_WLAN CLKREQ0# PERST0# BT_OFF#_R PLT_RST# 10,20,36,38,44
R4646 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
8,36,44 PCIE_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# BT_OFF# 12,44 BT_OFF# from EC, reserve connect to PCH
2 R57 1 @ 2 0_0402_5% 57 56 R56 1 @ 2 0_0402_5% 2
36,44 LAN_WAKE# GND7 W_DISABLE1# PCH_WLAN_OFF# 44

59 58 WLAN_SMB_DATA R58 1 @ 2 0_0402_5%

61 RSRVD/PETP1 I2C_DATA 60 WLAN_SMB_CLK 1 2 0_0402_5% SMB_DATA_S3 11,17
R59 @
RSRVD/PETN1 I2C_CLK SMB_CLK_S3 11,17
63 62
65 GND8 ALERT# 64 EC_TX_R R89 1 @ 2 0_0402_5%
RSRVD/PERP1 RSRVD EC_TX 44
67 66
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_WLAN

1
71 GND9 UIM_POWER_SNK/CLKREQ1# 70
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186
75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76

2
GND15 GND14

ARGOS_NASE0-S6701-TS40

8/16 Update Conn. P/N SP070013200 wei

Copy DG421 symbol

UART Transceiver
3 3

+3VALW +3VALW

+1.8VALW

1 100K_0402_5%

1 100K_0402_5%
+3VALW

U24 +3VALW +1.8VALW

16 1

2
VCCA DIR1
15 2

R259

R258

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
VCCB DIR2
SOC_UART_RXD 1 1
R4664 1 @ 2 0_0402_5% UART_B1 14 3 UART_TX_DEBUG

C4967

C4968
10 SOC_UART_RXD B1 A1
SOC_UART_TXD R4666 1 @ 2 0_0402_5% UART_B2 13 4 UART_RX_DEBUG
10 SOC_UART_TXD B2 A2 2 2
12 5

UART@

UART@
B3 A3
11 6
B4 A4 Place near U24.15&U24.16 Pin
10 7
GND DIR3
9 8
OE DIR4

SN74AVC4T774PWR_TSSOP16
4 @ 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 39 of 58
A B C D E
 A B C D E

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 40 of 58
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 41 of 58
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

1 1

SATA HDD P/N Pin Define Same as CG411 JHDD1

10
SATA_PTX_DRX_P0 C4932 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_P0 9 10
11 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
11 SATA_PTX_DRX_N0 C4933 1 2 0.01U_0201_6.3V7-K 8
7 8 12
SATA_PRX_DTX_N0 C4934 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_N0 6 7 GND2
11 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C4935 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_P0 5 6
11 SATA_PRX_DTX_P0 4 5
3 4 11
2 3 GND1
1 2
1
ELCO_006809610010846
Need short +5VS_HDD
ME@
J3 @
1 2
+5VS 1 2
JUMP_43X79

2 2

+5VS_HDD

1 1 1 1 1 1
C74 C76 C77 C78 C4956
1000P_0201_50V7-K C4930 1U_0402_10V6K 10U_0805_10V6K 10U_0805_10V6K 33P_0402_50V8J
EMC_NS@ 0.1U_0201_6.3V6-K @ @ RF@
2 2 2 2 2 2

For RF request: keep 0402

EMC

3 3

FOR 14"
+5VS to +5V_ODD +5VS Need short +5V_ODD SATA ODD Conn.
J4 @
1 2 JODD1
1 2 1
JUMP_43X79 SATA_PTX_DRX_P1 14@ C4936 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_P1_14 2 GND_1
11 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 14@ C4937 RX+
1 1 11 SATA_PTX_DRX_N1 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_N1_14 3
4 RX-
C85 C4931 SATA_PRX_DTX_N1 14@ C4938 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_N1_14 5 GND_2
10U_0603_10V6K 0.1U_0201_6.3V6-K 11 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C4939 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_P1_14 6 TX-
2 2 CD@ 11 SATA_PRX_DTX_P1 7 TX+
GND_3
8
9 DP
+5V_ODD 10 +5V_1
11 +5V_2 14
JODD2 12 MD GND1 15
1 ME@ 13 GND_4 GND2
SATA_PTX_DRX_P1 15@ C79 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_15 2 1 GND_5
SATA_PTX_DRX_N1 15@ C80 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 3 2 SUYIN_127382FB013S255ZL
4 3 ME@
4
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
15@ C81 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_15
SATA_PRX_C_DTX_P1_15
5 4
5
FOR 15" 4
15@ C82 1 2 0.01U_0201_10V6K 6
+5V_ODD
7
8
6
7 SATA ODD FFC Conn
8
9
10 GND1
GND2 Security Classification LC Future Center Secret Data Title
HIGHS_FC5AF081-2931H
Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
8/16 Update Conn. P/N SP01001YV00 wei DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 42 of 58
A B C D E F G H
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 43 of 58
5 4 3 2 1
 5 4 3 2 1

RE1 1 @ 2 0_0603_5%
For ESD +3VL
PLT_RST#
RE3 1 2 0_0603_5% +3VALW
1 @
Same as SOC LPC power
CE1 +3VL_EC_R
220P_0201_25V7-K +3VL_EC +3VL_EC
2 EMC@ RE4 1 @ 2 0_0402_5%
VFSPI Pin for IT8986HE Flash SPI Bus Power +3VALW All capacitors close to EC LE1 1 @ 2 0_0402_5%
+3VL_EC

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
+3VL_EC RE16 1 @ 2 0_0402_5%
+1.8VALW RE6 1 @ 2 0_0402_5% 2 1
2 2 2 2 2 2
+3VL_EC_R CE31 CE38

CE25

CE26

CE27

CE28

CE29

CE30

1
+1.8VALW RE17 1 @ 2 0_0402_5% VFSPI Close EC 1 2 0_0402_5% 1
0.1U_0201_6.3V6-K
EC_AGND 2
1000P_0201_25V7K
LE2 @ RE5
D 1 1 1 1 1 D
CE24 @ 1 10K_0402_5%

CD@
1 2 VCOREVCC
EC_AGND

2
0.1U_0201_6.3V6-K VFSPI
CLK_PCI CE37 1 LAN_WAKE#
2 10P_0201_25V8G BEAD change to 0ohm LAN_WAKE# 36,39

114
121
127

106
EMC@ minimum trace width 12 mil

12

11

26
50
92

74
UE1
+3VS

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC

VSTBY_FSPI
VSTBY(PLL)
VCORE
EC_LID_OUT# RE88 1 @ 2 10K_0402_5%
EC_FAN_SPEED RE10 1 2 10K_0402_5%
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

21 WRST#
4 24 +1.8VALW
+3VL_EC 12 KBRST# KBRST#/GPB6 V1P8 PWM0/GPA0 PWR_LED# 45
5 25 ENBKL RE9 1 @ 2 100K_0402_5%
11,38 SERIRQ LPC_FRAME# 6 SERIRQ/GPM6 V1P8 PWM1/GPA1 28 BATT_CHG_LED# 45
11,38 LPC_FRAME# LFRAME#/GPM5 V1P8 PWM2/GPA2 BATT_LOW_LED# 45 VGA_AC_DET
DE1 7 29 2 1
11,38 LPC_AD3 LAD3/GPM3 V1P8 PWM3/GPA3
1 2 @
11,38 LPC_AD2
8
LAD2/GPM2 V1P8 PWM PWM4/GPA4
30 0_0402_5%
EC_FAN_PWM @
RE89
VGA_GATE# 12 5 Pin Fan Conn
9 31
11,38 LPC_AD1 LAD1/GPM1 V1P8 PWM5/GPA5 EC_FAN_PWM 38
LRB751V-40T1G_SOD323-2 10 32
11,38 LPC_AD0 CLK_PCI LAD0/GPM0 V1P8 LPC PWM6/SSCK/GPA6 BEEP# 34
RE71 1 @ 2 0_0402_5% 13 34
11 CLK_PCI_EC LPCCLK/GPM4 V1P8 PWM7/RIG1#/GPA7 LAN_WAKE# SUSPWRDNACK 9
RE8 1 2 100K_0402_5% WRST# 14 120
15 WRST# TMRI0/GPC4 124 SUSP#
10 EC_SMI# PLT_RST# 22 ECSMI#/GPD4 V1P8 TMRI1/GPC6 SUSP# 46,54
1 10,20,36,38,39 PLT_RST# LPCRST#/GPD2V1P8
23 66
CE12 12 EC_SCI# 126 ECSCI#/GPD3 V1P8 ADC0/GPI0 67 NTC_V1 38
1U_0402_6.3V6K 54 PCH_PWR_EN GA20/GPB5 V1P8 ADC1/GPI1 BATT_TEMP NTC_V2 38
68
2 ADC2/GPI2 BATT_TEMP 51,52
IT8986E/AX ADC ADC3/GPI3
ADC4/GPI4
69
70 PCH_1.24V_EN
VR_CPU_PWROK
54
56
change 1.8VALW_PG to PCH_1.24V_EN 03/10
71

KSI[0..7]
LQFP-128L ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
72
73
Psys
EC_GPU_VR_HOT#
ADP_I 52
Psys 52,56
45 KSI[0..7] ADC7/CTS1#/GPI7
KSI0 58 +5VALW
KSO[0..17] KSI1 59 KSI0/STB# 78
45 KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 PMIC_EN PCH_WLAN_OFF# 39
C KSI2 60 79 C
61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC PMIC_EN 54 PMIC_EN connect to PMIC 03/10 USB_ON#
KSI3 DAC RE15 1 2 100K_0402_5%
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 EC_BT_OFF# RE67 1 @ 2 0_0402_5%
KSI4 DAC5/RIG0#/GPJ5 BT_OFF# 12,39
KSI5 63
KSI6 64 KSI5 85 EC_RTCRST#_ON +3VALW
+3VL_EC KSI6 PS2CLK0/TMB0/CEC/GPF0 EC_RTCRST#_ON 46
KSI7 65 86
EC_SMB_CK1 1 36 KSI7 PS2DAT0/TMB1/GPF1 89 1 PBTN_OUT# 10
PAD @ KSO0 PS2 TP58 @ RPE11
RPE7 EC_SMB_DA1 IT2 KSO0/PD0 V1P8 PS2CLK2/GPF4 PMIC_EN
PAD 1 @ KSO1 37 90 1 2 3
1 4 EC_SMB_CK0 1
IT3
KSO2 38 KSO1/PD1 Int. K/B V1P8 PS2DAT2/GPF5 TP57 @ PCH_PWR_EN 1 4
PAD @
2 3 EC_SMB_DA0 PAD 1 @
IT4
KSO3 39 KSO2/PD2 Matrix
IT5 KSO3/PD3
PAD 1 @ KSO4 40 96 10K_0404_4P2R_5% +3VL_EC
IT6 41 KSO4/PD4 GPH3/ID3 97 EC_LID_OUT# CMOS_ON# 28
2.2K_0404_4P2R_5% KSO5
+3VL_EC KSO5/PD5 GPH4/ID4 EC_BKL_EN EC_LID_OUT# 45
KSO6 42 EXTERNAL SERIAL FLASH 98
KSO6/PD6 GPH5/ID5 EC_BKL_EN 45 EC_ON_GPIO
KSO7 43 99 2 RE65 1
RPE8 1 44 KSO7/PD7 GPH6/ID6 VR_VNN_PWROK 57
KSI7 PAD @ KSO8 10K_0402_5%
EC_SMB_CK1 IT7 KSO8/ACK#
1 4 KSI6 PAD 1 @ KSO9 45 101 For Mirror Code
2 3 EC_SMB_DA1 1 IT8 46 KSO9/BUSY V1P8 FSCE#/GPG3 102 EC_SPI_CS0#_R 8
WRST# PAD @ KSO10
IT9 KSO10/PE V1P8 FMOSI/GPG4 EC_SPI_D0_R 8
KSO11 51 SPI Flash ROM 103 +3VL_EC
2.2K_0404_4P2R_5% KSO12 52 KSO11/ERR# V1P8 FMISO/GPG5 105 EC_SPI_D1_R 8 SUSP# RE18 1 @ 2 100K_0402_5%
+3VS KSO12/SLCT V1P8 FSCK/GPG7 EC_SPI_CLK_R 8
KSO13 53
For factory EC flash KSO14 54 KSO13 Mirror Code SUSP# RE19 1 2 100K_0402_5%
RPE9 55 KSO14
KSO15
1 4 EC_SMB_CK2 KSO16 56 KSO15 17 EC_TX SYSON RE21 1 2 100K_0402_5%
EC_SMB_DA2 KSO16/SMOSI/GPC3 V1P8 TXD/SOUT0/LPCPD#/GPE6 16 EC_RX EC_TX 39
2 3 KSO17 57
KSO17/SMISO/GPC5
UARTV1P8 RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 EC_RX 39
2.2K_0404_4P2R_5%
EC_SMB_CK1 115 82 SYS_PWROK RE12 1 2 100K_0402_5%
51,52 EC_SMB_CK1 SMCLK1/GPC1 V1P8 EGAD/GPE1 SYS_PWROK 9
BATT&Charger 51,52 EC_SMB_DA1
EC_SMB_DA1
EC_SMB_CK2
116
SMDAT1/GPC2 V1P8 EGCS#/GPE2
83
EC_MUTE# 34
21,38 EC_SMB_CK2 EC_SMB_DA2
117
SMCLK2/PECI/GPF6 V1P8 EGCLK/GPE3
84
NUM_LED# 45 Follow Intel request to add 100Kohm PD to avoid this leakage.
VGA&Thermal Sensor 21,38 EC_SMB_DA2 EC_SMB_CK0
118
SMDAT2/PECIRQT#/GPF7V1P8
87 77 RE86 1 @ 2 0_0402_5%
SM Bus EC_TS_ON 28 RTC_RST# 9
For PMIC EC_SMB_DA0 88 SMCLK0/GPF2 V1P8
SMDAT0/GPF3V1P8
GPJ1
PWRSW/GPB3
110 ON/OFF ON/OFF 45
95 RE87 1 2 0_0402_5%
12 EC_WAKE_SCI# CTX1/SOUT1/SMDAT3/GPH2/ID2 V1P8 RTC_TEST# 9
10 PMIC_THERMTRIP# 94 RTCRST@
BKOFF# 113 CRX1/SIN1/SMCLK3/GPH1/ID1 V1P8 107
28 BKOFF# CRX0/GPC0 GPE4/BTN# NOVO# 45

1
123 GPIO V1P8 119 QE3 D
Move EC_ME_PROTECT from UE1.119 to UC1.123 16 EC_ME_PROTECT CTX0/TMA0/GPB2 DSR0#/GPG6 EC_RTCRST#_ON 2
RE27 1 @ 2 0_0402_5% 112 G
B 0_0402_5% +3VL VSTBY0 B
GPG2 100

100K_0402_5%
1
VGA_AC_DET 2 1 RE30 125 SSCE0#/GPG2 76 S L2N7002KWT1G_SOT323-3

RTCRST@
21 VGA_AC_DET EC_RSMRST# 9

3
@ SYSON 122 SSCE1#/GPG0 TACH2/GPJ0 48 EC_ON_GPIO RE69 1 @ 2 0_0402_5%

RE50
54 SYSON WAKE
DTR1#/SBUSY/GPG1/ID7 V1P8 UP TACH1A/TMA1/GPD7 EC_FAN_SPEED EC_ON 38,53,54 RTCRST@
10 PM_SLP_S4# 21 47 EC_FAN_SPEED 38
18 RI2#/GPD1 V1P8 TACH0A/GPD6 19
10,54 PM_SLP_S3# RI1#/GPD0 V1P8 V1P8 L80HLAT/BAO/GPE0 CAPS_LED# 45
20
ENBKL 28 Exchange NUM_LED# & ENBKL(1.8V input)

2
USB_ON# 33 V1P8 L80LLAT/GPE7 108 ACIN#
31 USB_ON# GINT/CTS0#/GPD5 AC_IN#/GPB0 LID_SW#
35 109
36 LAN_PWR_ON# LPC_CLKRUN#_EC 93 RTS1#/GPE5 LID_SW#/GPB1 111 LID_SW# 45 EC_ON
RE58 2 1 0_0402_5%
+3VL 11 LPC_CLKRUN#_EC CLKRUN#/GPH0/ID0 V1P8 XLP_OUT/GPB4 @
RE70 1 @ 2 0_0402_5% 2 EC_GPU_VR_HOT# RE83 1 @ 2 0_0402_5%
8,36,39 PCIE_WAKE# GPJ7 GPIO GPU_VR_HOT# 21,55
3
56,57 EC_VR_ON GPH7
change from GPE4 10 AC_PRESENT
128

1
GPJ6
AVSS

D
VSS1
VSS2
VSS3
VSS4

VSS5

QE5 1
RE35 1 @ 2 10K_0402_5% ON/OFF 2
VGA_AC_DET @
RE33 1 2 0_0402_5% G CE41
RE36 1 @ 2 10K_0402_5% BKOFF# IT8986E-BX_LQFP128_14X14 47P_0201_25V8-J
1
27
49
91

75

104

L2N7002KWT1G_SOT323-3 S 2 EMC_NS@
Change RE72 to 0ohm jump

3
RE38 1 @ 2 10K_0402_5% LID_SW# PM_SLP_S3# @
NOVO#
PM_SLP_S4# RE72 1 @ 2 0_0402_5%
52,54,56,57 VR_HOT# H_PROCHOT# 9
1000P_0201_25V7K

1000P_0201_25V7K

0.01U_0201_6.3V7-K

RE40 1 2 10K_0402_5% BKOFF# SYSON

1
QE1 D
EMC_NS@

EMC_NS@

1 1 1 H_PROCHOT#_EC 1
2
EC4

EC_AGND
CE39

CE40

0.1U_0201_6.3V6-K
G CE14
47P_0201_25V8-J +3VL
2 2 2 2 2
L2N7002KWT1G_SOT323-3 S EMC_NS@

CE36
3
@
+3VL_EC

EMC_NS@
1
GPG2 RE44 2 1 10K_0402_5% 1
@ RE42
GPG2 RE46 2 1 10K_0402_5%
100K_0402_5%
+3VL EMC_NS@ +3VS
BATT_TEMP CE16 1 2 100P_0201_25V8J
when mirror, GPG2 pull high

2
when no mirror, GPG2 pull low +3VL ACIN# RE74 1 @ 2 0_0402_5%
10 ACIN#
EMC_NS@

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
4
3

A ACIN# CE17 1 2 100P_0201_25V8J A

1
RPE10 2 2 D QE2
100K_0404_4P2R_5% ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2

CE33

CE32
ACIN 52
5

+3VL LID_SW# G
G

@
1
2

1 1 S L2N7002KWT1G_SOT323-3

3
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

PMIC_SMB_CLK0 EC_SMB_CK0 @ ACIN change to hign active to cost QE2

4 3
S

2 2 54 PMIC_SMB_CLK0
D
CE34

CE35

QE4B @
G

L2N7002KDW1T1G_SOT363-6 Title
1 @1 RE81 1 @ 2 0_0402_5% Security Classification LC Future Center Secret Data
PMIC_SMB_DAT0 1 6 EC_SMB_DA0 Issued Date 2014/09/24 Deciphered Date 2015/03/23 EC ITE8586LQFP
S

54 PMIC_SMB_DAT0
D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
QE4A @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
L2N7002KDW1T1G_SOT363-6 C 1.0
RE82 1 @ 2 0_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 44 of 58
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch Novo button K/B Connector KSI[0..7]

KSI[0..7] 44
+3VL +3VALW KSO[0..17]
KSO[0..17] 44 JKB1
NOVO_BTN# 32 33
32 GND1

2
R923 1 @ 2 0_0402_5% ON/OFFBTN# 31 34
R82 R83 EMC_NS@ PWR_LED# R285 1 @ 2 0_0402_5% 30 31 GND2
PWR_CAPS_LED NUM_LED#_R 30

2
100K_0402_5% 100K_0402_5% SW3 C133 1 2 100P_0201_25V8J 44 NUM_LED# R279 1 15@ 2 0_0402_5% 29
KSO17_R 29

1
@ KSO17 R281 1 15@ 2 0_0402_5% 28
4 KSO16_R 28
D24 KSO16 R280 1 15@ 2 0_0402_5% 27

1
1

1
D15 AZ5123-01F.R7GR_DFN1006P2X2 KSI1 26 27
NOVO# 2 5 EMC@ KSI7 25 26
44 NOVO# 1 NOVO_BTN# 24 25
KSI6
ON/OFF R85 1 @ 2 0_0402_5% 3 KSO9 23 24
23

2
KSI4 22
LBAT54CWT1G_SOT323-3 NTC325-EKJ-A160T_3P KSI5 21 22

2
EMC@ KSO0 20 21
D @ D
CAPS_LED# 1 2 100P_0201_25V8J KSI2 19 20
C117
KSI3 18 19
NUM_LED#_R C118 1 2 100P_0201_25V8J KSO5 17 18
KSO1 16 17
+3VALW +3VL EMC_15@ 8/23 PWR LED function under check KSI0 15 16
KSO2 14 15
8/31 Update the P/N SN100008W00 wei KSO4 13 14
13

2
KSO7 12
R111 R114 KSO8 11 12
100K_0402_5% 100K_0402_5% CAPS_LED# NUM_LED#_R PWR_LED# KSO6 10 11
@ KSO3 9 10
KSO12 8 9

1
KSO13 7 8
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF KSO14 6 7
ON/OFF 44 8/16 Del Power Button wei 6

1
KSO11 5
D22 D23 D47 KSO10 4 5

1
J5 1 2 @ AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 KSO15 3 4
ON/OFFBTN# EMC@ EMC_15@ EMC@ CAPS_LED# R9427 1 @ 2 0_0402_5% CAPS_LED#_R 2 3
44 CAPS_LED# PWR_CAPS_LED 2
SHORT PADS +3VALW R84 1 2 1
200_0402_1% 1

AZ5123-01F.R7GR_DFN1006P2X2

2
place bottom side CVILU_CF32321D0RONH

1
D25 ME@

2
1
For EMC

2
EMC@

2
TP/B Connector +3VS TP_PWR

C +3VALW
R141 1 2 0_0402_5% TP_PWR Finger Print Connector FP_PWR USB20_N4_CONN C

EMC_NS@
2
R9425 1 2 2 To be confirm Pin define
0.1u_0201_10V6K

@ 0_0402_5% C116
EMC_NS@
1 JTP1 USB20_P4_CONN
C115 100P_0201_25V8J +3VS
1 6 JFP1
100P_0201_25V8J TP_I2C_SCL4_R 6
1 5 R3120 1 2 1
8 TP_I2C_SCL4_R TP_I2C_SDA4_R 5 USB20_N4 USB20_N4_CONN 1

2
2 4 8 0_0402_5% R3122 1 FP@ 2 0_0402_5% 2
C114

8 TP_I2C_SDA4_R 3 4 GND2 11 USB20_N4 USB20_P4 USB20_P4_CONN 2

FP@ R3121 1 FP@ 2 0_0402_5% 3 DT2
PCH_TP_INT# PCH_TP_INT#_R 3 11 USB20_P4 3

0.1u_0201_10V6K
R4676 1 @ 2 0_0402_5% 2 7 1 4
12 PCH_TP_INT# EC_LID_OUT#_R 2 GND1 4
R4675 1 @ 2 0_0402_5% 1 5 EMC_NS@
44 EC_LID_OUT# 1 6 5
FP@ 7 6
ELCO_04-6809-606-110-846-+ 2 8 7

C2061
TP_I2C_SDA4_R ME@ 8
TP_I2C_SCL4_R 9
TP_PWR 10 GND1
GND2
3

DT1 HIGHS_FC5AF081-2931H AZC199-02S.R7G_SOT23-3

1
2

EMC_NS@ R9418 Footprint is SP01001WB00. main source :SP01001WX00 ME@

10K_0402_5% 2nd source :SP01001WB00 lewis 2016/11/16 9/7 Add for ESD wei
8/23 Update FG Conn. P/N SP01001YV00 wei
1

PCH_TP_INT#
AZC199-02S.R7G_SOT23-3
1

For EMC

LED LED4 PWR_LED# KB Backlight Connector

PWR_LED# 1 2 R4672 1 2 1.5K_0402_5%
44 PWR_LED# +5VALW
1

L-C192WDT-LCFC_WHITE
B D16 B
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
+5VS

+5VALW
2

PWR_LED Change to M/B (310->320) 08/17 +VCC_KB_LED

2

Q31

1
R265 LP2301ALT1G_SOT23-3 To be confirm Pin define
10K_0402_5% KBL@
3

D
KBL@ 1

1 1 JKBL1 ME@

2
R266 C1106 C1107 +VCC_KB_LED 1

G
2
1 2 10U_0603_6.3V6M 0.1u_0201_10V6K 2 1
BATT_LOW_LED# LED1 1 2 R925 1 2 470_0402_5% BATT_LOW_LED# BATT_CHG_LED# KBL@ KBL@ 3 2 6
44 BATT_LOW_LED# +3VALW 2 2 3 GND2
100K_0402_5% 1 4 5
AZ5123-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

KBL@ C1108 4 GND1

L-C192JFCT-LCFC_SUPER_AMBER 1
1

D18 D19 0.01U_0201_10V6K C1110 CVILU_CF50041D0RN-10-NH

KBL@ 0.1u_0201_10V6K
1

2 @
BATT_CHG_LED# LED2 1 2 R924 1 2 1.5K_0402_5% 2
44 BATT_CHG_LED# +5VALW
EMC_NS@
L-C192WDT-LCFC_WHITE

1
2

D
EMC_NS@ EC_BKL_EN 2 Q32
44 EC_BKL_EN 8/31 Update KBL Conn. P/N SP011608241 wei
2

G 2N7002KW_SOT323-3
Check LED location and BOM structure when placement and Load BOM, PWR LED and BATT LED KBL@
1 S
have the same location on 14"/15" 02/26

3
C1109
0.1u_0201_10V6K
KBL@
2

LID Switch
A A

1
C195
U21 100P_0201_25V8J
1
GND 2
2 LID_SW#
C4945 3 Title
0.01U_0201_6.3V7-K OUTPUT LID_SW# 44 Security Classification LC Future Center Secret Data
R1
1 2
0_0402_5% 1 +VCC_LID 2 Issued Date 2013/08/08 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn.
+3VL VCC
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
AH9247-W-7_SC59-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 45 of 58

5 4 3 2 1
 A B C D E

+5VS/+3VS Load Switch

Load Switch modify load swtich from APL3523 to G5016KD1U TDFN 14P
+5VLP +5VALW
+5VALW To +5VS +3VS, C173 --> 2.78ms
+3VALW To +3VS +5VS, C176 --> 1.71ms

1
R156 R157 VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
100K_0402_5% 100K_0402_5% R4 1 @ 2 0_0402_5% 3VSON +3VALW +3VS
@ U13
Need
J11
Short
@
1 1 14 +3VS_LS 1 2 1

2
2 IN1_1 OUT1_2 13 1 2
SUSP IN1_2 OUT1_1 JUMP_43X118
32 SUSP 1 1
3VSON 3 12 C4929 1 2 2200P_0201_25V7-K C175
SUSP# R2 1 @ 2 0_0402_5% 5VSON C178 EN1 CT1 0.1U_0201_6.3V6-K
1U_0402_6.3V6K 4 11 @
2 +5VALW VBIAS GND 2
@

1
Q6 D 1 1 5VSON 5 10 C4928 1 2 1000P_0201_25V7K
2 +5VALW EN2 CT2 +5VS
44,54 SUSP# G 6 9
C180 C179 J12 @
1U_0402_6.3V6K 1U_0402_6.3V6K 7 IN2_1 OUT2_2 8 +5VS_LS 1 2
L2N7002KWT1G_SOT323-3 S 2 2 IN2_2 OUT2_1 1 2

3
1 15 JUMP_43X118 1
GPAD C174
C177 G5016KD1U_TDFN14_2X3
Need Short 0.1U_0201_6.3V6-K
1U_0402_6.3V6K @
2 @ 2

Delete +3.3VALW to +1.5VS +1.8V_PU Power Rail

2 2

+1.8VALW +1.8V_PU

R4658 1 @ 2 0_0603_5%

+1.8VS

R4659 1 @ 2 0_0603_5%

3 3

+3VALW to +3VALW_SOC +3VALW +3VALW_SOC +3VALW_SOC

For DisCharge
Need Short +1.8VS
J7 @ VTT +1.35V
1 2
1 2

1
JUMP_43X79
R159 R935 R939
Id=3.2A 47_0603_5% 47_0603_5% 47_0603_5%

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
@ @ @
LP2301ALT1G_SOT23-3 1 1

2
C4965

C4966
@
3 1
S

Q29

1
D Q8 D Q156 D Q165
0.01U_0201_10V6K

2 2
EMC_NS@

1 1 EMC_NS@ 2 SUSP 2 SUSP 2 SUSP

C129 C130 G G G
G
2

0.1U_0201_6.3V6-K
@ @ S L2N7002KWT1G_SOT323-3 S L2N7002KWT1G_SOT323-3 S L2N7002KWT1G_SOT323-3

3
2 2
@ @ @

44 EC_RTCRST#_ON R158 1 @ 2 0_0402_5%

Place near CLK_PCI_EC under +3VALW_SOC moat
1

4 1 4
C131
R164 0.1U_0201_6.3V6-K
100K_0402_5% @
@ 2
Security Classification LC Future Center Secret Data Title
2

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE

reserve to cut off SOC 3VALW when clear CMOS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 46 of 58
A B C D E
 5 4 3 2 1

CPU Thermal Holex3 GPU Thermal Holex2

Close to RJ45 Close to Audio jack PCB Fedical Mark PAD
H1 H2 H3 H4 H5 H6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
FD1 FD2 FD3 FD4 FD5 FD6

1
D D
pad_c6p0d4p0 pad_c6p0d4p0 pad_c6p0d4p0 pad_c7p0d3p3 pad_c7p0d3p3 CHASSIS1_GND
pad_ct7p0b8p0d3p0 pad_ct7p0b8p0d3p0

WLAN Standoff
H17 H18 H19 H20 H11 H10 H12 H13 H15 H16
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
pad_o2p6x2p9d2p6x2p9nPAD_CT7P0D3P0 PAD_CT7P0D3P0 pad_c3p3d3p3n pad_ct7p0b6p0d3p3 pad_ct5p5d2p5 pad_ct7p0d3p0 pad_ct7p0d3p0 pad_ct5p0d2p5 pad_cb5p5d2p5

C C

SH7 ME@ SH8 ME@ SH9 ME@

1 1 1
SH1 ME@ SH2 ME@ SH3 ME@ 1 1 1

1 1 1
1 1 1
SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P

SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

SH10 ME@ SH11 ME@ SH12 ME@

SH4 ME@ SH5 ME@ SH6 ME@ 1 1 1
1 1 1
1 1 1
1 1 1
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
B SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 B

USB3.0 Shielding DDR3L Shielding

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 47 of 58
5 4 3 2 1
 5 4 3 2 1

HDMI Logo B1 Stepping CPU

UL1 8107E@ UV1 PX@ UC1 UC1 UC1
ZZZ1 HDMI@

N3350 N3450 N4200

D D
RTL8107E-CG R17M-M1-70 GPU APOLLOLAKE_FCBGA1296 APOLLOLAKE_FCBGA1296 APOLLOLAKE_FCBGA1296
HDMI Logo SA00007FR00 SA000086K00 SA000080L30 SA000080M30 SA000080N30
RO00000040J LAN Chip GPU N3350_B1@ N3450_B1@ N4200_B1@

DAZ PCB PN 14&15 PCB MB PCB ODD/B BO Stepping CPU

ZZZ5 DAZ@ ZZZ2 PCB@ ZZZ6 ODD@ UC1 UC1 UC1

N3350 N3450 N4200

PCB PN PCB PN PCB PN APOLLOLAKE_FCBGA1296 APOLLOLAKE_FCBGA1296 APOLLOLAKE_FCBGA1296

DAZ14W00100 DA600013C10 DA600013110 SA000080L10 SA000080M10 SA000080N10
N3350_B0@ N3450_B0@ N4200_B0@

VRAM ID config
ZZZ4 S2GX4@ ZZZ4 H2GX4@ ZZZ4 M2GX4@
VRAM X76 BOM VRAM ID PU resistor PD resistor
Memory Type
PS_3[3:1] RV63 RV70

Samsung Hynix Micron Hynix

X7643G12002 X7643F12001 X7643G12001 100 4.53K 4.99K
H5GC4H24AJR-R0C

256Mx16 Micron
111 4.75K NC
EDW4032BABG-70-F
C C
UV5 S2G@ UV6 S2G@ UV7 S2G@ UV8 S2G@ RV63 S2G@ RV70 S2G@
Samsung
110 3.4K 10K
K4G41325FE-HC28

K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 3.4K_0402_1% 10K_0402_1%

SA00007VQ10 SA00007VQ10 SA00007VQ10 SA00007VQ10 SD03434018J SD03410028J 000 NC 4.75K
VRAM_Samsung 4GX4

010 4.53K 2K

UV5 H2G@ UV6 H2G@ UV7 H2G@ UV8 H2G@ RV63 H2G@ RV70 H2G@

001 8.45K 2K

H5GC4H24AJR-R0C H5GC4H24AJR-R0C H5GC4H24AJR-R0C H5GC4H24AJR-R0C 4.53K_0402_1% 4.99K_0402_1%

SA000081A00 SA000081A00 SA000081A00 SA000081A00 SD03445318J SD03449918J

VRAM_Hynix 4GX4

UV5 M2G@ UV6 M2G@ UV7 M2G@ UV8 M2G@ RV63 M2G@

B
EDW4032BABG-70-F EDW4032BABG-70-F EDW4032BABG-70-F EDW4032BABG-70-F 4.75K_0402_1% B
SA000081800 SA000081800 SA000081800 SA000081800 SD03447518J

VRAM_Micron 4GX4

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG424/DG524
Date: Thursday, March 09, 2017 Sheet 48 of 58
5 4 3 2 1
 5 4 3 2 1

+5VLP/ 100mA
V20B+
Silergy SUSP# EN_1.05VS +1.05VS / 6A

SYX8288C CONVERTOR
+5VALW/8A
Adaptor Converter PCH_PWR_EN EN_1.8VALW +1.05VGS / 3A
D
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD D

PAGE 53 1.8VALW_PG EN_LDO1

+1.8VS / 500mA
SUSP# EN_LDO2
+3VLP/ 100mA RICHTEK
Silergy LDO
LV5075 +1.8VALW / 1A
SY8286B
Converter +3VALW/6A MOIC
FOR SYSTEM FOR SYSTEM +VTT / 1A
EC_ON EN PGOOD ALW_PWRGD
PAGE 53
POWER

Controller +1.35V / 8A

SYSON EN_VDDQ

PM_SLP_S3# EN_VTT
TI
PGOOD PG for all MOIC power rail
BQ24780SRUYR PAGE 54

Battery Charger
Switch Mode
PAGE 52 Onsemi CPU Core/21A Silergy
NCP81236MNTXG SY8032ABC +1.24VALW / 2A
C Switch Mode VNN/4.8A Converter C

SMBus EC_VR_ON EN FOR CPU Core PGOOD VR_CPU_PWROK 1.8VALW_PG EN FOR SYSTEM
PAGE 57 PAGE 54

Battery
Li-ion
2S1P/30WH/39WH

Richtek
RT3662EBGQW
_WQFN32_4X4 +VGA_CORE/31A
VIDs
Switch Mode
PXS_PWREN EN FOR GPU VDDC PGOOD VR_VGA_PWRGD
PAGE 56

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 49 of 58
5 4 3 2 1
 5 4 3 2 1

VIN
EMC@
HCB2012KF-121T50_0805
JDCIN1 PF101 PL101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 3 7A_24VDC_F1206HI7000V024TM
GND2 EMC_NS@

1000P_0201_50V7-K
PC101

PC104
4 HCB2012KF-121T50_0805
GND3

1000P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K
PC102
5 PL102
GND4 6 1 2
GND5

2
EMC@ PC103
D 7 D
GND6

EMC_NS@

EMC_NS@
EMC@
1

1
HIGHS_PJSS0026-8B01H
ME@

+3VL
C VCCRTC C

PD101
RTC_VCC
2

1 RTC_VCC 20MIL
PR101 JRTC1 +3VL 20MIL
3 2 1 1
2 1 VCCRTC 20MIL
1K_0603_5% 3 2
GND1
2

BAT54CW_SOT323-3 4
PC105 GND2
1U_0402_6.3V6K
1

HIGHS_WS33020-S0351-HF
@ ME@

JRTC2
1
2 1
3 2
4 GND1
GND2

HIGHS_WS33020-S0351-HF
ME@

B B

35mm cable

RTC Battery for GCM BOM

A
(2nd source and quoted price ) A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-DCIN / RTC charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 50 of 58
5 4 3 2 1
 5 4 3 2 1

SUYIN_125022HB008M202ZL VBAT EMC@

D JBATT1 D
HCB2012KF-121T50_0805
1 PL201
1
2
2
EC_SMCA
1 2 BATT+ 2S1P BAT +6V
9
10 GND1 3
3
4 EC_SMDA
PR202 1
1
2 100_0402_1%
2
EC_SMB_CK1 44,52
1 2
~ 8.4 V
GND2 4 EC_SMB_DA1 44,52
5 PR201 100_0402_1%
5 6 PL202
6 7 HCB2012KF-121T50_0805
7

2
8
8 EMC@

1
ME@ PC201 PC202
1000P_0201_50V7-K 0.01U_0201_25V6-K

2
Reverse PD201 PD202 EMC@ EMC@
For EMI request
PD201

EMC_NS@
AZC199-02S.R7G_SOT23-3

1 PR209
1 2
+3VALW
100K_0402_1%

PR213
C BATT_TEMP_IN 1 2 C
10K_0402_5%
BATT_TEMP 44,52 A/D
1
1

PD202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 51 of 58
5 4 3 2 1
 5 4 3 2 1

PL301 EMC_NS@
HCB2012KF-121T50_0805
1 2

PL303 EMC_NS@
HCB2012KF-121T50_0805
AON6414AL_DFN8-5 1 2
VIN PQ311 N1
PQ312
N2
AON7408L_DFN8-5
@ PR301
1 1 PJ301 0.01_1206_1%
2 2 JUMP_43X118
5 3 3 5 1 2 1 4
1 2 V20B+
2 3

0.1U_0201_25V6-K

1000P_0201_50V7-K
D D

EMC_NS@

EMC_NS@
10U_0603_25V6-M

10U_0603_25V6-M
470P_0201_50V7-K

0.022U_0402_25V7K
4

2
PC301

PC312

PC331
1

2
EMC@

EMC@
PC303

PC304
1

PC302

1
PR302

1
4.7_0603_5%

5
2

AON6764_DFN8-5
PC305
1 2

PQ314
0.1U_0201_25V6-K
0.1U_0201_25V6-K BQ24780_BATDRV 4

1U_0603_25V6K

2
PC307

PC306

0.01U_0201_25V6-K
2

1
499K_0402_1%

3
2
1
2

PC308
PR303

1
VIN BATT+

2
432K and 64.9k change

BAT54CW_SOT323-3
to 43k and 6.49k.0.1u

PD302
change to 0.01u

3
decrease ACDET V20B+
deassert time

2200P_0201_25V7-K
VIN

10U_0805_25V6K

10U_0805_25V6K
1
1

2
4.02K_0603_1%

4.02K_0603_1%

ACN

EMC@
ACP
PR310

PR311

PC310

PC313

PC314
10_1206_5%

1
2
43K_0402_1%
1

5
PR314
BQ24780_VDD
2

1
PR313
C C
PC316

ACN
ACP

AON7408L_DFN8-5
PR315 1 2 7.15K_0402_1% PC315 2.2U_0603_10V6-K

1
2 1 780_VCC 28 24 1 2

PQ316
2
VCC REGN 4
1 2 1U_0603_25V6K ACDET 6
PC309 0.01U_0402_25V7K ACDET PR316 PC318
25 BST_CHG1 2 2 1
BTST PR317

3
2
1
BQ24780SRUYR_QFN24_4X4 2.2_0603_5% 0.047U_0603_16V7K 0.01_1206_1%
3 26 DH_CHG PL302
0.5C charge
CMSRC HIDRV
@ 1 2 CHG 1 4 BATT+
PR339 2 1 20K_0402_1% 4 4.7UH_PCMB053T-4R7MS_4A_20%
ACDRV 2 3
@

1
PR324 2 1 100K_0402_1% 27 LX_CHG
BQ24780_VDD PHASE
PR325 @ 0_0402_5% PR321

10U_0805_25V6K

10U_0805_25V6K
AON7408L_DFN8-5

2
1 2 ACIN_R 5 2.2_0805_5%

PC319
44 ACIN PR320 @ 0_0402_5% ACOK
EMC_NS@

PC320
1 2 EC_SMB_DA1_R 11

PQ317

1
44,51 EC_SMB_DA1 SDA PU301 23 DL_CHG 4
PR322 @ 0_0402_5% LODRV

1
1 2 EC_SMB_CK1_R 12 22
44,51 EC_SMB_CK1 SCL GND PC321
PR323 @ 0_0402_5% 1000P_0402_50V7K

3
2
1

2
1 2 ADP_I_R 7 29 EMC_NS@

0.1U_0201_25V6-K

0.1U_0201_25V6-K
44 ADP_I IADP PAD

2
IDCHG 8 18 BQ24780_BATDRV

PC322

PC323
PR341 @ 0_0402_5% IDCHG BATDRV
1 2 9

1
44,56 Psys PMON 17 PR338 2 1 10_0603_5%
BATSRC
100P_0201_25V8J

100P_0201_25V8J
2

PR340 @ 0_0402_5% 20 SRP_R PR328 2 1 10_0603_5% SRP

0.1U_0201_25V6-K
1 2 10 SRP
44,54,56,57 VR_HOT#

2
PROCHOT#
PC324

PC325

PC327
100P_0201_25V8J
1

13
CMPIN

1
BATPRES#
TB_STAT#
@ 14
PC1108
1

CMPOUT 19 SRN_R PR329 2 1 10_0603_5% SRN

B
ILIM 21 SRN B
ILIM
1

PR330

16

15
0_0402_5%
@
2

PR331 PR332
1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,51
14.7K_0402_1%
316K_0402_1%
0.1U_0201_25V6-K
1

100K_0402_1%
2

need config special

PC328

PR333

appliction
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 52 of 58
5 4 3 2 1
 5 4 3 2 1

+3VALW

2
PR407
100K_0402_5%
@
V20B+ @

1
PJ401 PU401
2 1
1.5A +3V_VIN 5 9 +3V_PWRGD
2 1 4 IN1 PG 1 +3VBS 1 2

EMC@ PC401

10U_0805_25V6K

10U_0805_25V6K
0.01U_0201_25V6-K
3 IN2 BS

1
PC403 0.1U_0603_25V7-M
2 IN3 +3VALW

SY8286BRAC_QFN20_3X3
JUMP_43X79

PC402

PC452
IN4 6 @

2
7 LX1 19 PL401 PJ402
@ 8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1
5A
18 GND2 LX3 2.2UH_PCMB053T-2R2MS_5.5A_20% 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
D
21 GND3 D
@

1
PR414 @ 0_0402_5% PR415 @ 0_0402_5% GND4 JUMP_43X79
1 2 EC_ON_R 1 2 +3VALW_EN 12 14 +3VALW_P PR403

PC434

PC432

PC431

PC435
38,44,54 EC_ON +3V_VIN 11 EN1 OUT 2.2_0805_5%

2
EN2 13 +3VALW_FB
FF
EMC_NS@ Vout=3.3V± 5%
10

2
15 NC1
NC2 100mA +3VLP Vset=3.37V± 1.5%

1
16 17

1M_0402_5%
0.1U_0201_25V6-K

1
NC3 LDO
OCP=12A

PR401
1
PC410

PC408

4.7U_0603_6.3V6K
1
1000P_0402_50V7K
OVP=(1.15~1.25)*Vout

2
EMC_NS@

PC409
2

2
UVP=(0.55~0.65)*Vout

2
@
Fsw=600Khz

PC411 PR405
1 2 1 2

1000P_0201_25V7K 1K_0402_1%

+3VLP @ +3VL
PJ404
2 1
2 1
JUMP_43X39

C C

+3VALW

2
PR406
100K_0402_5%
@
V20B+

1
@ PU402
PJ405
2 1
2.5A +5V_VIN 5 9 ALW_PWRGD
2 1 4 IN1 PG 1 +5VBS 1 2 @
+5VALW
0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
1

3 IN2 BS PC415 0.1U_0603_25V7-M

@
PC413

PC414

IN3
EMC_NS@

JUMP_43X79 2 PL402 PJ406

8A
PC412

IN4 6 +5VLX 1 2 +5VALW_P 2 1

PC436
2

7 LX1 19 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
8 GND1 LX2 20 @

1
18 GND2 LX3 JUMP_43X79
21 GND3 PR411

PC417

PC418

PC419

PC420

PC437
PR409 @ 0_0402_5% GND4 14 +5VALW_OUT 1 2 +5VALW_P 2.2_0805_5%

2
EC_ON_R 1 2 +5VALW_EN 12 OUT PR410 0_0402_5%
+5V_VIN EN1 EMC_NS@ Vout=5V± 3%
11 13

2
EN2 FF
15
Vset=5.1V± 1.5%
+5VLP

1
10 LDO
16 NC1 17 +5VVCC2 1 PC423
OCP=14A
100mA
1M_0402_5%
0.1U_0201_25V6-K

4.7U_0603_6.3V6K
NC2 VCC
1

1
PC416 1000P_0402_50V7K
OVP=(1.15~1.25)*Vout

2
1

EMC_NS@
PC421

PR412

PC422
SY8288CRAC_QFN20_3X3 1U_0603_25V6M
UVP=(0.55~0.65)*Vout

2
2

Fsw=600Khz
2

B B
PC424 PR413
+5VFB 1 2 1 2

1000P_0201_25V7K 1K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 53 of 58
5 4 3 2 1
 5 4 3 2 1

PR702 @ 0_0402_5%
1 2
EC_ON 38,44,53
PMIC_VCC
@
+5VALW
PR730
10,44 PM_SLP_S3#
PR738 2 1 0_0402_5% +5VLP
2 1 PR705 @ 0_0402_5%
PR706 @ 0_0402_5% 1 2
DDR_S5 PMIC_EN 44
1 2 10_0603_5%
44 SYSON @
PR707 @ 0_0402_5% 1 2
D
1 2 DDR_S3 PR704 0_0603_5%
D
44,46 SUSP#

PR708 @ 0_0402_5% PC702

1 2 1.8VALW_EN PC701 1 210U_0603_6.3V6M 2 1
44 PCH_PWR_EN
PR710 @ 0_0402_5% PR709 0.1U_0402_10V7K
1 2 1.05VS_EN VDDQ_IN1 2 @

1
PR711 @ 0_0402_5% 10_0402_5%

0.1U_0402_25V6
1 2 EC_LDO1_R

PC703
44,54 PCH_1.24V_EN

2
PR712 @ 0_0402_5%
1 2EC_LDO2_R

28

27

41
9
VCC

PMIC_EN

GND
VSYS
PR714 @ 0_0402_5%
EC_LDO1_R 29 25 1 2 PMIC_SMB_DAT0 44
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
1

1
EN_LDO1 SDA PR715 @ 0_0402_5%
@ @ @ @ @ @
1M_0402_5%

1M_0402_5%

1M_0402_5%
EC_LDO2_R 1 26 1 2

PR798

PR713
EN_LDO2 SCL PMIC_SMB_CLK0 44
2

2
PC705

PR756

PC706

PC704

PC707

PC708

PC709
1.05VS_EN 11 24 PR716 2 1 0_0402_5%
EN_V1P0A T_ALERT_B VR_HOT# 44,52,56,57
@
1

2
1.8VALW_EN 16 22
EN_V1P8A POK_V1P0A
DDR_S5 1.8VALW_PG PR718
@
31 21 2 1 100K_0402_5%
EN_VDDQ POK_V1P8A +3VALW Vout=1.0~1.1V
DDR_S3 36 23
+1.05VS OCP=10A
EN_VTT POK_VDDQ
+5VALW OVP=(1.3~1.4)*Vout
PL701
1.5A PJ701 12 PJ702
6A UVP=(0.55~0.65)*Vout

22U_0603_6.3V6-M

0.1U_0402_25V7-K
2 1 7 LX_V1P0A_12 13 LX_1P0 1 2 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2 1
1 @ 8 VIN_V1P0A_7 LX_V1P0A_13 14 0.47UH_CMMB062D-R47MS_15A_20% 2 1 Fsw=1.2MHz

1
JUMP_43X39 VIN_V1P0A_8 LX_V1P0A_14 15 JUMP_43X79
LX_V1P0A_15
@ @ +1.8VALW

PC710

PC711

PC712

PC713

PC714

PC715

PC716

PC717
C 10 C

2
2 VO_V1P0A
+5VALW PL702 @ @ Vout=1.782~1.818V
1.5A 2
PJ703
1 19 LX_V1P8A_17
17
18 LX_1P8 1 2 2
PJ704
1
3A OCP=6A
OVP=(1.15~1.25)*Vout

22U_0603_6.3V6-M
2 1 VIN_V1P8A_19 LX_V1P8A_18 1UH_PH041H-1R0MS_3.8A_20% 2 1
1 @

22U_0603_6.3V6-M

22U_0603_6.3V6-M
0.1U_0402_25V7-K
1

1
JUMP_43X39
@
VO_V1P8A_20
20 JUMP_43X79
@
UVP=(0.55~0.65)*Vout

PC718

PC719

PC720

PC721
Fsw=1.2MHz
2

2
2 33 UG_VDDQ
38 UGATE_VDDQ PR755 PC726
PC725 1 2 10U_0603_10V6K VDDQ_PWM VIN_VTT 32 BST_VDDQ 2 1 2 1
BOOT_VDDQ

LX_1P0

LX_1P8
PR731 EMC_NS@

PR732 EMC_NS@
1A 39 0_0402_5% 0.1U_0603_25V7-M
VTT
1
VTT 34 LX_VDDQ
10U_0603_6.3V6M PHASE_VDDQ
PC727

40 35 LG_VDDQ
2

VSNS_VTT LGATE_VDDQ

1
4.7_0603_5%

4.7_0603_5%
VDDQ_PWM
+1.8VALW 1
@
2 43K_0402_1% 30 VSNS_VDDQ
37
PR720
CS_VDDQ +1.24VALW

2
PJ706 @
1A 1 2 LDO1_VIN 5 6 LDO1_VOUT 2 1
1A
4.7U_0603_6.3V6K

1
PR734 0_0603_5% VIN_LDO1 LDO1 2 1

680P_0201_25V7-K

680P_0201_25V7-K
22U_0603_6.3V6-M
+1.8VS
1

1
@

EMC_NS@ PC760

PC761
JUMP_43X39
PC728

PC729

2
+3VALW Footprint need to apply
2

2
PR736 @ 0_0402_5%
LDO2_VOUT 150mA

EMC_NS@
3 1 2
150mAPR7351 @ 0_0402_5%
2 LDO2_VIN 4 LDO2
VIN_LDO2 2
FB_LDO2
1

14K_0402_1%

10U_0603_6.3V6M
4.7U_0603_6.3V6K

PR721

PC731
VREF=0.75V
2

PU701
PC730

2
LV5075AGQV_VQFN40_5X5
B B

2
1

10K_0402_1%
PR722
DIS ------8A
+5VALW
2
UMA-----4A
PJ708
VDDQ_IN 2A 2 1
2 1 V20B+

PC732 EMC@
5
JUMP_43X39

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7-K
@

1
PC733

PC734
AON7408L_DFN8-5
1

PC750

PQ701
+1.24VALW_P +1.24VALW

2
1U_0402_6.3V6K UG_VDDQ 4 @
2

500mA PJ709
+1.35V
PU702 2 1
PJ3303 6 PJ711 2 1

+1.8VALW 2 1 +1.24VALW_VIN 5 VPP 3 2A 2 1 JUMP_43X79

3
2
1
2 1 9 VIN VO1 4 2 1
TP VO2 PL703 @ 8A
PJ710
18.7K_0402_1%

22U_0603_6.3V6-M

22U_0603_6.3V6-M

JUMP_43X39 JUMP_43X39
2

+1.24VALW_EN 8 LX_VDDQ 1 2 VDDQ_PWM 2 1

1

7 VEN 2 +1.24VALW_FB PC755 2 1

@ @ @
PR753

PC756

PC757
GND

Note: the gap @ PCPC752 POK ADJ Note: the gap @ 0.47UH_CMMB062D-R47MS_15A_20% JUMP_43X79
220P_0201_25V7-K

0.1U_0402_25V6
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
.1U_0402_10V6-K

EMC_NS@
22U_0603_6.3V6-M @ @ @
2

1
@ S IC G971MF11U _SO8
PC753

PC741
AON7506_DFN
1

PR723

PC763

PC764

PC735

PC736

PC737

PC738

PC739

PC740
100K_0402_5%
1

PQ702 4.7_0805_5%
2

2
PR739 2 10_0402_5% EMC_NS@
PR751

44,54 PCH_1.24V_EN

1
LG_VDDQ
@

4
1

Vref=0.8V
34K_0402_1%

1 PC742
PR754
2

1.8VALW_PG 2
PR740
1
OCP=3.5A 680P_0402_50V7K
EMC_NS@
Fsw=1MHz
3
2
1

A @ +3VALW A
Vout=1.28~1.42V
2

0_0402_5%
OCP=15A
OVP=(1.15~1.25)*Vout
UVP=(0.55~0.65)*Vout
Fsw=1MHz

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 System PMIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 54 of 58
5 4 3 2 1
 5 4 3 2 1

+VGA_B+ PJ2401@ V20B+

JUMP_43X79

2 1
5A
2 1

+5VALW +VDDIO_GPU

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
EMC_PX@ PX@ PX@
PR2402 PX@

1
PX@ 4.7_0402_5%
1 2 VGA_VCC VGA_VDDIO 2 1

PC2402

PC2403
2

2
PC2401
PR2401 1 PX@ 1 PX@

AON6380_DFN8-5
4.7_0603_5% PX@
D D

PQ2401
PC2404 PC2405
PR2409 need change to SD000021D00_324K for f=300k. 2.2U_0402_6.3V6-K 2.2U_0402_6.3V6-K
2 2 V20B+ VGA_UGATE1 4
14 19
PX@ PX@ VGA_PVCC
VCC VDDIO VGA_VIN 2 1 +VGA_CORE
PR2406 1 2 PR2404 PX@

1
PR2405 @ 0_0402_5% 11.3K_0402_1% PX@ 4.7_0402_5% PL2401

3
2
1
1 2VGA_SET1_11 2 PR2403
0_0603_5%
1
PX@ 27 1
PC2408
1U_0402_25V6-K VGA_PHASE1
0.22UH_PCMB063T-R22MS_23A_20%
1 2
21A

2
PC2407 PVCC VIN PX@

1
EMC_PXNS@
2.2U_0402_6.3V6-K

1
2

4.7_0805_5%
PR2408 PX@ PR2407

PR2412
21

330U_D2_2V_Y

330U_D2_2V_Y
196K_0402_1% PR2410 @ 0_0402_5% PX@ PX@ 1.43K_0402_1% 1 1 1
1VGA_SET1_2 1 VGA_SET1 11 VSEN

330U_2.0V_M
2 2

AON6324_DFN8-5

AON6324_DFN8-5
SET1

PQ2403

PQ2402

PC2413

PC2406
PX@ 100P_0402_50V8J 150P_0402_50V8-J + + +

PC2410
PU2401 PX@ PC2411 2 1 2 1 PC2412 PC2414 PX@

VGA_SN2
VGA_LGATE1 PX@

PX@
PR2409 PX@ PH2401 PX@ RT3662EBGQW_WQFN32_4X4 4 4 0.47U_0402_25V6K
2 2 2

0.1U_0402_25V6
69.8K_0402_1% PR2413 @ 0_0402_5% 100K_0402_1%_TSM0B104F4251RZ PX@ PX@ 2 1
2 1VGA_TSEN_21 2 VGA_TSEN_1 2 1 3 VGA_COMP PR2414
2 1 2 1
COMP

2
30K_0402_1% PX@ PX@ @ PX@

2
VGA_FB

680P_0402_50V7K

PC2415
4 PR2415

3
2
1

3
2
1
FB

1
VGA_TSEN 10

EMC_PXNS@
10K_0402_1% PX@ PR2416

1
TSEN

PC2417
PR2419 2 @ PC2416 2 1

1
PR2418 RGND

VGA_ISEN1P
PR2417 @ 0_0402_5% PX@ 60.4K_0402_1% 100P_0402_50V8J

+VGA_CORE
2
1 2VGA_TSEN_31 2 2 1 PC2419 357_0402_1%
PX@ PX@ 0.1U_0402_25V6 PX@

2
PR2411
24K_0402_1% 22 2.2_0603_5% 2 1
VGA_VREF 13 NC 23 VGA_BOOT1 1 2
VREF_PINSET BOOT1 @
PC2418
1

24 VGA_UGATE1 0.1U_0402_25V6
PR2420 PH2402PX@ PX@ UGATE1
3.9_0402_1% 100K_0402_1%_TSM0B104F4251RZ PR2422 PR2423 25 VGA_PHASE1 1 2VGA_BOOT1_R
12.1K_0402_1% 7.87K_0402_1% PHASE1
PX@ PX@
1 2VGA_IMON_2 1 2 2 1VGA_IMON
12 26 VGA_LGATE1 PC2409
1VRFF_R_1
2

IMON LGATE1 0.22U_0603_25V7K

PR2425 PX@
C 14.3K_0402_1% C
1 2 PX@ VGA_IMON_1
7 VGA_ISEN1P
PC2420 ISEN1P VGA_CORE_SEN 21
0.47U_0402_25V6K 8 +VGA_CORE
2

ISEN1N VGA_VSS_SEN 21

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PX@
9 @ @ @ @ PX@ PX@ PX@ PX@
21,44 GPU_VR_HOT# VRHOT_L

1
15
20 VGA_PWROK PWROK

PC2423

PC2424
PC2421

PC2422

PC2425

PC2426

PC2427

PC2428
20 31

2
12,20 VR_VGA_PWRGD PGOOD BOOT2

30
UGATE2

16 29
21 GPU_SVC SVC PHASE2

28
17 LGATE2
21 GPU_SVD SVD

18 VGA_CORE
21 GPU_SVT SVT

12,24 PXS_PWREN
2 1 VGA_EN 32
EN ISEN2P
5 VGA_VCC Vboot=0.9V
PR2429 PX@
Ripple SEPC: DC=+-3% AC=+-5%
2

150K_0402_1% PX@ 33
GND 6
TDC :21A
PC2429 ISEN2N OCP :32A
1

1 2
PD2401@
.1U_0402_10V6-K OVP:1.8V
RB751V-40_SOD323-2 UVP:VID-500mV
FSW:400KH
B B

+3VGS +VDDIO_GPU
2

PX@ @ PX@ PX@

PR2430 PR2431 PR2432 PR2433
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
VR_VGA_PWRGD1

1
GPU_VR_HOT#
VGA_PWROK

VGA_PWROK

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-VGA_CORE_AMD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 55 of 58
5 4 3 2 1
 5 4 3 2 1

+1.05VS
+3VALW

PR3306

1
PR33051 2 8.2_0603_5% VCORE_VCC 1 12 VCORE_PVCC 1 2

1K_0402_1%
10K_0402_1%
+5VALW VCC PVCC +5VALW @ @ @ @

PR3301

PR3302

169_0402_1%

84.5_0402_1%
1

1
2.2_0603_5%

75_0402_1%
1U_0402_10V6-K
1
PC3301 2 14.7U_0603_10V6-K

PR3307

PR3303

PR3308
0_0402_5% @ PR3309 PR3310

PC3302
2

2
2 1 VCORE_EN 2 13 VCORE_VIN 1 2
44,57 EC_VR_ON V20B+

2
EN VIN

2
1.2_0603_5%
PR3311

2.2U_0603_10V7K

0.22U_0603_25V7K
1

1
19 2 1

PC3303

PC3304
D VCORE_VREADY 7 PSYS 20K_0402_1% PR3312
D
44 VR_CPU_PWROK VR_READY 20_0402_1%

2
Psys 44,52 VCORE_SVID_DAT
2 1
+VCORE_VREF CPU_SVID_DAT 11,57
PC3305
1 2 VCORE_VREF_R
PR3313 1 2 3.9_0402_1% 17 6 VCORE_SVID_CLK PR3314 @ 0_0402_5%
VREF VCLK VCORE_SVID_ALRT#
1 2
CPU_SVID_ALRT# 11,57
0.47U_0402_25V6K
+VCORE_VREF PR3304 1 2 30K_0402_1%VCORE_IMON 18 5 VCORE_SVID_ALRT#
IMON ALERT# VCORE_SVID_CLK 2 1
CPU_SVID_CLK 11,57
PR3315
PR33161 2 13.3K_0402_1% 4 VCORE_SVID_DAT 95.3_0402_1%
PR3318 @ 0_0402_5% VDIO
+VCORE_VREF PR3317 1 2 68.1K_0402_1%VCORE_SET1_R 1 2 VCORE_SET1 28
SET1 3
VRHOT# VR_HOT# 44,52,54,57

PR3319 1 2 2.1K_0402_1%
PU3301 PR3321
PR3322 @ 0_0402_5% 8 VCORE_BST 1 2 VCORE_BST_R
PR3320 1 2 18.7K_0402_1%VCORE_SET2_R 1 2 VCORE_SET2 27 RT3601EAGQW_WQFN28_4X4 BOOT
+VCORE_VREF

1
SET2 2.2_0603_5%
9 VCORE_HG PC3306
PR3323 24.3K_0402_1% UGATE 0.22U_0603_16V7K

2
1 2
10 VCORE_SW
PR3324 54.9K_0402_1% PR3325 @ 0_0402_5% PHASE
1 2 VCORE_SET3_R 1 2 VCORE_SET3 26
+VCORE_VREF SET3 VCORE_LG
11
PC3307 PC3308 LGATE
1 2 1 2

220P_0402_50V7K 68P_0402_50V8J 14
PR3337 @ 0_0402_5% PWM
1 2 1 2 1 2 VCORE_COMP 23 PR3328 1 2 402_0402_1% VCORE_SW
14 CPU_VCC_SENSE COMP
PR3326 PR3327 15
10K_0402_1% 23.2K_0402_1% DRVEN PC3309 1 2 0.47U_0402_25V6K
0.1U_0402_25V6

C
VCORE_FB 24 C
1000P_0402_50V7K

FB
PC3310

2 1PC3359
1 2 PR3329 1 2 499_0402_1%
PC3311
2

PR3359 @ @
100_0402_5% 680P_0402_50V7K PR3330 PH3301
1

VCORE_VSEN 25 20 VCORE_ISENP 2 1VCORE_ISENP_R 2 1

VSEN ISENP
EMC_NS@
20_0402_5% 4.7K_0402_1%_TSM0A472F34D1RZ

PR3338 @ 0_0402_5%
1 2 VCORE_RGNG 22
14 CPU_VSS_SENSE RGNG
0.1U_0402_25V6

PR3331 PH3302 21 VCORE_ISENN +CPU_CORE

PC3312

1 2 VCORE_TSEN_R 2 1 VCORE_TSEN
16 ISENN
+VCORE_VREF
2

TSEN

0.1U_0402_25V6
59K_0402_1% 100K_0402_1%_TSM0B104F4251RZ

1
EMC_NS@

PC3342
GND
PR3333

2
1 2 1 2
PR3335 121K_0402_1%

29
9.53K_0402_1%

PJ3301
VCC_VIN 2 1
3A
2 1 V20B+
JUMP_43X79
0.1U_0402_25V7-K
EMC_NS@

@
10U_0805_25V6K

10U_0805_25V6K
5

1
PC3313

B B
PC3314

PC3315
2

VCORE_HG 4

AON6380_DFN8-5 +CPU_CORE
PQ3301 PL3301
0.22UH_PCMB063T-R22MS_23A_20%
21A
3
2
1

VCORE_SW 1 2
5

EMC_NS@
2.2_0805_5%

@
PR3336

1
220U_D2_2VM_R6M

+CPU_CORE +
PC3316
1CORE_SN 2

VCORE_LG 4

AON6324_DFN8-5 2 3
PQ3302 VCORE_SW
1000P_0402_50V7K
EMC_NS@
3
2
1

PC3317

VID1=1.3V
2

+CPU_CORE Vboot=0V
DCR=2.5mohm
TDC/Iccmax=18/21A
OCP=33.6A
OVP=Vout+350mV
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

Loadline=6mΩ
PC3318

PC3319

PC3320

PC3321

PC3322

PC3323

PC3337

PC3325

PC3326

PC3336

PC3328

PC3329

PC3330

UVP=Vout-300mV
2

Fsw=600KHz
A A

@ @ @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC3335

PC3332

PC3333

PC3334

PC3331

PC3327

PC3324
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, March 09, 2017 Sheet 56 of 58
5 4 3 2 1
 5 4 3 2 1

+1.05VS
+3VALW

PR3412

1
PR34021 2 8.2_0603_5% VNN_VCC 1 12 VNN_PVCC 1 2

1K_0402_1%
10K_0402_1%
+5VALW VCC PVCC +5VALW @

PR3411

PR3401

75_0402_1%
169_0402_1%

84.5_0402_1%
1

1
2.2_0603_5%

1U_0402_10V6-K
1
PC3401 2 14.7U_0603_10V6-K

PC3402

PR3403

PR3404

PR3405
0_0402_5% @ PR3406 PR3407

2
2 1 VNN_EN 2 13 VNN_VIN 1 2
44,56 EC_VR_ON V20B+

2
EN VIN

2
1.2_0603_5%
PR3413

2.2U_0603_10V7K

0.22U_0603_25V7K
1

1
19 2 1

PC3403

PC3404
7 PSYS 20K_0402_1% PR3408
D 44 VR_VNN_PWROK VR_READY D
20_0402_1%

2
VNN_SVID_DAT 2 1
+VNN_VREF CPU_SVID_DAT 11,56
PC3405 PR3414
1 2VNN_VREF_R 1 2 3.9_0402_1% 17 6 VNN_SVID_CLK
VREF VCLK VNN_SVID_ALRT#
2 1 PR3409
CPU_SVID_ALRT# 11,56
0.47U_0402_25V6K 0_0402_5%
PR3410 1 2 35.7K_0402_1% VNN_IMON 18 5 VNN_SVID_ALRT#
+VNN_VREF IMON ALERT# VNN_SVID_CLK 2 1
CPU_SVID_CLK 11,56
PR3416 1 2 11.8K_0402_1% PR3415
4 VNN_SVID_DAT 95.3_0402_1%
PR3418 @ 0_0402_5% VDIO
PR3417 1 VNN_SET1_R
2 287K_0402_1% 1 2 VNN_SET1 28
+VNN_VREF SET1 3
VRHOT# VR_HOT# 44,52,54,56

PR3419 1 2 16K_0402_1%
PU3401 PR3420
PR3422 @ 0_0402_5% 8 VNN_BST 1 2 VNN_BST_R
PR3421 1 VNN_SET2_R
2 143K_0402_1% 1 2 VNN_SET2 27 RT3601EAGQW_WQFN28_4X4 BOOT
+VNN_VREF SET2

1
2.2_0603_5%
9 VNN_HG PC3406
UGATE 0.22U_0603_16V7K

2
PR3423 1 2 5.9K_0402_1%
10 VNN_SW
PR3425 @ 0_0402_5% PHASE
PR3424 1 VNN_SET3_R
2 102K_0402_1% 1 2 VNN_SET3 26
+VNN_VREF SET3 VNN_LG
11
PC3407 PC3408 LGATE
1 2 1 2

330P_0402_50V7K 33P_0402_50V8J 14
PR3437 @ 0_0402_5% PWM
1 2 1 2 1 2 VNN_COMP 23 PR3428 1 2 249_0402_1% VNN_SW
14 VNN_VCC_SENSE COMP
PR3426 PR3427 15
10K_0402_1% 86.6K_0402_1% DRVEN PC3410 1 2 0.47U_0402_25V6K
0.1U_0402_25V6

VNN_FB 24
1000P_0402_50V7K

FB
PC3409

C C
2

2 1PC3459
1 2 PR3429 1 2 499_0402_1%
PC3411
2

PR3459 @ @
100_0402_5% 680P_0402_50V7K PR3430 PH3401
1

VNN_VSEN 25 20 VNN_ISENP 2 1 VNN_ISENP_R 2 1

VSEN ISENP
EMC_NS@
20_0402_5% 4.7K_0402_1%_TSM0A472F34D1RZ

PR3438 @ 0_0402_5%
1 2 VNN_RGNG 22
15 VNN_VSS_SENSE RGNG
0.1U_0402_25V6

PR3431 PH3402 21 VNN_ISENN +VNN

PC3412

1 2 VNN_TSEN_R 2 1 VNN_TSEN 16 ISENN

+VNN_VREF
2

TSEN

0.1U_0402_25V6
174K_0402_1% 100K_0402_1%_TSM0B104F4251RZ

1
EMC_NS@

PC3439
GND
PR3433

2
1 2 1 2
PR3435 121K_0402_1%

29
8.66K_0402_1%

PJ3401
VNN_VIN_P 2 1
2 1 V20B+
10U_0805_25V6K

10U_0805_25V6K
1

JUMP_43X79
PC3414

PC3415

1
0.1U_0402_25V7-K
1

EMC_NS@

@
PC3413

68U_25V_M
+

PC3416
2

2
2

PQ3401 2
B B
2
3
4
9

0.47UH_PCMB053T-R47MS_13A_20% +VNN
VNN_HG 1 PL3401
10 1 2
5A
2.2_0805_5%
1

EMC_NS@

VNN_LG 8
PR3436

AON7934L_DFN10
7
6
5

+VNN
1VNN_SN

1000P_0402_50V7K

VNN_SW
EMC_NS@
PC3417
2

+VNN

VID1=1.3V
@ @ @ @ @ Vboot=1.05V
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

DCR=7.4mohm
1

1
PC3418

PC3419

PC3420

PC3435

PC3422

PC3436

PC3424

PC3425

PC3426

PC3427

PC3437

PC3429

PC3430

TDC/Iccmax=4/5A
OCP=8A
2

OVP=Vout+350mV
UVP=Vout-300mV
A A
Loadline=6mΩ
@ @ @
Fsw=600KHz
@ @ @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC3431

PC3432

PC3433

PC3434

PC3421

PC3423

PC3428
2

Title
<Title>

Size Document Number Rev

C <Doc> 1.0

Date: Thursday, March 09, 2017 Sheet 57 of 58

5 4 3 2 1
 5 4 3 2 1

20161216:SDV to SIT
1.p56-p57 add R=100ohm,C=680pF in FB pin;
2.pr3324 change to 55.4kohm,pr3323 change to 24.3k;
D 3.VNN pr3430 from 0ohm change to 20ohm, pr3428 from 210 change to 249ohm,pr3410 from 34k to 35.7k; D
4.Vcore pr3330 from 0ohm change to 20ohm, pr3328 change from 287ohm to 402ohm,pr3327 change from 28.7k to 23.2k, pr3304 change from 24k to 30k;
5. GPU change 14 items to support AMD request.

20161219:SDV to SIT
1.DEL 8pcs MLCC for VNN test result.(PC3422,PC3426,PC3434,PC3436,PC3437,PC3432,PC3435,PC3433)

20161226:SDV to SIT
1. PMIC change 1.24V Vin from 3VALW to1.8VALW;
2.chenge PR2431 from PX@ to @, PR2433 from @ to PX@,
3.change PR734 to @.

20170104:SDV to SIT
1. PMIC change LV5075B TO LV5075A

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. APLG320
Date: Thursday, March 09, 2017 Sheet 58 of 58
5 4 3 2 1