3354 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO.

8, AUGUST 2016

A Short-Channel-Effect-Degraded Noise Margin

Model for Junctionless Double-Gate MOSFET
Working on Subthreshold CMOS Logic Gates
Te-Kuang Chiang, Senior Member, IEEE

Abstract— Based on the device and equivalent transistor model,

we present a short-channel-effect (SCE)-degraded noise mar-
gin (NM) model for junctionless double-gate MOSFET working
on subthreshold CMOS logic gate. The device parameters such as
the thick silicon thickness, thick gate oxide thickness, high doping
density, and short channel length can severely degrade the NM
due to serious SCE. By contrast, both the small subthreshold
slope η and the balanced transistor strength S can suppress the
NM degradation more efficiently. The required minimum supply
voltage Vdd,min for the subthreshold CMOS logic gate is derived
by the criterion of the NM larger than thermal noise to ensure
the correct logic gate operation. Being similar to drain-induced
barrier lowering, allowable NM corresponding to the minimum
channel length can also be uniquely controlled and determined
by the scaling factor according to the scaling theory.
Index Terms— Junctionless double-gate MOSFET (JLDGFET),
noise margin (NM), scaling factor, scaling theory, subthreshold
CMOS logic gate, subthreshold slope, transistor strength.

I. I NTRODUCTION

R ECENTLY, the demand for ultralow power design has

increased tremendously for all modern very large scale
integration (VLSI) applications due to the increasing prob-
lems of leakage currents, thermal management, and reliability.
To achieve the ultralow power consumptions in digital cir-
cuits, the subthreshold current has been used in portable
computing devices and in the memory cell [1]–[4]. It is
demonstrated that subthreshold operation can achieve signif-
icant power savings in circuit applications requiring a low
to medium frequency of operation [5]. In these applications,
energy consumption is kept to a minimum by exploiting
the ultralow voltage operation with transistors working in
the subthreshold region. On the other hand, the miniatur-
ization of the devices driven by increasing the high pack-
ing density for ultra large scale integration has pushed the
feature sizes toward the nanometer regime. To extend the
scalability of CMOS technology in the nanometer regime,
short channel effect (SCE) such as large drain-induced bar-
rier lowering (DIBL) and poor subthreshold slope are the
Manuscript received February 14, 2016; revised May 4, 2016; accepted
June 14, 2016. Date of publication June 28, 2016; date of current version
July 21, 2016. This work was supported by the Ministry of Science and
Technology under Grant MOST 104-2221-E-390-014. The review of this brief
was arranged by Editor M. Ieong.
The author is with the Advanced Devices Simulation Laboratory,
Electrical Engineering Department, National University of Kaohsiung,
Kaohsiung 811, Taiwan (e-mail: tkchiang@nuk.edu.tw).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2016.2581826
0018-9383 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Fig. 1. Schematic of the CMOS inverter comprising (a) P-JLDGFET and
N-JLDGFET and (b) its circuit symbol. The input and output terminals of the
inverter are denoted by Vin and Vout . The supply voltage is Vdd . The node
voltages are defined as follows: Vin = VGp = VGn = VGn − VSn = VGSn ,
Vout = VDSn = Vdd − VSDp, VDSn = VDn − VSn , and VSDp = VSp − VDp .
major challenges [6], [7]. To alleviate the above-mentioned
problems, incorporating multigate device architecture in
silicon-on-insulator technology has minimized SCE and
extended the scaling of ultralow-power MOSFETs into the
nanoscale regime [8]. It is reported that the JL MOSFET
has a remarkably simpler fabrication process and improved
characteristics [9], [10]. In comparison with the conventional
junction-based transistor, the JL transistor not only allevi-
ates the challenges associated with the formation of steep
S/D junction in the nanoscale regime, but also makes it more
suitable for further device scaling. Up to now, the investigation
on JL transistors applied for the circuits primarily focused
on analog/ac behavior analysis [11], [12]. There are few
papers focusing on the dc behavior analysis. As logic gate in
VLSI is scaled down, SCE will degrade the circuit behavior
significantly, such that SCE should be seriously accounted
for in designing the VLSI circuit. In this brief, based on
our previously developed subthreshold current model [13]
and equivalent circuit model, we develop the NM model
CHIANG: SCE-DEGRADED NM MODEL FOR JLDGFET 3355

for the JLDG transistor working on the subthreshold CMOS

logic gate. It is shown that SCE induced by the thick silicon
film tsi , the thick gate oxide tox , and short-channel length
L g can bring about severe NM degradation. Being similar to
DIBL, allowable NM corresponding to the minimum channel
length can also be uniquely controlled and determined by the
scaling factor according to the scaling theory.
II. N OISE M ARGIN M ODEL D ERIVATION
Fig. 1(a) and (b) shows a typical schematic of the CMOS
inverter comprising N-FET and P-FET and its equivalent
logic gate symbol. To develop the NM model for the sub-
threshold CMOS logic gate, we need to use the subthreshold
current model of the JLDG devices. According to our previ-
ously developed subthreshold current model, the subthreshold
current for both the N-FET and P-FET can be expressed as
 −VDSn  VGSn −VTHCn
Fig. 2. (a) Equivalent output circuit of the inverter for high input.
Id,n = Ion 1 − e VT e θCn ηCn VT (b) Equivalent output circuit of the inverter gate for low input. REQ, p , REQ,n ,
 −VSDp  VSGp +VTHCp IEQ, p , and IEQ,n denote the equivalent resistor and the current source for
Id, p = Iop 1 − e VT e θCp ηCp VT (1) P-JLDGFET and N-JLDGFET, respectively. (c) KVL: VSDp + VDSn = Vdd .

with
⎧ √  

⎪
⎪ π Nd qμn VT VT θn
⎪
⎪ Ion = erf tsi W
⎪
⎪ 2L g θn VT
⎪
⎪
⎪
⎪ Cox
⎪
⎪θ n = (VGSn (1 − ηSn ) + Vfbn ηSn − VTHSn )
⎨
Csi tsi2 ηSn
√  
(2)
⎪
⎪ π Na qμ p VT VT θp
⎪
⎪ Iop =
⎪
⎪ erf tsi W
⎪
⎪ 2L g θp VT
⎪
⎪
⎪
⎪ Cox
⎩θ p = (VGSp (1 − ηSp ) − Vfbp ηSp + VTHSp)
Csi tsi2 ηSp
where VTHCn is the central-conduction-mode threshold
voltage for N-FET, VTHCp is the central-conduction-mode
threshold voltage for P-FET, ηSp is the surface-conduction-
mode subthreshold swing for P-FET, ηSn is the surface-
conduction-mode subthreshold swing for N-FET, ηCp is Fig. 3. Transfer curve of the CMOS inverter. The coordinates for the unit-
the central-conduction-mode subthreshold swing for P-FET, gain points are denoted by (VIL,max ,VOH,min ) and (VIH,min ,VOL,max ).
ηCn is the central-conduction-mode subthreshold swing for
N-FET [14], [15], and Vfbp and Vfbn are the flat-band voltage As Vin = Vdd is adopted for the inverter circuit shown in
for P-FET and N-FET, respectively. θCp and θCn are the ideal Fig. 1, Vout can be obtained according to Fig. 2(a). This yields
factors (1  θCp ,θCn < 2) to calibrate the subthreshold swing. S P VddηV−2Vin
Vout = IEQ, p × REQ,n = VT e T (4)
In Fig. 2, the equivalent circuit model for P-FET/N-FET Sn
including the current source and resistor of IEQ, p , IEQ,n , with
REQ, p , and REQ, p can be obtained by the Taylor’e series  
1 1 1 1
expansion of (1) [16] = + (5)
⎧ VSGp +VTHCp
η 2 ηCp ηCn
⎪
⎪ ηCp VT
⎪
⎪ I EQ, p = I op e where S p and Sn , transistor strength for P-type junctionless
⎪
⎪
⎪
⎪ VDSn VT VGSnη −VVTHCn double-gate MOSFET (P-JLDGFET) and N-type JLDGFET
⎪
⎨ REQ,n = = e Cn T
Isub,n Ion (N-JLDGFET), are defined as
(3)
⎪
⎪I
VGSn −VTHSn VTHCp −VTHCn
⎪
⎪ = I e ηCn VT
S p = Iop e ηCp VT , Sn = Ion e ηCn VT . (6)
⎪
⎪
EQ,n on
⎪
⎪ VSDp
V
VT SGp
+VTHSp
⎪
⎩ REQ, p = = e ηCp VT . Transistor strength in (6) is one of the key parameters to
Isub, p Iop indicate how strong a current the transistor can deliver to the
The noise margin (NM) can be defined by the unity-gain logic circuit. The ratio of S p to Sn and vice versa can be
points (VIL,max , VOH,min) and (VIH,min , VOL,max ) shown in used to determine the NM for the subthreshold logic gate,
Fig. 3. The coordinates of these points can be found by using which will be shown in (12) and (13). The unity-gain point of
the equivalent transistor model shown in Fig. 2(a) and (b). (VIH,min ,VOL,max) can be found by taking the derivative of (4)
3356 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 8, AUGUST 2016

with respect to Vin and setting this derivative to be −1. This

leads to
 
Vdd ηVT Sp 2
Vin = VIH,min = + ln + ln . (7)
2 2 Sn η
Equation (7) can be substituted into (4) to evaluate VOL,max
as
ηVT
Vout = VOL,max = . (8)
2
As Vin = 0 is adopted for the inverter circuit shown in Fig. 1,
Vout can be obtained according to Fig. 2(b) and (c). This
leads to
Sn VT  2Vin −Vdd 
Vout = Vdd − IEQ,n × REQp = Vdd − × e ηVT .
Sp
(9)
Being similar to (VIH,min ,VOL,max ), the unity-gain point of Fig. 4. NM versus the channel length L g for different gate oxide thicknesses.
(VIL,max ,VOH,min ) can be found by taking the derivative of (9)
with respect to Vin and setting this derivative to be −1. This
leads to
 
Vdd ηVT Sp 2
Vin = VIL,max = − ln + ln . (10)
2 2 Sn η
Equation (10) can be substituted into (9) to evaluate VOH,min
as
ηVT
Vout = VOH,min = Vdd − . (11)
2
According to Fig. 3, to evaluate the high NM of NM H , we
need to subtract (7) from (11). This yields
NM H = VOH,min − VIH,min
 
Vdd ηVT ηVT Sp 2
= − − ln + ln . (12)
2 2 2 Sn η
Similarly, the low NM of NM L can be obtained by subtract-
ing (8) from (10). This leads to
Fig. 5. NM versus the channel length L g for different silicon thicknesses.
NM L = VIL,max − VOL,max
 
Vdd ηVT ηVT Sn 2
= − − ln + ln . (13)
2 2 2 Sp η III. R ESULTS AND D ISCUSSION
NM of the logic gate can be obtained by selecting the small The 3-D device/circuit simulator device simulation for
value between NM H and NM L . This leads to smart integrated systems DESSIS [17] is used to validate
NM = Small{NM H , NM L }. (14) the proposed model. Both N-JLDGFET and P-JLDGFET
will have the same device parameters in the following sim-
Equation (14) provides a minimum value on the condition of
ulations unless otherwise stated. Fig. 4 shows NM versus
balanced transistor strength (i.e., S p = Sn ). Besides, to ensure
the channel length L g for different gate oxide thicknesses.
the logic circuit to operate correctly, NM should be ≥ thermal
In comparison with the thick tox of 3 nm, the thin tox of 1 nm
noise(∼ K T /q ∼ 26 mv at 27 °C), which leads to
  can suppress the NM degradation more efficiently. From the
2 KT viewpoint of the device physics, the thin gate oxide will induce
Vdd ≥ Vdd,min = ηVT + ηVT ln  + ln + (15)
η q the small subthreshold slope of η that can efficiently suppress
with NM degradation. In spite of alleviating NM degradation, the
 
S p Sn ultrathin gate oxide (note that in the realistic nanometer device,
 = Large , (16) the equivalent oxide thickness for the gate-stack/high dielectric
Sn S P
insulator will be used instead of the gate oxide thickness) will
where  takes the large value between S p /Sn and Sn /S p . For
initiate tunneling effects that will bring about additional static
the best case of a balanced transistor strength (i.e., S p = Sn ,
power consumption through the gate leakage current. How to
ln  = 0), to have the minimum supply voltage Vdd,min (15)
alleviate NM degradation without the penalty of additional
will be reduced to
  static power consumption should be accounted for in designing
2 KT
Vdd ≥ Vdd,min (NM) = ηVT 1 + ln + . (17) the low-power subthreshold CMOS circuit. Fig. 5 plots NM
η q versus the channel length L g for different silicon thicknesses.
CHIANG: SCE-DEGRADED NM MODEL FOR JLDGFET
Fig. 6. NM versus the channel length L g for different channel doping
concentrations.
Fig. 7. NM versus the scaling factor Lg/2λ for different combinations of
the device parameters.
As indicated in Fig. 5, thin silicon is desired to suppress
NM degradation. The main reason is that as the channel
length is further decreased, the thin silicon is suitable for
preventing a lateral electric field from penetrating the channel
region, which hence efficiently suppresses SCE and causes the
small NM degradation. Although the junctionless transistor is
heavily doped to improve the electrical performance for its
inherent gated-resistor characteristic, the high doping density
will degrade the NM behavior for the subthreshold logic gate.
Fig. 6 plots NM versus the channel length for different channel
doping concentrations. It is revealed that with increasing
channel doping density, the NM degradation will be enhanced
as the channel length is further decreased. It seems that the
deviation between model data and simulation results increases
for the short device with the thick silicon, thick gate oxide, and
high doping density. More details regarding the analysis for
the error between model data and simulation results can be
found in Appendix A. Being similar to DIBL, NM affected
by the SCE will abide by the scaling theory [18]. Fig. 7
plots NM versus the scaling factor α (= L g /2λ) for different
combinations of device parameters. Although both the scaling
length of λ (=[(4tsiεsi + Cox tsi2 )/(8Cox )]1/2 ) and the scaling
3357
Fig. 8. Minimum channel length versus silicon thickness for different
gate oxide thicknesses. (NM is kept at  50 mV according to scaling
factor = 2.2.)
factor of α (= L g /2λ) for the double-gate FET can be found
in [19], it should be pointed out that for junctionless transistor,
the scaling length will be derived from bulk-conduction-
mode instead of surface-conduction-mode due to the inherent
bulk-conduction mechanism of the junctionless transistor.
As shown in Fig. 7, when the scaling factor is decreased
below 3, NM degradation will become prominent among
different combinations of device parameters. To suppress the
NM degradation, the scaling factor should go beyond 5,
which implies that the different combination of device para-
meters such as tox , tsi , and L g should meet the criterion for
α = L g /2λ > 5 to reduce NM degradation efficiently. The
figure of merit of the scaling theory is to find the allowable
minimum channel length to fit the design criteria for the
subthreshold CMOS logic gate. Fig. 8 plots the minimum
channel length versus silicon thickness for a different gate
oxide thickness with the criterion of NM  50 mV, which
corresponds to the scaling factor of 2.2. With tsi = 15 nm,
the allowable minimum channel length will be increased from
25 to 40 nm as the gate oxide thickness is increased from
1 to 3 nm. This implies that to acquire a minimum channel
length with the allowable minimum NM (i.e., NM  50 mV),
the thin gate oxide can be determined uniquely by the scaling
theory. As for the inverter gate, it should be noted that the
leakage current will be prominent when both P-FET and
N-FET are switched ON simultaneously in the transition of
the output logic state. The leakage current and the relevant
power dissipation can be determined in Appendix B.
IV. C ONCLUSION
On the basis of the subthreshold current and equiva-
lent transistor model, an SCE-degraded NM model for the
JLDGFET working on subthreshold CMOS logic gate has
been developed. The model clearly demonstrates how the
device parameters such as the thick silicon, thick gate oxide,
high doping density, and short-channel length can degrade
the NM severely. By contrast, both the small subthreshold
slope and the balanced transistor strength can suppress the NM
degradation efficiently. Being similar to DIBL, allowable NM
3358
corresponding to the minimum channel length can be uniquely
determined and controlled by the scaling factor according to
the scaling theory. The model can be efficiently used to analyze
the behavior of NM as the JLDGFET device is working for
subthreshold CMOS logic gates. With modification, the model
can also be extended to NAND/ NOR gate.
A PPENDIX
A. Analysis of the Error Between Model Data and
Numerical Simulation Results in Figs. 4–6
According to the theory of root-mean-square (rms), the error
between model data and simulation results can be defined as

N P = 1.68 × 10−12 W.
i=1 (
NMi ) ×
L
2
σNM =
L2 − L1
NM = NMmodel − NMsimulator (1A)
where σNM is the rms error for the NM, N is the total
simulated points,
NM is the difference in NM between Circuit, vol. 40, no. 1, pp. 310–319, Jan. 2005.
model data and numerical simulation results in simulating
segment, L 2 − L 1 is the entire simulating space, and
L is the with a subthreshold power supply voltage,” IEEE J. Solid-State Circuits,
simulating segment. According to (1A) and Figs. 4–6, it can be
shown that σNM (tsi = 10 nm) = 1.20 mV, σNM (tsi = 15 nm) =
2.47 mV, σNM (tsi = 20 nm) = 4.44 mV, σNM (tox = 1 nm) =
1.20 mV, σNM (tox = 2 nm) = 2.50 mV, σNM (tox = 3 nm) =
6.25 mV, σNM (Nd = 1 × 1018 cm−3 ) = 0.88 mV,
σNM (Nd = 5 × 1018 cm−3 ) = 1.03 mV, and σNM (Nd =
1 × 1019 cm−3 ) = 1.54 mV. From the above-mentioned
analysis, it can be concluded that 1.20 mV  σNM  4.44 mV
as 10 nm  tsi  20 nm, 1.20 mV  σNM  6.25 mV as
1 nm  tox  3 nm, and 0.88 mV  σNM  1.54 mV as
1.0 × 1018 cm−3  Nd  1.0 × 1019 cm−3 . This clearly
indicates that σNM will become large as the channel length
is further decreased followed by the thick gate oxide, thick
silicon body, and high doping density, which is primarily
due to the underestimated subthreshold slope of the model.
To compensate the deviation between the model results and
numerical data, the ideal factor of θCn and θCp in (1) should be
larger than 1 (in our case, both of the ideal factors are assumed
as 1), which can be calibrated by the numerical simulation.
B. Leakage Current and Power Dissipation in the
Transition of the Output Logic State
The logic threshold of VTL at the transition of the output
logic state where both N-FET and P-FET are switched ON
simultaneously can be found by equating the P-FET and
N-FET currents in (1) with the constraint Vin = Vout = VTL ,
where VGSn = Vin , VDSn = Vout , VSDp = Vdd − Vout ,
ηCn ∼, ηC p , and VTHCn = −VTHCp are employed. Hence,
the output/input voltage can be found as
1 current model for quadruple-gate MOSFETs,” IEEE Trans. Electron
Vin = Vout = VT × ln (2A)
x
where x is the nonanalytical solution that satisfies the follow-
ing equation:
1−x 2
−1
= xη (3A)
A − Bx
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 8, AUGUST 2016
with
−Vin Iop ηV
Vdd Vdd −Vdd
Iop ηV
x =e VT , A= e T, B= e T e VT . (4A)
Ion Ion
Using the graphic method to solve (3A), x can be achieved.
By substituting x into (2A), the input/output voltage can
be determined. With the channel doping density of 1.0 ×
1018 cm−3 , tsi = 10 nm, tox = 1 nm, L g = 40 nm,
and Vdd = 0.2 V, the input/output voltage, leakage cur-
rent, and relevant power dissipation can be obtained as
Vin = 0.085 V, Id = 6.4 × 10−12 A, and P = 1.28 × 10−12 W,
respectively, which agrees well with the numerical simulation
results of Vin = 0.087 V, Id = 8.4 × 10−12 A, and
R EFERENCES
[1] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor
using a minimum energy design methodology,” IEEE J. Solid-State
[2] J. Chen, L. T. Clark, and T.-H. Chen, “An ultra-low-power memory
vol. 41, no. 10, pp. 2344–2353, Oct. 2006.
[3] S. Chakraborty, A. Mallik, C. K. Sarkar, and V. R. Rao, “Impact of
halo doping on the subthreshold performance of deep-submicrometer
CMOS devices and circuits for ultralow power analog/mixed-signal
applications,” IEEE Trans. Electron Devices, vol. 54, no. 2, pp. 241–248,
Feb. 2007.
[4] R. Vaddi, S. Dasgupta, and R. P. Agarwal, “Device and circuit co-
design robustness studies in the subthreshold logic for ultralow-power
applications for 32 nm CMOS,” IEEE Trans. Electron Devices, vol. 57,
no. 3, pp. 654–664, Mar. 2010.
[5] J. Rabaey et al., “Ultra-low-power design—The roadmap to disappearing
electronics and ambient intelligence,” IEEE Circuits Devices Mag.,
vol. 22, no. 4, pp. 23–29, Jul./Aug. 2006.
[6] A. Gnudi, S. Reggiani, E. Gnani, and G. Baccarani, “Semianalytical
model of the subthreshold current in short-channel junctionless symmet-
ric double-gate field-effect transistors,” IEEE Trans. Electron Devices,
vol. 60, no. 4, pp. 1342–1348, Apr. 2013.
[7] A. Koukab, F. Jazaeri, and J.-M. Sallese, “On performance scaling
and speed of junctionless transistors,” Solid-State Electron., vol. 79,
pp. 18–21, Jan. 2013.
[8] I. Ferain, C. A. Colinge, and J.-P. Colinge, “Multigate transistors as the
future of classical metal–oxide–semiconductor field-effect transistors,”
Nature, vol. 479, no. 7373, pp. 310–316, 2011.
[9] D. Ghosh, M. S. Parihar, G. A. Armstrong, and A. Kranti,
“High-performance junctionless MOSFETs for ultralow-power ana-
log/RF applications,” IEEE Electron Device Lett., vol. 33, no. 10,
pp. 1477–1479, Oct. 2012.
[10] M. S. Parihar, D. Ghosh, G. A. Armstrong, and A. Kranti, “Bipolar snap-
back in junctionless transistors for capacitorless dynamic random access
memory,” Appl. Phys. Lett., vol. 101, no. 26, pp. 263503-1–263503-4,
2012.
[11] S. Cho, K. R. Kim, B. G. Park, and I. M. Kang, “RF perfor-
mance and small-signal parameter extraction of junctionless silicon
nanowire MOSFETs,” IEEE Trans. Electron Devices, vol. 58, no. 5,
pp. 1388–1396, May 2011.
[12] Y.-C. Chang et al., “Study of junctionless pseudo tri-gate vertical MOS-
FETs for RF/analog applications,” in Proc. Int. Symp. Next-Generat.
Electron. (ISNE), Nov. 2010, pp. 93–95.
[13] C. Te-Kuang, “A new interface-trapped-charge-degraded subthreshold
Devices, vol. 61, no. 5, pp. 1611–1614, May 2014.
[14] T.-K. Chiang, “A quasi-two-dimensional threshold voltage model
for short-channel junctionless double-gate MOSFETs,” IEEE Trans.
Electron Devices, vol. 59, no. 9, pp. 2284–2289, Sep. 2012.
[15] C. Te-Kuang and J. L. Juin, “An analytical subthreshold current/swing
model for junctionless cylindrical nanowire FETs (JLCNFETs),” Facta
Univ. Ser., Electron. Energetics, vol. 26, no. 3, pp. 157–173, Dec. 2013.
CHIANG: SCE-DEGRADED NM MODEL FOR JLDGFET
[16] M. Alioto, “Understanding DC behavior of subthreshold CMOS logic
through closed-form analysis,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 57, no. 7, pp. 1597–1607, Jul. 2010.
[17] ‘DESSIS’: 3D/2D Device Simulator, Integrated Systems Engineering,
Synopsys, Mountain View, CA, USA, 2003.
[18] C. P. Auth and J. D. Plummer, “Scaling theory for cylindrical, fully-
depleted, surrounding-gate MOSFET’s,” IEEE Electron Device Lett.,
vol. 18, no. 2, pp. 74–76, Feb. 1997.
[19] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling
theory for double-gate SOI MOSFET’s,” IEEE Trans. Electron Devices,
vol. 40, no. 12, pp. 2326–2329, Dec. 1993.
3359
Te-Kuang Chiang (M’02–SM’14) received the
Ph.D. degree from National Cheng Kung University,
Tainan, Taiwan. He is currently a Full Professor of
Electrical engineering with the National University
of Kaohsiung, Kaohsiung, Taiwan.
Dr. Chiang is also a Reviewer of the IEEE
T RANSACTIONS ON E LECTRON D EVICES , the
IEEE T RANSACTIONS ON D EVICE AND M ATERI -
ALS R ELIABILITY , Solid-State Electronics, Micro-
electronics Reliability, and the IEEE E LECTRON
D EVICE L ETTERS .