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Features
• Output voltage tolerance ≤ ±2%
• Low-drop voltage
• Integrated overtemperature protection
• Reverse polarity protection
• Input voltage up to 42 V
• Overvoltage protection up to 65 V (≤ 400 ms)
• Short-circuit proof
• Suitable for use in automotive electronics
• Wide temperature range
• Adjustable reset and watchdog time
• Green Product (RoHS compliant)
Potential applications
General automotive applications.
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
The OPTIREG™ Linear TLE4271-2 is functional and electrical identical to TLE4271.
The device is a 5-V low drop fixed voltage regulator. The maximum input voltage is 42 V (65 V, ≤ 400 ms). Up to
an input voltage of 26 V and for an output current up to 550 mA it regulates the output voltage within a 2%
accuracy. The short circuit protection limits the output current of more than 650 mA. The IC can be switched
off via the inhibit input. An integrated watchdog monitors the connected controller. The device incorporates
overvoltage protection and temperature protection that disables the circuit at overtemperature.
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1 Block diagram
Temperature Saturation
Control and
Sensor
Protection
Circuit
1 7
Ι Q
Control
Amplifier
Buffer 3
Adjustment Bandgap RO
+
Reference
-
Reset
Generator 5
D
6
Watchdog WI
2 4
INH GND AEB01940
2 Pin configuration
1 7
I RO D Q
INH GND WI
3.3 Characteristics
Table 4 Characteristics
VI = 13.5 V; Tj = -40°C to 125°C; VINH > VU,INH (unless otherwise specified)
Parameter Symbol Values Unit Note or
Min. Typ. Max. Test Condition
Output voltage VQ 4.90 5.00 5.10 V IQ = 5 mA to 550 mA;
VI = 6 V to 26 V
Output voltage VQ 4.90 5.00 5.10 V VI = 26 V to 36 V;
IQ ≤ 300 mA
Output current limiting IQmax 650 800 – mA VQ = 0 V
Current consumption Iq – – 6 µA VINH = 0 V;
Iq = II IQ = 0 mA
Current consumption Iq – 800 – µA VINH = 5 V;
Iq = II IQ = 0 mA
Current consumption Iq – 1 1.5 mA IQ = 5 mA
Iq = II - IQ
Current consumption Iq – 55 75 mA IQ = 550 mA
Iq = II - IQ
Current consumption Iq – 70 90 mA IQ = 550 mA;
Iq = II - IQ VI = 5 V
Drop voltage Vdr – 350 700 mV IQ = 550 mA1)
Load regulation ∆VQ – 25 50 mV IQ = 5 mA to 550 mA;
VI = 6 V
Supply voltage regulation ∆VQ – 12 25 mV VI = 6 V to 26 V;
IQ = 5 mA
Power supply ripple rejection PSRR – 54 – dB ƒr = 100 Hz;
Vr = 0.5 Vpp
Reset generator
Switching threshold VRT 4.5 4.65 4.8 V –
Reset high voltage VROH 4.5 – – V –
Saturation voltage VRO,SAT – 60 – mV Rintern = 30 kΩ;
VQ = 1.0 V to 4.5 V
Saturation voltage VRO,SAT – 200 400 mV IR = 3 mA2);
VQ = 4.4 V
Reset pull-up R 18 30 46 kΩ Internally
connected to Q
Lower reset timing threshold VLD 0.2 0.45 0.8 V VQ < VRT
Charge current ID 8 14 25 µA VD = 1.0 V
Upper timing threshold VUD 1.4 1.8 2.3 V –
Delay time tD 8 13 18 ms CD = 100 nF
Reset reaction time tRR – – 3 µs CD = 100 nF
4 Circuit description
The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment,
to a voltage that is proportional to the output voltage and drives the base of a series transistor via a buffer.
Saturation control as a function of the load current prevents any over-saturation of the power element.
The reset output RO is in high-state if the voltage on the delay capacitor CD is greater or equal VUD. The delay
capacitor CD is charged with the current ID for output voltages greater than the reset threshold VRT. If the output
voltage gets lower than VRT (‘reset condition’) a fast discharge of the delay capacitor CD sets in and as soon as
VD gets lower than VLD the reset output RO is set to low-level.
The time for the delay capacitor charge from VUD to VLD is the reset delay time tD.
When the voltage on the delay capacitor has reached VUD and reset was set to high, the watchdog circuit is
enabled and discharges CD with the constant current IDWD. If there is no rising edge observed at the watchdog
input, CD will be discharge down to VLDW, then reset output RO will be set to low and CD will be charged again
with the current IDWC until VD reaches VUD and reset will be set high again.
If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge period CD is charged
again and the reset output stays high. After VD has reached VUD, the periodical behavior starts again.
Internal protection circuits protect the IC against:
• Overload
• Overvoltage
• Overtemperature
• Reverse polarity
ΙΙ 1 7
ΙQ
1000 μF 470 nF 22 μF
TLE 4271-2
2
Ι
3 RO
VΙ VQ
5 6 4
V INH ΙD Ι GND
V RO
VD CD V WI
AES01941
1 7
Input 5 V-Output
470 nF
Input 2
e.g. KL 15 TLE 4271-2
22 μF
Reset 3 5
to MC
4 6 100 nF
Watchdog
Signal
from MC AES01942
Figure 4 Circuit
Application description
The IC regulates an input voltage in the range of 6 V < VI < 40 V to VQnom = 5.0 V. Up to 26 V it produces a regulated
output current of more than 550 mA. Above 26 V the save-operating-area protection allows operation up to
36 V with a regulated output current of more than 300 mA. Overvoltage protection limits operation at 42 V. The
overvoltage protection hysteresis restores operation if the input voltage has dropped below 36 V. The IC can
be switched off via the inhibit input, which causes the quiescent current to drop below 10 µA. A reset signal is
generated for an output voltage of VQ < 4.5 V. The watchdog circuit monitors a connected controller. If there is
no positive-going edge at the watchdog input within a fixed time, the reset output is set to low. The delay for
power-on reset and the maximum permitted watchdog-pulse period can be set externally with a capacitor.
Reset circuitry
If the output voltage decreases below 4.5 V, an external capacitor CD on pin D will be discharged by the reset
generator. If the voltage on this capacitor drops below VDRL, a reset signal is generated on pin RO, i.e. reset
output is set low. If the output voltage rises above the reset threshold, CD will be charged with constant
current. After the power-on-reset time the voltage on the capacitor reaches VDU and the reset output will be
set high again. The value of the power-on-reset time can be set within a wide range depending of the
capacitance of CD.
Reset timing
The power-on reset delay time is defined by the charging time of an external capacitor Cd which can be
calculated as follows:
tD = CD × ∆V/ID (4.1)
Definitions:
• CD = delay capacitor
VΙ
VINH t
VU, INH
VL, INH
< t RR t
VQ
VRT
t RR t
VD
dV Ι D
=
dt C D
VUD
VLD
VD, SAT
t
VRO
tD
VRO, SAT
t
Watchdog timing
V WΙ
VΙ
VQ
t WΙ, tr t WD, P
VD
VUDW
VLDW
VR t WD, L
AED01928 AED01929
5.2 12
V
VQ V
VQ
5.1 10
VI = 13.5 V
5.0 8
4.9 6
R L = 25 Ω
4.8 4
4.7 2
4.6 0
-40 0 40 80 120 ˚C 160 0 2 4 6 8 V 10
Tj VΙ
AED01930 AED01931
1200 1.2
mA
I Q max IQ A
1000 1.0
800 0.8
T j = 125 ˚C
600 0.6 25 ˚C
400 0.4
200 0.2
0 0
-40 0 40 80 120 ˚C 160 0 10 20 30 40 V 50
Tj VI
AED03076 AED03077
6 80
mA
Ιq mA Ιq
70
5
60
4
50
3 40
VΙ = 13.5 V
30
2 VΙ = 13.5 V
20
1
10
0 0
0 20 40 60 80 mA 120 0 100 200 300 400 mA 600
ΙQ ΙQ
AED01934 AED02755
120 800
mV
Iq mA V Dr 700
100
600
80
500
R L = 10 Ω T j = 125 C
60 400
300
40
R L = 20 Ω 200 T j = 25 C
50 Ω
20
100
0 0
0 10 20 30 40 V 50 0 200 400 600 mA 1000
VI ΙQ
AED01944 AED01945
12 6
μA Ι INH, high V
Ι INH VQ
10 5
V Ι = 13.5 V
Ι INH, on
T j = 25 C
8 4
6 3
V Ι = 13.5 V
T j = 25 C
4 2
2 1
Ι INH, off
0 0
0 1 2 3 4 5 V 6 0 1 2 3 4 5 V 6
V INH V INH
AED01946 AED01947
14 6
μA V
Ι INH V INH
12
5
Ι INH, high
10
4
8
Ι INH, on 3
6
V INH, on
2
4
2 1
V INH, off
Ι INH, off
0 0
-40 0 40 80 120 160 -40 0 40 80 120 C 160
Tj Tj
AED01948
2.4
V
V Ι = 13.5 V
V
2.0
V UD , V UDW
1.6
1.2
0.8
0.4
V LDW
0
-40 0 40 80 120 C 160
Tj
Charge current ID, IDWC and discharge current IDWD Watchdog pulse time Tw versus
versus junction temperature Tj junction temperature Tj
AED01949 AED01950
16 80
µA I D, I DWC ms
I T W 70
14
12 60
10 50
VI = 13.5 V V Ι = 13.5 V
8 VD = 1 V 40
C D = 100 nF
6 30
4 20
I DWD
2 10
0 0
-40 0 40 80 120 ˚C 160 -40 0 40 80 120 C 160
Tj Tj
6 Package information
4.4
10 ±0.2
1.27 ±0.1
0...0.3
A B
8.5 1)
1±0.3 0.05
2.4
7.551)
9.25 ±0.2
0.1
(15)
2.7 ±0.3
4.7 ±0.5
0...0.15
7 x 0.6 ±0.1 0.5 ±0.1
6 x 1.27
0.25 M A B 8˚ MAX.
0.1 B
1) Typical
Metal surface min. X = 7.25, Y = 6.9
All metal surfaces tin plated, except area of cut. GPT09114
1) Dimensions in mm
7 Revision history
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