CISC stands for Complex Instruction Set
Computer
What do ARM stands for, it developed the
large variations in superscalars as application-
specific needs. Advance RISC Machines
RISC stands for Reduced Instruction Set
Computer
This input is used to force the Pentium to limit
addressable memory to 1 MB, to emulate the
memory space the memory space of 8086.
A20M (Address 20 Mask)
It is a special type of high speed RAM where
data and the address of the data are stored.
Cache
The following is true for r/m except: When
mod = 11, r/m indicates a REG field.
The Direction flag is cleared by this
instruction. CLD
It is another way of referring to a subroutine
and has to do with the assembler directives
PROC and ENDP used in the source file.
Procedures
Which of the following is a Logical
Instruction? TEST
Which of the following are Bit Manipulation
Instructions? All of the above
It is a collection of Instructions that is called
from one or many other different locations
within a program. Subroutine
This Instruction sets the carry flag. STC
These instructions are used to preserve the
contents of the outer loop counter. PUSH and
POP
mm=___ is automatically used for direct
addressing 00
This group of instructions allows the
programmer to choose where the processor
fetches its next instruction from Program
Transfer Instruction
What does IN AL, DX do? Reads byte of
data from I/O port (addressed by DX) into
AL
Which addressing mode execute its instruction
within CPU without the necessity of reference
memory for operands?
If SP = 1E00H before PUSH AX, what does it
equal after PUSH AX? 1DFEH
If AL contains FFH, what does it contain after
INC AL executes? 00H
Which of the following examples is an
Immediate Addressing Mode? MOV AL,
FFH
It transfers the source immediate byte or word
of data into the destination register or memory
location Immediate Addressing Mode
An example of Indexed Addressing Mode
ADD AL, [DI+16]
It moves a byte or a word between a memory
location and a register Direct Addressing
Mode
Data transfer group contains instructions that
transfer from _____ Memory to register,
register to register, register to memory
MOV DL, [SI] is a sample of which type of
addressing?
Which of the following examples is a direct
addressing mode? MOV [500H], AL
The source file is converted into a(n) _____
wherein it contains all the actual binary
information Object file
MOVS is used to _______ Copy the source of
the string to the destination string
What segment is used to store a destination
string?
Which of the following examples is an
Register Addressing Mode? None of the
choices
It transfers a byte or a word between a register
and a memory location addressed by an index
or base register Based Addressing Mode
Based addressing mode example MOV DX,
[BX+04]
What is the result of SHL AL, CL if AL =
3EH and CL = 04H E0H
This instruction pushes all registers to the
stack PUSHA
Mode MOV AX, [BX]
What are the contents of AH and AL after
MOV AX, 4 executes? AH = 0, AL = 04
CISC stands for______.
a. Complicated Instruction System Computer
b. Complex Instruction Set Computer
c. Complex Instruction System Computer
d. Complicated Instruction Set Computer
2. What do ARM stands for, it developed the
large variations in superscalars as per
application-specific needs
a. Advance RISC Machines
b. Advance Response Machines
c. Advance Robotic Machines
d. Advance Reprogrammable Machines
3. RISC stands for_____.
a. Reduced Instructive System Computer
b. Reused Instruction Set Computer
c. Reused Instruction System Computer
d. Reduced Instruction Set Comput
If SI = 1000H, what does MOV [SI], BH do?
Writes byte of data from BH into memory
location 1000H
In this addressing mode, the operands offset
address is found by adding the contents of SI
or DI register and 8-bit/16-bit displacements
Indexed addressing mod
The addressing mode in which the effective
address of the memory location is visibly part
of the instruction Direct Mode
A type of addressing mode, the offset address
of the operand is given by the sum of contents
of BX/BP registers and 8-bit/16-bit
displacement. Based addressing mode
This is an example of register Indirect
Addressing
Which is not a valid logical instruction? XO
4. Which technique does the Pentium Pro
employs here the processor looks ahead into
the instruction stream, executing instructions
out of order, so that the instruction pipeline
can be kept busy
a. Predication
b. Speculative Execution
c. Superthreading
d. Register renaming
5. Which two bit value has the highest priority
of Requestor Privilege level in a Segment
Selector for a Protected-mode Operation?
a. 00
b. 01
c. 10
d. 11
6. This input is used to force the Pentium to
limit addressable memory to 1MB to emulate
the memory space the memory of the 8086. a. CLC
a. A20M (Address 20Mask) b. STC
b. ADS (Address Strobe) c. CMC
c. AHOLD (Address Hold) d. CLD
d. AP (Address Parity)
12. It is another way of referring to a
7. A processor design, where single instruction subroutine and has to do with the assembler
can execute several low-level operations or directives PROC and ENDP used in the source
addressing modes within single instruction? file
a. CISC processor a. Procedures
b. RISC processor b. Processor
c. Celeron c. CALL
d. Athion d. RET

8. It is a special type of high speed RAM

where data and the address of the data are
stored.
a. Clock
b. Burst Ready 13. This instruction clears the carry flag.
c. Cache a. CLC
d. Bus Lock b. STC
c. CMC
9. The following is true for r/m except: d. CLD
a. r/m refers to registers that are enclosed in a 14. Which of the following is a logical
bracket instruction
b. When mod = 11, r/m indicates a REG field a. TEST
c. r/m specifies the addressing mode b. CMP
d. Both B and C c. ADC
d. SHL
10. D-bit indicates the _____.
a. Direction of Data flow 15. Which of the following are Bit
b. Destination of transfer Manipulation
c. Source of transfer Instructions
d. Both B and C a. Shift Instructions
b. Logical Instructions
11. The direction flag is cleared by this c. Rotate Instructions
instruction. d. All of the above
16. The ____ part specifies the addressing addressing
mode for the selected instruction a. 00
a. REG (reg) b. 01
b. R/M (r/m) c. 10
c. Addr-low d. 11
d. MOD (mm)

17. It is a collection of instructions that is

called from one or many other different
locations within a program.
a. Jump
b. Loop 23. This group of instructions allows the
c. Subroutine programmer to choose where the processor
d. Relative offset fetches its next instruction from
a. Bit Manipulation Instructions
18. It is used to examine the state of individual b. Arithmetic Instructions
bits, or groups of bits. c. Logical Instructions
a. CMP d. Program Transfer Instruction
b. TEST
c. Bit Scan forward 24. What does IN AL, DX do?
d. Bit test a. reads byte of data from I/O port (addressed
by DX) into AL
19. Using 100010dw mmregr/m in applicable b. writes byte of data from AL into I/O port
for the converting the following assembly (addressed by DX)
languages to machine codes except: c_._ _p_u_t_s_ _a_ _c_o_p_y_ _o_f_ _D_X_
a. MOV AX, [BX] _‘i_n_’ _A_L_ _
b. MOV ES, AX d. none of the above
c. MOV [BP+4891H], DL
d. MOV [1000H], DL 25. Which addressing mode execute its
instruction within CPU without the necessity
20. This instruction sets the carry flag. of reference memory for operands?
a. CLC a. Implied Mode
b. STC b. Immediate Mode
c. CMC c. Direct Mode
d. CLD d. Register Mode

21. These instructions are used to preserve the 26. If SP = 1E00H before PUSH AX, what
contents of the outer loop counter. does it equal after PUSH AX?
a. PUSH and LOOP a. 1DFEH
b. LOOP and POP b. 1E02H
c. PUSH and PUSH c. 1E00H
d. PUSH and POP d. none of the above

22. mm=___ is automatically used for direct

27. If AL contains FFH, what does it contain
after INC AL executes?
a. 00H
b. FEH
c. 100H
d. none

28. Which of the following examples is an

Immediate Addressing Mode?
a. MOV AL, FFH
b. MOV AX, [BX+4]
c. MOV [DI-8], BL
d. MOV [500H], AL

29. It transfers the source immediate byte or

word of data into the destination register or
memory location
a. Register Addressing Mode
b. Immediate Addressing Mode
c. Based Addressing Mode
d. Based Indexed Addressing
30.) 30. An example of Indexed Addressing
Mode
a. ADD AL, [DI+16]
b. MOV DX, [BX+04]
c. MOV AL, FFH
d. MOV CX, AX
 d. Register Indirect
31. It moves a byte Addressing
or a word between a
memory location and 34. Which of the
a register following examples
a. Register is a direct addressing
Addressing Mode mode?
b. Immediate a. MOV CL, [BX-
Addressing DI+2]
c. Indirect b. MOV AX,
Addressing Mode [BX+4]
d. Direct Addressing c. MOV [500H], AL
Mode d. none of the above

32. Data transfer

group contains
instructions that 35. The source file is
transfer from converted into a(n)
a. Memory to _____ wherein it
register, register to contains all the
memory, memory to actual binary
memory, register to information
register a. Machine code
b. Memory to b. Pseudo-opcode
memory, register to c. List file
register, register to d. Object file
memory
c. Memory to 36. MOVS is used to
memory, memory to _______
register, register to a. Move the signed
memory value to the
d. Memory to destination
register, register to b. Copy the source to
register, register to the destination
memory c. Move the source
to the destination
33. MOV DL, [SI] is d. Copy the source of
a sample of which the string to the
type of addressing? destination string.
a. Indirect
Addressing 37. What segment is
b. Register used to store a
Addressing destination string?
c. Base Addressing a. CS
b. DS 42. What is the result
c. ES of SHL AL, CL if
d. none of the above AL = 3EH and CL =
04H
38. Which of the a. AL = 03H
following examples b. AL = E4H
is an Register c. AL = E0H
Addressing Mode? d. none of the above
a. MOV CL, [BX-
DI+2] 43. This instruction
b. MOV DL, [SI] pushes all registers
c. MOV AL, 12H to the stack
d. none of the a. PUSHD
choices b. PUSH
c. PUSHF
d. PUSHA
40. It transfers a byte
or a word between a 44. If SI = 1000H,
register and a what does MOV
memory location [SI], BH do?
addressed by an a. reads byte of data
index or base register from memory
a. Base-Relative- location 1000H into
Plus Index BH
Addressing Mode b. writes byte of data
b. Register Indirect from BH into
Addressing Mode memory location
c. Based Addressing 1000H
Mode c_._
d. Indexed _i_l_l_e_g_a_l_,_
Addressing _o_n_l_y_ _D_I_
Mode _c_a_n_ _b_e_
_u_s_e_d_
_b_e_t_w_e_e_n_
_[_ _]_ _‘s_ _
d. none of the above
41. Based addressing
mode example
a. MOV CX, AX
b. MOV DX,
[BX+04]
c. MOV AL, FFH
d. MOV AX, [BX]
45. In this addressing mode, the operands 50. Which is not a valid logical instruction?
offset address is found by adding the a. AND
contents of SI or DI register and 8- bit/16-bit b. NAND
displacements c. XO
a. Based Addressing mode d. OR
b. Direct Mode
c. Indexed Addressing Mode
VILLAMOR COMPILED
d. Register Indirect Addressing Mode
1. Which of the following is not an
46. The addressing mode in which the addressing mode of 8051?
effective address of the memory location is a) register instructions
b) register specific instructions
visibly part of the instruction
c) indexed addressing
a. Implied Mode
b. Immediate Mode d) none
c. Direct Mode Answer: D. None
d. Register Mode 2. A symbol, ‘addr 16’ represents the 16-bit
address which is used by the instructions to
47. A type of addressing mode, the offset specify the
address of the operand is given by the sum a) destination address of call or jump
of contents of BX/BP registers and 8-bit/16- b) source address of JUMP
bit displacement. c) destination address of CALL
d) source address of call or jump
a. Based Addressing Mode
b. Direct Mode Answer: A. destination address of call or
jump
c. Immediate Mode
d. Register Indirect Addressing Mode 3. A storage of address that can be directly
accessed is
48. This is an example of register Indirect a) internal data RAM and SFRS
Addressing Mode b) internal data ROM
a. MOV CX, AX c) external data RAM
b. MOV AL, FFH d) external data ROM and SFRS
c. MOV DX, [BX+04] Answer: A. internal data RAM and
d. MOV AX, [BX] SFRS
4. The address register for storing the 16-bit
49. What are the contents of AH and AL addresses can only be
after MOV AX, 4 executes? a) stack pointer
b) accumulator
a. AH = ?? , AL = 04
b. AH = 04, AL = ?? c) instruction register
d) data pointer
c. AH = 0, AL = 04
d. none of the above Answer: B. data pointer
5. The address register for storing the 8-bit
addresses can be
a) R0 of selected bank of register
b) R1 of selected bank of register
c) stack pointer
d) all of the mentioned
Answer: D. all of the mentioned

6. The instruction, ADD A, R7 is an

example of
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
Answer: A. register instructions 12. The data address of look-up table is
7. The addressing mode, in which the found by adding the contents of
instructions has no source and destination a) accumulator with that of program counter
operands is b) accumulator with that of program counter
a) register instructions or data pointer
b) register specific instructions c) data register with that of program counter
c) direct addressing or accumulator
d) indirect addressing
Answer: B. register specific instructions
8. The instruction, RLA performs
a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right
Answer: B. rotation of accumulator to left
9. The instruction, ADD A, #100 performs
a) 100(decimal) is added to contents of
address register
b) 100(decimal) is subtracted from
accumulator
c) 100(decimal) is added to contents of
accumulator
d) none
Answer: C. 100(decimal) is added to
contents of accumulator
10. In which of these addressing modes, a
constant is specified in the instruction, after
the opcode byte?
a) register instructions
b) register specific instructions
c) direct addressing
d) immediate mode
Answer: D. immediate mode
11. The only memory which can be accessed
using indexed addressing mode is
a) RAM
b) ROM
c) main memory
d) program memory
Answer: D. program memory
d) data register with that of program counter
or data pointer
 17. In the following indexed addressing
13. The instruction, Add #45,R1 does, mode instruction, MOV 5(R1),LOC the
a) Adds the value of 45 to the address of R1 effective address is ______ .
and stores 45 in that address a) EA = 5+R1
b) Adds 45 to the value of R1 and stores it in b) EA = R1
R1 c) EA = [R1]
c) Finds the memory location 45 and adds d) EA = 5+[R1]
that content to that of R1 Answer: D. EA = 5+[R1]
d) None of the above
Answer: B. Adds 45 to the value of R1 18. The addressing mode/s, which uses the
and stores it in R1 PC instead of a general purpose register is
14. In case of, Zero-address instruction ______ .
method the operands are stored in _____ . a) Indexed with offset
a) Registers b) Relative
b) Accumulators
c) Push down stack
d) Cache
Answer: C. Push down stack
15. Add #45, when this instruction is
executed the following happen/s,
a) The processor raises an error and
requests for one more operand
b) The value stored in memory location 45 is
retrieved and one more operand is requested
c) The value 45 gets added to the value on
the stack and is pushed onto the stack
d) None of these
Answer: B. The value stored in memory
location 45 is retrieved and one more
operand is requested
16. The addressing mode which makes use
of in-direction pointers is ______ .
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
Answer: A. Indirect addressing mode
c) direct
d) both a and c
Answer: B. Relative
19. When we use auto increment or auto
decrement, which of the following is/are
true
1) In both, the address is used to retrieve the
operand and then the address gets altered.
2) In auto increment the operand is retrieved
first and then the address altered.
3) Both of them can be used on general
purpose registers as well as memory
locations.
a) 1,2,3
b) 2
c) 1,3
d) 2,3
Answer: D. 2,3
20. The addressing mode, where you
directly specify the operand value is
_______ .
a) Immediate
b) Direct
c) Definite
d) Relative
Answer: A. Immediate
21. The effective address of the following
instruction is , MUL 5(R1,R2)
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2]
d) 5*([R1]+[R2])
Answer: C. 5+[R1]+[R2]
22. _____ addressing mode is most suitable
to change the normal sequence of execution
of instructions .
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
Answer: A. Relative
COE121/C1
Quiz 3
1. Which addressing mode execute its
instructions within CPU without the
necessity of reference memory for
operands?
A. Implied Mode
B. Immediate Mode
C. Direct Mode
D. Register Mode
ANSWER: D. Register Mode
2. How is the effective address of base-
register calculated?
A. By addition of index register contents to
the partial address in instruction
B. By addition of implied register contents
to the partial address in instruction
C. By addition of index register contents to
the complete address in instruction
D. By addition of implied register contents
to the complete address in instruction
ANSWER: A. By addition of index register
contents to the partial address in instruction
3. It is an addressing mode in which the data
operand is a part of the instruction itself.
A. Implied Mode
B. Immediate Mode
C. Direct Mode
D. Register Mode
ANSWER: B. Immediate Mode
4. An example of immediate addressing
mode
A. MOV AL, FFH
B. MOV CX, AX
C. MOV DX, [BX+04]
D. MOV AX, [BX]
ANSWER: A. MOV AL, FFH
5. An example of register addressing mode
A. MOV CX, AX
B. MOV AL, FFH
C. MOV DX, [BX+04]
 D. MOV AX, [BX]
ANSWER: A. MOV CX, AX
6. The addressing mode in which the
effective address of the memory location is
written directly in the instruction.
A. Implied Mode
B. Immediate Mode
C. Direct Mode
D. Register Mode
ANSWER: C. Direct Mode
7. An example of direct addressing mode
A. MOV CX, AX
B. MOV AL, FFH
C. MOV DX, [BX+04]
D. MOV AX, [1592H]
ANSWER: D. MOV AX, [1592H]
8. This addressing mode allows data to be
addressed at any memory location through
an offset address held in any of the
following registers: BP, BX, DI & SI
A. Implied Mode
B. Immediate Mode
C. Direct Mode
D. Register Indirect Addressing Mode
ANSWER: D. Register Indirect Addressing
Mode
9. This is an example of register Indirect
Addressing Mode
A. MOV CX, AX
B. MOV AL, FFH
C. MOV DX, [BX+04]
D. MOV AX, [BX]
ANSWER: D. MOV AX, [BX]
10. A type of addressing mode, the offset
address of the operand is given by the sum
of contents of the BX/BP registers and 8-
bit/16-bit displacement.
A. Based addressing mode
B. Immediate Mode
C. Direct Mode
D. Register Indirect Addressing Mode
ANSWER: A. Based addressing mode
11. Based addressing mode example
A. MOV CX, AX
B. MOV DX, [BX+04]
C. MOV AL, FFH
D. MOV AX, [BX]
ANSWER: B. MOV DX, [BX+04]
12. In this addressing mode, the operands
offset address is found by adding the
contents of SI or DI register and 8-bit/16-bit
displacements.
A. Based addressing mode
B. Indexed addressing mode
C. Direct Mode
D. Register Indirect Addressing Mode
ANSWER: B. Indexed addressing mode
13. An example of indexed addressing mode
A. ADD AL, [DI+16]
B. MOV DX, [BX+04]
C. MOV AL, FFH
D. MOV CX, AX
ANSWER: A. ADD AL, [DI+16]
COE121-C1
Quiz#3
MULTIPLE CHOICE
1. The source file is converted into an
__________ wherein it contains all the
actual binary information.
A. Machine code
B. Pseudo-opcode
C. List file
D. Object file

ANSWER: D
2. An _________ is a special program that
will understand the contents of the object
file/
A. Assembler
B. Compiler
C. Linker
D. Library

ANSWER: A
3. This type of assemblers work with one
source line at a time and are restricted in
operation.
A. One-liner-assemblers
B. Special-assemblers
C. Cross-assemblers
D. Single-line-assemblers

ANSWER: D
4. ______ contains many new pseudocodes
to help the assembler generate the correct
machine code for the object file.
A. Module
B. Operands
C. Segments
D. Linker

ANSWER: C
 A. Memory to register, register to memory,
5. Data transfer group contains instructions memory to memory, register to register
that transfer from ____________.
B. Memory to memory, register to register, C. Memory to memory, memory to register,
register to memory register to memory
D. Memory to register, register to register,
register to memory

ANSWER: D
6. A _____ is a collection of bytes stored
sequentially in memory, whose length can
be up to _______.
A. String, 64KB
B. String, 8KBytes
C. Char, 1KB
D. Char, 64KB

ANSWER: A
7. Bit manipulation is used for __________.
A. AND, OR, NOR, NOT
B. AND, OR, XOR, NOT
C. AND, NOR, OR, XOR
D. TEST, NOR, AND, OR

ANSWER: B
8. Address is referred to ________ when the
processor’s address bus is formed by some
combination of segment register and an
additional numerical offset.
A. Effective Address
B. Immediate Addressing
C. Register Addressing
D. Base Addressing

ANSWER: A
9. MOV CX, 7 is a sample of which type of
addressing?
A. Indirect Addressing
B. Base Addressing
C. Register Addressing
D. Immediate Addressing

ANSWER: D
10. MOV AX, [BX+4] is a sample of which
type of addressing?
A. Indirect Addressing
B. Base Addressing
C. Register Addressing
D. Immediate Addressing

ANSWER: B
11. MOV DL, [SI] is a sample of which type
of addressing?
A. Indirect Addressing
B. Base Addressing
C. Register Addressing
D. Register Indirect Addressing

ANSWER: D
12. Base registers, BX or BP, is used as a
pointer to the desired memory location in
this type of addressing.
A. Indirect Addressing
B. Base Addressing
C. Register Addressing
D. Immediate Addressing

ANSWER: B
13. This instruction pushes all registers to
the stack.
A. PUSHD
B. PUSH
C. PUSHF
D. PUSHA

ANSWER: D

14. MOVS is used to ___________
A. Move the signed value to the destination
B. Move the source to the destination
C. Copy the source to the destination
D. Copy the source of the string to the
destination string.
ANSWER: D
15. BSWAP swaps bytes in a ______
A. 16-bit general purpose register
B. 32-bit general purpose register
C. 16-byte general purpose register
D. 32-byte general purpose register
ANSWER: B VILLARUEL, King Ralph
G.
COE121 / C1
Identification
1. It is a digital machine that can execute
many different software instructions and
controlling a wide
variety of electronic devices.
ANS. Microprocessor
2. It is either the “heart” or the “brain”
of the system, the master controller of all
operations that can be
performed.
ANS. Central Processing Unit (CPU)
3. They are actually microprocessors
themselves; their instruction set consists
mainly of simple instructions for
transferring data, and compex instructions
for performing a large variety of
mathematical operations.
ANS. Math Coprocessors
4. It is a type of RAM that retains its
information even when the power is turned
off.
ANS. Nonvolatile Memory (NVM)
5. It is a useful way to grab the proc
essor’s attention, get it to perform a special
task, and then resume
execution from the point where it left off.
ANS. Interrupt
6. They are actually souped
upmicroprocessors with built-in features
such as RAM, ROM, interval timers,parallel
I/O ports, and even A/D converters.
ANS. Microcontrollers
7. It is where the most electronics within the
PC were contained which is a single printed
circuit board.
ANS. Motherboard
8. It is the first single-chip microprocessor.
ANS. Intel 4004
9. It is the 8-bit microprocessor.
ANS. Intel 8008
10. It is ten times faster than the
performance of 8008.
ANS. Intel 8080
11. They are used to convert the binary form
intro current, voltage, or electric charge.
ANS. D/A Converter / Digital-to-Analog
Converter
12. 1 to 3 in high, it requires space, generate
tremendous heat, and requires large amount
of power.
ANS. Vacuum Tubes
13. Act as logical switches in digital circuits,
and it replaced the vacuum tubes.
ANS. Transistors
14. It is where the transistor was invented in
1947.
ANS. Bell Lab
15. He used very small wires to connect
transistors (first IC) that was in 1958.
ANS. Jack Kilby
16. He developed a single general-purpose
chip that could be programmed to carry out
a calculator’s function.
ANS. Ted Hoff
17. It is a type of RAM that is fast and easy ANS. C
to interface but comes in small sizes. 5.
ANS. Static RAM It is a type of flag register that contains carry
18. It is a special parallel operation used to out of MSB of result.
transfer data from a hard disk to a A. Overflow Flag (OF)
microcomputer’s memory. B. Auxiliary Flag (AF)
ANS. Direct Memory Access (DMA) C. Interrupt Flag (IF)
19. It is a type of RAM that has larger D. Carry Flag (CF)
capacity but requires refreshing. ANS. D
ANS. Dynamic RAM 6. 8-bit binary numbers are referred to
20. ROM stands for. as__________.
ANS. Read-Only Memory Multiple A. Word
Choice B. Double-Word
1. It is a type of a flag register that indicates C. Bytes
if result equals to zero. D. Kilobytes
A. Carry Flag (CF) ANS. C
B. Zero Flag (ZF) 7. 32-bit binary numbers are referred to as
C. Sign Flag (SF) __________.
D. Interrupt Flag (IF) A. Double-Word
ANS. B B. Long-Word
2. Intel C. Word
CPUs are also called __________computers, D. Both A and B
while Motorola processors are called ANS. D
__________ computers. 8. The first practical IC was developed in
A. little endian; big endian this year.
B. big endian; little endian A. 1959
C. little indian; big indian B. 1961
D. big indian; little indian C. 1967
ANS. A D. 1973
3. ANS. A
It is a type of flag register that provides 9. This processor is considered as one of the
single-step capability for debugging. XTs or experimental technologies.
A. Trap Flag (TF) A.
B. Nested Task (NT) Intel 80186
C. Overflow Flag (OF) B.
D. Auxiliary Flag (AF) Pentium Pro
ANS. A C.
4. A method that began with the 8-bit 8080 Pentium III
and has been used on all upgrades from the D.
8085 to the Pentium. Intel 8088
A. pipelining ANS. A
B. UV pipelining
C. byte-swapping
D. branch prediction
10. This element is the one responsible in 15. Which among the choices is not a
creating signals or commands for the software interrupt?
execution of the A. Mobile Legends
instruction. Failure
A. Control Signal B. Program Loader Failure
B. Control Bus C. Word Processor Failure
C. Control Unit D. Worm
D. Control Logic ANS. B
ANS. D 16. This element serves as a medium of
11. If pin INTR is connected to the ground, communication between the processor and
which flag is affected? the outside world.
A. Interrupt Flag (IF) A. Modem
B. Carry Flag (CF) B. Ethernet Cable
C. Auxiliary Flag (AF) C. I/O Port
D. Trap Flag (TF) D. Coprocessor
ANS. A ANS. C
12. This register is the 17.
one responsible in pointing to the address of Which of the following is part of the
the next instruction to be fetched and Microprocessor?
executed. A. I/O Port
A. Program Counter B. Memory
B. Program Sequencer C. Arithmetic Logic Unit (ALU)
C. Program Accumulator D. Video Display Adapter
D. Program Yasuo ANS. C
ANS. A 18. Which of the following is
13. This element is the one responsible in not part of the Microprocessor?
decoding the operation code of A. Memory
an instruction. B. Arithmetic Logic Unit (ALU)
A. Instruction Encoder C. General-purpose Registers
B. Instruction Converter D. Coprocessor
C. Instruction Interpreter ANS. A
D. Instruction Decoder 19. Which among the flags is affected by the
ANS. D direction flow during string operations?
14. This element is the one responsible in A. Carry Flag (CF)
monitoring the bus operation. B. Interrupt Flag (IF)
A. Bus Snooping C. Trap Flag (TF)
B. Watchdog Monitor D.Direction Flag (DF)
C. Branch Prediction ANS. D
D. Address Bus
ANS. B
20. He noticed that the number of transistors ;
per square inch on integrated circuits had C. CF=1; AF=0; ZF=0; I
doubled every year since their invention. F=0;
His law predicts that this trend will continue D. CF=1; AF=1; ZF=0; IF=0
into the foreseeable future. ANS. A
A. Mandy Moore 23. Simulate the given instructions (below)
B. Gordon Moore and determine which among the choices is
C. Bill Gates correct.
D. Paul Allen Initially
ANS. B CF=0; AF=0
21. Simulate the given instructions (below) ; ZF=0
and determine which among the choices is ; IF=1
correct. Initially CF=0; AF=0; ZF=0; MOV AL, FF
I MOV BL, 01
F=0 ADD
MOV AL, 1F AL, BL
MOV BL, F1 CLC
ADD CLI
AL, BL A. CF=1; AF=1; ZF=1; IF=1
Assume that there is an interr ;
upt. B. CF=0
A. CF=1; AF=1; ZF=1 ; AF=1; ZF=0; IF=1
; IF=1 ;
; C. CF=0
B. CF=1; AF=1; ZF=0 ; AF=0; ZF=0; I
; IF=1 F=0;
; D. C
C. CF=1; AF=0; ZF=0; I F=0
F=0; ; AF=1; ZF=0; IF=0
D. C ANS. D
F=1; AF=1; ZF=0; IF=0 24 Simulate the given instructions (below)
ANS. B and determine which among
22. Simulate the given instructions (below) the choices is correct.
and determine which among the choices is Initially CF=0; AF=0; ZF=1; IF=0
correct. MOV AL, 3A
Initially CF=1; AF=1; ZF=1; IF=1 MOV BL,
MOV C
AL, 1F 2
MOV BL, F1 ADD
ADD AL, BL
AL, BL STC
A. CF=1; AF=1; ZF=1; IF=1 A. CF=0; AF=0
; ; ZF=1; I
B. CF=1; AF=1; ZF=0; IF=1 F=0
; Multiple Choice
B. CF=0; AF=1; ZF=1 1. What element is responsible for
; IF=1 monitoring the bus operation?
; A. Bus snooping
C. CF=1 B. Watchdog monitor
; AF=0; ZF=1 C. Instruction register
;I ANSWER: B
F=0; 2. Pointing to the address of the next
D. C instruction to fetched and executed is the
F=1 responsibility of this register.
; AF=1; ZF=0; IF=0 A. Program counter
ANS. A B. Data segment
25. Simulate the given instructions C. Direction flag
(below) and determine which among the ANSWER: A
choices is correct. 3. It is a signal that indicates the need of
Initially CF=0; AF=0; ZF=0; IF=0 attention, perform special task and resume
MOV AL, AE the pre-empted operation.
MOV BL, A. Interrupts
9A B. Commands
SUB C. Operands
AL, BL ANSWER: A
A. CF=0; AF=0 4. During the flow of string
; ZF=0 operations, this flag is affected.
; IF=0 A. Sign flag
; B. Carry flag
B. CF=0; AF=1; ZF=1; IF=1 C. Direction flag
; ANSWER: C
C. CF=1; AF=0; ZF=1; I 5. This instruction allows you to transfer the
F=0; data or address to a register or variable.
D. CF=1 A. ADD instruction
; AF=1; ZF=1 B. SUB instruction
;I C. The MOV instruction
F=1 ANSWER: C
ANS. A COE121 6.
- Pushing Flags onto stack is the use of this
C1 instruction.
Quiz#1 A. PUSHA
I. B. PUSHF
C. PUSHD
ANSWER: B
7. What data type has a size of 2bytes or 0
16bits? ANSWER: B
A. Doubleword 14.
B. Word Binary word of -28
C. Quadword A. 1110 0100
ANSWER: B B. 0000 0000 1110 0100
8. Data type that has a size of 4bytes or C. 0001 0011 0000 1000
32bits ANSWER: B 15.
A. Doubleword The 2nd generation of microprocessors is
B. Word __________.
C. Quadword A. Transistors
ANSWER: A B. Vacuum tube computers
9. This flag is a way for the processor to C. Intel 8080
wave the programmer that a zero condition ANSWER: A
has occurred. 16. The Intel 80586 is also known as
A. Carry flag ___________.
B. The zero flag A. First microprocessor
C. Overload flag B. ENIAC
ANSWER: C. The Pentium
B ANSWER: C
10. CISC stands for: 17. This law states that y=x 2 or the number
A. Computer Instruction Set Configurations or complexity of transistors per IC doubles
B. Complex Instruction Set Configuration every 2 years.
C. Complex Instruction Set Computer A. The Moore’s law
ANSWER: C B. Newton’s law
11. ASCII code for EECE C. Mealy’s law
A. 45h, 45h, 43h, 45h ANSWER: A
B. 43h, 43h, 45h, 43h 18.
C. 46h, 46h, 41h, 46h Advance technologies
ANSWER: A developed Intel _____.
12. BCD of 3431 (packed) A. 80486
A. 0000 00011 0000 0100 0000 0011 0000 B. 8080
0001 C. 8086
B. 0011 0100 0011 0001 ANSWER: A
C. 0000 0101 0100 1000 19. The first practical IC was developed in
ANSWER: ______.
B A. 1989
13. Binary and normalized form of - B. The year 1959
1.75. C. 1890
A. 1.11 and 1.11x2 ANSWER: B
1
B. 1.11 and 1.11x2
0
1.01 and 1.01x2
20. The single general-purpose chip that 1. The following are types of RAM except ?
could be programmed to carry out the A. Static RAM
calculator’s function was developed by: B. Dynamic RAM
A. Ed Roberts C. Nonvolatile memory
B. Bill Gates D. Volatile memory
C. Ted Holf ANS: D
ANSWER: C 2. A special parallel operation that is used to
1. The vision of Mapua Institute of transfer data from a hard disk to a
Technology is to be ____ microcomputer’s memory?
A. be among the best universities in the A. Direct memory access (DMA)
world B. Random access memory (RAM)
B. be the best universities in the Philippines C. Read only memory (ROM)
C. be among the great universities in the D. None of the choices
world ANS: A
D. shall be the best engineering school in the 3. The first processor in the 80x86 family
world was the ______?
ANS: A A. Pentium
2. The institute shall provide a learning B. 16-bit 8086
environment in order for _____ C. 8-bit 8086
A. Its students to be good engineers D. None of the choices
B. its students to acquire the attributes that ANS: B
will make them globally competitive. 4. by common practice, 8-bit binary
C. Its students to acquire the attributes of an numbers are referred to as ____ ?
engineers A. Bits
D. None of the above B. Bytes
ANS: B C. Kilobytes
3. The institute shall engage in the following D. Megabytes
except one? ANS: B
A. Research 5. Sixteen-bit numbers are known as ____ ?
B. Development A. Double-words
C. Competition B. Long-words
D. Innovation C. Words
ANS: C D. None of the choices
4. the institute shall provide state-of-the- ANS: C
art _______ to problems of industries and 6. A method that began with the 8-bit 8080
communities and has been used on all upgrades from the
A. Answers 8085 to the Pentium is a technique called
B. Designs _____ ?
C. Both A and B A. Byte-changer
D. Solutions B. Byte-swapping
ANS: D C. Byte-swarming
D. None of the choices
ANS: B
7. Motorola processors are called ____ ? 4. _____ is the first processor in the 80x86
A. Little-endian family, which was capable of addressing
B. Huge-endian _____
C. Large-endian Ans. 16-bit 8086, 1 MB of memory
D. None of the choices 5. A ______ contains all the memory
ANS: D locations that can be reached when a
8. what instruction are used to move data particular number in a certain segment
among registers, memory, and the out register is used.
side world ? Ans. Segment
A. Data transport instructions 6. Intel CPUs are also called ________
B. Data network instructions computers, while Motorola processors are
C. Data transfer instructions called _______ computers. Ans. Little-
D. None of the choices endian, big- endian
ANS: C ENUMERATIONS:
9. A hardware ________ is an event that 1. Enumerate the 4 data registers of the
occurs while the processor is executing an 80x86 family of
instruction. It temporarily suspends microprocessors.
execution of the main program in favor of a Ans:
special routine that services it. • _AX
A. Error • _BX
B. Interrupt • _CX
C. Restrict • _DX
D. Interject 2. List the 6 main groups of instructions in
ANS: B the80x86 instruction set.
10. this instructions is capable of performing Ans:
logical, shift and rotate operations. Many • _Data Transfer Instruction
common boolean operations (AND, OR, • _Arithmetic Instructions
NOT) are available in the logical • _Bit Manipulation Instructions
instructions. • _String Instructions
A. Bit Manipulation Instructions • _Program Transfer Instructions
B. Byte Manipulation Instructions • _Processor Control Instructions
C. Both A and B SOLVING:
D. None of the above 1. Determine the content of each of the flags
ANS: A after the execution of each of the following
IDENTIFICATION: instructions. Note that the given instructions
1. _____ is the heart of the system, the will function as a part of a program. Show
master controller of all operation that can be your solution.
performed. INSTRUCTIONS
Ans. CPU (Central processing unit) CF
2. _____ special devices that often used in 0
simple control system because of their many AF
features. 0
Ans. Microcontrollers ZF
0
SF 0
0 SF
PF 0
0 PF
OF 0
0 OF
TF 0
0 TF
DF 0
0 DF
IF 0
0 IF
NT 0
0 NT
IOPL 0
00 CLC IOPL
STI 00
MOV AL, AC CLC
MOV BL, F3 0
STC 0
ADD AL, BL 0
CLI 0
MOV CL, AL 0
MOV AL, D2 0
STD 0
SUB AL, CL 0
CLD 0
1. It is assumed that after 3rd instruction 0
there is an interrupt. 00
2. It is assumed that after 4th instruction STI
there is an error. 0
3. It is assumed that before 6th instruction 0
there is an overflow. 0
4. It is assumed that after 7th instruction the 0
task is nested. 0
5. It is assumed that before 9th 0
the privilege level is third to the highest. 0
Ans: 0
INSTRUCTIONS 1
CF 0
0 00
AF MOV AL, AC
0 0
ZF 0
0 00
0 CLI
0 1
0 0
0 1
0 1
1 1
0 1
00 0
MOV BL, F3 0
0 0
0 0
0 00
0 MOV CL, AL
0 1
0 0
0 1
0 1
1 1
0 1
00 0
STC 0
1 0
0 1
0 10
0 MOV AL, D2
1 1
1 0
0 1
0 1
1 1
0 1
00 0
ADD AL, BL 0
1 0
0 1
1 10
1 STD
1 1
1 0
0 1
0 1
1 1
0 1
0 123A
0 3.ADD AX, BX
0 03C3
1 123B
10 -
SUB AL, CL 123C
1 4.MOV DX, 7EBF
1 BABF7E
1 123D
1 -
1 123F
1 5.SUB DX, AX
0 2BD0
0 1240
0 -
1 1241
10 6.HLT
CLD F4
1 1242
1 What is the OpCode for the operator MOV
1 AX?
1 a.DE
1 b. F8
1 c. B0
0 d. B8
0 Ans: D
0 2. These are signals that indicate need of
1 attention, perform special task and resume
10 the pre-empted operation.
Multiple Choices a. Operation Code
1. Using the given information in table #1 b. Commands
and determine which among the choices is c. Interrupts
correct. d. Control Signals
INSTRUCTION/S CONTENT/S or Ans: C
OPCODE ADDRESS/ES 3. Using the given information in the table,
1.MOV AX, DEF8 determine which among the choices is
B8F8DE correct. INSTRUCTION/S CONTENT/S
1234 or OPCODE ADDRESS/ES
- 1.MOV AX, DEF8
1237 B8F8DE
2.MOV BX, AD23 1234
BB23AD -
1238 1237
- 2.MOV BX,
AD23 B8F8DE
BB23AD 1234
1238 -
- 1237
123A 2.MOV BX, AD23
3.ADD AX, BX BB23AD
03C3 1238
123B -
- 123A
123C 3.ADD AX, BX
4.MOV DX, 7EBF 03C3
BABF7E 123B
123D -
- 123C
123F 4.MOV DX, 7EBF
5.SUB DX, AX BABF7E
2BD0 123D
1240 -
- 123F
1241 5.SUB DX, AX
6.HLT 2BD0
F4 1240
1242 -
At what address will the program counter 1241
point to if the next to be fetched and 6.HLT
executed is F4
instruction #5? 1242
a. 123F What is the OpCode
b. 1240-1241 for the operator MOV BX?
c. 1240 a. AD
d. 1241 b. BB
ANS: C c. 23
4. This is the main focus of all the designers d. B1
of computers. ANS: BB
a. Processor Identification
b. Speed 1. This element is consist of circuits needed
c. Functionality to get information or data into the program
d. Time of execution Ans: Input Devices
ANS: B 2. This is an enhancement of the usual
5.Using the given information in table #1 microprocessor because aside from the ALU
and determine which among the choices is and the control unit, read write memory,
correct. INSTRUCTION/S CONTENT/S read only memory, EEPROM, peripheral
or OPCODE ADDRESS/ES devices and I/O interfaces were added
1.MOV AX, DEF8 Ans: Microcontrollers
3. Developed the method of evaporating alu 3. This data dependency exists if the second
minum in specific places on a silicon wafer instruction reads an operand written to it by
to connect transistors the first
Ans: Robert Noyce instruction.
4. A group of lines that has a related A. write after read
function within the microprocessor system B. execute
Ans: System Bus C. execute after read
5. An element which functions as a floating D. read after write
point, graphics, signal processing, and even Ans. D
encryption 4. The history bits are initially set to 01.
Ans: Coprocessor What will be the history bits after this
6. Invented the single general purpose chip sequence; taken->taken->
that could be programmed to carry out not taken-> not taken-> not taken-> taken?
calculator’s functions A. 11
Ans: Ted Hoff B. 00
7. A type of special circuit which is disabled C. 10
during normal program execution D. 01
Ans: Interrupt Logic Ans. D
8. Used to indicate results of Arithmetic and 5. This specifies the percentage of hits to
Logical instructions total cache accesses
Ans: ALU A. miss ratio
9. An element in the operation of B. accuracy
microprocessor where all the data and C. precision
instructions are first stored D. hit ratio
Ans: Instruction Register Ans. D
10. The element which decodes theoperation 6. Average access time for a system that
code of an instruction contains 15ns cache and 75ns RAM if the hit
Ans: Instruction Decoder ration is 0.89 is
1. A _____ cycle is run if the Pentium _______?
detects an interval parity error. A. 23.25ns
A. shutdown B. 22.22ns
B. restart C. 25.23ns
C. bus snooping D. 20ns
D. Debug Ans. A
Ans. A 7. This translate linear addresses into
2. Bus ______ cycle is when the Pentium physical addresses
processor is able to watch the system bus in A. MESI
a multiprocessor B. TTL
system. C. TTF
A. clearing D. TLB
B. snooping Ans. D
C. sweeping
D. cleaning
Ans. B
8. This is a Pentium’s mechanism that is 2. The state in which data requested for
used to maintain cache coherency in its data processing by a component or application is
cache. found in the cache memory?
A. TLB A. Cache Hit
B. TTL B. Cache miss
C. TTF C. Cache Drop
D. MESI D. Cache fluff
Ans. D ANSWER: A
9. Busy instruction pipelines use this 3. A processor design, where single
technology instruction can execute several low-level
A. Passive Execution operations or are capable of multi-step
B. Dynamic Execution operations or addressing modes within
C. Passive Distribution single instruction?
D. Dynamic Distribution A. CISC processor
Ans. B B. RISC processor
10. Compute for the number of clock cycles C. Celeron
of the following instructions in UV D. Athlon
pipelining. ANSWER: A
MOV AX, 02 4. A type of microprocessor architecture that
MOV BX, 03 utilizes a small, highly-optimized set of
MOV CX, 04 instructions, rather than a more specialized
ADD AX, CX set of instructions often found in other
INC BX types of architectures?
SUB BX, AX A. CISC processor
MOV CX, BX B. RISC processor
DEC CX C. Celeron
A. 8 D. Athlon
B. 9 ANSWER: B
C. 10 5. A CPU that implements a form of
D. 11 parallelism called instruction-level
Ans. C parallelism within a single processor?
1. The state where the data requested for A. Supervector processor
processing by a component or application is B. RISC processor
not found in the cache memory? C. Pentium II
A. Cache Hit D. Superscalar processor
B. Cache miss ANSWER: D
C. Cache drop 6. An implementation technique where
D. Cache fluff multiple instructions are overlapped in
ANSWER: B execution?
A. Superscaling
B. Pipelining
C. RISC
D. CISC
ANSWER: B
7. IBM, Motorola, and Apple developed the
_________ superscalars. An RISC design
but provides for more than 200 instructions
at the instruction set.
A. PowerPC
B. PowerRISC
C. IPhone
D. PowerLaptop
ANSWER: A
8. What do ARM stands for, it developed the
large variations in superscalars as per
application-specific needs.
A. Advance RISC Machines
B. Advance Robotic Machines
C. Advance RISC Monitor
D. Advance Robotic Monitor
ANSWER: A
9. A memory cache that stores recent
translations of virtual memory to physical
addresses for faster retrieval?
A. Translation lookafter buffer
B. Transfer lookbefore buffer
C. Translation lookaside buffer
D. Translate lookaside buffer
ANSWER: C
10. First used in the P6 or sixth-generation
processors, ______ is an innovative
combination of three processing techniques
designed to help the processor manipulate
data more efficiently.
A. Static execution
B. Superscalar execution
C. Multiple execution
D. Dynamic execution
ANSWER: D
Identification
1. What type of dependency exists between
these two instructions? SUB DX, CX
ADD BX, DX
Ans: Read after Write
2. This bus state indicates that no bus cycle
is currently running.
Ans: Ti
3. This bus cycles require additional
decoding and use the byte enable outputs
for selection.
Ans: special cycle
4. This cycle transfers bytes that are non-
cacheable between the processor and
memory.
Ans: Single transfer cycle
5. This cycle is used by the cache for line
loads and writebacks.
Ans: burst cycle
6. This is examined first whenever the
processor tries to read data from the main
memory.
Ans: Cache
7. This helps identify possible interruptions
to the normal flow of instruction through U
and V pipelines.
Ans: Branch Prediction
8. This put its buses into a high-impedance
state, beginning with the next clock cycle.
Ans: BOFF
9. This cycle is run if the Pentium detects an
interval parity error.
Ans: Shutdown
10. In this cycle the Pentium processor is
able to watch the system bus in a
multiprocessor system.
Ans: Bus Snooping
MULTIPLE CHOICE
1. CISC stands for ___________________.
A. Complex Instructive System Computer
B. Complex Instruction System Computer
C. Complex Instruction Set Computer
D. Complex Instructive Set Computer
ANSWER: C
2. RISC stands for ___________________.
A. Reduced Instructive System Computer
B. Reduce Instruction System Computer
C. Reduced Instructive Set Computer
D. Reduced Instruction Set Computer
ANSWER: D
3. RISC machines are designed to have the 8. Bus _______ input provides a second way
following goals in mind except for a different bus master to take control of
_____________. the Pentium’s buses.
A. Utilize compiler extensively A. BOFF
B. Make good use of registers B. HOLD
C. Pipeline Everything C. INTR
D. Reduce access to hard drive D. FLUSH
ANSWER: D ANSWER: B
4. ____________ technique is used to 9. An internal parity error is detected by the
enable one instruction to complete with each Pentium allowing the _________ to run.
one clock cycle. A. Shutdown
A. Non-pipelining B. Halt
B. Cache Organization C. Pipelined
C. Branch Prediction D. inquire
D. Pipelining ANSWER: A
ANSWER: D 10. The Pentium is known as a superscalar
5. Choosing to make the instruction set machine because ___________.
smaller using fewer instructions and simpler A. it is capable of executing three integer or
addressing codes was the decision of three floating-point instructions
____________designers. simultaneously.
A. Computer B. it is capable of executing ten integer or
B. CISC ten floating-point instructions
C. RISC simultaneously.
D. System C. of its Pentium’s twin U and W pipelines.
ANSWER: C D. it can perform parallel instruction
6. As the Pentium also contains six 16-bit execution of multiple instructions.
segment registers, 32-bit stack pointer, and ANSWER: D
eight ______. 11. Also known as an external cache.
A. Floating point registers A. Second-level cache
B. Index registers B. Third-level cache
C. Control flags C. Data cache
D. Offset Addresses D. None of the above
ANSWER: A ANSWER: A
7. A __________ allows a new 8-byte chunk 12. Which is true about caches?
to transfer every clock cycle. A. It speeds up access to memory and
A. Burst operation reduce traffic on the processor’s buses.
B. Bus operation B. When an instruction or data is found in
C. Pipelining the cache it is called a hit.
D. Brach Prediction C. When an instruction or data is not found
ANSWER: A in the caches it is called a miss.
D. All of the above.
ANSWER: D
13. Bus snooping is used to maintain 3. RISC is also known as _________.
consistent data in a __________________. A. Resized Instruction Set Compatibility
A. Multiprocessor system where each B. Reduced Instructions Set Computers
processor has one cache. C. Resized Instructions Set Compatibilities
B. Multiprocessor system where each D. Reduced Instruction Set Computer
processor has a separate cache. ANS: D.
C. Multiprocessor system where both 4. CISC stands for __________.
processors has a separate cache. A. Complex Instruction Set ComputerB.
D. Multiprocessor system where both Complexity Instruction Set Computer
processors has one cache. C. Both A and B
ANSWER: B D. Neither A and B
14. TLB stands for ___________. ANS: A.
A. Translation Logical Buffers 5. Which is
B. Translation Logical Bus Operations NOT
C. Translation Lookaside Bus Operations a goal of a RISC machine?
D. Translation Lookaside Buffers A. Pipeline everything.
ANSWER: D B. Make good use of registers.
15. Label the format of a segment selector. C. Keep instructions and addressing modes
Write the letter. complex.
A. TI D. Utilize the compiler extensively.
B. Index(13-bit) ANS: C.
C. Index (16-bit) 6. It is used to store frequently used
D. RPL instructions, such as those in a short loop.
ANSWER: A. Data Cache
1. This input is used to force the Pentium to B. Instruction Cache
limit addressable memory to 1 MB, to C. Address Cache
emulate the memory D. None of the above
space the memory space of the 8086. ANS: B.
A. A20M (Address 20 Mask) 7. It is used to store frequently used data.
B. ADS (Address Strobe) A. Data Cache
C. AHOLD (Address Hold) B. Instruction CacheC. Address Cache
D. AP (Address Parity) D. None of the above
ANS: A. ANS: A.
2. It is a special type of high speed RAM 8. It is a technique used to enable one
where data and the address of the data are instruction to complete with each clock
stored. cycle.
A. Clock A. Clock
B. Burst Ready B. Pipelining
C. Cache C. Non-pipelining
D. Bus Lock D. Float Pointing
ANS: C. ANS: B.
9. Which technique is used in the execution C. Complier Prediction
of these three instructions? D. Register Prediction
I ANS: A.
5 10. This cycle is used to transfer up to 8
I bytes of non-cacheable data between the
4 processor and
I memory.
3 A. Burst Cycles
I B. Locked Operation
2 C. Single Transfer Cycle
I D. BOFF
1 ANS: C.
F
I 11. This operation cannot be broken down
4I into smaller sub-operation. The data
3 accessed during this
I operation often comes in the form of
2 semaphore.
I A. BOFF
1 B. Lock Operation
D C. Single Transfer Operation
I D. Atomic Operation
3 ANS: D.
I 12. It is a special type of counter variable
2 that must be read, updated and stored in one
I single,
1 uninterruptable operation.
E A. Lock OperationB. Burst
Clock C. Semaphore
Cycle D. BOFF
123 ANS: C.
45 13. It provides a way for other processors in
A. Clock a multiprocessor system to instantly take
B. Pipelining over the Pentium’s
C. Non-pipelining buses.
D. Float Pointing A. BOFF
ANS: B. B. Shutdown
9. The Pentium employs a technique called C. Bus Hold
______ that helps identify possible D. HALT
interruptions to the ANS: A.
normal flow of instruction through the U
and V pipelines.
A. Branch Prediction
B. Normal Prediction
14. It is used to help maintain consistent
data in a multiprocessor system where each
processor has a
separate cache.
A. TLBs
B. Triple Ported
C. Cache Coherency
D. Bus Snooping
ANS: D.
15. Which is NOT one of the Pentium’s
hardware interrupt signals?
A. INTR
B. KEN
C. NMI
D. SMIANS: B.
16. It contains a 13-bit index field that is
used to select one of 8,192 segment
descriptors that reside
either in GDT or LDT.
A. Segment Selectors
B. Segment Descriptors
C. Both A and B
D. None of the above
ANS: A.
17. It is accomplished by interweaving
micro-ops from each instruction through a
single instruction
pipeline.
A. Ultrathreading
B. Superthreading
C. Hyperthreading
D. Overthreading
ANS: C.
18. Which is NOT a component of NetBurst
Architecture?
A. HyperPiped Line Technology
B. Rapid Execution Engine
C. Execution Trace Cache
D. None of the above
ANS: D.
REGISTER QUESTIONS.
1. Machine code for LAHF Answer: 9F
1. Prevent changing the location POPA which *note: 9E kapag SAHF
register is not loaded with data
Answer: SP or ESP
*note: POPA Pop All Registers; Intel 80x86; move 2. Machine code ROL BYTE PTR[SI], 1 Answer:
memory pointed to by stack pointer to all 16-bit general final value = 82H → D004 - 1101 0000 0000 0100
purpose
registers (except for SP); does not affect flags
3. Machine code XOR AX, CX
2. Pushes all registers to the stack Answer: 31C8 or 0011 0001 1100 1000
Answer: PUSHA
*note: PUSH - push data onto stack SIMULATION QUESTIONS.
PUSHW - push word onto stack
PUSHD - push double word onto stack 1. Result of executing RCR AX, CL if CL
PUSHA - push all registers to stack (60) contains 2 and AX contains ABCDh
Order: AX, CX, DX, BX, SP, BP, SI, DI Answer: AAF3 Machine Code: D3D8
PUSHF - push flags onto stack (9C)
2. AX, BX, CX = 1234H, 5678H, 9ABCH ; result of
3. Lower byte of flag reg = 83H. Which flag SHRD BX, CX, 8?
registers are set as a result of LAHF Answer: BC56 Machine Code: 0FAC CB08
instruction?
Answer: SF 3. Result of executing RCL DL, 1; cleared flags; DL
contains 93h
4. The higher byte of the flag register contains Answer: 26h Machine Code: D0D2
83h. Which flag registers are cleared as a result
of executing LAHF instruction? 4. SHLD AX, BX, 4
Answer: AF Answer: 2345H Machine Code: 0FA4 D804

5. Based from order, when PUSHA is applied 5. ROR AX, 1

which register is PUSHED first? Answer: 4FA5H Machine Code: D1C8
Answer: AX
6. What is the result of NEG AX if AX contains
6. Based from order, when PUSHA is applied FFECh?
which register is PUSHED last? Answer: 0014h Machine Code: F7D8h
Answer: DI
*note: Processors pushed the registers in the order:
AX, CX, DX, BX, SP, BP, SI and DI. The SP word
INSTRUCTION QUESTIONS.
pushed is the value before the first register is
pushed.
1. Instruction that sets carry flag to 1
7. Flag register contains 10000011 on its lower Answer: STC
*note: Sets carry flag to 0 - CLC
byte which flag registers are set as a result of
executing LAHF instruction?
Answer: SF and CF 2. What does the command IN AL, DX mean?
Answer: IN AL, DX : Input byte from I/O port in
8. What segment is used for store destination DX into AL
string?
a. ES 3. Which of the ff is a bit manipulation instruction?
b. Any a. SHL DL, 2
c. DS b. Any
d. CS c. ROL AX,1
Answer: ES

MACHINE CODE QUESTIONS.

 d. NOT AL Answer: B *to get in-degree: add vertically
*to get out-degree: add
horizontally
*note: Bit Manipulation: NOT, AND, OR, XOR, TEST, BT, BTC,
BTR, BTS, SHL/SAL, SHR/SAR, ROL/ROR, RCL/RCR,
Arithmetic: ADD, ADC, INC, DEC, SUB, SBB, DEC, CMP, 2. Which of the ff correctly describes
MUL, IMUL, DIV, IDIV, NEG, CBW, CWD, DAA, DAS, AAA, the graph Matrix: a b c a101
AAS, AAM, AAD b001
c111
4. Which of the following is a logical instruction? a. Simple directed graph with 3 vertices
Answer: TEST b. Pseudograph with 3 vertices
c. Directed multigraph with 3 vertices
5. Direction flag is set to 0 using this instruction. d. Simple multigraph with 3 vertices
Answer: CLD Answer: Directed multigraph with 3 vertices

6. These instructions are used to preserve the 3. The adjacency matrix of the graph is seen
contents of the outer loop counter below, determine how many edges are in the
Answer: PUSH and POP graph.

PROPOSITION QUESTIONS.

1. Which is a valid conclusion? Answer: 10

Choices:
(a) All hummingbirds are richly colored
4. Give the adjacency matrix of the graph G
(b) No large birds live on honey
{a,b,c,d}, How many number of paths from a to d
(c) Birds that do not live on honey are dull in
has a length exactly equal to 4?
color
0 1 1 0
(d) Hummingbirds are small
Answer: C 1 0 0 1

2. Consider the symbolic logic taken from Lewis 1 0 0 1

Caroll illustrating how quantifiers are used in 0 1 1 0
statements. Which of the following is/are
premises? Answer: 8
I. All lions are fierce
II. Some lions dont drink coffee 5. The graph is represented by the adjacency matrix
III. Some fierce creatures do not drink coffee below. Determine the out-degree in vertex d
Answer: I and II

3. There exists x not P(x)

there is an x for which P(x) is Answer: 3

false P(x) is true for every x there
is an x for which P(x) is true 6. V = {a,b,c,d,e},
every x, P(x) is false E = {(a,b),(a,c),(b,c),(c,d),(c,e),(d,e)} is classified as?
[Hamiltonian but not Eulerian; neither H or E; H and
GRAPH / MATRIX QUESTIONS. E; E but not H]
Answer: Eulerian cycle but not Hamiltonian
1. Determine in-degree in vertex b?
Matrix: a b c d a0230 b1 7. Which of the ff vertex is called a pendant?
221 Answer: Leaf
c2110
d1002 Answer: 5
8. Given the undirected graph V = {a,b,c,d,e} with E Answer: B
= {(a,b).(a,d),(b,c),(c,d),(d,e)} is classified as?
Answer: Eulerian Path Note: 2. Set A = {integer numbers}, which is
Eulerian circuit - visits every edge exactly once antisymmetric
and starts and ends on the same vertex a. R = {(a,b) | a > b}
Hamiltonian path - visit every vertex only once b. R = {(a,b) | a + b = 3}
c. R = {(a,b) | a - b = -4}
10. How many pass will it take in order to sort the d. R = {(a,b) | a = b or a = -b}
single digit array 3 5 4 1 2 using selection sort? a.) Answer: A
5
b.) 4 3. Which of the following relations from Set A =
c.) 6 [1,2,3,4] to Set A is considered transitive?
d.) 10 Answer: Answer: {(1,1),(1,2),(2,1)}
4
4. A U A’ = U
11. Given the following points below, what is the Answer: Complement Law
longest/shortest route?
Gr to SW 113 mi Gr to Kal 56 mi 5. What law: p v p = p
Gr to Det 147 mi Gr to Tol 167 mi Answer: idempotent law
Kal to SW 137 mi Kal to Det 135 mi *note:
Kal to Tol 133 mi Tol to Det 58 mi pwede din daw p^p = p
Tol to SW 142 mi Det to SW 98 mi p ^ 1 or p v 0 - identity
law
p ^ (pvq) = p or p v (p^q) = p - absorption law
a.) Det- Tol- Kal- GR-Sw – Det - SHORTEST
b.) Det – Tol-Gr-Kal-Sw-Det
6. How many base theorems and postulates to
c.) Det-GR-Sw-Tol-Kal-Det - LONGEST
prove x + xy = x
d.)Det-Sw-Tol-GR-Kal-Det
Answer: 3
*note: ( X(1+Y)) 3 namely; LAW OF UNION,
BIG-O NOTATION QUESTIONS. DISTRIBUTIVE, LAW OF INTERSECTION)

1. An algorithm that uses Hamiltonian cycle to 7. Determine which of the given relations on the
solve set of all integers is an antisymmetric relation where
uses a Big-O notation of (x, y) is an element of R. x is not equal to y x is
Answer: logarithmic complexity greater than or equal to y2 x is a multiple of y xy is
greater than or equal to 1
2. An algorithm that uses Eulerian Path/Bubble 8. Determine which of the given relations on the
Sort set of all integers is an equivalence relation where
to solve uses a Big-O notation of (x, y) is an element of R.
Answer: linear complexity
x is a multiple of y
3. An algorithm that uses Selection to solve uses a x greater than or equal to y2
Big-O notation of x = y2
Answer: quadratic x and y are both negative or both nonnegative

SET THEORY QUESTIONS.
1. Which of the ff relation from Set A {integer
numbers} is considered as equivalence relation?
a. R = {(a,b) | a > b or a = b }
b. R = {(a,b) | a b (mod m) with m > 1}
c. R = {(a,b) | a + b = 3}
d. R = {(a,b) | a < b}
LOGIC QUESTIONS.
1. Under precedence of logical operators which is
performed last? Answer: Biconditional
2. Which of the ff logical operator is performed
first?
Answer: And
*note: precedence of logical operators →
NOT(Negation), AND(Conjunction), OR(Disjunction),
IMPLICATION, BICONDITIONAL(Equivalence)
3. The expression below is regarded as (p ^ q) -> (p
v q)
Answer: TAUTOLOGY
Answer: LSI
*note: (if more than 100 gates, matic LSI)
SSI - less than 100, about 10 gates
MSI - less than 500 or more than 10 but less than 100
gates
LSI - 500 to 300000 or have more than 100 gates

(p ^ q) ->
p q p^q pvq
(p v q) 7. What is the highest privilege (RPL) in
protected mode? Answer: 00
0 0 0 0 1 *note: 00 - highest
11- lowest
0 1 0 1 1

1 0 0 1 1 8. System signal used in troubleshooting

techniques for 8088 hardware architecture?
1 1 1 1 1
Answer: INTR

4. Which of the propositional expression is 9. Addressing mode executes its instructions

contradiction? within CPU without the necessity of reference
a. (p ^ q)’ -> p memory for operands? Answer: Register Mode
b. (p -> q)’ -> q’
c. (p -> q)’ -> p 10. Which technique does the Pentium Pro
d. (p->(p v q))’ Answer: D employs where the processor looks ahead into
the instruction stream pipeline can be kept busy?
OTHER MICROPROCESSOR QUESTIONS. Answer: Speculative execution

1. Signal that has I/O clk 11. If 8088 has frequency of 4MHz, the time of one
Answer: CLK T state? [200 ns; 80 ns, 250 ns; 300 ns]
Answer: 250 ns
2. How many additional control reg are activated
based from Pentium’s protected mode 12. This input is used to force the Pentium to limit
Answer: 5 addressable memory to 1 Mb to emulate the
memory space of the 8086.
3. 8088 I/O ad space, number of I/O ports? Answer: A20M
Answer: 4096
*note: The 8088's I/O addressing space contains 13. mm = __ is automatically used for direct
65 addressing Answer:
536 (2^16) 00

14. A processor running in this mode can exploit

4. Standard bus connector agreed by PC bus
connector agreed upon by the PC business
comprising of 62 pins found in early PC
motherboards that allow expansion with the
8088
microprocessor
Answer: ISA
connector
5. ARM stands for
Answer: Advanced RISC Machines
6. 10 - 1000 gates in a single package:
only the lowest 20 bits of its address bus and is
therefore limited to the meager 1MB memory
space. Answer: Real mode
15. This method of storing 16-bit numbers in
memory, wherein the lower byte is already
read/write to the lower memory address
Answer: Little Endian
16. Intel introduced cache memory for this
microprocessor when it was launched. The Western
Design Center, Inc (WDC) introduced this
microprocessor in 1982 and was used as the CPU
in the Apple IIe and IIc personal computers.
Answer: CMOS 8502

17. The ____ part specifies the addressing mode for

the selected instruction
a. MOD
b. Addr-low
c. REG
d. R/M

18. 17. Which is false for r/m

a. r/m register enclosed in brackets (tama)
b. r/m used for addressing mode (tama)
c. r/m specifies addressing mode
d. Mode = 11; r/m = register field

ADDER / MULTIPLIER QUESTIONS.

1. Decimal parallel adder that adds 5 decimal digits

requires how many BCD adder stages?
Answer: 5
*in parallel adder n digits need n stages (pag multiplier n-1)
2. 74LS83 is an example 4-bit parallel adder to COMBINATORIAL CIRCUIT QUESTIONS.
expand to 8-bit you must
Answer: Two half adders with the carry output of 1. If the function v(w+x+y)z would be implemented
one connected to the input of the other using NOR gates?
Answer: Six NOR gates will be used
3. 2 bit by 2 bit multiplier can be constructed by
using: 2. 4-bit magnitude comparator combinational
Answer: 2 Half Adders and 4 AND gates circuit A < B what logic gate?
Answer: 4-input OR gate
4. How many 4-binary adders are needed to create
a single digit binary adder? 3. 4-bit magnitude comparator combinational
Answer: 4 circuit A = B what logic gate?
Answer: 4-input AND gate

SEQUENTIAL CIRCUIT QUESTIONS. 4. Exclusive-OR (XOR) logic gates can be

constructed from what other logic gates?
1. Given a synchronous sequential circuit what is Answer: AND gates, OR gates, and NOT gates
the next state with input = 0, if the current state is BASE N OPERATIONS QUESTIONS.
010?
Answer: 100 1. 10110 - 01101 using 1’s complement
Answer: 01001
2. Given a synchronous sequential circuit what is
the next state with input = 1, if the current state is 10110
001? + 10010 (1’s complement of subtrahend)
1 01000 (There is an overflow, Add 1 to Result)
Answer: 010
+ 1
01001
*solved state table
2. Using 2’s complement, what is the binary
equivalent of -7?
Answer: 1001
7 is 111 in binary
To get 2’s complement, subtract given from 111
 111 – 111 = 000 4. 4 input (D0-D3) priority encoder circuit
Then add 1 = 000 + 1 = 001 contain 3 output (x,y) pertaining to arbitrary
For the sign, put 0 as MSB for positive or 1 for
negative.
values. What is the function for most significant bit
For negative 7, put 1 as MSB = 1 001 = 1001
y? Answer: D3 + D1D2’

3. The binary value 0111 represent a decimal 5. 3x8 decoder D0 to D7 which output is
value activated high if input x’yz’
of 1 in this decimal code Answer: D2
Answer: 8 4 -2 -1
For other coding, we replace the 8 4 2 1 with other 6. 2 to 4 line decoder, made of NAND gates which
values. input would produce an output of 1011 from D0 to
We know that 0111 in decimal is 7 because of the D3
common 8 4 2 1 coding. 8(0) + 4(1) + 2(1) + 1(1) = 7
1XX
001
In this case, we replace it by 8 4 -2 -1.
(8) (4) (-2) (-1) 011
0 1 1 1 8(0) + 4(1) - 2(1) - 1(1) = 1 010

4. The 2’s complement representing the value -12 Answer: 001

is
Answer: 10100 FLIP FLOP QUESTIONS.
12 is 1100 in binary
To get 2’s complement, subtract given from 1111 1. Master slave D-flip flop is similar to a
1111 – 1100 = 0011 synchronous edge triggered flip flop, therefore
Then add 1 = 0011 + 1 = 0100 For the sign,
put 0 as MSB for positive or 1 for negative. it should have the ff behavior except?
For negative 12, put 1 as MSB = 1 0100 = 10100 Answer: a change in output is activated by
a clock pulse.
5. 88. The 2-4-2-1 code of 7 is:
Answer: 1101 2. Race condition in R-S Latch
7 is 0111 in binary. 8(0) + 4(1) + 2(1) + 1(1) = 7 Answer: R =1 S=1
We replace the 8 4 2 1 coding with 2 4 2 1
2( ) + 4( ) + 2( ) + 1( ) = __ ASCII PARITY QUESTIONS.
We can see that 2 + 4 + 1 will make 7 so we multiply
them by 1. The 2 in the most significant bit has more
priority than the other. 1. If an ASCII of A is used with odd parity, the
2(1) + 4(1) + 2(0) + 1(1) = 7 results is
Therefore 7 is 1101 in 2-4-2-1 code. Answer: 1100 0001

ENCODER / DECODER QUESTIONS. 2. If an ASCII of A is used with even parity the

results is
1. 4 input (D0-D3) priority encoder circuit contain 3 Answer: 0100 0001
output (x,y) pertaining to arbitrary values. What is
the function for least significant bit x? 3. A parity bit is used in error detecting codes, if an
Answer: D2 + D3 ASCII of T is used with odd parity the result is
Answer: 0101 0100
2. 4 input (D0-D3) priority encoder circuit contain 3
output (x,y) pertaining to arbitrary values. What is
the function for least significant bit y?
Answer: D2 + D3 K-MAP QUESTIONS.
3. 4 input (D0-D3) priority encoder circuit
1. F = xy + x’z express as product of maxterms
contain 3 output (x,y) pertaining to arbitrary
Answer: M(0,2,4,5)
values. What is the function for most significant bit
x? Answer: D3 + D1D2’
2. . The complement of F = [x(y’z’ + yz)] Answer:
F’ = x(y+z’)(y’+z)
 0 F=xy’z’ + xyz x\yz 00 01 8. Determine the canonical form of the simplified
11 10 0 0 0 Boolean expression F2 = xy‘z‘ + x‘y a. m (0,5,7)
0 1 1 0 1 b. m (2,4,7)
0 c. m (2,3,4)
d. m (1,6,7)
F’ = x(y+z’)(y’+z)
9. Simplify the Boolean function.
3. Simplify the Boolean function to a minimum A B C T
number of literals
A B C T1 0 0 0 1
0 0 0 1
0 0 1 1 0 0 1 1
0 1 0 1
0 1 1 0 0 1 0 1
1 0 0 0
1 0 1 0 0 1 1 0
1 1 0 0
1 0 0 0
1 1 1 0
1 0 1 0
A'(B' + C)
A + BC 1 1 0 0
A'B + C
ABC + A'B'C' 1 1 1 0
Answer: T=A’B’C’+A’B’C+A’BC’
4. Simplify F(v, w, x, y, z) = Σm (0, 1, 2, 4, 5, 8, 9,
10, 12, 16, 17, 18, 20, 21, 24, 26, 29) using 10. Express the function below as a standard form
Karnaugh map. product of maxterms. F = xy + x'z
a. v’w’y’ + v’x’z’ + vxz + v’y’z’ + v’x’y’ + vxy’z
b. w’y’ + x’z’ + v’y’z’ + v’x’y’ + vxy’z (x + y + z)(x + y' + z)(x' + y + z')
c. none of the choices (x + y + z)(x + y' + z)(x' + y + z)
d. vw’y’+ v’x’z’ + vxz + v’y’z’ + v’x’y’ + v’xy’z (x' + y)(x + z)(y + z)
(x + y + z)(x + y' + z)(x' + y + z)(x' + y + z')
5. What is the canonical form of the simplified
function F = C ‘D + ABC ‘+ ABD ‘+ A ‘B ‘D a. M 11. Express the following function as a sum of
(0,1,2,3,5,9,11,12,14) minterms: (xy + z)(y + xz)
b. M (1,3,4,5,6,7,9,10,12,14,15) x’yz + xy’z + xyz’ + xyz
c. M (0,2,4,6,7,8,10,11,15) x’y’z + xy’z + xyz x’yz +
d. M (1,3,5,9,12,13,14) x’y’z + xyz’+ xyz
x’y’z + xyz’ + x’y’z’
6. Determine the canonical form of the simplified
Boolean expression F = x‘y‘z + xy a. m (0,5,7)
b. m (2,4,7)
c. m (2,3,7)
d. m (1,6,7)

7. Determine the canonical form of the simplified

Boolean expression F=x‘y‘z‘ + xz a. m (0,5,7)
b. m (2,4,7)
c. m (0,2,3,7)
d. m (1,6,7)
 12. Simplify the Boolean function to a minimum
number of literals. 2. Questions about RAM
A B C T2 a. STATIC RAM – fast, easy interface, small
0 0 0 0 size (16 bytes per chip)
0 0 1 0 b. DYAMIC RAM – high density (256K per
0 1 0 0 chip), requires numerous refreshing
0 1 1 1 cycles to retain data.
1 0 0 1 NOTE: Both STATIC and DYNAMIC lose info
1 0 1 1 when turned off
1 1 0 1 c. NVRAM – retains memory even power is
1 1 1 1 turned off.

A + BC 3. Internal high speed memory

ABC + A'B'C' (*not sure if it is the exact question)
A'(B' + C') Answer: CACHE
AB + C Other info:
- Advance microprocessor load more than
A\BC 00 01 11 10 one instruction into this special buffer to
0 0 0 1 0 space time
1 1 1 1 1 - While microprocessor is decoding other
instruction, other memory can be read
13. Simplify the Boolean function from instruction cache.
F(A,B,C,D) = m(0,2,3,5,7,8,10,11,13,15)
-
4. Which of the following cannot be found in
B'C + CD + BD
microprocessor/ microcontroller/ CPU
B'D' + BD + B'C
Choices: [Memory, ALU, Register]
B'D' + BD + A'C'D
Answer: Memory
A'B'D' + AB'D' + CD
Other info:
- Register is a temporary storage of
OTHER LOGIC CIRCUITS QUESTIONS.
information inside the CPU.
- ALU is a circuit contained in CPU that is
1. Product term wherein which all variables appear
used to perform arithmetic and logical
once rather complement or uncomplemented
operations
Answer: minterm
- Memory is part of the computer that is
used to store information permanently or
2. Digital integrated circuits are classified not only
by their complexity or logical operation, but also by temporarily.
the specific circuit technology to which they
belong. 5. Which of the following is BIT
The circuit technology is referred to as ____. MANIPULATION?
Answer: digital logic family Choices: [SHL, OR, AND]
Answer: SHL
3. This is the time needed by a gate in processing Other IMPORTANT info:
its input signals before the output signal can be Under BIT MANIPULATION: (Logical
generated Instructions, Shift and Rotate Instructions)
Answer: propagation delay time BIT MANIPULATION – SHL, SAL, SHR,
SHLD/SHRS, ROL, ROR, RCL/RCR
Added Questions (From Feb 22, 2018) LOGICAL INSTRUCTIONS - NOT, AND,
MICROPROCESSOR OR, XOR, TEST
1. Intel’s server and workstation powerhouse. PROGRAM TRANSFER INSTRUCTION –
Choices: [Celeron, Xeon] JMP, RET, INT, BOUND, PROC, ENDP,
Answer: Xeon (Ref: Intel Microprocessor by CALL, IRET
James Antonakos)
 PROCESSOR CONTROL INSTRUCTIONS 14. Where will you know if it is in 16 bit or 32 bit?
– CLC/STC, CMC, CLD/STD, CLI/STI, HLT, Choices: [AV, D, G, RPL]
NOP, LOCK Answer: D

6. First Commercial 8 bit Reference: (read COE121 LECTURE

Answer: Intel 8008 NOTE 5_MICRO_COMANLISES)

7. Developed a single general-purpose chip that 15. Memory of 8 bit?

could be programmed to carry out a Choices: [16kB, 8kB, 64kB]
calculator’s function. Answer: 16 kB
Answer: Ted Hoff Other info:
4 bit microprocessor – 4 kB of memory
8. Which is used as the medium of 8 bit – 16 kB
communication between the processor and 16 bit – 1MB
the outside world. Reference: (read COE121 LECTURE
Answer: I/O Port NOTE 1_MICRO_COMANLISES)

9. Who made calculator into computer? 16. Translation lookaside buffer

Answer: Charles Babbage
10. … fast retrieval?
Choices: [Static RAM, Dynamic RAM, ROM,
NVRAM]
Answer: Static RAM
11. Understand the code
Choices: [Interpreter, Compiler, Assembler,
Debugger]
Answer: Assembler
Other info:
- Assembler – convert assembly language
into machine code. It takes basic
computer instructions and converts them
into a pattern of bits that the computer’s
processor can use to perform basic
operations.
- Compiler – convert high level languages
(like C, C++) into machine code
- Interpreter – computer program which
executes a statement directly (at
runtime).
- 18. What gate comes before/after the decoder in
12. Type of RAM that changes during regular
interval
Choices: [Static RAM, Dynamic RAM, ROM,
NVRAM]
Answer: Dynamic RAM (not sure)
13. INT AX, DX
Answer: Read from DX, write to AX
- is a memory cache that stores recent
translations of virtual memory to physical
addresses for faster retrieval.
Reference: Wikipedia
17. Other questions based on the following
- Choices: [pseudo opcode, machine
code]
- Stack Pointer – points to next
- ALL Addressing Mode
- e.g. Register Addressing Mode,
Immediate Addressing mode, Direct
Addressing, etc
Read: LECTURE NOTE
5_MICRO_COMANLISES)
- Flags (when will be set, when will it retain
its information)
Read: LECTURE NOTE_FLAGS
a majority voting circuit?
Choices: [ AND, OR, XOR gate]
Answer: AND gate (after nung decoder)
AND gates are all connected to an OR gate
19. P^P = P or PvP = P
Answer: Idempotent Law
20. CMP
Answer: Invert carry flag
 21. Vertex F
Answer: Pendant

22. 4-bit subtractor

Choices: NAND, OR, XOR, AND

23. INTR
Answer: flag ground

24. TI
Choices:
Field 1 segment

25. Physical address _____ frame

Choices: 64 kB, 16 kB, 32 kB,
Appendices

K-map ASCII Table

Sequential Circuit state table solution: