Computers now on the market are heat at a rate equal to its processor fre- 80s.
fre- 80s. Several other reversible logic gates
faster, smaller and more complex than
their predecessors. However, the price
paid for this speed and complexity is
increased power consumption. The pri-
mary reasons for the rise in power con-
sumption are the increase in clock fre-
quency and the increased number of
transistors packed onto a chip.
In any digital computer, an array of
0s and 1s represents a number. Every
operation in a computer corresponds to
the manipulation of the bits, e.g., flip-
ping of 0 to 1 or 1 to 0. Internally, com-
puters consist of millions of gates
that perform logic operations.
In most cases, these logic
operations are so called
irreversible. That is, some
Reversible logic
W! David Pan and
Mahesh Nalasani
information about the inputs
is erased every time a logic
operation (function) is per-
formed. Thus, we cannot
deduce the inputs from just
knowing the outputs alone.
In addition, distinct logi-
cal states of a computer
must be represented by dis-
tinct physical states of the computer
hardware. Suppose that n bits are
erased (reset to zeros) due to irre-
versible logic operations. Before the
erasure operation, these n bits could be
in any of the 2n possible states. After
the erasure, they are compressed to just
one state. In order to compress the logi-
cal states of the computer, however,
one must compress its physical states,
thereby lowering the entropy of the
hardware. By the Second Law of
Thermodynamics, such decrease of
entropy of the hardware leads to dissi-
pated energy. According to R.
Landauer’s research in the 1960s, the
amount of energy (heat) dissipated for
every irreversible bit operation is given
by KT ln2, where K is the Boltzmann’s
constant (1.3807×10-23 JK-1) and T is the
operating temperature. For T equal to
room temperature (300 K), KT ln2 is
approximately 2.8×10 -21 J, which is
small but non-negligible.
If we assume that every transistor
out of the 40 million transistors in a
processor (e.g., Pentium IV) dissipates
38
quency (e.g., 1 GHz), then its power
consumption will be approximately
4×1016×KT ln2 = 0.05 Watt. (Note: This
assumes that the processor works at the
temperature of 300 K.) This rate at
which heat is generated is still small.
However, according to Moore’s law, the
speed, the complexity and, hence, the
heat dissipation—due to the informa-
tion loss—will increase exponentially. If
this current trend continues, there will
be an intolerable amount of heat gener-
ated by computer sys-
tems not
so far down the
road. Definitely, we should
be looking for revolutionary
technologies that permit extremely
low power consumption and heat dissi-
pation in computing.
Reversible logic operations
One highly promising computing
technology is the employment of
reversible logic operations, which do
not erase information. Thus, they dissi-
pate (virtually) zero heat. But, before
we discuss the reversible logic, let’s
consider a reversible system in general.
For any system to be reversible, it has
to be able to operate in a backward
direction. This ability allows us to
reproduce the inputs from the outputs
of the system.
In 1973, C. H. Bennett concluded
that no energy would dissipate from a
system as long as the system was able
to return to its initial state from its final
state regardless of what occurred in
between. The logic supporting the
process of running the system in the
backward direction is called reversible
logic. Toffoli and Fredkin discovered
reversible logic in the late 70s and early
0278-6648/05/$20.00 © 2005 IEEE
have since been proposed, including
the Feynman gate, Kerntopf gate, Peres
gate and the Margolus gate.
As the basic elements of any logic
circuit, logic gates are used to realize
Boolean functions. By combining
reversible logic gates, we can construct
reversible circuits that can perform
complex logical and arithmetic opera-
tions. For a gate to be reversible, the
logic function it realizes has to be bijec-
tive. That is, there must be a one-to-one
m a p p i n g
between
©EYEWIRE COMPOSITE: MKC
inputs and outputs.
By definition, any
reversible gate has an “inverse”
(also called a “dual”). One can run the
logical operations backwards by cascad-
ing a reversible logic gate with its dual.
Reversible circuits are also called
lossless circuits, as there is neither ener-
gy loss nor information loss. These cir-
cuits are very attractive for applications
where extremely low power consump-
tion, or heat dissipation, is desirable in
areas ranging from communications,
low power VLSI (Very Large-Scale
Integration) technology, optical com-
puting to nanotechnology. Reversible
logic has been found to be very useful
in quantum computing where the quan-
tum evolution is inherently reversible.
The basic gate
(1, 1) Reversible logic gates. Any
logic gate can be characterized by its
number of inputs and outputs. A (m, n)
gate has m inputs and n outputs. A
trivial (1, 1) reversible gate is an input-
copying gate: the input simply passes
though the gate unchanged. (This is the
simplest logic gate with a single input
and a single output.) We can use this
IEEE POTENTIALS
gate to “fan-out” the input signal. Since
the output is a mere copy of the input,
we can easily recover the input from
the output.
Another example is the one-bit
inverter, with its output being the
inverse of its input. Thus, the inverter’s
input can be regenerated by inverting
its output. In general, a logic gate is
said to be reversible if the logic func-
tion it realizes is bijective. That is, not
only can its outputs be uniquely deter-
mined from the inputs, but its inputs
can also be obtained from the outputs.
Therefore, m = n is a necessary condi-
tion for a gate to be reversible.
(2, 2) Reversible logic gates. Now,
let’s look at reversible logic gates with
two inputs. A conventional exclusive-
OR (XOR) gate takes two single-bit
inputs A and B, and yields one single-
bit output X. If A = B, then X = 1; oth-
erwise X = 0.
However, the (2, 1) XOR gate is not
reversible, because we cannot uniquely
determine what the input vector (B, A)
is from the output. For instance, the
output X = 1 could have come from
either one of the two possible input
vectors, (0, 1) and (1, 0).
The reader may be wondering if all
(2, 2) gates are reversible. The answer
is negative. Consider a (2, 2) gate with
input vector (B, A) and output vector
BA YX
00 00
01 11
10
11 10
Fig. 1 The truth table of an irreversible
(2, 2) gate. Both inputs (0 1) and (1
0) are mapped to the same output
(Y X) = (1 1).
(Y, X), where X=A , B, and Y = A + B
(“+” denotes the OR operation). The
logic function of this gate is shown in
Fig. 1. Clearly, this is not a reversible
gate, since there exists a 2-to-1 map-
ping from the input to the output.
In order for a (2, 2) gate to be
reversible, the mapping of its logic
function should be such that the set of
output vectors is a permutation of the
set of input vectors, (00, 01, 10, 11). It
then follows that there exist 4! = 24
possible reversible (2, 2) logic gates.
Feynman gate is one of the most well
known reversible (2, 2) logic gates.
FEBRUARY/MARCH 2005
The Feynman gate
A Feynman gate with input vector
(B, A) and output vector (Y, X) imple-
ments the logic functions: Y = B , and
X =A B. The input-to-output map-
pings are shown in Fig. 2.
It can be seen from Fig. 2 that the
Feynman gate is a reversible (2, 2) gate.
In this instance, one of the inputs B
serves as a control signal: If B = 0, then
the output X is simply duplicating the
input A; if B = 1, then the output X =
A 1 = A, an inverse of the input A.
For this reason, the Feynman gate is
also called the controlled NOT (1-
CNOT) gate, or the quantum XOR gate
(Fig. 3) due to its popularity in the field
of quantum computing.
In general, a k-CNOT gate is a (k+1,
k+1) gate. It leaves the first k inputs
(called control inputs) unchanged and
inverts the last input if all of the k con-
trol inputs are 1s. We have just seen the
Feynman gate used as an example of a
1-CNOT gate. However, there is the
trivial example of the 0-CNOT gates —
one-bit inverter, and the important
example of the 2-CNOT gates—or the
Toffoli gate—which brings us to the (3,
3) reversible gates.
("# ") Reversible logic gates
Let’s assume that the (3, 3) gates
under consideration have an input vec-
BA YX
00 00
01 01
10 11
11 10
Fig. 2 The truth table of the Feynman
gate. The arrows show the per-
mutation of the set of in
put vectors.
tor (C, B, A) and an output vector (Z, Y,
X). Similar to the case of (2, 2) gates,
any (3, 3) reversible gate should gener-
ate a set of output vectors that is a per-
mutation of the set of input vectors,
(000, 001, 010, 011, 100, 101, 110, 111).
Thus, there exist 8! = 40,320 possible (3,
3) reversible logic gates. We now will
examine two important (3, 3) reversible
gates.
The Toffoli gate. This gate has the
input-output relations: Z = C, Y = B,
and X = A ( (CB) (note that CB stands
for C AND B). The Toffoli gate is a 2-
CNOT gate since it passes the two
inputs (B and C) unchanged and it
inverts the input A when B = 1 and C =
1 (see Fig. 4).
By definition, any reversible gate has
an “inverse” (also called a “dual”). This
is a gate that reverses its logic function.
A gate is said to be self-reversible if its
dual is the same as itself. In the case of
the single-bit inverter, the dual gate is
itself. This is also true for the (1,1) fan-
out gate we have described. The Toffoli
gate is self-reversible as well.
The proof of self-reversibility is
straightforward. (Note: not all reversible
gates are self-reversible.) Proof: In Fig.
5, the outputs of the second gate are R
= Z, Q = Y, P = X (ZY), and its inputs
are, in turn, the outputs of the first gate.
Hence, we have Z = C, Y = B, and X =
A (BC). By substituting X, Y, Z with
A, B, C, we obtain R = Z + C, Q = Y =
B, and P = X (ZY) = A (CB) (CB)
=A ((CB) (CB)) = A 0 = A.
One observation we can make
regarding the Toffoli gate in Fig. 4 is
that the Hamming weight (number of
logical ones) of an input vector is not
always the same as that of its output
vector. For example, the Hamming
weight changes from three to two when
(111) is mapped to (110).
Therefore, the Toffloli gate is not a
so-called conservative gate, whose out-
put preserves the number of logical
ones in the input. Conservative logic is
B Y
A X
Fig. 3 The quantum XOR gate, where A
and B are two qubits with B being
the control qubits.
useful as it allows us to build sequential
circuits with zero internal power dissi-
pation. Examples of gates that are both
conservative and reversible include the
Margolus gate and the Fredkin gate.
The Fredkin gate. This gate has been
employed by many reversible logic cir-
cuits (see Fig. 8 for an example).
Consider a (3, 3) Fredkin, which real-
izes Z = C, Y = BC + AC , and X = BC +
AC, where (C, B, A) is the input vector,
and (Z, Y, X) is the output vector. The
Fredkin gate is also self-reversible (with
a proof similar to that given for the
Toffoli gate). As depicted in Fig. 6, the
Fredkin gate uses C as its control input:
39
If C = 0, then the outputs are simply circuits in that the circuit creates some has more outputs than its conventional
duplicates of the inputs; otherwise if C redundant outputs. These outputs irreversible counterpart for the same
= 1, then the two input lines (A and B) appear to be “useless” in terms of real- number of inputs. We need them so
are interchanged (the lower half of the izing the desired logic functions (e.g., that we can retrieve the inputs to the
table). Obviously, the Fredkin gate is sum and carry out in the case of the reversible gate from its outputs. These
conservative. adder). Nevertheless, we must not dis- redundant outputs that are added to
In fact, the Fredkin gate is a univer- card these redundant outputs. make a logic function reversible are
sal gate in that it can be “programmed” Otherwise, information will be erased. called “garbage bits.”
(The circuit is no longer reversible with
unequal numbers of input and output CBA ZYX
CBA ZYX
000 000 000 000
001 001 Z 001 001
C R 010 010
010 010
Y
011 011 B
T X T Q 011 011
100 100 A P 100 100
101 101 101 110
110 111 Fig. 5 Two identical Toffoli gates are 110 101
cascaded. The outputs of the
111 110 second gate are the same as the 111 111
inputs to the first gate: R = C, Q =
Fig. 4 The truth table of the Toffoli gate. B, and P = A. Fig. 6 The truth table of the Fredkin
The arrows show the permutation gate, where C is the control input.
of the set of input vectors.
as different basic building blocks of vir- lines.)
tually any reversible logic circuits. For Moreover, if we want to feed any Challenges and promises
example, we can construct the follow- intermediate output signal to more than Our discussion has focused on logi-
ing logic gates by pre-setting some inputs two succeeding gates, we need at least cal reversibility – the inputs and outputs
of the Fredkin gate of reversible logic
as follows (see also gates that can be
Fig. 7): C C C C C C
uniquely retrievable
• AND gates from each other.
If input B = 0, 0 AC B B+C 0 C However, we have
then Z = C, Y + AC,
and X + AC. A
F AC 1
F B+C 1
F C
not touched upon the
other aspect of
• OR gates (a) (b) (c) reversible logic—
If input A = 1, physical reversibility,
then Z = C, Y = BC + C Fig. 7 Fredkin gate implementation of (a) AND; (b) OR; and (c) which is related to the key issue
= B + C, and X = BC + C FAN-OUT / NOT. as to whether we can build physi-
=B+C. cal gates and circuits that can
• FAN-OUT / NOT gate one fan-out gate to duplicate the signal. actually operate backwards and con-
If A = 1 and B = 0, then Z = C, Y = C, By contrast, in conventional irreversible sume (almost) zero power.
and X = C . logic circuits duplication is much sim- As such, we are still confronted with
Fig. 8 illustrates a full adder that is pler to achieve—multiple fan-outs of many challenges before actually turning
built with Fredkin gates, where A and B any output are allowed. reversible logic into a practical competi-
are single-bit inputs, and Cin denotes In general, any reversible logic gate tive technology. For example, we need
the single-bit “carry efficient synthesiz-
input.” The single- ing methods to
bit output for the Cin minimize garbage
sum is: Sum = 0 Sum bits, and we are
(Cin(A B )) +
(C in (A B)), and 1
F F F short of simula-
tion, synthesis,
the single-bit out- testing and verify-
put for the “carry ing tools for
A
output” is: C out = d e s i g n i n g
Cin (A + B) + (AB). B reversible logic.
In this adder 0 Cout
But researchers
example, the reader
may have noticed 1
F F F around the world
have been doing
that the reversible some exciting
logic circuit is quite research and mak-
different from conven- Fig. 8 Fredkin gate implementation of a single-bit full adder. Note that those ing progress in this
tional irreversible logic outputs (with dashed lines) other than the desired outputs (Sum and Cout) direction. The MIT
have to be retained in order for the adder to be reversible.

40 IEEE POTENTIALS
“Pendulum” project has been one such
pioneering effort, which yielded an
architecturally reversible, proof-of-con-
cept processor implemented by using
split-level charge recovery logic.
There is little doubt that reversible
logic (and reversible computing in a
broader sense) will become increasing-
ly “hot” in the near future. The energy
dissipated per irreversible logic opera-
tion is gradually approaching the funda-
mental limit of KT ln2. Coupled with
the exponential growth of the speed
and the complexity of the computing
systems, we may be forced to rely on
this “cool” technology to achieve ultra
low-power computing.
Read more about it
• C. H. Bennett, “Logical reversibility
of computation,” IBM Journal of
Research and Development, 17 (1973),
pp. 525-532.
• C. H. Bennett, “Notes on the histo-
ry of reversible computation,” IBM
Journal of Research and Development,
32 (1988), pp.16-23.
• P. Kerntopf, “Synthesis of multi-
purpose reversible logic gates,”
Euromicro Symposium on Digital
System Design, Sep. 2002.
• J. W. Bruce, M. A. Thornton, L.
Shivakumaraiah, P. S. Kokate, and X. Li,
“Efficient adder circuits based on a con-
servative reversible logic gate,” IEEE
Computer Society Annual Symposium
on VLSI, April 2002, pp. 83-88.
• A. De Vos, B. Raa and L. Storme,
“Generating the group of reversible
logic gates,” Institute of Physics
Publishing: Journal of Physics A:
Mathematical and General 35(33)
(2002), pp. 7063-7078.
• V. V. Shende, A. K. Prasad, I. L.
Markov, and J. P. Hayes, “Reversible
logic circuit synthesis,” IEEE
Transactions on Computer-Aided
Design of Integrated Circuits and
Systems, June 2003, pp. 710-722.
• D. Maslov and G. W. Dueck,
“Reversible Cascades with Minimal
Garbage,” IEEE Transactions on
Computer-Aided Design of Integrated
Circuits and Systems, Nov. 2004, pp.
1497-1509.
Websites:
•http://www.research.ibm.com/peo-
ple/b/bennetc/chbbib.htm:
Bibliography of Charles H. Bennett
•http://www.ai.mit.edu/~cvieri/reve
rsible.html: MIT AI Lab Reversible
Computing Home Page
•http://www.ece.pdx.edu/~mperko
ws/PQLG/: Portland Logic Group at
Portland State University
•http://www.elis.rug.ac.be/ELISgrou
ps/solar/projects/computer.html:
Reversible Computers at the Ghent
University
•http://www.cise.ufl.edu/research/r
evcomp/: Reversible and Quantum
Computing Group at the University of
Florida.
About the authors
W. David Pan is an Assistant
Professor of Electrical and Computer
Engineering at the University of
Alabama in Huntsville. He received his
Ph.D. degree in Electrical Engineering
from the University of Southern
California, Los Angeles, in 2002, and his
M.S. degree in Computer Engineering
from the University of Louisiana at
Lafayette in 1998.
Dr. Pan has held summer research
positions at the Advanced System Lab,
SGS-Thomson (ST) Microelectronics,
San Diego, CA, and at AT&T Labs –
Research, Middletown, NJ. His research
interests include multimedia signal pro-
cessing and communications, as well as
the emerging quantum computing.
Mahesh Nalasani is a graduate stu-
dent in the Department of Electrical and
Computer Engineering at the University
of Alabama in Huntsville. He received
his B. Tech degree in Electronics and
Communications Engineering from
Jawaharlal Nehru Technological
University (JNTU), Hyderabad, India in
2001.
Nalasani worked as a lecturer in the
Department of Electronics at JNTU from
2001 to 2002. His research interests are
in image/video coding and power-effi-
cient VLSI design.

The more things change, the more they remain the same

College graduates with good communication skills have a hiring advantage according to a study published by the National
Association of Colleges and Employers (NACE). "Since 1999, communication skills—both written and verbal—have topped employ-
ers’ lists," says Marilyn Mackes, NACE executive director. Moreover, candidates have "two key opportunities to demonstrate”
them—”on their resume and in the interview." Says Mackes, "Ironically, when we asked employers what skill was most lacking in col-
lege job candidates, good communication skills also topped the list." However,
employers have a pretty extensive wish list of other skills and qualities they are look- Employers rate candidate qualities/skills
ing for as well including a strong work ethic. (5-point scale, 1=not important
And that's assuming the candidate meets the employer’s basic criteria for job and 5=extremely important)
candidates, such as the requisite degree, experience or GPA. "For example,” Mackes
states, “nearly 70 percent of employers reported that they screen college job candi- Communication skills (written and verbal) 4.7
Honesty/integrity 4.7
dates based on GPA, and the largest group said they use a 3.0 as their 'cutoff.’
Interpersonal skills (relates well to others) 4.5
Candidates who fail to meet that cutoff aren't considered for job opportunities."
Strong work ethic 4.5
A candidate's work experience is also important to employers. Even unrelated
Teamwork skills (works well with others) 4.5
work experience can help a candidate stand out. “Employers are looking for evi- Analytical skills 4.4
dence that a candidate has the skills, qualities and abilities they believe are impor- Motivation/initiative 4.4
tant to workplace success and work experience—even if it's not directly related to Flexibility/adaptability 4.3
the job at hand—can provide that evidence," explains Mackes. The ability to pro- Computer skills 4.2
vide that evidence relates back to good communication skills. Because, according Detail-oriented 4.1
to Mackes, "Successful candidates know how to showcase their work experience on Leadership skills 4.0
their resume and during the interview demonstrate to employers that they have a Organizational skills 4.0

strong work ethic or the necessary teamwork skills."

Source: Job Outlook 2005, National Association of Colleges and Employers. <www.naceweb.org>

FEBRUARY/MARCH 2005 41