EECS 105 Fall 2004, Lecture 42

Lecture 42: Review of active

MOSFET circuits

Prof. J. S. Smith

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Final Exam
z Covers the course from the beginning
z Date/Time: SATURDAY, MAY 15, 2004 8-11A
z Location: BECHTEL auditorium
z One page (Two sides) of notes

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Observed Behavior: ID-VDS

I DS / k VGS = 4V

non-linear resistor region I DS

“constant” current VDS

VGS = 3V
resistor region
VGS

VGS = 2V

VDS

z For low values of drain voltage, the device is like a resistor

z As the voltage is increases, the resistance behaves non-linearly
and the rate of increase of current slows
z Eventually the current stops growing and remains essentially
constant (current source)
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Observed Behavior: ID-VDS

I DS / k VGS = 4V

non-linear resistor region I DS

“constant” current VDS

VGS = 3V
resistor region
VGS

VGS = 2V

VDS

As the drain voltage increases, the E field across the oxide at the drain end
is reduced, and so the charge is less, and the current no longer increases
proportionally. As the gate-source voltage is increased, this happens
at higher and higher drain voltages.
The start of the saturation region is shaped like a parabola

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Finding ID = f (VGS, VDS)

z Approximate inversion charge QN(y): drain is
higher than the source Æ less charge at drain end
of channel

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Inversion Charge at Source/Drain

The charge under the gate along the gate, but we are going to
make a simple approximation, that the average charge is the average
of the charge near the source and drain
Q N ( y = 0) + Q N ( y = L )
QN ( y ) ≈
2

Q N ( y = 0) = QN ( y = L) =

− Cox (VGS − VTn ) − Cox (VGD − VTn )

VGD = VGS − VDS

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Average Inversion Charge

Source End Drain End

Cox (VGS − VT ) + Cox (VGD − VT )

QN ( y ) ≈ −
2
Cox (VGS − VT ) + Cox (VGS − VSD − VT )
QN ( y ) ≈ −
2
C (2V − 2VT ) − CoxVSD V
QN ( y ) ≈ − ox GS = −Cox (VGS − VT − DS )
2 2

z Charge at drain end is lower since field is lower

z Notice that this only works if the gate is inverted along its
entire length
z If there is an inversion along the entire gate, it works well
because Q is proportional to V everywhere the gate is
inverted
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Drift Velocity and Drain Current

“Long-channel” assumption: use mobility to find v

µnVDS
v( y ) = − µn E ( y ) ≈ − µn (−∆V / ∆y ) =
L
And now the current is just charge per area, times
velocity, times the width:
VDS V
I D = −WvQN ≈ W µ Cox (VGS − VT − DS )
L 2
W VDS
I D ≈ µ Cox (VGS − VT − )VDS
L 2

Inverted Parabolas

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Square-Law Characteristics

Boundary: what is ID,SAT?

TRIODE REGION

SATURATION REGION

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

The Saturation Region

When VDS > VGS – VTn, there isn’t any inversion

charge at the drain … according to our simplistic model

Why do curves
flatten out?

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Square-Law Current in Saturation

Current stays at maximum (where VDS = VGS – VTn )

W V
ID = µCox (VGS − VT − DS )VDS
L 2
W V −V
I DS , sat = µ Cox (VGS − VT − GS T )(VGS − VT )
L 2
W µ Cox
I DS , sat = (VGS − VT ) 2
L 2
Measurement: ID increases slightly with increasing VDS
model with linear “fudge factor”
W µ Cox
I DS , sat = (VGS − VT ) 2 (1 + λVDS )
L 2
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

A Simple Circuit: An MOS Amplifier

Input signal Supply “Rail” VDD

RD

vo

I DS
vs
vGS = VGS + vs Output signal
VGS

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small Signal Analysis

z Step 1: Find DC operating point. Calculate
(estimate) the DC voltages and currents (ignore
small signals sources)
z Substitute the small-signal model of the
MOSFET/BJT/Diode and the small-signal models
of the other circuit elements.
z Solve for desired parameters (gain, input
impedance, …)

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

A Simple Circuit: An MOS Amplifier

Input signal VDD

RD Supply “Rail”

vo

I DS
vs
vGS = VGS + vs Output signal
VGS

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small-Signal Analysis

Step 1. Find DC Bias – ignore small-signal source

IGS,Q

VGS,BIAS was found in

Lecture 15
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small-Signal Modeling

What are the small-signal models of the DC supplies?

Shorts!
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small-Signal Models of Ideal Supplies

Small-signal model:
∂i
gsupply = supply = ∞
∂vsupply

rsupply = 0

short
∂isupply
gsupply = =0
∂vsupply

rsupply = ∞

open
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small-Signal Circuit for Amplifier

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Low-Frequency Voltage Gain

Consider first ω Æ 0 case … capacitors are open-circuits

vout = − g m vs ( RD || ro )

Av = − g m ( RD || ro )
Design Variable
Transconductance
W 2I
g m = µn Cox (VGS − VT ) = D , SAT
L VGS − VT

Design Variables
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Voltage Gain (Cont.)

Substitute transconductance:

⎛ 2I ⎞
Av = ⎜ − D , SAT ⎟ ( RD || ro ) g m RD
⎝ VGS − VT ⎠
Output resistance: typical value λn= 0.05 V-1
⎛ 1 ⎞ ⎛ 1 ⎞
ro = ⎜ ⎟⎟ = ⎜ ⎟ k Ω = 200 kΩ
⎜λ I
⎝ n D , SAT ⎠ ⎝ 0.05 ⋅ 0.1 ⎠
Voltage gain: ⎛ 2 ⋅ 0.1 ⎞
Av = − ⎜ ⎟ ( 25 || 200 ) = −14.3
⎝ 0.32 ⎠
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Input and Output Waveforms

Output small-signal voltage amplitude: 14 x 25 mV = 350

Input small-signal voltage amplitude: 25 mV

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

What Limits the Output Amplitude?

1. vOUT(t) reaches VSUP or 0 … or

2. MOSFET leaves constant-current region and enters

triode region

VDS ≤ VDS , SAT = VGS − VTn = 0.31V

vo , MIN = VDS , SAT = 0.32 V

amp = 2.5 − 0.32V = 2.18V

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Maximum Output Amplitude

vout(t)= -2.18 V cos(ωt) Æ vs(t) = 152 mV cos(ωt)

How accurate is the small-signal (linear) model?

vs 0.152
= ≈ 0.5
VGS − VTn 0.32
Significant error in neglecting third term in expansion
of iD = iD (vGS)

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

One-Port Models (EECS 40)

z A terminal pair across which a voltage and
associated current are defined
iab
+
Circuit
vab Block
−

iab iab
Rthev
+ +
vab vthev vab Rthev ithev

− −

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small-Signal Two-Port Models

iin iout
+ +
vin vout
− −

z We assume that input port is linear and that the

amplifier is unilateral:
– Output depends on input but input is independent of
output.
z Output port : depends linearly on the current and
voltage at the input and output ports
z Unilateral assumption is good as long as “overlap”
capacitance is small (MOS)
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Two-Port Small-Signal Amplifiers

Rs Rout

+
vs vin Rin Av vin RL
−

Voltage Amplifier
iin

is Rs Rin Ai iin Rout RL

Current Amplifier
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Two-Port Small-Signal Amplifiers

Rs

+
vs vin Rin Gm vin Rout RL
−

Transconductance Amplifier
iin Rout

is Rs Rin Rmiin RL

Transresistance Amplifier
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Common-Source Amplifier (again)

How to isolate DC level?

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

DC Bias
5V

Neglect all AC signals

2.5 V

Choose IBIAS, W/L

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Load-Line Analysis to find Q

VDD − Vout
I RD =
RD

Q
1
5V slope =
ID = 10k
10k

0V
ID =
10k
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small-Signal Analysis

Rin = ∞

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Two-Port Parameters:
Find Rin, Rout, Gm Generic Transconductance Amp
Rs

+
vs vin Rin Gm vin Rout RL
−

Rin = ∞

Gm = g m Rout = ro || RD
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Two-Port CS Model

Reattach source and load one-ports:

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Maximize Gain of CS Amp

Av = − g m RD || ro
z Increase the gm (more current)
z Increase RD (free? Don’t need to dissipate extra
power)
z Limit: Must keep the device in saturation

VDS = VDD − I D RD > VDS , sat

z For a fixed current, the load resistor can only be
chosen so large
z To have good swing we’d also like to avoid getting
too close to saturation
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Current Source Supply

z Solution: Use a
current source!
z Current independent
of voltage for ideal
source

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CS Amp with Current Source Supply

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Load Line for DC Biasing

Both the I-source and the transistor are idealized for DC bias
analysis
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Two-Port Parameters
From current
source supply

Rin = ∞
Gm = g m

Rout = ro || roc
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

P-Channel CS Amplifier

DC bias: VSG = VDD – VBIAS sets drain current –IDp = ISUP

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Common Gate Amplifier

Notice that
IOUT must equal DC bias:
-Is

I SUP = I BIAS = I DS

Gain of transistor
tends to hold this
node at ss ground:
low input impedance
load for current input
current gain=1
Impedance buffer
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CG as a Current Amplifier: Find Ai

iout = id = −it

Ai = −1

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CG Input Resistance

vgs = −vt

⎛v −v ⎞
At input:
it = − g m vgs + g mb vt + ⎜ t out ⎟
⎝ ro ⎠
Output voltage: v = −i (r || R ) = i (r || R )
out d oc L t oc L

⎛ v − ( roc || RL ) it ⎞
it = g m vt + g mb vt + ⎜ t ⎟
⎝ ro ⎠

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Approximations…
z We have this messy result
1
g m + g mb +
1 i ro
= t =
Rin vt r || RL
1 + oc
ro
z But we don’t need that much precision. Let’s start
approximating:
1 RL
g m + g mb >> roc || RL ≈ RL ≈0
ro ro

1
Rin =
g m + g mb

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CG Output Resistance

vs v −v
− g m vgs − (− g mb vs ) + s t = 0
RS ro

⎛ 1 1⎞ v
vs ⎜ + g m + g mb + ⎟ = t
⎝ RS ro ⎠ ro

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CG Output Resistance

Substituting vs = itRS
⎛ 1 1⎞ v
it RS ⎜ + g m + g mb + ⎟ = t
⎝ RS ro ⎠ ro

The output resistance is (vt / it)|| roc

⎛ ⎛ r ⎞⎞
Rout = roc || ⎜ RS ⎜ o + g m ro + g mb ro + 1⎟ ⎟
⎜ ⎟
⎝ ⎝ RS ⎠⎠

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Approximating the CG Rout

Rout = roc || [ro + g m ro RS + g mb ro RS + RS ]

The exact result is complicated, so let’s try to
make it simpler:
g m ≈ 500 µS g mb ≈ 50 µS ro ≈ 200kΩ

Rout ≅ roc || [ro + g m ro RS + RS ]

Assuming the source resistance is less than ro,

Rout ≈ roc || [ro + g m ro RS ] = roc || [ro (1 + g m RS )]

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CG Two-Port Model

Function: a current buffer

• Low Input Impedance
• High Output Impedance

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Common-Drain Amplifier
In the common drain amp,
the output is taken from a W 1
terminal of which the current I DS = µ Cox (VGS − VT ) 2
is a sensitive L 2
function

2 I DS
VGS = VT +
W
µ Cox
L Weak IDS dependence

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CD Voltage Gain

Note vgs = vt – vout vout

= g m vgs − g mb vout
roc || ro
vout
= g m ( vt − vout ) − g mb vout
roc || ro
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CD Voltage Gain (Cont.)

vout
KCL at source node: = g m ( vt − vout ) − g mb vout
roc || ro

⎛ 1 ⎞
⎜ + g mb + g m ⎟ vout = g m vt
⎝ roc || ro ⎠

Voltage gain (for vSB not zero):

vout gm
=
vin 1
+ g mb + g m
roc || ro
vout gm
≈ ≈1
vin g mb + g m
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CD Output Resistance

Sum currents at output (source) node:

vt
Rout = ro || roc || it = g m vt + g mb vt
it
1
Rout ≈
g m + g mb
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CD Output Resistance (Cont.)

ro || roc is much larger than the inverses of the
transconductances Æ ignore
1
Rout ≈
g m + g mb

Function: a voltage buffer

• High Input Impedance
• Low Output Impedance
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Voltage and current gain

Current tracks input

voltage tracks input

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Bias sensitivity
z When a transistor biasing circuit is designed, it is
important to realize that the characteristics of the
transistor can vary widely, and that passive
components vary significantly also.
z Biasing circuits must therefore be designed to
produce a usable bias without counting on specific
values for these components.
z One example is a BJT base bias in a CE amp. A
slight change in the base-emitter voltage makes a
very large difference in the quiescent point. The
insertion of a resistor at the emitter will improve
sensitivity.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Insensitivity to transistor parameters

z Most of the circuit parameters are independent of
variation of the transistor parameters, and depend
only on resistance ratios. That is often a design
goal, but in integrated circuits we will not want to
use so many resistors.

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

NMOS pullup
z Rather than using a big (and expensive) resistor,
let’s look at a NMOS transistor as an active pullup
+V
device

vout
Note that when the transistor is connected this way, it is not an amplifier,
it is a two terminal device. When the gate is connected to the drain of
this NMOS device, it will be in saturation, so we get the equation for
the drain current:

⎛W ⎞
⎟ µ n C ox (V SG − VTn ) (1 + λ nV SD )
2
ID = ⎜
⎝ 2L ⎠
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small signal model

z So we have:
⎛W ⎞
⎟ µ n C ox (V SG − VTn ) (1 + λ nV SD )
2
ID = ⎜
⎝ 2L ⎠
⎛W ⎞ ⎛W ⎞
⎟ µ n C ox (∆ V − VTn ) (1 + λ n ∆ V ) ≈ ⎜ ⎟ µ n C ox (∆ V − VTn )
2 2
=⎜
⎝ 2L ⎠ ⎝ 2L ⎠
z The N channel MOSFET’s transconductance is:
∂
gm = (iD ) = ⎛⎜ W ⎞⎟µ nCox (VSG − VTn ) ≅ 2⎛⎜ W ⎞⎟µ nCox (I D )
∂vSG Q ⎝L⎠ ⎝L⎠

z And so the small signal model for this device will

be a resistor with a resistance:
⎛ 1 ⎞
r = ⎜⎜ ⎟⎟
⎝ gm ⎠
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

IV for NMOS pull-up

z The I-V characteristic of this pull-up device:
⎛W ⎞
I D1 = ⎜ ⎟ µ n C ox (V DD − VTn )2
⎜L ⎟
⎝ ⎠

I (VDD − Vt 2 )

VDD
V
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Active Load
z We can use this as the pullup device for an NMOS common
source amplifier:
⎛W ⎞
I D 1 = ⎜⎜ 1 ⎟⎟ µ n C ox (V gs 1 − VTn 1 )
VDD 2

2
⎝ 1⎠
L

⎛W ⎞
M2 I D 2 = ⎜⎜ 2 ⎟⎟ µ n C ox (V gs 2 − VTn 2 )2
⎝ 2 L2 ⎠

+ V0 = VDD − Vgs 2
+ M1
vout
vin 2I 2
− V0 = VDD − Vt 2 −
− µ nCox (W2 / L2 )

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Active Load
Since I2=I1 we have:
2 I1
VDD V0 = VDD − Vt 2 −
µ nCox (W2 / L2 )

And since: Vgs1 = Vi

M2

+ V0 = VDD − Vtn1 −
(W1 / L1 ) (V − V )
+ M1
vout
(W2 / L2 ) i t1
vin
−
−

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Behavior
z If the output voltage goes higher than one threshold
below VDD, transistor 2 goes into cutoff and the
amplifier will clip.
z If the output goes too low, then transistor 1 will fall
out of the saturation mode.
z Within these limitations, this stage gives a good
linear amplification.

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

CMOS Diode Connected Transistor

z Short gate/drain of a transistor
and pass current through it
z Since VGS = VDS, the device
is in saturation since VDS >
VGS-VT
z Since FET is a square-law (or
weaker) device, the I-V curve
is very soft compared to PN
junction diode

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Diode Equivalent Circuit

−1
⎛ di ⎞ v
RD = ⎜ OUT ⎟ = t
⎜ dvOUT ⎟ it
⎝ I OUT = 0 ⎠

1
RD ≈
gm
Equivalent Circuit:
RD iOUT

+
VD +- vOUT

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

The Integrated “Current Mirror”

z M1 and M2 have the same
VGS
z If we neglect CLM (λ=0),
then the drain currents are
equal
z Since λ is small, the
High Res currents will nearly mirror
one another even if Vout is
Low Resis not equal to VGS1
z We say that the current
IREF is mirrored into iOUT
z Notice that the mirror
works for small and large
signals!

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Current Mirror as Current Sink

z The output current of M2 is only weakly dependent on

vOUT due to high output resistance of FET
z M2 acts like a current source to the rest of the circuit
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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Small-Signal Resistance of I-Source

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Improved Current Sources

Goal: increase roc

Approach: look at amplifier output resistance
results … to see topologies that boost resistance

Rout >> ro

Looks like the output

impedance of a common-
source amplifier with source
degeneration

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Effect of Source Degeneration

vt = (it − g m vgs )ro + vRS

vgs ≈ −vRS
vRS = it RS
1
Req ≈ vt = (it + g m RS it )ro + it RS
gm
vt
Ro = ≈ (1 + g m RS ) ro
it
z Equivalent resistance loading gate is dominated by
the diode resistance … assume this is a small
impedance
z Output impedance is boosted by factor (1 + g m RS )

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Cascode (or Stacked) Current Source

Insight: VGS2 = constant AND

VDS2 = constant

Small-Signal Resistance roc:

Ro ≈ (1 + g m RS ) ro

Ro ≈ (1 + g m ro ) ro

Ro ≈ g m r02 >> ro

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Drawback of Cascode I-Source

Minimum output voltage to keep both transistors in

saturation: V =V +V
OUT , MIN DS 4, MIN DS 2, MIN

VDS 2, MIN > VGS 2 − VT 0 = VDSAT 2

VD 4 > VDSAT 2 + VGS 4 = VGS 2 + VGS 4 − VT 0
iOUT

vOUT
VOUT , MIN = VGS 2 + VGS 4 − VT 0
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Current Sinks and Sources

Sink: output current goes Source: output current comes

to ground from voltage supply

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EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Current Mirrors
We only need one reference current to set up all the current
sources and sinks needed for a multistage amplifier.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Summary of Cascaded Amplifiers

General goals:

1. Boost the gain (except for buffers)

2. Improve frequency response
3. Optimize the input and output resistances:
Rin Rout
Voltage: ∞ 0
Current: 0 ∞
Transconductance:
∞ ∞
Transresistance:
0 0
Department of EECS University of California, Berkeley

37
EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Start: Two-Stage Voltage Amplifier

• Use two-port models to explore whether the combination

“works”

CS1 CS2

CS1,2

Results of new 2-port: Rin = Rin1, Rout = Rout2

Av = −Gm1 ( Rin 2 || Rout1 ) × ( −Gm 2 Rout 2 )

Av = Gm1Gm 2 ( Rin 2 || Rout1 )( Rout 2 )

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith

Cascading stages

CS1 CS2 CD3

Input resistance: ∞

Voltage gain (2-port parameter):

Av = − g m1 ( ro1 || roc1 ) × g m 2 ( − ro 2 || roc 2 )
Output resistance:
1
Rout =
g m + g mb
Department of EECS University of California, Berkeley

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