practically, you cant put S=1 and R=1 simultaneously. There is always a certain delay.

So, if S=1 reaches first, the FF sets to Q=1. But,

again, R=1 reaches and then, the FF changes to Q’=1. Here, both the outputs cant be 1 as it violates that Q and Q’ are inverse. So, it
generally takes the Flipflop to one of the state of set or reset. The state is determined by various factors like the speed gap between
the two lines being high and the transistor inside the gaes used in flipflops even if both lines are high at the same time(Too much
details to go into!!) So, basically, we cant predict the output and hence, we never use it and define it as invalid or forbidden.

A JK flip flop can be formed by using two cross coupled NOR gates connected with two AND gates in series.The J input in addition is
connected to the Qbar output and the K input is connected to the Q output.Using the NOR gate circuitry make it active high.

It can also be formed by using two cross coupled NAND gates connected with two NAND gates in series.Again as mentioned in the
upper scenario the J input is connected to Qbar output and the K input is connected to the Q output.Using the NAND gate circuitry
make it active low.

So as we can see from the truth table when J and K input both are zero on the triggering edge of clock pulse there is no change of
state and that state is Q(0) and mostly it is the previous state.

When J input is 1 and K input is 0 on the triggering edge of clock pulse,then output is in set state.

When J input is 0 and K input is 1 on the triggering edge of clock pulse,then the output is in reset state.

When J and K input both are 1 on the triggering edge of clock pulse,then the output toggle wrt what was the state in the previous
clock cycle.

So as it can be seen from the timing diagram,on the application of the first edge of clock pulse when both J and K are 0,output is
0,on the second clock pulse when J is 1 and K is 0,output is set and it's 1,on the application of the 3rd clock pulse when both J and K
are 1,output gets toggled wrt previous state and it is 0.

SR Flip Flop:-A SR flip flop also consist of two inputs mainly as S and R called as Set and Reset and output as Q and inverted
output Qbar.A SR flip flop is constructed using two cross coupled NOR gates connected with two AND gates in series.When both S
and R input are 0,there is no change in output and it holds the previous state.When S is 0 and R is 1,output is on reset state.When
S is 1 and R is 0,output is in set state.But,

When both the inputs are 1,output is in invalid state and it goes in a metastable state where we wouldn't able to
predict the output and here lies the main difference with JK flip flop.a) When both S and R inputs are 1,output
goes to a metastable state but when both the inputs of J and K are 1 output is in toggle state wrt previous
state.b) JK flip flop often termed as Universal flip flop because all other flips like D,T and SR can be derived
from that while this is not the case wrt SR flip flops.c) SR flip flops when used as latch can be help in the bounce
elimination of the switches which is one of its major advantages while this is not the case with JK flip flops.

There are problems associated with JK flip flop too where in the case when both J and K input are 1,output can change more than
once in a single clock cycle which gives rise to race condition.

One more problem occurs with JK flip flop is that propagation delay of flip flop is less than the propagation delay of clock pulse
width.

So to avoid all these problems master slave JK flip flops has been taken into consideration.

n TTL circuits also, input transistor T1 is a multi-emitter transistor driving the phase-splitter transistor T2. As stated above, this phase-
splitter drives the push-pull output transistors T3 and T4. The output section, consisting of transistors T3 and T4, diode D, and the
100-ohm resistor, is known as a totem-pole configuration, since it looks like a totem-pole with its ups and downs. It may be noted
that a totem pole is a stick held by kings, emperors, and holy men in their hands to exhibit their authority. In another type of NAND
gate, called the open-collector NAND gate, transistor T3 and diode D are removed.ex- Now consider the condition A = B = 1. In this
case, both the diodes A and B remain reverse biased. So, current flows from +VCC through the base-collector diode of T1 into the
base of T2 turning it ON. Collector current of T2 starts flowing now, developing enough voltage (0.8 V) at its emitter E2 to turn T4 ON.
Also since T2 is ON, its collector-emitter voltage drops to the saturation value of VCES2 = 0.2 V and its collector voltage VC2= 0.8 + 0.2
= 1 V.  With diode D present, T3 remains OFF. However since T4 is ON, the collector-emitter voltage of T4, VCES4 = 0.2 V, and the
output Z is at logic 0. Thus for the situation A = B = 1, we have Z = 0.

In CMOS technology, both N-type and P-type transistors are used to design logic functions. The same signal which turns ON a

transistor of one type is used to turn OFF a transistor of the other type. This characteristic allows the design of logic devices using

only simple switches, without the need for a pull-up resistor.

In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network between the output and the low voltage

power supply rail (Vss or quite often ground). Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection

of p-type MOSFETs in a pull-up network between the output and the higher-voltage rail (often named Vdd).

Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be ON when the

n-type MOSFET is OFF, and vice-versa.

Ing-As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF. So the output Vout will get two paths

through two ON pMOS to get connected with V dd. The output will be charged to the Vdd level. The output line will not get any path to

the GND as both the nMOS are off. So, there is no path through which the output line can discharge. The output line will maintain

the voltage level at Vdd; so, High.

1. TTL circuits use bipolar

junction transistors (BJTs) while CMOS circuits use field effect transistors (FETs) ie.,by connecting NMOS and PMOS
(MOSFETs).
2. A single logic gate in a CMOS chip can consist of as little as two FETs while a logic gate in a TTL chip can consist of a
substantial number of parts as extra components like resistors are needed.
3. A single gate in a CMOS chip can consume around 10nW while an equivalent gate on a TTL chip can consume around
10mW of power, which is why CMOS is the preferred chip in mobile devices where power is supplied by a limited
source like a battery.
4. CMOS are more susceptible to electrostatic discharge. Mere touching the terminals induce enough static electricity to
damage the device permanently.
5. The basic gates used in standard TTL are NAND gates while NAND-NOR gates are used in CMOS circuits.
6. Fan-out( number of standard loads that can be connected to the output of the gate under normal operation) for TTL is
10 while it is 50 for CMOS.
7. Propagation delay for TTL is 10 ns and for CMOS, it is 70 ns.
8. Fan-in ( Number of inputs that can be connected to a gate) for TTL is around 12–14 and it is greater than 10 for
CMOS.
9. For TTL, the noise margin is 0.5 V while for CMOS, it is 1.5V .
10. Noise immunity of CMOS is a lot better than TTL circuits.
11. CMOS circuits are simpler to construct and has a higher packing density than TTL logic family.

If A or B is low, the base-emitter junction of Q1 is forward biased and its base-collector junction is reverse biased.
Then there is a current from Vcc through R1 ti the base emitter junction of Q1 and into the LOW input, which
provides a path to the ground for the current. Hence there is no current into the base of Q2 and making it into cur-
off. The collector of Q2 is HIGH and turns Q3 into saturation. Since Q3 acts as a emitter follower, bu providing a
low impedance path from Vcc to the output, making the output into HIGH. At the same time, the emitter of Q2 is
at ground potential, keping Q4 OFF.When A and B are high, the two input base emitter junctions of Q1 are reverse
niased and its base collector junction is forward biased. This permits current through R1 and the base collector
junction of Q1 into the base of Q2, thus driving Q2 into saturation. As a result Q4 is turned ON by Q2, and
producing LOW ourput which is near ground potential. At the same time, the collector of Q2 is sufficiently at LOW
voltage level to keep Q3 OFF.
Transistor Q1 actually behaves as cluster of diodes placed back to back. With any of the input at logic low, corresponding emitter

base junction is forward biased and the voltage drop across the base of Q1 is around 0.9V, not enough for the transistors Q2 and

Q3 to conduct. Thus output is either floating or Vcc, i.e. High level.

Similarly when all inputs are high, all base emitter junctions of Q1 are reverse biased and transistor Q2 and Q3 get enough base

current and are in saturation mode. Clearly output is at logic low. (For a transistor to go to saturation, collector current should be

greater than β times the base current).

It has open collector output that is suitable for wired GATE

We can use Schottky TTL for speed
Higher Power consumption
Poor Noise Margin