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Intel SKL-U/KBL-U Platform Block Diagram 01


VRAM DDR3L R17M-M1-30/70 PCIE x4
256x16*4 1GHz PCB 6L STACK UP
64bit 23x23
256x16*4 1GHz TDP 18W/25W
D D
PAGE 24,25 PAGE 19~23 DDI1 LAYER 1 : TOP
HDMI CONN V1.4 LAYER 2 : SGND
DDR4 SO-DIMM 2133MHz
PAGE 29 LAYER 3 : IN1(High)
Maxima 8GBs
LAYER 4 : IN2(Low)
PAGE 17 eDP X2 Lane
Intel SKL/KBL U LAYER 5 : SVCC
DDR4 SO-DIMM 2133MHz eDP
LAYER 6 : BOT
Maxima 8GBs PAGE 27
Power : 15 (Watt)
PAGE 18
DDI2 DP to VGA Translator
Package : BGA1356 VGA Port
SATA0 6GB/s RTD2166-CG
SATA SSD Or SATA HDD PAGE 26 PAGE 26
M.2 2.5" Size : 40 X 24 (mm)
DB PAGE 36
SATA2 6GB/s
2nd SATA SSD USB3.0
M.2
PAGE 35
C PORT1 PORT2 C

SATA1 1.5GB/s
VIA VL711 ODD Card Reader(DB)
USB3.0 CONN USB3.0 CONN USB2.0 CONN RTS5141-GR
PAGE 35 PAGE 31 PAGE 31 PAGE 31 PAGE 31
SATA1 1.5GB/s
SMBus
USB2.0 PORT1 PORT2 PORT4 PORT6
PORT7 PORT3 PORT8
SPI ROM SPI
PCIE
PAGE 10

LPC Interface
NIC WLAN/BT COMBO
HDA Webcam Touch Screen
RTL8166EN-CG 10/100 M.2
TPM PAGE 36 PAGE 27 PAGE 27
Touch Pad Embedded Controller RTL8111HSH-CG 1000
B SLB9665TT2.0 B
KBC IT8987
PAGE 33 PAGE 37 PAGE 34 PAGE 30
Audio Codec
FAN
ALC3227-CG RJ45 CONN
PAGE 33 PAGE 28
PAGE 30
Keyboard
Speaker
PAGE 33
PAGE 28

Combo Jack
PAGE 28

Digital MIC
A A
PAGE 27

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5
1A
Block Diagram
Date: Wednesday, March 08, 2017 Sheet 1 of 51

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5 4 3 2 1

+3V
+1.0V
<4,10,11,12,13,14,15,17,18,26,27,28,29,30,31,33,34,35,37,43,45>
<4,37,42,43>
<29>
<29>
<29>
IN_D2#
IN_D2
IN_D1#
IN_D2#
IN_D2
IN_D1#
IN_D1
E55
F55
E58
F58
U1A

DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
SKL_ULT ? Need apply PN
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
C47
C46
D46
C45
INT_EDP_TXN0
INT_EDP_TXP0
INT_EDP_TXN1
INT_EDP_TXP1
INT_EDP_TXN0
INT_EDP_TXP0
INT_EDP_TXN1
<27>
<27>
<27>
Reserve EDP_HPD opposites circuit!
02
HDMI
+VCCSTPLL <4,5,6,9,42> <29> IN_D1 IN_D0# DDI1_TXP[1] EDP_TXP[1] INT_EDP_TXP1 <27>
F53 A45
<29> IN_D0# IN_D0 DDI1_TXN[2] EDP_TXN[2]
G53 B45
<29> IN_D0 IN_CLK# DDI1_TXP[2] EDP_TXP[2]
F56 A47
<29> IN_CLK# IN_CLK DDI1_TXN[3] EDP_TXN[3]
G56 B47
<29> IN_CLK DDI1_TXP[3] EDP_TXP[3]
DDI1_TX0_N C50 E45 INT_EDP_AUXN
<26> DDI1_TX0_N DDI1_TX0_P DDI2_TXN[0] DDI EDP_AUXN INT_EDP_AUXP INT_EDP_AUXN <27>
D D50 EDP F45 D
<26> DDI1_TX0_P DDI2_TXP[0] EDP_AUXP INT_EDP_AUXP <27>
DDI1_TX1_N C52
<26> DDI1_TX1_N DDI1_TX1_P DDI2_TXN[1]
D52 B52
<26> DDI1_TX1_P DDI2_TXP[1] EDP_DISP_UTIL
A50
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50 ULT_EDP_HPD
C51 DDI2_TXN[3] DDI1_AUXP E48
DDI2_TXP[3] DDI2_AUXN F48 INT_DDI1_AUXN <26>
DDI2_AUXP G46 INT_DDI1_AUXP <26>
R2
DISPLAY SIDEBANDS DDI3_AUXN F46
DDI3_AUXP 100K_4
L13
<29> SDVO_CLK GPP_E18/DDPB_CTRLCLK
L12 L9 HDMI_HPD_CON
<29> SDVO_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 DDI1_HPD_CON HDMI_HPD_CON <29>
L7
N7 GPP_E14/DDPC_HPD1 L6 DDI1_HPD_CON <26>

SI +3V R9055
2.2K_4
DDPC_CTRLDATA N8 GPP_E20/DDPC_CTRLCLK
GPP_E21/DDPC_CTRLDATA
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
N9
L10 ULT_EDP_HPD
ULT_EDP_HPD <27>
N11
* 1 DDPD_CTRLDATA N12 GPP_E22/DDPD_CTRLCLK R12 PCH_LVDS_BLON
TP3 GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_DPST_PWM PCH_LVDS_BLON <27>
R11
EDP_RCOMP EDP_BKLTCTL PCH_DISP_ON PCH_DPST_PWM <27>
E52 U13
+VCCIO EDP_RCOMP EDP_VDDEN PCH_DISP_ON <27>
R3 24.9_1%_4
*SKL_ULT
1 OF 20 ?
eDP_COMPIO and ICOMPO signals should be shorted near REV = 1
balls and routed with typical impedance <25 mohms

C C

U1D SKL_ULT ? Need apply PN


CATERR# D63
Close to EC
EC_PECI A54 CATERR#
<37> EC_PECI PECI +VCCSTPLL
R4 499/F_4 PROCHOT# C65
<37,43> H_PROCHOT# PM_THRMTRIP# PROCHOT# JTAG
C63
<37> PM_THRMTRIP# THERMTRIP# PM_THRMTRIP#
A65 XDP_TCK0 R5 1K_4
SKTOCC# B61
CPU MISC PROC_TCK D60 XDP_TDI_CPU
C55 PROC_TDI XDP_TDO_CPU
BPM#[0] A61
D55 PROC_TDO XDP_TMS_CPU Processor pull-up (CPU)
+VCCSTPLL BPM#[1] C60
B54 PROC_TMS PROC_TEST#
C56 BPM#[2]
PROC_TRST#
B59 TO BE REPLACED WITH 1K OHMS FOR SKL .
R6 *49.9/F_4 CATERR# BPM#[3] 470 OHM IS FOR I/P
B56 JTAG_TCK_PCH
A6 PCH_JTAG_TCK JTAG_TDI_PCH
GPP_E3/CPU_GP0 D59
A7 PCH_JTAG_TDI JTAG_TDO_PCH
GPP_E7/CPU_GP1 A56
BA5 PCH_JTAG_TDO JTAG_TMS_PCH
GPP_B3/CPU_GP2 C59
AY5 PCH_JTAG_TMS XDP_TRST#_CPU
+1.0V GPP_B4/CPU_GP3 C61
PCH_TRST# A59 JTAGX_PCH
R8 49.9/F_4 PROC_POPIRCOMP AT16 JTAGX
R10 *51_4 JTAGX_PCH R11 49.9/F_4 PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
B R12 49.9/F_4 EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP B
R13 51_4 JTAG_TMS_PCH R14 49.9/F_4 EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
JTAG_TDI_PCH BOM XDP_TRST#_CPU R863
PLACE NEAR CPU +1.0V
R15 51_4 *0_4/SPROC_TEST#

JTAG_TDO_PCH *SKL_ULT ? XDP_TMS_CPU


R16 51_4 4 OF 20 R17 *51_4
REV = 1
R18 51_4 JTAG_TCK_PCH XDP_TDI_CPU R19 *51_4

Close to Chipset XDP_TDO_CPU R20 *51_4

+1.0V

H_PROCHOT# R21 1K_4

XDP_TCK0 R22 51_4

XDP_TRST#_CPU R23 51_4

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 02 -- SKYPAKE 1/15 (eDP/DDI) 1A

Date: Wednesday, March 08, 2017 Sheet 2 of 51


5 4 3 2 1
5 4 3 2 1

<17>
<17>
<18>
<18>
<17>
M_A_DQSN[7:0]
M_A_DQSP[7:0]
M_B_DQSN[7:0]
M_B_DQSP[7:0]
M_A_DQ[63:0]
03
<18> M_B_DQ[63:0]

+1.2VSUS <6,17,18,40,42>
SkyLake ULT Processor (DDR4)
D D

Need apply PN
? ?
SKL_ULT SKL_ULT
U1B U1C

AU53 M_A_CLKN0 <17>


Need apply PN
M_A_DQ0 AL71 DDR0_CKN[0] AT53 M_A_DQ32 AY39 AN45
M_A_DQ1 DDR0_DQ[0] DDR0_CKP[0] M_A_CLKP0 <17> M_A_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] M_B_CLKN0 <18>
AL68 AU55 M_A_CLKN1 <17>
AW39 AN46
M_A_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 M_A_DQ34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] AP45 M_B_CLKN1 <18>
M_A_DQ3 DDR0_DQ[2] DDR0_CKP[1] M_A_CLKP1 <17> M_A_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] M_B_CLKP0 <18>
AN69 AW37 AP46
M_A_DQ4 AL70 DDR0_DQ[3] BA56 M_A_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] M_B_CLKP1 <18>
M_A_DQ5 DDR0_DQ[4] DDR0_CKE[0] M_A_CKE0 <17> M_A_DQ37 DDR0_DQ[36]/DDR1_DQ[4]
AL69 BB56 M_A_CKE1 <17>
BA39 AN56
M_A_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 M_A_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] AP55 M_B_CKE0 <18>
M_A_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 M_A_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] AN55 M_B_CKE1 <18>
M_A_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3] M_A_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2] AP53
M_A_DQ9 AR68 DDR0_DQ[8] AU45 M_A_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
M_A_DQ10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 M_A_CS#0 <17> M_A_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] BB42
M_A_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 M_A_CS#1 <17> M_A_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] AY42 M_B_CS#0 <18>
M_A_DQ12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 M_A_DIM0_ODT0 <17> M_A_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] BA42 M_B_CS#1 <18>
M_A_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1] M_A_DIM0_ODT1 <17> M_A_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0] AW42 M_B_DIM0_ODT0 <18>
M_A_DQ14 AU70 DDR0_DQ[13] BA51 M_A_A5 M_A_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] M_B_DIM0_ODT1 <18>
M_A_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 M_A_A9 M_A_A5 <17> M_A_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] AY48 M_B_A5
M_B_DQ0 AF65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 M_A_A6 M_A_A9 <17> M_B_DQ32 AU40 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 M_B_A9 M_B_A5 <18>
M_B_DQ1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 M_A_A8 M_A_A6 <17> M_B_DQ33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 M_B_A6 M_B_A9 <18>
M_B_DQ2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52M_A_A7 M_A_A8 <17> M_B_DQ34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 M_B_A8 M_B_A6 <18>
M_B_DQ3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 M_A_BG#0 M_A_A7 <17> M_B_DQ35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 M_B_A7 M_B_A8 <18>
C C
M_B_DQ4 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54M_A_A12 M_A_BG#0 <17> M_B_DQ36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 M_B_A7 <18>
M_B_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 M_A_A11 M_A_A12 <17> M_B_DQ37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 M_B_A12 M_B_BG#0 <18>
M_B_DQ6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 M_A_A11 <17> M_B_DQ38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 M_B_A11 M_B_A12 <18>
M_B_DQ7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 M_A_ACT# <17> M_B_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 M_B_A11 <18>
M_B_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_A_BG#1 <17> M_B_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 M_B_ACT# <18>
M_B_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] AU46 M_A_A13 M_B_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] M_B_BG#1 <18>
M_B_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 M_A_A13 <17> M_B_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] BA43 M_B_A13
M_B_DQ11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 M_A_CAS# <17> M_B_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 M_B_A13 <18>
M_B_DQ12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 M_A_WE# <17> M_B_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 M_B_CAS# <18>
M_B_DQ13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 M_A_RAS# <17> M_B_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 M_B_WE# <18>
M_B_DQ14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 M_A_A2 M_A_BS#0 <17> M_B_DQ46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 M_B_RAS# <18>
M_B_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 M_A_A2 <17> M_B_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 M_B_A2 M_B_BS#0 <18>
M_A_DQ16 BB65 DDR1_DQ[15]/DDR0_DQ[31] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 M_A_A10 M_A_BS#1 <17> M_A_DQ48 AY31 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 M_B_A2 <18>
M_A_DQ17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 M_A_A1 M_A_A10 <17> M_A_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46M_B_A10 M_B_BS#1 <18>
M_A_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 M_A_A0 M_A_A1 <17> M_A_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 M_B_A1 M_B_A10 <18>
M_A_DQ19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 M_A_A3 M_A_A0 <17> M_A_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 M_B_A0 M_B_A1 <18>
M_A_DQ20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[3] BB52 M_A_A4 M_A_A3 <17> M_A_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 M_B_A3 M_B_A0 <18>
M_A_DQ21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[4] M_A_A4 <17> M_A_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3] BA47 M_B_A4 M_B_A3 <18>
M_A_DQ22 BA63 DDR0_DQ[21]/DDR0_DQ[37] AM70 M_A_DQSN0 M_A_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4] M_B_A4 <18>
M_A_DQ23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQSN[0] AM69 M_A_DQSP0 M_A_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] BA38 M_A_DQSN4
M_A_DQ24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSP[0] AT69 M_A_DQSN1 M_A_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 M_A_DQSP4
M_A_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSN[1] AT70 M_A_DQSP1 M_A_DQ57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 M_A_DQSN5
M_A_DQ26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSP[1] AH66 M_B_DQSN0 M_A_DQ58 AY25 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 M_A_DQSP5
M_A_DQ27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 M_B_DQSP0 M_A_DQ59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] AT38 M_B_DQSN4
M_A_DQ28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 M_B_DQSN1 M_A_DQ60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 M_B_DQSP4
M_A_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 M_B_DQSP1 M_A_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 M_B_DQSN5
M_A_DQ30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSP[1]/DDR0_DQSP[3] BA64 M_A_DQSN2 M_A_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 M_B_DQSP5
M_A_DQ31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 M_A_DQSP2 M_A_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3] BA30 M_A_DQSN6
M_B_DQ16 AT66 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 M_A_DQSN3 M_B_DQ48 AU27 DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 M_A_DQSP6 +1.2VSUS
B M_B_DQ17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 M_A_DQSP3 M_B_DQ49 AT27 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 M_A_DQSN7 B
M_B_DQ18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSP[3]/DDR0_DQSP[5] AR66 M_B_DQSN2 M_B_DQ50 AT25 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 M_A_DQSP7
M_B_DQ19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 M_B_DQSP2 M_B_DQ51 AU25 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] AR25 M_B_DQSN6
M_B_DQ20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 M_B_DQSN3 M_B_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 M_B_DQSP6
M_B_DQ21 AP66 DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
AR60 M_B_DQSP3 M_B_DQ53 AN27 DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQSP[6]
DDR1_DQSN[7]
AR22 M_B_DQSN7 20mils width R24
M_B_DQ22 AT65 M_B_DQ54 AN25 AR21 M_B_DQSP7 470/F_4
M_B_DQ23 AU65 DDR1_DQ[22]/DDR0_DQ[54] AW50 M_A_ALERT# M_B_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
M_B_DQ24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR0_ALERT# AT52 M_A_PARITY M_A_ALERT# <17> M_B_DQ56 AT22 DDR1_DQ[55] AN43 M_B_ALERT#
M_B_DQ25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR0_PAR M_A_PARITY <17> M_B_DQ57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 M_B_PARITY M_B_ALERT# <18>
M_B_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58] DDR_VREF_CA
AY67 SM_VREF SM_VREF <17>
20mils width M_B_DQ58 AU21 DDR1_DQ[57]
DDR1_DQ[58]
DDR1_PAR
DRAM_RESET#
AT13 SM_DRAMRST# M_B_PARITY <18>
DDR3_DRAMRST# <17,18>
M_B_DQ27 AN60 AY68 SMDDR_VREF_DQ0_M3 M_B_DQ59 AT21 AR18 SM_RCOMP_0 R25 121/F_4
M_B_DQ28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR0_VREF_DQ BA67 SMDDR_VREF_DQ1_M3 TP7 M_B_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 R26
NIL-DDR CH - SMDDR_VREF_DQ1_M3 <18> 80.6/F_4
M_B_DQ29 AP61 DDR1_DQ[28]/DDR0_DQ[60] A DDR1_VREF_DQ M_B_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 R27 100/F_4
M_B_DQ30 AT60 DDR1_DQ[29]/DDR0_DQ[61] AW67DDR_VTT_CNTL M_B_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
M_B_DQ31 DDR1_DQ[30]/DDR0_DQ[62] DDR_VTT_CNTL DDR_VTT_CNTL <18> M_B_DQ63 DDR1_DQ[62]
AU60 AN21
DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[63]
NIL-DDR CH -
B BOM
*SKL_ULT ? *SKL_ULT
2 OF 20 3 OF 20 ?
REV = 1 REV = 1

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 03 -- SKYLAKE 2/15(DDR4 I/F) 1A

Date: Wednesday, March 08, 2017 Sheet 3 of 51


5 4 3 2 1
5 4 3 2 1

<10,11,12,14,15,18> +3V_DEEP_SUS
<2,10,11,12,13,14,15,17,18,26,27,28,29,30,31,33,34,35,37,43,45>
<15,31,36,37,39,40,41,42,45,46,49>
<2,5,6,9,42>
<2,37,42,43>
+3V
+3VS5
+VCCSTPLL
+1.0V
04
+BAT_RTC
U1K
SKL_ULT
?
Need apply PN
<13,15> +3V_RTC_2
SYSTEM POWER MANAGEMENT
PCH Pull-high/low(CLG)
AT11 PCH_SLP_S0_N 1 *
GPP_B12/SLP_S0# TP942
AP15
AN10 GPD4/SLP_S3# BA16 SUSB# <37>
PLTRST#
D SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 1 SUSC# <37> +3V_DEEP_SUS D
*
SYS_RESET# GPD10/SLP_S5# TP941
RSMRST# AY17
<37> RSMRST# RSMRST# SLP_SUS#_EC
AN15 SUSWARN# R28 *10K_4
A68 SLP_SUS# AW 15 SLP_SUS#_EC <37>
R29 *10K_4 PROCPWRGD
EC1 H_VCCST_PWRGD B65 PROCPW RGD SLP_LAN# BB17 GPD9 1 *
VCCST_PW RGD GPD9/SLP_W LAN# AN16 1 TP8
*220p/50V_4 C1 *0.1u/16V_4 *
SYS_PWROK B6 GPD6/SLP_A# TP940 RF_OFF_PCH R31 10K_4
PCH_PWROK BA20 SYS_PW ROK BA15 DNBSWON#
<37> EC_PWROK PCH_PW ROK GPD3/PW RBTN# DNBSWON# <37>
DSWROK_EC_R BB20 AY15 AC_PRESENT_EC
DSW _PW ROK GPD1/ACPRESENT AU13 RF_OFF_PCH AC_PRESENT_EC <37> +3VS5
TP8518 1SUSWARN# AR13 GPD0/BATLOW # RF_OFF_PCH <36>
*0_4/S R34 SUSACK# AP11 GPP_A13/SUSW ARN#/SUSPW RDNACK PCIE_WAKE# R35 1K_4
GPP_A15/SUSACK# AU11
* PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTRUDER#_R R305 1M_4 AC_PRESENT_EC R37 *10K_4
<30,36> PCIE_WAKE# W AKE# INTRUDER# +3V_RTC_2
LAN_WAKE# AM15
AW 17 GPD2/LAN_W AKE# AM10 LAN_WAKE# R38 *10K_4
AT15 GPD11/LANPHYPC GPP_B11/EXT_PW R_GATE# AM11
GPD7/RSVD GPP_B2/VRALERT#
+3V
*SKL_ULT SYS_RESET#
11 OF 20 ? R39 10K_4
REV = 1
RSMRST# R40 10K_4

DSWROK_EC R41 100K/F_4

C C

For DS3 Sequence


+1.0V +5VS5 +3VS5

R43 R44 R45


+1.0V +VCCSTPLL 15K/F_4 100K_4 10K_4
R46 *0_4/S DSWROK_EC_R
<37> DSWROK_EC
HWPG
R47 R48
1K_4 *1K_4

3
+1.0V_PWRGD_G2 2 Q1
Ra 2N7002K R49
D1 1 2 MEK500V-40 H_VCCST_PWRGD_R R50 60.4/F_4 H_VCCST_PWRGD 100K_4
<37,39,40,41> HWPG

3
PLTRST#(CLG)

1
+1.0V_PWRGD_G1 2 Q2
Check Rise/Fall time less than 100ns METR3904-G

1
PLTRST# <19,30,34,36,37> C3 C2 R51
*10P/50V_4 0.1U/16V_4 100K_4

R52
100K/F_4
B B

Ra close to CPU side


H_VCCST_PWRGD trace 0.3" - 1.5"

System PWR_OK(CLG)
SYS_PWROK EC_PWROK

R54
10K/F_4

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 04 -- SKYLAKE 3/15(PowerManger) 1A

Date: Wednesday, March 08, 2017 Sheet 4 of 51


5 4 3 2 1
5 4 3 2 1

Under CPU
<7,43>

<2,4,6,9,42>
<6>
+VCC_CORE
<2,4,37,42,43> +1.0V
+VCCSTG
+VCCSTPLL
+VCC_CORE
U1L SKL_ULT ? Need apply PN
CPU POWER 1 OF 4
+VCC_CORE Under CPU
05
A30 G32
A34 VCC_A30 VCC_G32 G33
A39 VCC_A34
VCC_A39
32A VCC_G33
VCC_G35
G35
A44 G37 C6 C7 C8 C11 C12 C13 C15
C4 C9 C10 C5 C14 C16 C17 C18 AK33 VCC_A44 VCC_G37 G38 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
10U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 47U/6.3VS_8 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 AK35 VCC_AK33 VCC_G38 G40
D AK37 VCC_AK35 VCC_G40 G42 D
AK38 VCC_AK37 VCC_G42 J30
AK40 VCC_AK38 VCC_J30 J33
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 C26 C27 C28 C29 C30 C31 C32 C33
C19 C20 C21 C22 C23 C24 C25 AM32 VCC_AL40 VCC_K33 K35 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
10U/6.3V_6 10U/6.3V_4 10U/6.3V_4 10U/6.3V_4 10U/6.3V_4 10U/6.3V_6 10U/6.3V_4 AM33 VCC_AM32 VCC_K35 K37
AM35 VCC_AM33 VCC_K37 K38
AM37 VCC_AM35 VCC_K38 K40
AM38 VCC_AM37 VCC_K40 K42
VCC_AM38 VCC_K42
G30
VCC_G30 VCC_K43
K43 R55 *100/F_4 +VCC_CORE Close CPU
K32 E32
RSVD_K32 VCC_SENSE VCC_SENSE <43>
C34 C35 C36 C37 C38 C39 E33
22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 AK32 VSS_SENSE VSS_SENSE <43> 100- ±1%
RSVD_AK32 B63 H_CPU_SVIDALRT# R56 *100/F_4 pull-up to VCC
AB62 VIDALERT# A63 VR_SVID_CLK_R near processor.
P62 VCCOPC_AB62 VIDSCK D64 H_CPU_SVIDDAT
V62 VCCOPC_P62
VCCOPC_V62
3.2A VIDSOUT
G20
VCCSTG_G20 +VCCSTG
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
50mA
AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE
AE62
AG62 VCCEOPIO_AE62
VCCEOPIO_AG62
2A
C C
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE BOM
U
Layout note: need routing together and ALERT need between CLK and DATA.
*SKL_ULT ?
12 OF 20
REV = 1

Close CPU +VCCSTPLL

+VCC_CORE R57
CLOSE TO CPU
56.2/F_4
PLACE THE PU RESISTORS
SVID ALERT
H_CPU_SVIDALRT# R58 220/F_4 VR_SVID_ALERT# <43>
C40 C41 C42 C43 C44 C45 C46 C47
47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8

C48
*0.1U/16V_4
+VCC_CORE

C49 C50 C51 C52 C53 C54 C55 C56 +VCCSTPLL


10U/6.3V_4 10U/6.3V_4 10U/6.3V_6 10U/6.3V_4 10U/6.3V_4 10U/6.3V_4 10U/6.3V_4 10U/6.3V_6
B B

PLACE THE PU RESISTORS R59


*54.9/F_4
CLOSE TO VR
PULL UP IS IN THE VR MODULE
SVID CLK
VR_SVID_CLK_R R60 *0_4/S VR_SVID_CLK <43>

+VCCSTPLL

R61
100/F_4
CLOSE TO CPU
PLACE THE PU RESISTORS
SVID DATA
H_CPU_SVIDDAT R62 *0_4/S VR_SVID_DATA <43>

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 05 -- SKYLAKE 4/15 (POWER-1) 1A

Date: Wednesday, March 08, 2017 Sheet 5 of 51


5 4 3 2 1
5 4 3 2 1

06
+VCCSTPLL <2,4,5,9,42>
+VCCSA <43,44>
+1.2VSUS <3,17,18,40,42>
+1.0V_DEEP_SUS <9,13,15,41,42>
+1.0V <2,4,37,42,43>
+3VPCU <13,31,33,36,37,38,39>

Under CPU Need apply PN +VCCIO


+1.2VSUS ?
U1N SKL_ULT

CPU POWER 3 OF 4 Under CPU Close CPU


AU23 AK28
VDDQ_AU23
AU28
VDDQ_AU28 2.8A 3.1A VCCIO1
VCCIO2
AK30
D AU35 AL30 D
C60 C61 C62 C57 C58 C59 AU42 VDDQ_AU35 VCCIO3 AL42 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72
10U/6.3V_6 10U/6.3V_6 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 BB23 VDDQ_AU42 VCCIO4 AM28 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_4 10U/6.3V_4 10U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
BB32 VDDQ_BB23 VCCIO5 AM30
BB41 VDDQ_BB32 VCCIO6 AM42
BB47 VDDQ_BB41 VCCIO7 +VCCSA
VDDQ_BB47
BB51
VDDQ_BB51
AK23 Under CPU
5.1AVCCSA1
VCCSA2
AK25
G23
AM40 VCCSA3 G25
C73 C74 C75 C76 VDDQC VCCSA4 G27 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90
A18 VCCSA5
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 +VCCSTPLL VCCST 60mA VCCSA6
G28 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_4 10U/6.3V_6 10U/6.3V_4 10U/6.3V_6 10U/6.3V_4 10U/6.3V_6 10U/6.3V_6
C91 C92 J22
A22 VCCSA7
VCCSTG_A2220mA
*10U/6.3V_4 1U/6.3V_4 J23
+VCCSTG VCCSA8
Close CPU VCCSA9
J27
+VCCPLL_OC
AL23
VCCPLL_OC 120mA VCCSA10
K23 Close CPU
K25
K20 VCCSA11 K27 C93 C94 C95 C96 C97 C98
VCCPLL_K20 VCCSA12
Close CPU Under CPU +VCCPLL
K21
VCCPLL_K21130mA VCCSA13
K28 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_4 10U/6.3V_4
+VCCSTPLL +VCCSTG K30
VCCSA14 +VCCIO
R63 *0_4/S AM23 VCCIO_VCCSENSE
VCCIO_SENSE AM22 VCCIO_VSSSENSE
VSSIO_SENSE
H21
VSSSA_SENSE VSSSA_SENSE <43> VCCIO_VCCSENSE
H20 R66 100/F_4
VCCSA_SENSE VCCSA_SENSE <43>
+1.2V_VCCPLL_OC +VCCPLL_OC
14 OF 20 VCCIO_VSSSENSE R67 100/F_4
*SKL_ULT ?
R69 *0_6/S
C REV = 1 C

+VCCSTPLL +VCCPLL
IO Thrm Protect
R70 *0_6/S

Under CPU
+3VPCU +3VPCU

+VCCSTG +VCCPLL_OC

R71 R73
C99 C100 20K/F_4 20K/F_4
1U/6.3V_4 1U/6.3V_4
For 75 degree, 1.2v limit, (HW) For 75 degree, 1.2v limit, (HW)
THERMISTOR <37> THERMISTOR_SHDN <37>

Close A18 Ball THER_CPU THER_PIPE

+VCCSTPLL TM1 C101 TM0 C103

B
PV 100K_4 NTC 0.1U/16V_4
PV
100K_4 NTC 0.1U/16V_4

C104 C105
*1U/6.3V_4 *22U/6.3V_6

Close CPU

+VCCSTPLL +VCCPLL

C106 C107
1U/6.3V_4 1U/6.3V_4

+1.2VSUS

A A

C108 C109 C110 C111 C112 C113 C114 C115 C116 C117
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4

PROJECT : 0P1B
Quanta Computer Inc.
Close to CPU Size Document Number Rev
Custom
NB5 06 -- SKYLAKE 5/15 (POWER-2) 1A

Date: Wednesday, March 08, 2017 Sheet 6 of 51


5 4 3 2 1
5 4 3 2 1

+VCCGT
+VCC_CORE
+1.2VSUS
<43>
<5,43>
<3,6,17,18,40,42>

U1M SKL_ULT ? Need apply PN +VCCGT


07
CPU POWER 2 OF 4 Close CPU
N70
+VCCGT_+VCORE A48 VCCGT56 N71
Under CPU A53 VCCGT1 VCCGT57 R63
+VCCGT A58 VCCGT2
VCCGT3
57A VCCGT58
VCCGT59
R64 C122 C123 C124 C125 C126 C127
A62 R65 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8 47U/6.3VS_8
D A66 VCCGT4 VCCGT60 R66 D
AA63 VCCGT5 VCCGT61 R67
AA64 VCCGT6 VCCGT62 R68
AA66 VCCGT7 VCCGT63 R69
C119 C120 C121 C118 C128 AA67 VCCGT8 VCCGT64 R70
10U/6.3V_6 10U/6.3V_4 10U/6.3V_6 10U/6.3V_4 10U/6.3V_6 AA69 VCCGT9 VCCGT65 R71
AA70 VCCGT10 VCCGT66 T62
AA71 VCCGT11 VCCGT67 U65 C129 C132 C133 C134 C135 C136 C140 C141
AC64 VCCGT12 VCCGT68 U68 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6
AC65 VCCGT13 VCCGT69 U71
AC66 VCCGT14 VCCGT70 W 63
AC67 VCCGT15 VCCGT71 W 64
AC68 VCCGT16 VCCGT72 W 65
C130 C131 C137 C138 C139 AC69 VCCGT17 VCCGT73 W 66
10U/6.3V_4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_4 AC70 VCCGT18 VCCGT74 W 67
AC71 VCCGT19 VCCGT75 W 68
J43 VCCGT20 VCCGT76 W 69 C142 C143 C144 C145
J45 VCCGT21 VCCGT77 W 70 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6
+VCC_CORE J46 VCCGT22 VCCGT78 W 71
+VCCGT_+VCORE J48 VCCGT23 VCCGT79 Y62
+VCCGT J50 VCCGT24 VCCGT80
R998 *0.0002_8 +VCCGT_+VCORE J52 VCCGT25
J53 VCCGT26 AK42 +VCCGTX_+VCORE
VCCGT27 VCCGTX_AK42
For R-U42 不不 J55
J56 VCCGT28
VCCGT29
7A VCCGTX_AK43
VCCGTX_AK45
AK43
AK45
J58 AK46
+VCCGT J60 VCCGT30 VCCGTX_AK46 AK48 C303 C304
+VCCGT +VCCGT_+VCORE K48 VCCGT31 VCCGTX_AK48 AK50 *22U/6.3V_6 *22U/6.3V_6
K50 VCCGT32 VCCGTX_AK50 AK52 AK52 1 *
+VCCGT_+VCORE K52 VCCGT33 VCCGTX_AK52 AK53 TP842
R995 0.0002_8 R992 0_4
C K53 VCCGT34 VCCGTX_AK53 AK55 C
VCCGT35 VCCGTX_AK55 +VCC_CORE
For U22 不不 +VCCGT
K55
K56 VCCGT36
VCCGT37
VCCGTX_AK56
VCCGTX_AK58
AK56
AK58
K58 AK60 +VCCGTX_+VCORE +VCCGTX_+VCORE R994 *0.0002_8
K60 VCCGT38 VCCGTX_AK60 AK70
Pin K52 NC on KBL- R BOM. L62 VCCGT39 VCCGTX_AK70 AL43
L63 VCCGT40 VCCGTX_AL43 AL46 C302
L64 VCCGT41 VCCGTX_AL46 AL50 *22U/6.3V_6
C146 C147 C148 C149 C150 C151 L65 VCCGT42 VCCGTX_AL50 AL53
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 L66 VCCGT43 VCCGTX_AL53 AL56
L67 VCCGT44 VCCGTX_AL56 AL60
L68 VCCGT45 VCCGTX_AL60 AM48 +VCCGTX_+VCORE
L69 VCCGT46 VCCGTX_AM48 AM50
L70 VCCGT47 VCCGTX_AM50 AM52
L71
M62
VCCGT48
VCCGT49
VCCGTX_AM52
VCCGTX_AM53
AM53
AM56
C300
*22U/6.3V_6
C301
*22U/6.3V_6
1.U22--->R994 不不不
N63 VCCGT50 VCCGTX_AM56 AM58
C152
1U/6.3V_4
C153
1U/6.3V_4
C154
1U/6.3V_4
C155
1U/6.3V_4
C156
1U/6.3V_4
C157
1U/6.3V_4 N64
N66
VCCGT51
VCCGT52
VCCGTX_AM58
VCCGTX_AU58
AU58
AU63
2.U42--->R994 不不
N67 VCCGT53 VCCGTX_AU63 BB57
N69 VCCGT54 VCCGTX_BB57 BB66
VCCGT55 VCCGTX_BB66
J70 AK62
<43> VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
J69 AL61
<43> VSSGT_SENSE VSSGT_SENSE
BOM
VSSGTX_SENSE
1.U22---C300/C301/C302/C303/C304 不不不
*SKL_ULT
REV = 1
13 OF 20
? 2.U42---C300/C301/C302/C303/C304 不不
B B

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 07 -- SKYLAKE 6/15 (POWER-3) 1A

Date: Wednesday, March 08, 2017 Sheet 7 of 51


5 4 3 2 1
5 4 3 2 1

08
U1R U1P U1Q
?
Need apply PN Need apply PN Need apply PN
SKL_ULT SKL_ULT ? SKL_ULT ?
D D
GND 3 OF 3 GND 1 OF 3 GND 2 OF 3

F8
VSS_F8 L18 A5 AL65 AT63 BA49
G10 VSS_L18 VSS_A5 VSS_AL65 VSS_AT63 VSS_BA49
VSS_G10 L2 A67 AL66 AT68 BA53
G22 VSS_L2 VSS_A67 VSS_AL66 VSS_AT68 VSS_BA53
VSS_G22 L20 A70 AM13 AT71 BA57
G43 VSS_L20 VSS_A70 VSS_AM13 VSS_AT71 VSS_BA57
VSS_G43 L4 AA2 AM21 AU10 BA6
G45 VSS_L4 VSS_AA2 VSS_AM21 VSS_AU10 VSS_BA6
VSS_G45 L8 AA4 AM25 AU15 BA62
G48 VSS_L8 VSS_AA4 VSS_AM25 VSS_AU15 VSS_BA62
VSS_G48 N10 AA65 AM27 AU20 BA66
G5 VSS_N10 VSS_AA65 VSS_AM27 VSS_AU20 VSS_BA66
VSS_G5 N13 AA68 AM43 AU32 BA71
G52 VSS_N13 VSS_AA68 VSS_AM43 VSS_AU32 VSS_BA71
VSS_G52 N19 AB15 AM45 AU38 BB18
G55 VSS_N19 VSS_AB15 VSS_AM45 VSS_AU38 VSS_BB18
VSS_G55 N21 AB16 AM46 AV1 BB26
G58 VSS_N21 VSS_AB16 VSS_AM46 VSS_AV1 VSS_BB26
VSS_G58 N6 AB18 AM55 AV68 BB30
G6 VSS_N6 VSS_AB18 VSS_AM55 VSS_AV68 VSS_BB30
VSS_G6 N65 AB21 AM60 AV69 BB34
G60 VSS_N65 VSS_AB21 VSS_AM66 VSS_AV69 VSS_BB34
VSS_G60 N68 AB8 AM61 AV70 BB38
G63 VSS_N68 VSS_AB8 VSS_AM61 VSS_AV70 VSS_BB38
VSS_G63 P17 AD13 AM68 AV71 BB43
G66 VSS_P17 VSS_AD13 VSS_AM68 VSS_AV71 VSS_BB43
VSS_G66 P19 AD16 AM71 AW 10 BB55
H15 VSS_P19 VSS_AD16 VSS_AM71 VSS_AW 10 VSS_BB55
VSS_H15 P20 AD19 AM8 AW 12 BB6
H18 VSS_P20 VSS_AD19 VSS_AM8 VSS_AW 12 VSS_BB6
VSS_H18 P21 AD20 AN20 AW 14 BB60
H71 VSS_P21 VSS_AD20 VSS_AN20 VSS_AW 14 VSS_BB60
VSS_H71 R13 AD21 AN23 AW 16 BB64
J11 VSS_R13 VSS_AD21 VSS_AN23 VSS_AW 16 VSS_BB64
VSS_J11 R6 AD62 AN28 AW 18 BB67
J13 VSS_R6 VSS_AD62 VSS_AN28 VSS_AW 18 VSS_BB67
VSS_J13 T15 AD8 AN30 AW 21 BB70
J25 VSS_T15 VSS_AD8 VSS_AN30 VSS_AW 21 VSSBB70
VSS_J25 T17 AE64 AN32 AW 23 C1
J28 VSS_T17 VSS_AE64 VSS_AN32 VSS_AW 23 VSS_C1
VSS_J28 T18 AE65 AN33 AW 26 C25
J32 VSS_T18 VSS_AE65 VSS_AN33 VSS_AW 26 VSS_C25
VSS_J32 T2 AE66 AN35 AW 28 C5
J35 VSS_T2 VSS_AE66 VSS_AN35 VSS_AW 28 VSS_C5
VSS_J35 T21 AE67 AN37 AW 30 D10
J38 VSS_T21 VSS_AE67 VSS_AN37 VSS_AW 30 VSS_D10
VSS_J38 T4 AE68 AN38 AW 32 D11
J42 VSS_T4 VSS_AE68 VSS_AN38 VSS_AW 32 VSS_D11
VSS_J42 U10 AE69 AN40 AW 34 D14
J8 VSS_U10 VSS_AE69 VSS_AN40 VSS_AW 34 VSS_D14
VSS_J8 U63 AF1 AN42 AW 36 D18
K16 VSS_U63 VSS_AF1 VSS_AN42 VSS_AW 36 VSS_D18
VSS_K16 U64 AF10 AN58 AW 38 D22
K18 VSS_U64 VSS_AF10 VSS_AN58 VSS_AW 38 VSS_D22
C VSS_K18 U66 AF15 AN63 AW 41 D25 C
K22 VSS_U66 VSS_AF15 VSS_AN63 VSS_AW 41 VSS_D25
VSS_K22 U67 AF17 AP10 AW 43 D26
K61 VSS_U67 VSS_AF17 VSS_AP10 VSS_AW 43 VSS_D26
VSS_K61 U69 AF2 AP18 AW 45 D30
K63 VSS_U69 VSS_AF2 VSS_AP18 VSS_AW 45 VSS_D30
VSS_K63 U70 AF4 AP20 AW 47 D34
K64 VSS_U70 VSS_AF4 VSS_AP20 VSS_AW 47 VSS_D34
VSS_K64 V16 AF63 AP23 AW 49 D39
K65 VSS_V16 VSS_AF63 VSS_AP23 VSS_AW 49 VSS_D39
VSS_K65 V17 AG16 AP28 AW 51 D44
K66 VSS_V17 VSS_AG16 VSS_AP28 VSS_AW 51 VSS_D44
VSS_K66 V18 AG17 AP32 AW 53 D45
K67 VSS_V18 VSS_AG17 VSS_AP32 VSS_AW 53 VSS_D45
VSS_K67 W 13 AG18 AP35 AW 55 D47
K68 VSS_W 13 VSS_AG18 VSS_AP35 VSS_AW 55 VSS_D47
VSS_K68 W6 AG19 AP38 AW 57 D48
K70 VSS_W 6 VSS_AG19 VSS_AP38 VSS_AW 57 VSS_D48
VSS_K70 W9 AG20 AP42 AW 6 D53
K71 VSS_W 9 VSS_AG20 VSS_AP42 VSS_AW 6 VSS_D53
VSS_K71 Y17 AG21 AP58 AW 60 D58
L11 VSS_Y17 VSS_AG21 VSS_AP58 VSS_AW 60 VSS_D58
VSS_L11 Y19 AG71 AP63 AW 62 D6
L16 VSS_Y19 VSS_AG71 VSS_AP63 VSS_AW 62 VSS_D6
VSS_L16 Y20 AH13 AP68 AW 64 D62
L17 VSS_Y20 VSS_AH13 VSS_AP68 VSS_AW 64 VSS_D62
VSS_L17 Y21 AH6 AP70 AW 66 D66
VSS_Y21 AH63 VSS_AH6 VSS_AP70 AR11 AW 8 VSS_AW 66 VSS_D66 D69
AH64 VSS_AH63 VSS_AR11 AR15 AY66 VSS_AW 8 VSS_D69 E11
AH67 VSS_AH64 VSS_AR15 AR16 B10 VSS_AY66 VSS_E11 E15
18 OF 20 AJ15 VSS_AH67 VSS_AR16 AR20 B14 VSS_B10 VSS_E15 E18
*SKL_ULT VSS_AJ15 VSS_AR20 VSS_B14 VSS_E18
REV = 1 ? AJ18 AR23 B18 E21
AJ20 VSS_AJ18 VSSAR23 AR28 B22 VSS_B18 VSS_E21 E46
AJ4 VSS_AJ20 VSS_AR28 AR35 B30 VSS_B22 VSS_E46 E50
AK11 VSS_AJ4 VSS_AR35 AR42 B34 VSS_B30 VSS_E50 E53
AK16 VSS_AK11 VSS_AR42 AR43 B39 VSS_B34 VSS_E53 E56
AK18 VSS_AK16 VSS_AR43 AR45 B44 VSS_B39 VSS_E56 E6
AK21 VSS_AK18 VSS_AR45 AR46 B48 VSS_B44 VSS_E6 E65
AK22 VSS_AK21 VSS_AR46 AR48 B53 VSS_B48 VSS_E65 E71
AK27 VSS_AK22 VSS_AR48 AR5 B58 VSS_B53 VSS_E71 F1
AK63 VSS_AK27 VSS_AR5 AR50 B62 VSS_B58 VSS_F1 F13
AK68 VSS_AK63 VSS_AR50 AR52 B66 VSS_B62 VSS_F13 F2
AK69 VSS_AK68 VSS_AR52 AR53 B71 VSS_B66 VSS_F2 F22
B AK8 VSS_AK69 VSS_AR53 AR55 BA1 VSS_B71 VSS_F22 F23 B
AL2 VSS_AK8 VSS_AR55 AR58 BA10 VSS_BA1 VSS_F23 F27
AL28 VSS_AL2 VSS_AR58 AR63 BA14 VSS_BA10 VSS_F27 F28
AL32 VSS_AL28 VSS_AR63 AR8 BA18 VSS_BA14 VSS_F28 F32
AL35 VSS_AL32 VSS_AR8 AT2 BA2 VSS_BA18 VSS_F32 F33
AL38 VSS_AL35 VSS_AT2 AT20 BA23 VSS_BA2 VSS_F33 F35
AL4 VSS_AL38 VSS_AT20 AT23 BA28 VSS_BA23 VSS_F35 F37
AL45 VSS_AL4 VSS_AT23 AT28 BA32 VSS_BA28 VSS_F37 F38
AL48 VSS_AL45 VSS_AT28 AT35 BA36 VSS_BA32 VSS_F38 F4
AL52 VSS_AL48 VSS_AT35 AT4 F68 VSS_BA36 VSS_F4 F40
AL55 VSS_AL52 VSS_AT4 AT42 BA45 VSS_F68 VSS_F40 F42
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA45 VSS_F42 BA41
AL64 VSS_AL58 VSS_AT56 AT58 VSS_BA41
VSS_AL64 VSS_AT58
17 OF 20
BOM
16 OF 20
*SKL_ULT *SKL_ULT
REV = 1 ? REV = 1 ?

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 08 -- SKYLAKE 7/15 (GND) 1A

Date: Wednesday, March 08, 2017 Sheet 8 of 51


5 4 3 2 1
5 4 3 2 1

?
09
U1S
SKL_ULT
Need apply PN
RESERVED SIGNALS-1

E68 BB68
D B67 CFG[0] RSVD_TP_BB68 BB69 D
*TP504 1 CFG2 D65 CFG[1] RSVD_TP_BB69
*TP505 1 CFG3 D67 CFG[2] AK13
*TP109 1 CFG4 E70 CFG[3] RSVD_TP_AK13 AK12
*TP110 1 CFG5 C68 CFG[4] RSVD_TP_AK12 Need apply PN
*TP111 1 CFG6 D68 CFG[5] BB2 U1T SKL_ULT ?
*TP112 1 CFG7 C67 CFG[6] RSVD_BB2 BA3
F71 CFG[7] RSVD_BA3
SPARE
G69 CFG[8]
F70 CFG[9] AU5 AW 69 F6
G68 CFG[10] TP5 AT5 AW 68 RSVD_AW 69 RSVD_F6 E3 XTAL24_IN_E3
H70 CFG[11] TP6 AU56 RSVD_AW 68 RSVD_E3 C11
G71 CFG[12] +1.8V_DEEP_SUS AW 48 RSVD_AU56 RSVD_C11 B11
H69 CFG[13] D5 XTAL24_OUT_C7 C7 RSVD_AW 48 RSVD_B11 A11
G70 CFG[14] RSVD_D5 D4 R77 *0_4 U12 RSVD_C7 RSVD_A11 D12
CFG[15] RSVD_D4 B2 U11 RSVD_U12 RSVD_D12 C12
E63 RSVD_B2 C2 H11 RSVD_U11 RSVD_C12 F52
F63 CFG[16] RSVD_C2 C158 RSVD_H11 RSVD_F52
CFG[17] B3 *1U/6.3V_4
E66 RSVD_B3 A3
CFG[18] RSVD_A3 20 OF 20
F66
CFG[19] AW 1 *SKL_ULT
REV = 1 ?
+1.0V_DEEP_SUS CFG_RCOMP E60 RSVD_AW 1
R78 49.9/F_4
CFG_RCOMP Close to CPU
E1
R79 *1K_4 E8 RSVD_E1 E2
within 100mil
ITP_PMODE RSVD_E2
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
RSVD_AY1 RSVD_BB4
D1 A4
C D3 RSVD_D1 RSVD_A4 C4 C
RSVD_D3 RSVD_C4 C444 *27P/50V_4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45

1
2
A69 R555
AL25 RSVD_A69 B69 XTAL24_IN_E3 R9050 *0_4 XTAL24_IN_E3_R Y11
AL27 RSVD_AL25 RSVD_B69 *1M_4
RSVD_AL27 *24MHZ/20ppm
AY3 R80 0_4 XTAL24_OUT_C7R9051 *0_4 XTAL24_OUT_C7_R
C71 RSVD_AY3

3
4
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70 C555 *27P/50V_4
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70
RSVD_TP_BA68
TP1
TP2
BB3 For KBL R U42
J71
J68 RSVD_J71 VSS_AY71
AY71
AR56
R81 0_4 (i)Non-stuff on KBL-U
MV RSVD_J68 ZVM#
R9064 *0_4 F65 AW 71
G65 VSS_F65 RSVD_TP_AW 71 AW 70
VSS_G65 RSVD_TP_AW 70
F61 AP56
E61 RSVD_F61 MSM# C64 R82 *100K_4
RSVD_E61 PROC_SELECT# +VCCSTPLL

BOM 19 OF 20
B *SKL_ULT B
REV = 1 ?

Processor Strapping The CFG signals have a default value of '1' if not terminated on the board.
1 0 Circuit
CFG3 CFG3
Disable: Enable: Set DFX Enable in DFX interface MSR R83 *1K_4
(Physcial Debug Enable)
DFX Privacy
CFG4 CFG4
Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP R84 1K_4
(DP Presence Strap)

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 09 -- SKYLAKE 8/15 (RSV) 1A

Date: Wednesday, March 08, 2017 Sheet 9 of 51


5 4 3 2 1
5 4 3 2 1

+3V_DEEP_SUS
+3V
+5V
+1.0V
+3VS5
<4,11,12,14,15,18>
<2,4,11,12,13,14,15,17,18,26,27,28,29,30,31,33,34,35,37,43,45>
<26,27,28,29,33,35,36,45>
<2,4,37,42,43>
<4,15,31,36,37,39,40,41,42,45,46,49>
10
?
U1E
SKL_ULT
Need apply PN
SPI - FLASH
SMBUS, SMLINK
PCH_SPI1_CLK AV2 R7 SMB_PCH_CLK
D SPI0_CLK GPP_C0/SMBCLK D
PCH_SPI1_SO AW3 R8 SMB_PCH_DAT
PCH_SPI1_SI AV3 SPI0_MISO GPP_C1/SMBDATA R10 SML0ALERT#
PCH_SPI_IO2 SPI0_MOSI GPP_C2/SMBALERT# SML0ALERT# <11>
AW2
PCH_SPI_IO3 AU4 SPI0_IO2 R9 SMB_ME0_CLK
PCH_SPI_CS0# AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SMB_ME0_DAT
AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML1ALERT#
SPI0_CS1# GPP_C5/SML0ALERT# SML1ALERT# <11>
AU1
SPI0_CS2# W3 SMB_ME1_CLK
GPP_C6/SML1CLK V3 SMB_ME1_DAT
SPI - TOUCH GPP_C7/SML1DATA AM7
M2 GPP_B23/SML1ALERT#/PCHHOT#
SIO_EXT_SMI# M3 GPP_D1/SPI1_CLK
<37> SIO_EXT_SMI# GPP_D2/SPI1_MISO
PCI_SERR# J4
<37> PCI_SERR#
V1 GPP_D3/SPI1_MOSI 5
V2 GPP_D21/SPI1_IO2
M1 GPP_D22/SPI1_IO3 AY13
LPC LAD0 <34,36,37>
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 BA13
GPP_A2/LAD1/ESPI_IO1 LAD1 <34,36,37>
BB13 LAD2 <34,36,37>
C LINK GPP_A3/LAD2/ESPI_IO2 AY12
GPP_A4/LAD3/ESPI_IO3 LAD3 <34,36,37>
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# LFRAME# <34,36,37>
G2 BA11 EC2 18P/50V_4
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
CL_RST#
AW9 CLK_PCI_EC_R R85 22/F_4 CLK_24M_KBC <37>
AW13 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 CLK_PCI_LPC_R R86 22/F_4
<37> EC_RCIN# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 CLK_24M_DEBUG <36>
AW11CLKRUN# CLKRUN# <37>
AY11 GPP_A8/CLKRUN#
<34,37> SERIRQ GPP_A6/SERIRQ PDC EMI(near PCH)
EC3 18P/50V_4
5 OF 20
*SKL_ULT CLK_PCI_TPM <34>
REV = 1 R87 *0/F_4
?

EC4 EMI(near PCH)


C *18P/50V_4 C

GPIO Pull UP PCH SPI ROM(CLG)

Vender Size P/N


EON 8MB AKE3EZN0Q01 (EN25QH64-104HIP)
+3V +3V_DEEP_SUS
Winbond 8MB AKE3EFP0N07 (W25Q64FVSSIQ)
GigaDevice 8MB AKE3EGN0Q01 (GD25B64BSIGR)
SERIRQ R88 10K_4 SMB_PCH_CLK R89 2.2K_4 Socket DFHS08FS023
CLKRUN# R90 8.2K/F_4 SMB_PCH_DAT R91 2.2K_4

SIO_EXT_SMI# R92 10K_4 SMB_ME0_CLK R93 499/F_4


PCH_SPI_CS0#_R
<37> PCH_SPI_CS0#_R
EC_RCIN# SMB_ME0_DAT PCH_SPI1_CLK_R
R94 10K_4 R95 499/F_4 <37> PCH_SPI1_CLK_R
PCH_SPI1_SI_R need place to TOP
PCI_SERR# SMB_ME1_CLK <37> PCH_SPI1_SI_R PCH_SPI1_SO_R
R96 10K_4 R97 1K_4 <37> PCH_SPI1_SO_R
* 1 PCH_SPI_CS0#_R
SMB_ME1_DAT TP17 PCH_SPI1_CLK_R
R98 1K_4 * 1
TP18 PCH_SPI1_SI_R
* 1
TP19 PCH_SPI1_SO_R
* 1
TP20 BIOS_WP#
B * 1 B
TP21
* 1 HOLD#
TP22

PCH SPI ROM(CLG)


+3VSPI

SI +3V_DEEP_SUS R101 *0_4/S

U3
SMBus/Pull-up(CLG) PCH_SPI_CS0#
PCH_SPI1_CLK
PCH_SPI1_SI
R102
R103
R104
15/F_4
15/F_4
15/F_4
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
1
6
5
CE#
SCK
VDD
8 +3VSPI

R105 1K_4
PCH_SPI1_SO R106 15/F_4 PCH_SPI1_SO_R 2 SI 7HOLD#
SO HOLD# R107 15/F_4
+3V 3 4
C159 WP# VSS
22P/50V_4 W25Q64FVSSIQ C160
5

AKE3EFP0N07 0.1U/16V_4

4 3 SMB_ME1_CLK C161 1U/6.3V_4 +3VSPI R108 1K_4


<18,26,37> MBCLK2 CPU heat pipe local thermal sensor
Q3A *2N7002KDW DDR thermal sensor PCH_SPI_IO2 R109 15/F_4 BIOS_WP# PCH_SPI_IO3
EC
2

1 6 SMB_ME1_DAT
<18,26,37> MBDATA2
Q3B *2N7002KDW
A A
+3V
5

+3V R110 4.7K_4

4 3 SMB_PCH_DAT
<17,18,26,33> SMB_RUN_DAT Touch Pad
Q4A 2N7002KDW XDP
DDR4 PROJECT : 0P1B
2

R111 4.7K_4
Quanta Computer Inc.
+3V
1 6 SMB_PCH_CLK
<17,18,26,33> SMB_RUN_CLK
Q4B 2N7002KDW Size Document Number Rev
Custom
NB5 10 -- SKYLAKE 09/15(SPI/LPC/SM) 1A

Date: Wednesday, March 08, 2017 Sheet 10 of 51


5 4 3 2 1
5 4 3 2 1

11
D
Functional Strap Definitions D

DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
+3V_DEEP_SUS

ACZ_SPKR
<14,28> ACZ_SPKR
No Boot:
TOP SWAP OVERRIDE R113 The signal has a weak internal pull-down.
R112 HIGH - TOP SWAP ENABLE *4.7K_4 0 = Enable security measures defined in the Flash
*20K/F_4 LOW-DISABLED Descriptor.
HIGH: LPC SELECTED FOR SYSTEM FLASH 1 = Disable Flash Descriptor Security (override). This
WEAK INTERNAL PD ACZ_SDOUT strap should only be asserted high using external
<14> ACZ_SDOUT
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.

R114 1K_4 ACZ_SDOUT


C <37> GPIO33_EC C

+3V_DEEP_SUS +3V

R115 R116
1K_4 No Boot: *4.7K_4
The signal has a weak internal pull-down. No Boot:
0 = Disable Intel ME Crypto Transport Layer Security The signal has a weak internal pull-down.
<10> SML0ALERT#
SML0ALERT# (TLS) cipher suite (no confidentiality). <14> GPP_B18
GPP_B18 0 = Disable No Reboot mode.
1 = Enable Intel ME Crypto Transport Layer Security 1 = Enable No Reboot mode
R117 (TLS) cipher suite (with confidentiality). Must be R118
(PCH will disable the TCO
*20K/F_4 pulled up to support Intel AMT with TLS and Intel 10K_4 Timer system reboot feature).
SBA (Small Business Advantage) with TLS. This function is useful when running ITP/XDP.

+3V_DEEP_SUS

B B

R119

GSPI1_MOSI
No Boot: *10K_4
<14> GSPI1_MOSI The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS No Boot:
R120
*20K/F_4
Destination bit (Chipset Configuration Registers: Offset <10> SML1ALERT#
SML1ALERT#
The signal has a weak internal pull-down.
3410h:Bit 10). This strap is used in conjunction with Boot 0 = LPC Is selected for EC.
BIOS Destination Selection 0 strap. 1 = eSPI Is selected for EC.
Bit 10 Boot BIOS Destination R121
20K/F_4
0 SPI
1 LPC

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 11 -- SKYLAKE 10/15(HDA) 1A

Date: Wednesday, March 08, 2017 Sheet 11 of 51


5 4 3 2 1
5 4 3 2 1

+3V
+3VS5
<2,4,10,11,13,14,15,17,18,26,27,28,29,30,31,33,34,35,37,43,45>
<4,15,31,36,37,39,40,41,42,45,46,49>
+3V_DEEP_SUS <4,10,11,14,15,18> U1H

PCIE/USB3/SATA
SKL_ULT
?
Need apply PN
SSIC / USB3
H8 USB30_RX1-
12
USB3_1_RXN G8 USB30_RX1+ USB30_RX1- <31>

<19> PEG_RXN0
H13 USB3_1_RXP C13 USB30_TX1- USB30_RX1+ <31>USB3.0
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB30_TX1+ USB30_TX1- <31>
<19> PEG_RXP0 PEG_TXN0_C B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX1+ <31>
<19> PEG_TXN0 C162 0.22U/10V_4
C163 0.22U/10V_4 PEG_TXP0_C A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX2-
<19> PEG_TXP0 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX2+ USB30_RX2- <31>
H6
D G11 USB3_2_RXP/SSIC_1_RXP B13 USB30_TX2- USB30_RX2+ <31> D
<19>
<19>
PEG_RXN1
PEG_RXP1
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB30_TX2+ USB30_TX2- <31> USB3.0
PEG_TXN1_C D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB30_TX2+ <31>
<19> PEG_TXN1 C168 0.22U/10V_4
C169 0.22U/10V_4 PEG_TXP1_C C16 PCIE2_TXN/USB3_6_TXN J10 USB30_RX3-
<19> PEG_TXP1 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB30_RX3+ USB30_RX3- <32>
H10
dGPU H16 USB3_3_RXP/SSIC_2_RXP B15 USB30_TX3- USB30_RX3+ <32>
<19>
<19>
PEG_RXN2
PEG_RXP2
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB30_TX3+ USB30_TX3- <32> USB3.0 to SATA
PEG_TXN2_C D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB30_TX3+ <32>
<19> PEG_TXN2 C164 0.22U/10V_4
C165 0.22U/10V_4 PEG_TXP2_C C17 PCIE3_TXN E10
<19> PEG_TXP2 PCIE3_TXP USB3_4_RXN +3V
F10
G15 USB3_4_RXP C15
<19> PEG_RXN3 PCIE4_RXN USB3_4_TXN
F15 D15
<19> PEG_RXP3 PEG_TXN3_C B19 PCIE4_RXP USB3_4_TXP
<19> PEG_TXN3 C167 0.22U/10V_4
C166 0.22U/10V_4 PEG_TXP3_C A19 PCIE4_TXN AB9 USBP1- R970 *100K_4 GPU_EVENT# R122 *10K_5%_4
<19> PEG_TXP3 PCIE4_TXP USB2N_1 USBP1- <31>
AB10 USBP1+ USB3.0 Port
USB2P_1 USBP1+ <31> DGPU_HOLD_RST# R123
F16 *10K_4
E16 PCIE5_RXN AD6 USBP2-
PCIE5_RXP USB2N_2 USBP2- <31> DGPU_PWR_EN
C19 AD7 USBP2+ USB3.0 Port R124 *10K_4
PCIE5_TXN USB2P_2 USBP2+ <31>
D19
PCIE5_TXP AH3 USBP_CAM- DGPU_PWROK R125 *10K_4
G18 USB2N_3 AJ3 USBP_CAM+ USBP_CAM- <27>
<30> PCIE_RXN6_LAN
F18 PCIE6_RXN USB2P_3 USBP_CAM+ Camera
<27>
<30> PCIE_RXP6_LAN PCIE6_RXP
LAN <30> PCIE_TXN6_LAN C174 0.1U/16V_4 PCIE_TXN6_LAN_C D20 AD9 USBP3- USBP3- <31>
C175 0.1U/16V_4 PCIE_TXP6_LAN_C C20 PCIE6_TXN USB2N_4 AD10 USBP3+ SATA_LED# R126 10K_4
<30> PCIE_TXP6_LAN PCIE6_TXP USB2P_4 USBP3+ USB2.0
<31> Port
F20 AJ1 USBP8- GC6_FB_EN R127 *10K_4
<36> SATA_RXN1 PCIE7_RXN/SATA0_RXN USB2N_5 USBP8- <32>
E20 AJ2 USBP8+ U3 to SATA
<36> SATA_RXP1 PCIE7_RXP/SATA0_RXP USB2P_5 USBP8+ <32> ODD_PRSNT#_R
HDD/SSD B21 USB2 R128 10K_4
<36> SATA_TXN1 PCIE7_TXN/SATA0_TXN
A21 AF6 USBP6-
<36> SATA_TXP1 PCIE7_TXP/SATA0_TXP USB2N_6 USBP6- <31>
AF7 USBP6+ SD
USB2P_6 USBP6+ <31> ODD_DET
C
<35> SATA_RXN2 G21 R9063 10K_4 C
F21 PCIE8_RXN/SATA1A_RXN AH1 USBP4-
<35> SATA_RXP2 PCIE8_RXP/SATA1A_RXP USB2N_7 USBP4- <36>
ODD D21 AH2 USBP4+ BT
<35> SATA_TXN2 PCIE8_TXN/SATA1A_TXN USB2P_7 USBP4+ <36>
C21
<35> SATA_TXP2 PCIE8_TXP/SATA1A_TXP AF8 USBP7- DEVSLP0 R8561 10K_4
USB2N_8 USBP7- <27>
E22 AF9 USBP7+ Touch Screen
<36> PCIE_RXN5_WLAN PCIE9_RXN USB2P_8 USBP7+ <27>
E23
<36> PCIE_RXP5_WLAN PCIE9_RXP
0.1U/16V_4 PCIE_TXN5_WLAN_C B23 AG1
WLAN <36>
<36>
PCIE_TXN5_WLAN
PCIE_TXP5_WLAN
C172
C173 0.1U/16V_4 PCIE_TXP5_WLAN_C A23 PCIE9_TXN USB2N_9 AG2 Type C 2017/9/8 DGPU_HOLD_RST# R129 100K_4 DIS ONLY
PCIE9_TXP USB2P_9
F25 AH7
PLACE 'Ra' WITHIN 500 MILS
E25 PCIE10_RXN
PCIE10_RXP
USB2N_10
USB2P_10
AH8 Ra FROM USB2_COMP PIN WITH
D23 TRACE IMPEDANCE LESS THAN 0.5 OHMS
C23 PCIE10_TXN AB6 USB2_COMP R130 113/F_4
PCIE10_TXP USB2_COMP AG3 USB2_ID R303 1K_4
R131 100/F_4 F5 USB2_ID AG4 USB2_VBUSSENSE R304 1K_4
E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 DGPU_HOLD_RST# If OTG is not implemented on the platform,
GPP_E9/USB2_OC0# DGPU_HOLD_RST# <19>
D56
D61 PROC_PRDY# GPP_E10/USB2_OC1#
C9
D9
GPU_EVENT#
DGPU_PWR_EN
then USB2_ID and USB2_VBUSSENSE should both
+3V_DEEP_SUS
R132 10K_4 PIRQA# BB11 PROC_PREQ#
GPP_A7/PIRQA#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
B9 DGPU_PWROK DGPU_PR_EN
DGPU_PWROK
<13,46,49>
<37,46,48,49>
be connected to ground.
E28 J1 DEVSLP0
need check
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 DEVSLP0 <36>
E27 J2 GC6_FB_EN R9052 *0_4
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
DEVSLP2 DEVSLP2 <35> R9052 for BASE U
E30 PCIE11_TXP/SATA1B_TXP H2 ODD_PRSNT#_R R901 *0_4/S ZERO_ODD_DP#
<35> SATA_RXN3 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 ZERO_ODD_DP# <35>
F30 H3 R9062 *0_4/S
<35> SATA_RXP3 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 ODD_DET <35>
2nd SSD A25 G4 1
PV
<35> SATA_TXN3 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 TP8517
B25
<35> SATA_TXP3 PCIE12_TXP/SATA2_TXP SATA_LED#_R
B H1 * R134 *0_4/S SATA_LED# SATA_LED# <31>
B
GPP_E8/SATALED#
PDC
2016/9/7 *SKL_ULT REV = 1 ? 8 OF 20

For Base-U the SATA1B/SATA2 delete PCI-E Port Mapping Table USB3.0 Port Mapping Table USB2.0 Port Mapping Table
PCI-E Port Function CLK RQ Port Function
USB3.0 Function USB2.0 Function
Port1 dGPU Port0 VGA PORT-1 USB3.0 MB PORT-1 Cobime USB3.0 MB
Port2 dGPU Port1 Un-used
PORT-2 USB3.0 MB PORT-2 Cobime USB3.0 MB
PORT-3 NC PORT-3 Webcam
Port3 dGPU Port2 Un-used PORT-4 NC PORT-4 USB2.0 Small Board
Port4 dGPU Port3 WLAN 1005 Change Name from DEVSLP2 to DEVSLP0
PORT-5 USB3.0 to SATA
DEVSLP0 and GC6_FB_EN SWAP PORT-6 SD Card
Port5 Port4 LAN 1005 GPIO35 and ACC_LED# SWAP PORT-7 WLAN (BT)
Port6 LAN Port5 Un-used
PORT-8 Touch Screen
PORT-9 NC
Port7 HDD/SSD PORT-10 NC
A
Port8 ODD A

Port9 WLAN

Port10 PROJECT : 0P1B


Port11
Quanta Computer Inc.
Size Document Number Rev
Port12 2nd SSD Custom
NB5 11 -- SKYLAKE 10/15(HDA) 1A

Date: Wednesday, March 08, 2017 Sheet 12 of 51


5 4 3 2 1
5 4 3 2 1

+3V_RTC_2
+BAT_RTC
+1.8V_DEEP_SUS
+3V
<4,15>

<9,15,41,49>
<2,4,10,11,12,14,15,17,18,26,27,28,29,30,31,33,34,35,37,43,45>
13
U1J SKL_ULT ? Need apply PN
CLOCK SIGNALS

CLK_VGA_N D42
<19> CLK_GFX_N CLK_VGA_P CLKOUT_PCIE_N0
VGA C42
<19> CLK_GFX_P PCIE_CLKREQ_VGA# CLKOUT_PCIE_P0
AR10
D GPP_B5/SRCCLKREQ0# D
B42 +1.0V_DEEP_SUS
A42 CLKOUT_PCIE_N1 F43
PCIE_CLKREQ_CR# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17
C41 CLKOUT_PCIE_N2 GPD8/SUSCLK R135
PCIE_CLKREQ_SSD# AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN 2.7K/F_4
CLK_REQ/Strap Pin(CLG)
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT
CLK_PCIE_WLANN D40 XTAL24_OUT
<36> CLK_PCIE_WLANN CLK_PCIE_WLANP CLKOUT_PCIE_N3 XCLK_BIASREF XCLK_BIASREF +3V
WLAN C40 E42
<36> CLK_PCIE_WLANP PCIE_CLKREQ_WLAN# CLKOUT_PCIE_P3 XCLK_BIASREF
AT10
<36> PCIE_CLKREQ_WLAN# GPP_B8/SRCCLKREQ3# RTC_X1
AM18
CLK_PCIE_LANN B40 RTCX1 AM20 RTC_X2 R137
<30> CLK_PCIE_LANN CLK_PCIE_LANP CLKOUT_PCIE_N4 RTCX2 PCIE_CLKREQ_VGA#
LAN <30> CLK_PCIE_LANP A40 *60.4/F_4 R136 10K_4
PCIE_CLKREQ_LAN# AU8 CLKOUT_PCIE_P4 AN18 SRTC_RST#
<30> PCIE_CLKREQ_LAN# GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST#
AM16
E40 RTCRST# PCIE_CLKREQ_WLAN# R138 10K_4
E38 CLKOUT_PCIE_N5
PCIE_CLKREQ5# AU7 CLKOUT_PCIE_P5 PCIE_CLKREQ_LAN#
1005 SWAP CLK RQ Port GPP_B10/SRCCLKREQ5# TBT R139 10K_4

PCIE_CLKREQ_CR# R140 10K_4


GPU CLK REQ PCIE_CLKREQ_SSD# R141 10K_4
10 OF 20
*SKL_ULT PCIE_CLKREQ5#
REV = 1 ? R142 10K_4

PCIE_CLKREQ_VGA#
DIS: Stuff
UMA: No Stuff
3

Q850
R850 30K_1%_4 2 METR5213-G R9056
<12,46,49> DGPU_PR_EN
*10K_4

Need apply PN
1

C850 U1I
SKL_ULT ?
C C
0.47u/6.3V_4
CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 R143 100/F_4
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 PDC GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP R144 200/F_4
EMMC_RCOMP
9 OF 20
*SKL_ULT
REV = 1 ?

B B

RTC Circuitry(RTC) External Crystal


RTC Clock 32.768KHz The 24 MHz (50 Ohm ESR) XTAL used for Skylake-U
30mils needs to be replaced by 38.4 MHz (30 Ohm ESR) XTAL
for Cannonlake-U.
+3V_RTC_2

* 1
TP8521

R146 R151 C176 27P/50V_4


C177 15P/50V_4 RTC_X1 RTC_RST# 10K_4
1

1
2
20K/F_4 EC_RTC_RST <37>
5

XTAL24_IN R9048 40.2_4 XTAL24_IN_R R148 Y2


RTC Power trace width 20mils. C178 1M_4 24MHZ/20ppm
Y1 R147 1U/6.3V_4 4 3 RTC_RST# XTAL24_OUT
R9049 40.2_4 XTAL24_OUT_R
32.768KHZ/20ppm 10M_4 +3V_RTC_0 R149

3
4
2 20K/F_4 Q5A 2N7002KDW
PV
+3VPCU SRTC_RST#
R150 3 R9061 *0_4 EC_SRTC_RST <37> C180 27P/50V_4
2

C179 15P/50V_4 RTC_X2 +3V_RTC_0 1K_4 +3V_RTC_1


1
D2
BAT54CW-7-F C181 1 6 SRTC_RST#
PV
1

A C182 A
1U/6.3V_4 1U/6.3V_4 Q5B 2N7002KDW
+

4 3
R153
-

RTC1 10K_4
RTC Battery
2

RTC_RST# R152 *0_6 SRTC_RST#

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 13 -- SKYLAKE 12/15 (CLK/EMMC) 1A

Date: Wednesday, March 08, 2017 Sheet 13 of 51


5 4 3 2 1
5 4 3 2 1

14
+3V <2,4,10,11,12,13,15,17,18,26,27,28,29,30,31,33,34,35,37,43,45>
+3V_DEEP_SUS <4,10,11,12,15,18>

Skylake (GPIO)
U1F SKL_ULT ? Need apply PN
LPSS ISH

AN8 P2 GPP_D9
GPP_B15/GSPI0_CS# GPP_D9 GPP_D9 <36>
AP7 P3
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 SPK_ID
GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BT_OFF
D
<11> GPP_B18 GPP_B18/GSPI0_MOSI GPP_D12 BT_OFF <36> D
+3V_DEEP_SUS AM5 M4
TP8520
* 1 TP_INTH#_BIOS AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
BT_OFF R154 10K_4 AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1
<11> GSPI1_MOSI GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
PCH_TEMPALERT# R155 10K_4 AB1 GPP_D8/ISH_I2C1_SCL
AB2 GPP_C8/UART0_RXD AD11
W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
SIO_EXT_SCI# R156 10K_4 AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
TP823
* 1 UART2_RXD AD1 U1 PCH_TEMPALERT#
UART2_RXD R157 49.9K/F_4 TP824
* 1 UART2_TXD AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
ACCEL_INTA# AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
SIO_EXT_SCI# AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
<37> SIO_EXT_SCI# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
UART2_TXD R158 49.9K/F_4
AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
SPK_ID R401 *10K_4 U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
U9 GPP_C18/I2C1_SDA AY8
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
AH9 GPP_A19/ISH_GP1 BB7
+3V AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7
ACCEL_INTA# R159 *10K_4 AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
AF11
C GPP_D9 R8565 10K_4 AF12 GPP_F8/I2C4_SDA C
GPP_F9/I2C4_SCL

6 OF 20
*SKL_ULT
REV = 1 ?

HDA Bus(CLG) ACZ_SDOUT

ACZ_SDIN0
+3V_DEEP_SUS R160 *1K_4 ACZ_SYNC
ACZ_RST#
R161 33_4 ACZ_SYNC
<28> ACZ_SYNC_AUDIO
R162 33_4 ACZ_RST# C8525 C8526 C8527
<28> ACZ_RST#_AUDIO
2p/50V_4 2p/50V_4 2p/50V_4
R163 *10K_4 BOARD_ID0 R164 10K_4 R165 33_4 ACZ_SDOUT
+3V_DEEP_SUS <28> ACZ_SDOUT_AUDIO
R166 10K_4 BOARD_ID1 R167 *10K_4 R168 33_4 ACZ_BCLK
<28> BIT_CLK_AUDIO
R169 10K_4 BOARD_ID2 R170 *10K_4
C183
R171 10K_4 BOARD_ID3 R172 *10K_4 15P/50V_4

R173 10K_4 BOARD_ID4 R174 *10K_4


B B
R175 *10K_4 BOARD_ID5 R176 10K_4
U1G SKL_ULT ? Need apply PN
R177 10K_4 BOARD_ID6 R178 *10K_4
AUDIO
R179 10K_4 BOARD_ID7 R180 *10K_4
ACZ_SYNC BA22
R181 10K_4 BOARD_ID8 R182 *10K_4 ACZ_BCLK AY22 HDA_SYNC/I2S0_SFRM
ACZ_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDXC
<11> ACZ_SDOUT ACZ_SDIN0 HDA_SDO/I2S0_TXD
<28> ACZ_SDIN0 BA21
AY21 HDA_SDI0/I2S0_RXD AB11 BOARD_ID0
ACZ_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 BOARD_ID1
J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 BOARD_ID2
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 BOARD_ID3
Skylake AY20
I2S1_SFRM GPP_G3/SD_DATA2
W12
BOARD_ID4
BOARD_ID[8:7] BOARD_ID[6:5] Board ID [4:3] BOARD_ID[2:1] BOARD_ID0 AW20 W11
U I2S1_TXD GPP_G4/SD_DATA3 W10 BOARD_ID5
AK7 GPP_G5/SD_CD# W8 BOARD_ID6
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 BOARD_ID7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
GPP_F2/I2S2_TXD BOARD_ID8
Model ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 AK10
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7
BA9
BB9
GPP_A16/SD_1P8_SEL
H5 AB7 R183 200/F_4
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
00 SKL U 00 14" : UMA
0: GPP_D20/DMIC_DATA0
Reserve Reserve
Definition 01 KBL U 01 15" : DIS
1: D8 AF13
C8 GPP_D17/DMIC_CLK1 GPP_F23
(Default = 00) (Default = 00) GPP_D18/DMIC_DATA1
10 Base U 10 Reserve ACZ_SPKR AW5
<11,28> ACZ_SPKR GPP_B14/SPKR
A
11 KBL R(4+2) 11 Reserve A

7 OF 20
*SKL_ULT
REV = 1 ?

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 14 -- SKYLAKE 13/15 (GPIO) 1A

Date: Wednesday, March 08, 2017 Sheet 14 of 51


5 4 3 2 1
5 4 3 2 1

<4,10,11,12,14,18>
<9,13,41,42>
<9,41,49>
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.8V_DEEP_SUS

<4,31,36,37,39,40,41,42,45,46,49>
+BAT_RTC
+3VS5
15
D ? D
U1O
SKL_ULT
Need apply PN
CPU POWER 4 OF 4

+VCCPRIM AB19
C184 1U/6.3V_4 AB20 VCCPRIM_1P0_AB19 AK15 +VCCPGPPA
P18 VCCPRIM_1P0_AB20 VCCPGPPA
2.899A
VCCPRIM_1P0_P18 VCCPGPPB
AG15 +VCCPGPPB
+3V_DEEP_SUS
Y16 +VCCPGPPC
AF18 VCCPGPPC Y15 +VCCPGPPD
+1.0V_DEEP_SUS VCCPRIM_CORE_AF18 VCCPGPPD
C185 1U/6.3V_4 AF19 T16 +VCCPGPPE
V20 VCCPRIM_CORE_AF19 VCCPGPPE AF16
2.57A
VCCPRIM_CORE_V20 VCCPGPPF
+VCCPGPPF +VCCPGPPA
V21 AD15 +VCCPGPPG
VCCPRIM_CORE_V21 VCCPGPPG
Ca and Cb close to CPU less then 100 mils C186 1U/6.3V_4 +VCCPGPPB
AL1 V19
PCH Internal VRM +VCCDSW_1.0V
C187 1U/6.3V_4 DCPDSW _1P0 VCCPRIM_3P3_V19 +3V_DEEP_SUS
+VCCPGPPC
Ca K17 T1 +VCCPRIM_1.0V_T1
+1.0V_DEEP_SUS
+VCCMPHYAON_1P0 L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 +VCCPGPPD
+1.0V_DEEP_SUS VCCMPHYAON_1P0_L1 +VCCATS_1.8V
C188 1U/6.3V_4 AA1
VCCATS_1P8 +1.8V_DEEP_SUS
N15 +VCCPGPPE
N16 VCCMPHYGT_1P0_N15 AK17 +VCCRTCPRIM_3.3V
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3V_DEEP_SUS
N17 1.714A +VCCPGPPG
+1.0V_DEEP_SUS VCCMPHYGT_1P0_N17
C189 1U/6.3V_4 P15 AK19 +VCCRTC R309 *0_4/S
C190 47U/6.3VS_8 P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
+3V_RTC_2 20mils
VCCMPHYGT_1P0_P16 VCCRTC_BB14
+1.0V_DEEP_SUS +VCCAMPHYPLL_1P0 K15 BB10 DCPRTC Cb C191 0.1U/16V_4 +1.0V_DEEP_SUS +1.8V_DEEP_SUS
close to CPU/1004 +1.0V_DEEP_SUS
C192 1U/6.3V_4 L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L15 A14 +VCCCLK1
1 2 L668 +VCCAPLL_1.0V V15 VCCCLK1
VCCAPLL_1P0 0.03A +VCCPGPPF
120/300MA K19 +VCCCLK2
+VCCPRIM AB17 VCCCLK2
+1.0V_DEEP_SUS VCCPRIM_1P0_AB17
C C654 C653 Y18 L21 +VCCCLK3 C
2p/50V_4 2p/50V_4 VCCPRIM_1P0_Y18 VCCCLK3
AD17 N20 +VCCCLK4
+3VS5 VCCDSW _3P3_AD17 VCCCLK4
C193 1U/6.3V_4 AD18 0.09A
AJ17 VCCDSW _3P3_AD18 L19 +VCCCLK5
C194 1U/6.3V_4 VCCDSW _3P3_AJ17 VCCCLK5
AJ19 A10 +VCCCLK6
+V3.3DX_1.5DX_ADO VCCHDA VCCCLK6 C195 1U/6.3V_4
+VCCSPI AJ16 AN11
+3V_DEEP_SUS VCCSPI GPP_B0/CORE_VID0 AN13
AF20 GPP_B1/CORE_VID1
+VCCSRAM_1.0V AF21 VCCSRAM_1P0_AF20
+1.0V_DEEP_SUS VCCSRAM_1P0_AF21
C196 1U/6.3V_4 T19
T20 VCCSRAM_1P0_T19
VCCSRAM_1P0_T20
+VCCPRIM_3.3V AJ21
+3V_DEEP_SUS VCCPRIM_3P3_AJ21
+VCCPRIM_1.0V AK20
+1.0V_DEEP_SUS VCCPRIM_1P0_AK20
+VCCAPLLEBB N18
+1.0V_DEEP_SUS VCCAPLLEBB
C197 1U/6.3V_4 E
15 OF 20
*SKL_ULT
close to CPU/1004 REV = 1 ?
+VCCATS_1.8V +VCCRTC +VCCRTCPRIM_3.3V
+V3.3DX_1.5DX_ADO +3V +1.0V_DEEP_SUS

L666 2 1 120/300MA
B C203 C204 C198 C199 C200 C201 C202 B

C650
*1U/6.3V_4 *22U/6.3V_6 +3VS5
for DS3 +3V_DEEP_SUS 1U/6.3V_4 0.1U/16V_4 1U/6.3V_4 1U/6.3V_4 0.1U/16V_4
2p/50V_4

C651
2p/50V_4

R9054 0_6

R211 C205
*100K_4 1U/6.3V_4
U4 +VCCPGPPB +VCCPGPPC +VCCPGPPE

4 1
VIN#1 VOUT
5 2
VIN#2 GND C206 C207 C208
3 C209 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
<37,41,42> SLP_SUS_ON EN
0.1U/16V_4

C210 *AL005245000
*10P/50V_4

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 15 -- SKYLAKE 14/15(PCH POWER) 1A

Date: Wednesday, March 08, 2017 Sheet 15 of 51


5 4 3 2 1
5 4 3 2 1

16
D D

C C

del XDP

B B

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5 16 -- SKYLAKE 15/15 XDP&APS * 1A

Date: W ednesday, March 08, 2017 Sheet 16 of 51


5 4 3 2 1
5 4 3 2 1

<3> M_A_A[13:0] M_A_A0


M_A_A1
M_A_A2
M_A_A3
144
133
132
131
JDIM1A
A0
A1
A2
DQ0
DQ1
DQ2
8
7
20
21
M_A_DQ4
M_A_DQ0
M_A_DQ7
M_A_DQ3
M_A_DQ[63:0] <3>

2.48A
+1.2VSUS

111
112
117
JDIM1B

VDD1
VDD2
17
M_A_A4 128 A3 DQ3 4 M_A_DQ1 118 VDD3 255
M_A_A5 126 A4 DQ4 3 M_A_DQ5 123 VDD4 VDDSPD +3V
M_A_A6 127 A5 DQ5 16 M_A_DQ2 124 VDD5
M_A_A7 122 A6 DQ6 17 M_A_DQ6 129 VDD6 257
A7 DQ7 VDD7 VPP1 +2.5VSUS
M_A_A8 125 28 M_A_DQ9 130 259
M_A_A9 121 A8 DQ8 29 M_A_DQ12 135 VDD8 VPP2
D M_A_A10 146 A9 DQ9 41 M_A_DQ10 136 VDD9 D
M_A_A11 120 A10/AP DQ10 42 M_A_DQ14 141 VDD10 258
M_A_A12 119 A11 DQ11 24 M_A_DQ8 142 VDD11 VTT DDR_VTT
M_A_A13 158 A12 DQ12 25 M_A_DQ13 147 VDD12
151 A13 DQ13 38 M_A_DQ15 148 VDD13
<3> M_A_WE# A14/W E# DQ14 M_A_DQ11 VDD14 +SMDDR_VREF_DQ0 R227 +SMDDR_VREF_DIMM
156 37 153 164 *0_6/S
<3> M_A_CAS# A15/CAS# DQ15 VDD15 VREF_CA
152 50 M_A_DQ17 154
<3> M_A_RAS# A16/RAS# DQ16 M_A_DQ21 VDD16
49 159
*TP105 1 162 DQ17 62 M_A_DQ22 160 VDD17
*TP106 1 165 S2#/C0 DQ18 63 M_A_DQ18 163 VDD18
S3#/C1 DQ19 46 M_A_DQ20 VDD19
DQ20 45 M_A_DQ16
114 DQ21 58 M_A_DQ23 1 2

DDR4 SODIMM 260 PIN


<3> M_A_ACT# 143 ACT# DQ22 59 M_A_DQ19 5 VSS1 VSS48 6
R228 240_4
+1.2VSUS <3> M_A_PARITY 116 PARITY DQ23 70 M_A_DQ28 9 VSS2 VSS49 10
PM_EXTTS#0 <3> M_A_ALERT# 134 ALERT# DQ24 71 M_A_DQ24 15 VSS3 VSS50 14
<18> PM_EXTTS#0 EVENT# DQ25 VSS4 VSS51
108 83 M_A_DQ31 19 18
<3,18> DDR3_DRAMRST# RESET# DQ26 M_A_DQ27 VSS5 VSS52
84 23 22
C216 *0.1U/16V_4 DQ27 66 M_A_DQ25 27 VSS6 VSS53 26

DDR4 SODIMM 260 PIN


DQ28 67 M_A_DQ29 31 VSS7 VSS54 30
DQ29 79 M_A_DQ26 35 VSS8 VSS55 36
1005 Change R228 from 10K to 240 and PU to +1.2VSUS DQ30 M_A_DQ30 VSS9 VSS56
80 39 40
DQ31 174 M_A_DQ37 43 VSS10 VSS57 44
DQ32 173 M_A_DQ33 47 VSS11 VSS58 48
DQ33 187 M_A_DQ38 51 VSS12 VSS59 52
DQ34 186 M_A_DQ35 57 VSS13 VSS60 56
DQ35 170 M_A_DQ32 61 VSS14 VSS61 60
DQ36 169 M_A_DQ36 65 VSS15 VSS62 64
DQ37 183 M_A_DQ34 69 VSS16 VSS63 68

(260P)
DQ38 182 M_A_DQ39 73 VSS17 VSS64 72
C DQ39 195 M_A_DQ40 77 VSS18 VSS65 78 C
150 DQ40 194 M_A_DQ43 81 VSS19 VSS66 82
<3> M_A_BS#0 BA0 DQ41 M_A_DQ41 VSS20 VSS67
145 207 85 86
<3> M_A_BS#1 BA1 DQ42 M_A_DQ47 VSS21 VSS68
115 208 89 90
<3> M_A_BG#0 BG0 DQ43 M_A_DQ45 VSS22 VSS69
113 191 93 94

(260P)
+3V <3> M_A_BG#1 BG1 DQ44 VSS23 VSS70
190 M_A_DQ44 99 98
149 DQ45 203 M_A_DQ42 103 VSS24 VSS71 102
<3> M_A_CS#0 S0# DQ46 M_A_DQ46 VSS25 VSS72
157 204 107 106
<3> M_A_CS#1 S1# DQ47 VSS26 VSS73
109 216 M_A_DQ53 167 168
<3> M_A_CKE0 CKE0 DQ48 M_A_DQ52 VSS27 VSS74
110 215 171 172
<3> M_A_CKE1 CKE1 DQ49 M_A_DQ55 VSS28 VSS75
228 175 176
R229 R230 R231 137 DQ50 229 M_A_DQ50 181 VSS29 VSS76 180
<3> M_A_CLKP0 CK0 DQ51 M_A_DQ49 VSS30 VSS77
*10K_4 *10K_4 *10K_4 139 211 185 184
<3> M_A_CLKN0 CK0# DQ52 M_A_DQ48 VSS31 VSS78
138 212 189 188
CHA_SA0 CHA_SA1 CHA_SA2 <3> M_A_CLKP1 CK1 DQ53 M_A_DQ54 VSS32 VSS79
140 224 193 192
<3> M_A_CLKN1 CK1# DQ54 M_A_DQ51 VSS33 VSS80
225 197 196
R232 R233 R234 155 DQ55 237 M_A_DQ56 201 VSS34 VSS81 202
<3> M_A_DIM0_ODT0 ODT0 DQ56 M_A_DQ60 VSS35 VSS82
10K_4 10K_4 10K_4 161 236 205 206
<3> M_A_DIM0_ODT1 ODT1 DQ57 VSS36 VSS83
249 M_A_DQ59 209 210
SMB_RUN_CLK 253 DQ58 250 M_A_DQ63 213 VSS37 VSS84 214
<10,18,26,33> SMB_RUN_CLK SMB_RUN_DAT 254 SCL DQ59 232 M_A_DQ57 +1.2VSUS +1.2VSUS 217 VSS38 VSS85 218
<10,18,26,33> SMB_RUN_DAT SDA DQ60 M_A_DQ61 VSS39 VSS86
233 223 222
CHA_SA0 256 DQ61 245 M_A_DQ62 227 VSS40 VSS87 226
CHA_SA1 SA0 DQ62 M_A_DQ58 VSS41 VSS88
Follow reference board +1.2VSUS CHA_SA2
260
166 SA1 DQ63
246 231
235 VSS42 VSS89
230
234
SA2 M_A_DQSP[7:0] <3> VSS43 VSS90
DIMM0 SA0,1,2=LLL EZIW
DQS0
13 M_A_DQSP0 R236 R237 239
VSS44 VSS91
238
R235 *240_4 M_A_CB0 92
CB0 DQS1
34 M_A_DQSP1 240_4 240_4 243
VSS45 VSS92
244
R238 *240_4 M_A_CB1 91
CB1 DQS2
55 M_A_DQSP2 247
VSS46 VSS93
248
R239 *240_4 M_A_CB2 101
CB2 DQS3
76 M_A_DQSP3 M_A_DQSP8 M_A_DQSN8 251
VSS47 VSS94
252
R240 *240_4 M_A_CB3 105
CB3 DQS4
179 M_A_DQSP4
B
R241 *240_4 M_A_CB4 88
CB4 DQS5
200 M_A_DQSP5 B
*240_4 M_A_CB5 87 221 M_A_DQSP6
R242
R243 *240_4 M_A_CB6 100 CB5 DQS6 242 M_A_DQSP7 Place these Caps near So-Dimm0. 263 261
CB6 DQS7 VSS99 GND
R244 *240_4 M_A_CB7 104
CB7 DQS8
97 M_A_DQSP8 1uF/10uF 4pcs on each side of connector 264
VSS100 GND1
262

12 11 M_A_DQSN0 M_A_DQSN[7:0] <3>


+1.2VSUS 33 DM0 DQS#0 32 M_A_DQSN1
DM1 DQS#1 M_A_DQSN2 DDR4-DIMM0_H=4.0_STD
54 53 +1.2VSUS DDR_VTT
75 DM2 DQS#2 74 M_A_DQSN3
178 DM3 DQS#3 177 M_A_DQSN4 C217 1U/6.3V_4 C218 1U/6.3V_4 <2,4,10,11,12,13,14,15,18,26,27,28,29,30,31,33,34,35,37,43,45> +3V
199 DM4 DQS#4 198 M_A_DQSN5 <3,6,18,40,42> +1.2VSUS
220 DM5 DQS#5 219 M_A_DQSN6 C219 1U/6.3V_4 C220 1U/6.3V_4 <18,40> DDR_VTT
241 DM6 DQS#6 240 M_A_DQSN7 +SMDDR_VREF_DIMM
96 DM7 DQS#7 95 M_A_DQSN8 C221 1U/6.3V_4 C222 1U/6.3V_4 VREF DQ0 M1 Solution
DM8 DQS#8
C223 1U/6.3V_4 C224 1U/6.3V_4 +1.2VSUS
DDR4-DIMM0_H=4.0_STD
C225 1U/6.3V_4 C226 10U/6.3V_6

C227 1U/6.3V_4 C228 10U/6.3V_6


R245
C229 1U/6.3V_4 +SMDDR_VREF_DIMM 1K/F_4

C230 1U/6.3V_4 C231 *0.1U/16V_4 R246 2/F_6 +SMDDR_VREF_DIMM


<3> SM_VREF
C232 *2.2U/10V_4
C233 10U/6.3V_6
+1.2VSUS +2.5VSUS C234 R247
C235 10U/6.3V_6 0.022U/25V_4 1K/F_4
EC7 180P/50V_4 C236 1U/6.3V_4
A C237 10U/6.3V_6 R248 24.9/F_4 A
EC8 180P/50V_4 C238 1U/6.3V_4
C239 10U/6.3V_6
C240 10U/6.3V_6
C241 10U/6.3V_6
C242 10U/6.3V_6
C243 10U/6.3V_6
+3V PROJECT : 0P1B
C244 10U/6.3V_6
C245 0.1U/16V_4
Quanta Computer Inc.
C246 10U/6.3V_6
C247 2.2U/10V_4 Size Document Number Rev
Custom
NB5 17 -- DDR4 DIMM0-STD(4.0H) 1A

Date: Wednesday, March 08, 2017 Sheet 17 of 51


5 4 3 2 1
5 4 3 2 1

JDIM2A

18
<3> M_B_A[13:0] M_B_A0 M_B_DQ12
144 8 +1.2VSUS
M_B_A1 133 A0 DQ0 7 M_B_DQ8 M_B_DQ[63:0] <3> JDIM2B
M_B_A2 132 A1 DQ1 20 M_B_DQ11 111
M_B_A3 131 A2 DQ2 21 M_B_DQ10 2.48A 112 VDD1
M_B_A4 128 A3 DQ3 4 M_B_DQ9 117 VDD2
M_B_A5 126 A4 DQ4 3 M_B_DQ13 118 VDD3 255
A5 DQ5 VDD4 VDDSPD +3V
M_B_A6 127 16 M_B_DQ15 123
M_B_A7 122 A6 DQ6 17 M_B_DQ14 124 VDD5
M_B_A8 125 A7 DQ7 28 M_B_DQ4 129 VDD6 257
M_B_A9 A8 DQ8 M_B_DQ0 VDD7 VPP1 +2.5VSUS
121 29 130 259
M_B_A10 146 A9 DQ9 41 M_B_DQ3 135 VDD8 VPP2
M_B_A11 120 A10/AP DQ10 42 M_B_DQ6 136 VDD9
M_B_A12 119 A11 DQ11 24 M_B_DQ5 141 VDD10 258
M_B_A13 A12 DQ12 M_B_DQ1 VDD11 VTT DDR_VTT
D 158 25 142 D
151 A13 DQ13 38 M_B_DQ2 147 VDD12
<3> M_B_WE# A14/W E# DQ14 M_B_DQ7 VDD13
156 37 148
<3> M_B_CAS# A15/CAS# DQ15 M_B_DQ17 VDD14 +SMDDR_VREF_DQ1 R249
<3> M_B_RAS#
152 50 153 164 *0_6/S SMDDR_VREF_DQ1_M1
A16/RAS# DQ16 49 M_B_DQ16 154 VDD15 VREF_CA
*TP107 1 162 DQ17 62 M_B_DQ18 159 VDD16
*TP108 1 165 S2#/C0 DQ18 63 M_B_DQ19 160 VDD17
S3#/C1 DQ19 46 M_B_DQ21 163 VDD18
DQ20 45 M_B_DQ20 VDD19
114 DQ21 58 M_B_DQ22
<3> M_B_ACT# 143 ACT# DQ22 59 M_B_DQ23 1 2

DDR4 SODIMM 260 PIN


<3> M_B_PARITY PARITY DQ23 M_B_DQ25 VSS1 VSS48
116 70 5 6
<3> M_B_ALERT# PM_EXTTS#0 134 ALERT# DQ24 71 M_B_DQ24 9 VSS2 VSS49 10
<17> PM_EXTTS#0 EVENT# DQ25 VSS3 VSS50
108 83 M_B_DQ30 15 14
<3,17> DDR3_DRAMRST# RESET# DQ26 M_B_DQ31 VSS4 VSS51
84 19 18
DQ27 66 M_B_DQ28 23 VSS5 VSS52 22

DDR4 SODIMM 260 PIN


C248 *0.1U/16V_4
DQ28 67 M_B_DQ29 27 VSS6 VSS53 26
DQ29 79 M_B_DQ26 31 VSS7 VSS54 30
DQ30 80 M_B_DQ27 35 VSS8 VSS55 36
DQ31 174 M_B_DQ36 39 VSS9 VSS56 40
DQ32 173 M_B_DQ37 43 VSS10 VSS57 44
DQ33 187 M_B_DQ39 47 VSS11 VSS58 48
DQ34 186 M_B_DQ35 51 VSS12 VSS59 52
DQ35 170 M_B_DQ32 57 VSS13 VSS60 56
DQ36 169 M_B_DQ33 61 VSS14 VSS61 60
DQ37 183 M_B_DQ34 65 VSS15 VSS62 64
DQ38 182 M_B_DQ38 69 VSS16 VSS63 68 Place these Caps near So-Dimm1.

(260P)
DQ39 195 M_B_DQ44 73 VSS17 VSS64 72
150 DQ40 194 M_B_DQ41 77 VSS18 VSS65 78
1uF/10uF 4pcs on each side of connector
<3> M_B_BS#0 BA0 DQ41 M_B_DQ42 VSS19 VSS66
145 207 81 82
<3> M_B_BS#1 BA1 DQ42 M_B_DQ43 VSS20 VSS67
C 115 208 85 86 C
<3> M_B_BG#0 BG0 DQ43 M_B_DQ45 VSS21 VSS68 +SMDDR_VREF_DQ1
113 191 89 90

(260P)
<3> M_B_BG#1 +1.2VSUS
BG1 DQ44 190 M_B_DQ40 93 VSS22 VSS69 94
149 DQ45 203 M_B_DQ46 99 VSS23 VSS70 98 C249 1U/6.3V_4 C250 *0.1U/16V_4
<3> M_B_CS#0 S0# DQ46 M_B_DQ47 VSS24 VSS71
+3V 157 204 103 102
<3> M_B_CS#1 S1# DQ47 M_B_DQ48 VSS25 VSS72
109 216 107 106 C251 1U/6.3V_4 C252 *2.2U/10V_4
<3> M_B_CKE0 CKE0 DQ48 M_B_DQ52 VSS26 VSS73
110 215 167 168
<3> M_B_CKE1 CKE1 DQ49 M_B_DQ55 VSS27 VSS74
228 171 172 C253 1U/6.3V_4
137 DQ50 229 M_B_DQ54 175 VSS28 VSS75 176 DDR_VTT
<3> M_B_CLKP0 CK0 DQ51 M_B_DQ49 VSS29 VSS76
139 211 181 180 C254 1U/6.3V_4
<3> M_B_CLKN0 CK0# DQ52 M_B_DQ53 VSS30 VSS77
138 212 185 184
<3> M_B_CLKP1 CK1 DQ53 M_B_DQ50 VSS31 VSS78
R250 R251 R252 140 224 189 188 C255 1U/6.3V_4 C256 1U/6.3V_4
<3> M_B_CLKN1 CK1# DQ54 M_B_DQ51 VSS32 VSS79
*10K_4 10K_4 *10K_4 225 193 192
M_B_ODT0 155 DQ55 237 M_B_DQ57 197 VSS33 VSS80 196 C257 1U/6.3V_4 C258 1U/6.3V_4
CHB_SA0 CHB_SA1 CHB_SA2 <3> M_B_DIM0_ODT0 M_B_ODT1 ODT0 DQ56 M_B_DQ56 VSS34 VSS81
161 236 201 202
<3> M_B_DIM0_ODT1 ODT1 DQ57 M_B_DQ58 VSS35 VSS82
249 205 206 C259 1U/6.3V_4 C260 1U/6.3V_4
R253 R254 R255 253 DQ58 250 M_B_DQ62 209 VSS36 VSS83 210
<10,17,26,33> SMB_RUN_CLK 254 SCL DQ59 232 M_B_DQ61 213 VSS37 VSS84 214
10K_4 *10K_4 10K_4 C261 1U/6.3V_4 C262 1U/6.3V_4
<10,17,26,33> SMB_RUN_DAT SDA DQ60 M_B_DQ60 VSS38 VSS85
233 217 218
CHB_SA0 256 DQ61 245 M_B_DQ59 223 VSS39 VSS86 222 C263 10U/6.3V_6 C264 10U/6.3V_6
CHB_SA1 260 SA0 DQ62 246 M_B_DQ63 227 VSS40 VSS87 226 C265 10U/6.3V_6
+1.2VSUS CHB_SA2 166 SA1 DQ63 +1.2VSUS 231 VSS41 VSS88 230 C266 10U/6.3V_6
SA2 13 M_B_DQSP1 M_B_DQSP[7:0] <3> 235 VSS42 VSS89 234 C267 10U/6.3V_6
M_B_CB0 92 DQS0 34 M_B_DQSP0 239 VSS43 VSS90 238 C268 10U/6.3V_6
R256 *240_4 CB0 DQS1 VSS44 VSS91
M_B_CB1 91 55 M_B_DQSP2 243 244 +3V
Follow reference R257
R258
*240_4
*240_4 M_B_CB2 101 CB1 DQS2 76 M_B_DQSP3 247 VSS45 VSS92 248 C269 10U/6.3V_6
CB2 DQS3 VSS46 VSS93
board DIMM1 R259 *240_4 M_B_CB3
M_B_CB4
105
88 CB3 DQS4
179
200
M_B_DQSP4
M_B_DQSP5
R261 251
VSS47 VSS94
252 C270 10U/6.3V_6 C271 0.1U/16V_4
R260 *240_4 240_4
SA0,1,2=LHL R262 *240_4 M_B_CB5 87 CB4
CB5
DQS5
DQS6
221 M_B_DQSP6 C272 10U/6.3V_6 C273 2.2U/10V_4
R263 *240_4 M_B_CB6 100 242 M_B_DQSP7 M_B_DQSP8 C274 10U/6.3V_6
B M_B_CB7 104 CB6 DQS7 97 M_B_DQSP8 263 261 +2.5VSUS B
R264 *240_4 CB7 DQS8 VSS99 GND
+1.2VSUS 264 262
12 11 M_B_DQSN1 M_B_DQSN[7:0] <3> VSS100 GND1 +1.2VSUS C275 1U/6.3V_4
+1.2VSUS 33 DM0 DQS#0 32 M_B_DQSN0
54 DM1 DQS#1 53 M_B_DQSN2 EC9 180P/50V_4 C276 1U/6.3V_4
DM2 DQS#2 M_B_DQSN3 DDR4-DIMM0_H=4.0_RVS
75 74
178 DM3 DQS#3 177 M_B_DQSN4 R265 EC10 180P/50V_4 C277 10U/6.3V_6
199 DM4 DQS#4 198 M_B_DQSN5
DM5 DQS#5 240_4
220 219 M_B_DQSN6 C278 10U/6.3V_6
241 DM6 DQS#6 240 M_B_DQSN7 M_B_DQSN8
96 DM7 DQS#7 95 M_B_DQSN8
DM8 DQS#8

DDR4-DIMM0_H=4.0_RVS +1.2VSUS

Co-lay for ODT VREF DQ1 M1 Solution


From Intel MOW, ODT directly connection to CPU
+1.2VSUS +3V_DEEP_SUS
Local Thermal Sensor R266
1K/F_4
DDR4 Thermal Sensor SMDDR_VREF_DQ1_M3 R267 2/F_6 SMDDR_VREF_DQ1_M1
<3> SMDDR_VREF_DQ1_M3
U6 C279 *0.01U/50V_4
C280
R268 R269 R270 MBCLK2 8 1 0.022U/25V_4 R271
<10,26,37> MBCLK2 SCLK VCC +3V
*47K/F_4 *47K/F_4 *47K/F_4 1K/F_4
MBDATA2 7 2 DDR_THERMDA
<10,26,37> MBDATA2 SDA DXP R272

3
PM_EXTTS#0 6 3 24.9/F_4
ALERT# DXN
2

A C281 2 Q7 A
R273 *10K/F_4 4 5 *2200P/50V_4 *METR3904-G
+3V OVERT# GND

1
DDR_THERMDC
1 3 *EMC1412-1-ACZL-TR
<3> DDR_VTT_CNTL DDR_VTT_PG_CTRL_R <40>
Need Check PN(EOD)
Q6 *DRC5144E0L
Main:AL001412003 EMC1412-1-ACZL-TR(98h)
PROJECT : 0P1B
<38,39,45,49> +5VPCU Quanta Computer Inc.
<3,6,17,40,42> +1.2VSUS 2nd:AL000431014 TMP431ADGKR(98h)
<17,40> DDR_VTT Size Document Number Rev
<4,31,32,39,40,41,42,43,44,45,46,48> +5VS5 Custom
NB5 18 -- DDR4 DIMM1-RVS(4.0H) 1A
<2,4,10,11,12,13,14,15,17,26,27,28,29,30,31,33,34,35,37,43,45> +3V
Date: Wednesday, March 08, 2017 Sheet 18 of 51
5 4 3 2 1
19
U1010G

DP POWER NC/DP POWER


U1010A
AG15 AE11
AG16 NC_DP_VDDR#1 NC#AE11 AF11
AF16 NC_DP_VDDR#2 NC#AF11 AE13
AG17 NC_DP_VDDR#3 NC#AE13 AF13
AG18 NC_DP_VDDR#4 NC#AF13 AG8
AG19 NC_DP_VDDR#5 NC#AG8 AG10
1.8V ( 40mA) NC_DP_VDDR#6 NC#AG10
PEG_TXP0 AF30 AH30 C_PEG_RXP0 C1179 0.22u/10V_4 AF14
<12> PEG_TXP0 PCIE_RX0P PCIE_TX0P PEG_RXP0 <12> +1.8V_VGA DP_VDDR
PEG_TXN0 AE31 AG31 C_PEG_RXN0 C1180 0.22u/10V_4
<12> PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 <12>
C1331 C1114
PEG_TXP1 AE29 AG29 C_PEG_RXP1 C1190 0.22u/10V_4 10U/6.3VS_6 1u/6.3V_4
<12> PEG_TXP1 PEG_TXN1 AD28 PCIE_RX1P PCIE_TX1P AF28 C_PEG_RXN1 PEG_RXP1 <12>
C1286 0.22u/10V_4
<12> PEG_TXN1 PCIE_RX1N PCIE_TX1N PEG_RXN1 <12>
AG20 AF6
AG21 NC_DP_VDDC#1 NC#AF6 AF7
PEG_TXP2 AD30 AF27 C_PEG_RXP2 C1500 0.22u/10V_4 AF22 NC_DP_VDDC#2 NC#AF7 AF8
<12> PEG_TXP2 PEG_TXN2 AC31 PCIE_RX2P PCIE_TX2P AF26 C_PEG_RXN2 PEG_RXP2 <12> AG22 NC_DP_VDDC#3 NC#AF8 AF9
<12> PEG_TXN2 PCIE_RX2N PCIE_TX2N
C1501 0.22u/10V_4
PEG_RXN2 <12> 1.0V ( 32mA) NC_DP_VDDC#4 NC#AF9
AD14
+1.0V_VGA DP_VDDC
PEG_TXP3 AC29 AD27 C_PEG_RXP3 C1502 0.22u/10V_4
<12> PEG_TXP3 PEG_TXN3 AB28 PCIE_RX3P PCIE_TX3P AD26 C_PEG_RXN3 PEG_RXP3 <12>
C1503 0.22u/10V_4 C1118 C1117
<12> PEG_TXN3 PCIE_RX3N PCIE_TX3N PEG_RXN3 <12> AG14 AE1
1u/6.3V_4 0.1u/16V_4
AH14 NC_DP_VSSR#1 NC#AE1 AE3
AB30 AC25 AM14 NC_DP_VSSR#2 NC#AE3 AG1
AA31 PCIE_RX4P PCIE_TX4P AB25 AM16 NC_DP_VSSR#3 NC#AG1 AG6
PCIE_RX4N PCIE_TX4N AM18 NC_DP_VSSR#4 NC#AG6 AH5
AF23 NC_DP_VSSR#5 NC#AH5 AF10
AA29 Y23 AG23 NC_DP_VSSR#6 NC#AF10 AG9
PCIE_RX5P PCIE_TX5P NC_DP_VSSR#7 NC#AG9

PCI EXPRESS INTERFACE


Y28 Y24 AM20 AH8
PCIE_RX5N PCIE_TX5N AM22 NC_DP_VSSR#8 NC#AH8 AM6
AM24 NC_DP_VSSR#9 NC#AM6 AM8
Y30 AB27 AF19 NC_DP_VSSR#10 NC#AM8 AG7
W 31 PCIE_RX6P PCIE_TX6P AB26 AF20 NC_DP_VSSR#11 NC#AG7 AG11
PCIE_RX6N PCIE_TX6N AE14 NC_DP_VSSR#12 NC#AG11
DP_VSSR
W 29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N
AF17 AE10
V30 W 24 NC_UPHYAB_DP_CALR NC#AE10
U31 NC#V30 NC#W 24 W 23
NC#U31 NC#W 23
MESO_S3
U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30 T24
N31 NC#P30 NC#T24 T23
GPU Reset Signal
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26 +3V_VGA

M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23 R1294
C1504 *0.1u/16V_4 1K_1%_4
L29 M27 D1500
K30 NC#L29 NC#M27 N26 PCIE_RST# 1
NC#K30 NC#N26 <4,30,34,36,37> PLTRST# PEGX_RST#
3
PEGX_RST# <20>
<12> DGPU_HOLD_RST# R1303 *0_5%_4/S DGPU_HIN_RST# 2

CLOCK
CLK_GFX_P AK30 BAT54AW-L R1296
<13> CLK_GFX_P CLK_GFX_N AK32 PCIE_REFCLKP 100K_1%_4
<13> CLK_GFX_N PCIE_REFCLKN

CALIBRATION
Y22 SUN_PCIE_CALRP R1493 1.69K_1%_4
PCIE_CALR_TX +1.0V_VGA
R1474 1K_1%_4 TEST_PG N10 AA22 SUN_PCIE_CALRN R1494 1K_1%_4
TEST_PG PCIE_CALR_RX

PEGX_RST# AL27
PERSTB

MESO_S3

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5
1A 1A
M1-70_S3_PCIE/DP POWER
Date: Wednesday, March 08, 2017 Sheet 19of 51
20
+3V_VGA
Thermal Solution(Close to GPU)
+1.8V_VGA +1.8V_VGA
C1505 *0.01u/50V_4 U1010B
U1500
R1304
10K_1%_4 R1246 R1492
DGPUT_CLK 8 1 AF2 8.45K_1%_4 8.45K_1%_4
SMBCLK VCC +3V_VGA NC#AF2
DVO AF4
DGPUT_DATA 7 2 GPU_THERMDA NC#AF4
SMBDATA DXP PS_0
PS0 => 11001 (BIT5~1) PS_1
PS1 => 11001 (BIT5~1)
N9 AG3
VGA_ALERT VGA_ALERT_R 6 3 L9 DBG_DATA16 NC#AG3 AG5
R1300 *0_5%_4
ALERT DXN DBG_DATA15 DPA NC#AG5
C1506 AE9
R1295 *10K_1%_4 4 5 *2200p/50V_4 Y11 DBG_DATA14 AH3 R1256 C1153 R1491 C1376
+3V_VGA THERM GND DBG_DATA13 NC#AH3
AE8 AH1 2K_1%_4 *0.01u/50V_4 2K_1%_4 *0.082u/16V_4
GPU_THERMDC AD9 DBG_DATA12 NC#AH1
<37> DGPU_OVT# AC10 DBG_DATA11 AK3
*G781P8 AD7 DBG_DATA10 NC#AK3 AK1
AC8 DBG_DATA9 NC#AK1
Main:AL000781012 G781P8(98h) AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
AB8 DBG_DATA6 NC#AM3
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5 +1.8V_VGA +1.8V_VGA
AB2 DBG_DATA3 NC#AM5
DBG_DATA2 DPB
Y8 AJ7
Y7 DBG_DATA1 NC#AJ7 AH6
DBG_DATA0 NC#AH6 R1244 R1245
+3V_VGA AK8 *0_5%_4 3.24K_1%_4
NC#AK8 AL7
NC#AL7
GPU_GPIO5 PS_2
PS2 => 11000 (BIT5~1) PS_3
PS3 => 11000 (BIT5~1)
R1305 10K_1%_4 R1302 *10K_1%_4
W6 DPC
R1449 *10K_1%_4 DGPU_TDI V6 NC#W6
+1.8V_VGA NC#V6 V4 R1254 C1151 R1255 C1152
R1309 *10K_1%_4 DGPU_TMS NC#V4 U5 4.75K_1%_4 *0.68U/4V_4 5.62K_1%_4 *0.01u/50V_4
AC5 NC#U5
R1395 *10K_1%_4 DGPU_TDO AC6 NC#AC5
N#CAC6 V2
DGPU_TCK R1399 *10K_1%_4 NC#V2
Y4 4.75K CS24752FB12
R1520 *5.1K_1%_4 TESTEN R1526 1K_1%_4 R17M-M1-70: Stuff R1065 R1070 AA5 NC#Y4 W5 8.45K CS28452FB12
NC#AA5 NC#W5
DGPU_TRSTB
R17M-M1-30: NA *10K_1%_4 *10K_1%_4 AA6
NC#AA6 4.53K CS24532FB08
R1601 *10K_1%_4 2.00K CS22002FB19
Y2 6.98K CS26982FB01
*10K_1%_4 PCIE_REQ_GPU# NC#Y2 J8
R1602 TP1501
NC#J8 4.99K CS24992FB26
U1
R1603 *10K_1%_4 DGPU_PROCHOT# TP1502 NC#U1/BP_0 AA1 TP1527
U3 NC#AA1/PLL_ANALOG_IN AA3
NC#U3/BP_1 NC#AA3/PLL_ANALOG_OUT
R1187 *16.2K_1%_4 PS_3[3:1] Vendor Type Vendor P/N PU PD
Y6
NC#Y6
+3V_VGA R17M-M1-70: Stuff 000 Micron 256Mx16 *4 MT41J256M16LY-091G:N NC 4.75K
R17M-M1-30: NA 001 Samsung 256Mx16 *4 K4W4G1646E-BC1A 8.45K 2.00K
R1381 4.7K_5%_4 R1 010 Hynix 256Mx16 *4 H5TC4G63EFR-N0C 4.53K 2.00K
R3 SCL
+3V_VGA
R1380 4.7K_5%_4
SDA I2C
+3V_VGA 011 Micron 256Mx16 *8 MT41J256M16LY-091G:N 6.98K 4.99K
AM26 R1269 *10K_1%_4
GENERAL PURPOSE I/O DCM/NC_R AK26
R1609 *4.7K_5%_4
NC_AVSSN#AK26 100 Samsung 256Mx16 *8 K4W4G1646E-BC1A 4.53K 4.99K
R1610 *4.7K_5%_4 U6
GPIO_0 AL25 +3V_VGA
R1614
NC_G 101 Hynix 256Mx16 *8 H5TC4G63EFR-N0C 3.24K 5.62K
*10K_1%_4 AJ25
DGPUT_DATA R1611 DGPUT_DATA_R
*0_5%_4/S U8 NC_AVSSN#AJ25 R1619 *4.7K_5%_4
DGPUT_CLK R1612 DGPUT_CLK_R
*0_5%_4/S U7 SMBDATA AH24
R1613 GPU_GPIO5
*0_5%_4/S T9 SMBCLK NC_B AG25
<37> DGPU_PROCHOT_EC# GPU_GPIO6 T8 GPIO_5_AC_BATT NC_AVSSN#AG25
R1615 *1K_1%_4 R1620

2
<46> DGPU_OCP_L T7 PCC/GPIO_6 AH26
NC_GPIO_7 DAC1 NC_HSYNC
*4.7K_5%_4
1 3
TP1503 GPIO8 P10 AJ27
P4 GPIO_8_ROMSO NC_VSYNC/WAKEb TP1528
C1509 TP1504 GPIO9 Q1501
*0.1u/16V_4 TP1505 GPIO10 P2 GPIO_9_ROMSI *2N7002K
TP1506 GPIO11 N6 GPIO_10_ROMSCK AD22
TP1507 GPIO12 N5 NC_GPIO_11 NC_RSET R1621
TP1508 GPIO13 N3 NC_GPIO_12 AG24
NC_GPIO_13 NC_AVDD *4.7K_5%_4
AE22
GPU_SVD_JET N1 NC_AVSSQ R17M-M1-70: Stuff
GPIO_15_PWRCNTL_0
VGA_ALERT
M4
R6 GPIO_16 NC_VDD1DI
AE23
AD23
R17M-M1-30: NA
R1604 *0_5%_4/S GPIO_17_THERMAL_INT NC_VSS1DI
AMD recommend TEMP_FAIL M2
GPU_SVC_JET P8 GPIO_19_CTF AM12
Q1500A P7 GPIO_20_PWRCNTL_1 NC
*2N7002KDW R1616 TP1509 GPIO22 N8 GPIO_21 Level: 1.8V
3 4 DGPUT_DATA 10K_1%_4 DGPU_PROCHOT# AK10 GPIO_22_ROMCSB AK12 GPU_SVD R1207 *0_5%_4 SVI2_DATA
<37> GPUT_DATA GPIO_29 NC_SVI2#1/GPIO_SVD GPU_SVT SVI2_DATA <46>
TP1520 GPIO30 AM10 AL11 R1201 *0_5%_4
PCIE_REQ_GPU# N7 GPIO_30 NC_SVI2#2/GPIO_SVT AJ11 GPU_SVC SVI2_CLK SVI2_SVT <46>
R1204 *0_5%_4 SVI2_CLK <46>
R1606 *0_5%_4 TP1521 DGPU_TRSTB L6 CLKREQB NC_SVI2#3/GPIO_SVC
5

PEGX_RST# <19> JTAG_TRSTB


R17M-M1-70: Stuff
R1607 *4.7K_5%_4
+3V_VGA TP1522 DGPU_TDI L5 AL13 R17M-M1-30: NA Level Setting by Power BOM!!
TP1523 DGPU_TCK L3 JTAG_TDI NC_GENLK_CLK AJ13
TP1524 DGPU_TMS L1 JTAG_TCK NC_GENLK_VSYNC Level: 3.3V
JTAG_TMS
2

TP1525 DGPU_TDO K4 GPU_SVD_JET R1635 0_5%_4 SVI2_DATA


K7 JTAG_TDO GPU_SVC_JET SVI2_CLK
DGPUT_CLK
TESTEN
TESTEN DAC2 R1637 0_5%_4
6 1 AF24 AG13
<37> GPUT_CLK NC#AF24 NC_SWAPLOCKA AH12
*2N7002KDW NC_SWAPLOCKB R17M-M1-70: NA
Q1500B
W8
R17M-M1-30: Stuff
R1605 *0_5%_4/S NC_GENERICB AC19 PS_0
W7 PS_0
AD10 NC_GENERICD AD19 PS_1
AJ9 NC_GENERICE_HPD4 PS_1
AL9 NC#AJ9 AE17 PS_2
DBG_CNTL0 PS_2 For R17M-M1-30 debug
AE20 PS_3
PS_3 +3V_VGA
TP1526 PX_EN AB16 AE19 TS_A R1251 *0_5%_4
PX_EN TS_A

AC16
C1507 8.2p/50V_4 NC_DBG_VREFG R1639 R1640 +1.8V_VGA
10K_1%_2 *10K_1%_2
27M-XTALI DDC/AUX

5
AE6
NC_DDC1CLK
2
1

PLL/CLOCK AE5
Y1500 NC_DDC1DATA R17M-M1-70: NA GPU_SVD_JET 3 4 SVI2_DATA
27MHZ/10ppm R1608
1M_5%_4 NC_AUX1P
AD2
AD4
R17M-M1-30: Stuff Q1502A
*DMN5L06DWK-7
NC_AUX1N Q1502B
4
3

27M-XTALO 27M-XTALI AM28 *DMN5L06DWK-7


27M-XTALO AK28 XTALIN GPU_SVC_JET 6 1 SVI2_CLK
C1508 8.2p/50V_4 XTALOUT
AD13
R1617 10K_1%_4 AC22 NC_AUX2P AD11

2
R1618 10K_1%_4 AB22 XO_IN NC_AUX2N
XO_IN2 R1642 R1641
*10K_1%_2 10K_1%_2 +1.8V_VGA
MV AE16
L1501 GPU_THERMDA T4 NC#AE16 AD16
1.8V(13mA TSVDD) GPU_THERMDC DPLUS NC#AD16
1 2 T2 THERMAL
+1.8V_VGA DMINUS
*0_HCB1608KF-121T30(120+-25%,3A)/S AC1
NC_DDCVGACLK AC3 TP1529
R5 NC_DDCVGADATA TP1530
C1567 R1638 10K_1%_4
1u/6.3V_4 +1.8V_TSVDD AD17 GPIO28_FDO
AC17 TSVDD
TSVSS
For AMD tuning timing purpose
R17M-M1-70: NA
R17M-M1-30: Stuff

MESO_S3

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5
1A
M1-70_S3_MAIN
Date: Wednesday, March 08, 2017 Sheet 20of 51
CONFIGURATION STRAPS-- SEE EACH DATABOOK FOR STRAP DETAILS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
21
THEY MUST NOT CONFLICT DURING RESET

STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS

U1010E
TX_PW RS_ENB GPIO0 PCIE FULL TX OUTPUT SW ING
0
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED
AA27 A3 X
AB24 PCIE_VSS#1 GND#1 A30
AB32 PCIE_VSS#2 GND#2 AA13 RSVD GPIO2 RESERVED 0
AC24 PCIE_VSS#3 GND#3 AA16 RSVD GPIO8 RESERVED 0
AC26 PCIE_VSS#4 GND#4 AB10
AC27 PCIE_VSS#5 GND#5 AB15
AD25 PCIE_VSS#6 GND#6 AB6 BIF_VGA DIS GPIO9 VGA ENABLED 0
AD32 PCIE_VSS#7 GND#7 AC9
AE27 PCIE_VSS#8 GND#8 AD6
AF32 PCIE_VSS#9 GND#9 AD8 RSVD GPIO21 RESERVED 0
AG27 PCIE_VSS#10 GND#10 AE7 U1010F
AH32 PCIE_VSS#11 GND#11 AG12
K28 PCIE_VSS#12 GND#12 AH10 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM
PCIE_VSS#13 GND#13 0
K32 AH28
L27 PCIE_VSS#14 GND#14 B10 LVDS CONTROL
M32 PCIE_VSS#15 GND#15 B12 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0 0 1
N25 PCIE_VSS#16 GND#16 B14
N27 PCIE_VSS#17 GND#17 B16
P25 PCIE_VSS#18 GND#18 B18 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS (Removed on Seymour/W histler) 0
P32 PCIE_VSS#19 GND#19 B20
R27 PCIE_VSS#20 GND#20 B22 AL15
T25 PCIE_VSS#21 GND#21 B24 NC_UPHYAB_TMDPA_TX0N AK14 RSVD H2SYNC RESERVED 0
T32 PCIE_VSS#22 GND#22 B26 NC_UPHYAB_TMDPA_TX0P
U25 PCIE_VSS#23 GND#23 B6 AH16
U27 PCIE_VSS#24 GND#24 B8 NC_UPHYAB_TMDPA_TX1N AJ15 AUD[1] HSYNC SEE DATABOOK FOR DETAIL 0
V32 PCIE_VSS#25 GND#25 C1 NC_UPHYAB_TMDPA_TX1P AUD[0] VSYNC SEE DATABOOK FOR DETAIL 0
W25 PCIE_VSS#26 GND#26 C32 AL17
W26 PCIE_VSS#27 GND#27 E28 NC_UPHYAB_TMDPA_TX2N AK16
W27 PCIE_VSS#28 GND#28 F10 NC_UPHYAB_TMDPA_TX2P RSVD GENERICC RESERVED 0
Y25 PCIE_VSS#29 GND#29 F12 AH18
Y32 PCIE_VSS#30 GND#30 F14 NC_UPHYAB_TMDPA_TX3N AJ17
PCIE_VSS#31 GND#31 F16 NC_UPHYAB_TMDPA_TX3P
GND#32 F18 AL19
GND#33 F2 NC_TXOUT_L3P AK18
GND#34
GND#35
F20 NC_TXOUT_L3N NOTE1: AMD RESERVED CONFIGURATION STRAPS
M6 F22
N11 GND#56 GND#36 F24 TMDP
GND#57 GND#37 F26
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED,
N13 GND#38 F6 AH20 THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET.
N16 GND#58 GND#39 NC_UPHYAB_TMDPB_TX0N
N18
N21
GND#59
GND#60
GND#61
GND GND#40
GND#41
GND#42
F8
G10
G27
NC_UPHYAB_TMDPB_TX0P

NC_UPHYAB_TMDPB_TX1N
AJ19

AL21 GPIO21 H2SYNC GENERICC GPIO8 GPIO2


P6 G31 AK20
P9 GND#62 GND#43 G8 NC_UPHYAB_TMDPB_TX1P
R12 GND#63 GND#44 H14 AH22
R15 GND#64 GND#45 H17 NC_UPHYAB_TMDPB_TX2N AJ21
R17 GND#65 GND#46 H2 NC_UPHYAB_TMDPB_TX2P
R20 GND#66 GND#47 H20 AL23
T13 GND#67 GND#48 H6 NC_UPHYAB_TMDPB_TX3N AK22
T16 GND#68 GND#49 J27 NC_UPHYAB_TMDPB_TX3P
T18 GND#69 GND#50 J31 AK24
T21 GND#70 GND#51 K11 NC_TXOUT_U3P AJ23
T6 GND#71 GND#52 K2 NC_TXOUT_U3N
U15 GND#72 GND#53 K22
U17 GND#73 GND#54 K6
U20 GND#74 GND#55 T11
U9 GND#75 GND#84 R11 MESO_S3
V13 GND#76 GND#85
V16 GND#77
V18 GND#78
Y10 GND#79
Y15 GND#80
Y17 GND#81 A32
Y20 GND#82 VSS_MECH#1 AM1
AA11 GND#83 VSS_MECH#2 AM32
M12 GND#86 VSS_MECH#3
V11 GND#87
GND#88

MESO_S3

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5
1A
1A
M1-70_S3_GND/LVDS/Strap
Date: W ednesday, March 08, 2017 Sheet 21 of 51
22
U1010D
PCIE_VDDR : 1.8V @ 100mA
MEM I/O AM30
PCIE_PVDD +1.8V_VGA
1.5V ( DDR3, MVDDQ = 1.5V@2A) PCIE
+1.5V_VGA H13 AB23
H16 VDDR1#1 NC#AB23 AC23 C1527 C1528
H19 VDDR1#2 NC#AC23 AD24 1u/6.3V_4 10U/6.3VS_6
C1510 C1511 C1512 C1513 C1514 C1515 J10 VDDR1#3 NC#AD24 AE24
10U/6.3VS_6 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 J23 VDDR1#4 NC#AE24 AE25
J24 VDDR1#5 NC#AE25 AE26
J9 VDDR1#6 NC#AE26 AF25
K10 VDDR1#7 NC#AF25 AG26
K23 VDDR1#8 NC#AG26
K24 VDDR1#9
K9 VDDR1#10 L23
C1516 C1517 L11 VDDR1#11 PCIE_VDDC#1 L24 +1.0V_VGA
0.1u/16V_4 0.01u/50V_4 L12 VDDR1#12 PCIE_VDDC#2 L25
VDDR1#13 PCIE_VDDC#3 PCIE_VDDC : 0.95V @ 2.5A (GEN3.0)
L13 L26
L20 VDDR1#14 PCIE_VDDC#4 M22
L21 VDDR1#15 PCIE_VDDC#5 N22
L22 VDDR1#16 PCIE_VDDC#6 N23 C1529 C1530 C1531 C1532 C1533 C1534 C1535
VDDR1#17 PCIE_VDDC#7 N24 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10U/6.3VS_6
PCIE_VDDC#8 R22
PCIE_VDDC#9 T22
+1.8V_VGA LEVEL PCIE_VDDC#10 U22
PCIE_VDDC#11 TDP=25W/TDC=36A/
TRANSLATION V22
PCIE_VDDC#12 EDC=54A(1ms)/EDP=35W(sustained)/Peak=53W(1ms) +VGA_CORE
VDD_GPIO18 @13mA AA20
AA21 VDD_CT#1
VDD_CT#2 VDDC+VDDCI: 0.85~1.1V(36A peak )( Ripple < 87.2mV)
AB20 AA15
AB21 VDD_CT#3 CORE VDDC#1 N15
C1518 VDD_CT#4 VDDC#2 N17
1u/6.3V_4 +3V_VGA VDDC#3 R13 C1536 C1537 C1538 C1539 C1540 C1541 C1542 C1543
VDDC#4

POWER
I/O VDDC#5
R16 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4
VDD_GPIO33@25mA AA17 R18
AA18 VDDR3#1 VDDC#6 Y21
AB17 VDDR3#2 VDDC#7 T12
AB18 VDDR3#3 VDDC#8 T15
C1519 VDDR3#4 VDDC#9 T17
1u/6.3V_4 V12 VDDC#10 T20
Y12 NC_VDDR4#1 VDDC#11 U13 C1544 C1545 C1546 C1547 C1548 C1549 C1550 C1551
U12 NC_VDDR4#2 VDDC#12 U16 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4
NC_VDDR4#3 VDDC#13 U18
VDDC#14 V21
Memory Phase Lock Loop Power : Dedicated analog power pin for memory PLLs 1.8V @ 90mA VDDC#15 V15
L1502 VDDC#16 V17
1 2 MPV18 VDDC#17 V20
+1.8V_VGA VDDC#18 +
*0_6/S Y13
VDDC#20 Y16 C1552 C1553 C1554 C1555 C1556 C1557 C1558
C1520 C1521 C1522 VDDC#21 Y18 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 *330u/2.5V_3528H1.9
1u/6.3V_4 10U/6.3VS_6 10U/6.3VS_6 VDDC#22 AA12
VDDC#23 M11
VDDC#24 N12
VDDC#25 U11
VDDC#26 AB11 R1634 *0_5%_8
Engine Phase Lock Loop Power : Dedicated analog power pin for engine PLL 1.8V @ 75mA
VDDC/VARY_BL AB12
+VGA_CORE On GPU Bottom Center
VDDC/DIGON AB13
L1503 VDDC/GENERICA W9 R17M-M1-70: Stuff
VDDC/GENERICC
+1.8V_VGA
1
*0_6/S
2 SPV18 PLL
VDDC/DDC2CLK
AC11
AC13
R17M-M1-30: NA
VDDC/DDC2DATA AC14
VDDC/HPD1 BIF_VDDC : 0.95V @ 1.4A
C1523 C1524 U10 +1.0V_VGA
1u/6.3V_4 10U/6.3VS_6 MPV18 L8 VDDC/GPIO_1 T10
MPLL_PVDD VDDC/GPIO_2 W10
VDDC/GPIO_18 Y9 C1559
VDDC/GPIO_14_HPD2 1u/6.3V_4
R21
SPV18 H7 BIF_VDDC_1 U21
SPLL_PVDD BIF_VDDC_2
VDDCI: 0.9V~1.15V @ 5A
Engine Phase Lock Loop Power :Dedicated digital power pin for engine PLL 0.95V @ 100mA M13
ISOLATED VDDCI#1 +VGA_CORE
M15
L1504 CORE I/O VDDCI#2 M16
1 2 +1.0V_VGA_SPV10 H8 VDDCI#3 M17 C1560 C1561 C1562 C1563 C1564 C1565 C1566
+1.0V_VGA SPLL_VDDC VDDCI#4
*0_6/S M18 0.1u/16V_4 0.1u/16V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10U/6.3VS_6 10U/6.3VS_6
VDDCI#5 M20
C1525 C1526 J7 VDDCI#6 M21
0.1u/16V_4 1u/6.3V_4 SPLL_PVSS VDDCI#7 N20
VDDCI#8
W1 R1622 *0_5%_4 +VGA_CORE
NC#W1/FB_VDDCI W3 R1623 *0_5%_4
NC#W3/FB_VSS
AC20 R1624 *0_5%_4
NC#FB_VDDC VGPU_CORE_SENSE <46>
AD20 R1625 *0_5%_4
NC#FB_VSS VSS_GPU_SENSE <46>
MESO_S3
R17M-M1-70: Stuff
R17M-M1-30: NA

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5
1A
1A
M1-70_S3_POWER
Date: W ednesday, March 08, 2017 Sheet 22 of 51
23
U1010C

VMA_ODT0 VMA_DQ0 K27 K17 VMA_MA0


<24,25> VMA_ODT0 DQA0_0 MAA0_0
VMA_ODT1 VMA_DQ1 J29 J20 VMA_MA1
<24,25> VMA_ODT1 DQA0_1 MAA0_1
VMA_DQ2 H30 H23 VMA_MA2
VMA_RAS0# VMA_DQ3 H32 DQA0_2 MAA0_2 G23 VMA_MA3
<24,25> VMA_RAS0# DQA0_3 MAA0_3
VMA_RAS1# VMA_DQ4 G29 G24 VMA_MA4
<24,25> VMA_RAS1# DQA0_4 MAA0_4
VMA_DQ5 F28 H24 VMA_MA5
VMA_CAS0# VMA_DQ6 F32 DQA0_5 MAA0_5 J19 VMA_MA6
<24,25> VMA_CAS0# DQA0_6 MAA0_6
VMA_CAS1# VMA_DQ7 F30 K19 VMA_MA7
<24,25> VMA_CAS1# DQA0_7 MAA0_7
VMA_DQ8 C30 G20 VMA_MA13
VMA_WE0# VMA_DQ9 F27 DQA0_8 MAA0_8 L17 VMA_MA15
<24,25> VMA_WE0# DQA0_9 MAA0_9
VMA_WE1# VMA_DQ10 A28

MEMORY INTERFACE
<24,25> VMA_WE1# DQA0_10
VMA_DQ11 C28 J14 VMA_MA8
VMA_CSA0#_0 VMA_DQ12 E27 DQA0_11 MAA1_0 K14 VMA_MA9
<24> VMA_CSA0#_0 DQA0_12 MAA1_1
VMA_CSA0#_1 VMA_DQ13 G26 J11 VMA_MA10
<24,25> VMA_CSA0#_1 DQA0_13 MAA1_2
VMA_CSA1#_0 VMA_DQ14 D26 J13 VMA_MA11
<24> VMA_CSA1#_0 DQA0_14 MAA1_3
VMA_CSA1#_1 VMA_DQ15 F25 H11 VMA_MA12
<24,25> VMA_CSA1#_1 DQA0_15 MAA1_4
VMA_DQ16 A25 G11 VMA_BA2
VMA_CKE0 VMA_DQ17 C25 DQA0_16 MAA1_5 J16 VMA_BA0
<24,25> VMA_CKE0 DQA0_17 MAA1_6
VMA_CKE1 VMA_DQ18 E25 L15 VMA_BA1
<24,25> VMA_CKE1 DQA0_18 MAA1_7
VMA_DQ19 D24 G14 VMA_MA14
VMA_CLK0 VMA_DQ20 E23 DQA0_19 MMA1_8 L16
<24,25> VMA_CLK0 DQA0_20 MAA1_9
VMA_CLK0# VMA_DQ21 F23
<24,25> VMA_CLK0# DQA0_21
VMA_DQ22 D22 E32 VMA_DM0
VMA_CLK1 VMA_DQ23 F21 DQA0_22 WCKA0_0 E30 VMA_DM1
<24,25> VMA_CLK1 DQA0_23 WCKA0B_0
VMA_CLK1# VMA_DQ24 E21 A21 VMA_DM2
<24,25> VMA_CLK1# DQA0_24 WCKA0_1
VMA_DQ25 D20 C21 VMA_DM3
VMA_WDQS[7..0] VMA_DQ26 F19 DQA0_25 WCKA0B_1 E13 VMA_DM4
<24,25> VMA_WDQS[7..0] VMA_DQ27 A19 DQA0_26 WCKA1_0 D12 VMA_DM5
VMA_RDQS[7..0] VMA_DQ28 D18 DQA0_27 WCKA1B_0 E3 VMA_DM6
<24,25> VMA_RDQS[7..0] VMA_DQ29 F17 DQA0_28 WCKA1_1 F4 VMA_DM7
VMA_DM[7..0] VMA_DQ30 A17 DQA0_29 WCKA1B_1
<24,25> VMA_DM[7..0] VMA_DQ31 DQA0_30 VMA_RDQS0
C17 H28
VMA_DQ[63..0] VMA_DQ32 E17 DQA0_31 EDCA0_0 C27 VMA_RDQS1
<24,25> VMA_DQ[63..0] VMA_DQ33 DQA1_0 EDCA0_1 VMA_RDQS2
D16 A23
VMA_MA[15..0] VMA_DQ34 F15 DQA1_1 EDCA0_2 E19 VMA_RDQS3
<24,25> VMA_MA[15..0] DQA1_2 EDCA0_3
VMA_DQ35 A15 E15 VMA_RDQS4
VMA_DQ36 D14 DQA1_3 EDCA1_0 D10 VMA_RDQS5
VMA_BA0 VMA_DQ37 F13 DQA1_4 EDCA1_1 D6 VMA_RDQS6
<24,25> VMA_BA0 DQA1_5 EDCA1_2
VMA_BA1 VMA_DQ38 A13 G5 VMA_RDQS7
<24,25> VMA_BA1 DQA1_6 EDCA1_3
VMA_BA2 VMA_DQ39 C13
<24,25> VMA_BA2 VMA_DQ40 E11 DQA1_7 H27 VMA_WDQS0
VMA_DQ41 A11 DQA1_8 DDBIA0_0 A27 VMA_WDQS1
VMA_DQ42 C11 DQA1_9 DDBIA0_1 C23 VMA_WDQS2
VMA_DQ43 F11 DQA1_10 DDBIA0_2 C19 VMA_WDQS3
+1.5V_VGA +1.5V_VGA VMA_DQ44 A9 DQA1_11 DDBIA0_3 C15 VMA_WDQS4
VMA_DQ45 C9 DQA1_12 DDBIA1_0 E9 VMA_WDQS5
VMA_DQ46 F9 DQA1_13 DDBIA1_1 C5 VMA_WDQS6
VMA_DQ47 D8 DQA1_14 DDBIA1_2 H4 VMA_WDQS7
VMA_DQ48 E7 DQA1_15 DDBIA1_3
R1501 R1510 VMA_DQ49 A7 DQA1_16 L18 VMA_ODT0
40.2_1%_4 40.2_1%_4 VMA_DQ50 C7 DQA1_17 ADBIAO K16 VMA_ODT1
VMA_DQ51 F7 DQA1_18 ADBIA1
VMA_DQ52 A5 DQA1_19 H26 VMA_CLK0
MVREFS MVREFD VMA_DQ53 E5 DQA1_20 CLKA0 H25 VMA_CLK0#
VMA_DQ54 C3 DQA1_21 CLKA0B
VMA_DQ55 E1 DQA1_22 G9 VMA_CLK1
VMA_DQ56 G7 DQA1_23 CLKA1 H9 VMA_CLK1#
C1416 R1500 C1431 R1504 VMA_DQ57 G6 DQA1_24 CLKA1B
1u/6.3V_4 100_1%_4 1u/6.3V_4 100_1%_4 VMA_DQ58 G1 DQA1_25 G22 VMA_RAS0#
VMA_DQ59 G3 DQA1_26 RASA0B G17 VMA_RAS1#
VMA_DQ60 J6 DQA1_27 RASA1B
VMA_DQ61 J1 DQA1_28 G19 VMA_CAS0#
VMA_DQ62 J3 DQA1_29 CASA0B G16 VMA_CAS1#
VMA_DQ63 J5 DQA1_30 CASA1B
DQA1_31 H22 VMA_CSA0#_0
MVREFD K26 CSA0B_0 J22 VMA_CSA0#_1
MVREFS J26 MVREFDA CSA0B_1
MVREFSA G13 VMA_CSA1#_0
J25 CSA1B_0 K13 VMA_CSA1#_1
R1497 120_1%_4MEM_CALRP0 K25 NC CSA1B_1
25mm (max) 5mm (max) 25mm (max) MEM_CALRP0 K20 VMA_CKE0
From GPU CKEA0 VMA_CKE1
J17
CKEA1
R1459 51_5%_4 R1466 10_1%_4 DRAM_RST_C G25 VMA_WE0#
<24,25> DRAM_RST_M WEA0B
DRAM_RST_C L10 H10 VMA_WE1#
DRAM_RST WEA1B
CLKTESTA K8
C1302 R1470 CLKTESTB L7 CLKTESTA
120p/50V_4 4.99K_1%_4 CLKTESTB

C1002 C1003 MESO_S3


*0.1u/16V_4 *0.1u/16V_4
PROJECT : 0P1B
Place all these components very close to GPU. (Within 25mm)
R1008
*51.1_1%_4
R1009
*51.1_1%_4
Quanta Computer Inc.
Keep all component close to each Other. (within 5mm) Size Document Number Rev

NB5
1A
1A
This basic topology should be used for DRAM_RST for DDR3/GDDR5. M1-70_S3_MEM
Date: Wednesday, March 08, 2017 Sheet 23 of 51
5 4 3 2 1

<23,25>
<23,25>
VMA_MA[15..0]
VMA_DM[7..0]
<23,25>
<23,25>
<23,25>
VMA_DQ[63..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0]
DDR3L
24
U1013 U1012 U1008 U1007

VREFC_VMA1 M8 E3 VMA_DQ8 VREFC_VMA2 M8 E3 VMA_DQ18 VREFC_VMA3 M8 E3 VMA_DQ59 VREFC_VMA4 M8 E3 VMA_DQ34


VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ14 VREFD_VMA2 H1 VREFCA DQL0 F7 VMA_DQ19 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ62 VREFD_VMA4 H1 VREFCA DQL0 F7 VMA_DQ38
VREFDQ DQL1 F2 VMA_DQ10 VREFDQ DQL1 F2 VMA_DQ16 VREFDQ DQL1 F2 VMA_DQ57 VREFDQ DQL1 F2 VMA_DQ35
VMA_MA0 N3 DQL2 F8 VMA_DQ13 VMA_MA0 N3 DQL2 F8 VMA_DQ20 VMA_MA0 N3 DQL2 F8 VMA_DQ60 VMA_MA0 N3 DQL2 F8 VMA_DQ39
VMA_MA1 P7 A0 DQL3 H3 VMA_DQ9 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ21 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ58 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ32
VMA_MA2 P3 A1 DQL4 H8 VMA_DQ12 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ23 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ63 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ37
D VMA_MA3 N2 A2 DQL5 G2 VMA_DQ11 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ17 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ56 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ33 D
VMA_MA4 P8 A3 DQL6 H7 VMA_DQ15 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ22 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ61 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ36
VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7
VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA6 R8 A5
VMA_MA7 R2 A6 D7 VMA_DQ5 VMA_MA7 R2 A6 D7 VMA_DQ31 VMA_MA7 R2 A6 D7 VMA_DQ52 VMA_MA7 R2 A6 D7 VMA_DQ47
VMA_MA8 T8 A7 DQU0 C3 VMA_DQ3 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ27 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ51 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ43
VMA_MA9 R3 A8 DQU1 C8 VMA_DQ6 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ30 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ55 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ46
VMA_MA10 L7 A9 DQU2 C2 VMA_DQ2 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ24 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ50 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ42
VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ4 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ28 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ54 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ44
VMA_MA12 N7 A11 DQU4 A2 VMA_DQ1 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ25 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ49 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ41
VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ7 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ29 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ53 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ45
VMA_MA14 T7 A13 DQU6 A3 VMA_DQ0 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ26 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ48 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ40
VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7
A15 +1.5V_VGA A15 +1.5V_VGA A15 +1.5V_VGA A15 +1.5V_VGA

M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2


<23,25> VMA_BA0 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9
<23,25> VMA_BA1 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9
M3 G7 M3 G7 M3 G7 M3 G7
<23,25> VMA_BA2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
<23,25> VMA_CLK0 CK VDD#N9 VMA_CLK0# CK VDD#N9 <23,25> VMA_CLK1 CK VDD#N9 VMA_CLK1# CK VDD#N9
K7 R1 K7 R1 K7 R1 K7 R1
<23,25> VMA_CLK0# K9 CK VDD#R1 R9 VMA_CKE0 K9 CK VDD#R1 R9 <23,25> VMA_CLK1# K9 CK VDD#R1 R9 VMA_CKE1 K9 CK VDD#R1 R9
<23,25> VMA_CKE0 CKE VDD#R9 +1.5V_VGA CKE VDD#R9 +1.5V_VGA <23,25> VMA_CKE1 CKE VDD#R9 +1.5V_VGA CKE VDD#R9 +1.5V_VGA

K1 A1 VMA_ODT0 K1 A1 K1 A1 VMA_ODT1 K1 A1
<23,25> VMA_ODT0 ODT VDDQ#A1 VMA_CSA0#_0 ODT VDDQ#A1 <23,25> VMA_ODT1 ODT VDDQ#A1 VMA_CSA1#_0 ODT VDDQ#A1
L2 A8 L2 A8 L2 A8 L2 A8
<23> VMA_CSA0#_0 J3 CS VDDQ#A8 C1 VMA_RAS0# J3 CS VDDQ#A8 C1 <23> VMA_CSA1#_0 J3 CS VDDQ#A8 C1 VMA_RAS1# J3 CS VDDQ#A8 C1
<23,25> VMA_RAS0# RAS VDDQ#C1 VMA_CAS0# RAS VDDQ#C1 <23,25> VMA_RAS1# RAS VDDQ#C1 VMA_CAS1# RAS VDDQ#C1
K3 C9 K3 C9 K3 C9 K3 C9
<23,25> VMA_CAS0# CAS VDDQ#C9 VMA_WE0# CAS VDDQ#C9 <23,25> VMA_CAS1# CAS VDDQ#C9 VMA_WE1# CAS VDDQ#C9
L3 D2 L3 D2 L3 D2 L3 D2
<23,25> VMA_WE0# WE VDDQ#D2 E9 WE VDDQ#D2 E9 <23,25> VMA_WE1# WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_RDQS1 F3 VDDQ#F1 H2 VMA_RDQS2 F3 VDDQ#F1 H2 VMA_RDQS7 F3 VDDQ#F1 H2 VMA_RDQS4 F3 VDDQ#F1 H2
VMA_WDQS1 G3 DQSL VDDQ#H2 H9 VMA_WDQS2 G3 DQSL VDDQ#H2 H9 VMA_WDQS7 G3 DQSL VDDQ#H2 H9 VMA_WDQS4 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9

C VMA_DM1 E7 A9 VMA_DM2 E7 A9 VMA_DM7 E7 A9 VMA_DM4 E7 A9 C


VMA_DM0 D3 DML VSS#A9 B3 VMA_DM3 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3 VMA_DM5 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 +1.5V_VGA
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_RDQS0 C7 VSS#G8 J2 VMA_RDQS3 C7 VSS#G8 J2 VMA_RDQS6 C7 VSS#G8 J2 VMA_RDQS5 C7 VSS#G8 J2
VMA_WDQS0 B7 DQSU VSS#J2 J8 VMA_WDQS3 B7 DQSU VSS#J2 J8 VMA_WDQS6 B7 DQSU VSS#J2 J8 VMA_WDQS5 B7 DQSU VSS#J2 J8 R1226 100_1%_4 VMA_MA0 R1483 100_1%_4
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 R1236 100_1%_4 VMA_MA1 R1485 100_1%_4
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 R1240 100_1%_4 VMA_MA2 R1487 100_1%_4
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 R1239 100_1%_4 VMA_MA3 R1489 100_1%_4
T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 R1235 100_1%_4 VMA_MA4 R1490 100_1%_4
<23,25> DRAM_RST_M RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 VMA_MA5
T1 T1 T1 T1 R1234 100_1%_4 R1488 100_1%_4
VSS#T1 T9 VSS#T1 T9 VSS#T1 T9 VSS#T1 T9 R1232 100_1%_4 VMA_MA6 R1486 100_1%_4
VSS#T9 VSS#T9 VSS#T9 VSS#T9 R1222 100_1%_4 VMA_MA7 R1482 100_1%_4
J1 J1 J1 J1 R1220 100_1%_4 VMA_MA8 R1478 100_1%_4
L1 NC#J1/ODT1 B1 L1 NC#J1/ODT1 B1 L1 NC#J1/ODT1 B1 L1 NC#J1/ODT1 B1 R1216 100_1%_4 VMA_MA9 R1480 100_1%_4
J9 NC#L1/CS1 VSSQ#B1 B9 J9 NC#L1/CS1 VSSQ#B1 B9 J9 NC#L1/CS1 VSSQ#B1 B9 J9 NC#L1/CS1 VSSQ#B1 B9 R1211 100_1%_4 VMA_MA10 R1473 100_1%_4
NC#J9/CKE1 VSSQ#B9 D1 NC#J9/CKE1 VSSQ#B9 D1 NC#J9/CKE1 VSSQ#B9 D1 NC#J9/CKE1 VSSQ#B9 D1 R1217 100_1%_4 VMA_MA11 R1481 100_1%_4
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 R1212 100_1%_4 VMA_MA12 R1476 100_1%_4
VMA_ZQ1 L8 VSSQ#D8 E2 VMA_ZQ2 L8 VSSQ#D8 E2 VMA_ZQ3 L8 VSSQ#D8 E2 VMA_ZQ4 L8 VSSQ#D8 E2 R1225 100_1%_4 VMA_MA13 R1231 100_1%_4
L9 ZQ VSSQ#E2 E8 L9 ZQ VSSQ#E2 E8 L9 ZQ VSSQ#E2 E8 L9 ZQ VSSQ#E2 E8 R1218 100_1%_4 VMA_MA14 R1219 100_1%_4
NC#L9/ZQ1 VSSQ#E8 F9 NC#L9/ZQ1 VSSQ#E8 F9 NC#L9/ZQ1 VSSQ#E8 F9 NC#L9/ZQ1 VSSQ#E8 F9 R1233 100_1%_4 VMA_MA15 R1230 100_1%_4
Should be 240 VSSQ#F9
Should be 240 VSSQ#F9
Should be 240 VSSQ#F9
Should be 240 VSSQ#F9
Ohms +-1% G1 Ohms +-1% G1 Ohms +-1% G1 Ohms +-1% G1 R1214 100_1%_4 VMA_BA0 R1479 100_1%_4
VSSQ#G1 G9 VSSQ#G1 G9 VSSQ#G1 G9 VSSQ#G1 G9 R1229 100_1%_4 VMA_BA1 R1477 100_1%_4
R1292 VSSQ#G9 R1272 VSSQ#G9 R1191 VSSQ#G9 R1175 VSSQ#G9 R1208 100_1%_4 VMA_BA2 R1475 100_1%_4
240_1%_4 96-BALL 240_1%_4 96-BALL 240_1%_4 96-BALL 240_1%_4 96-BALL R1271 100_1%_4 VMA_CKE0 R1270 100_1%_4
SDRAM DDR3 SDRAM DDR3 INT SDRAM DDR3 SDRAM DDR3 R1454 100_1%_4 VMA_CKE1 R1453 100_1%_4
H5TC4G63EFR-N0C H5TC4G63EFR-N0C H5TC4G63EFR-N0C H5TC4G63EFR-N0C R1512 100_1%_4 VMA_ODT0 R1279 100_1%_4
R1189 100_1%_4 VMA_ODT1 R1193 100_1%_4
R1514 100_1%_4 VMA_RAS0# R1515 100_1%_4
R1464 100_1%_4 VMA_RAS1# R1455 100_1%_4
R1283 100_1%_4 VMA_CAS0# R1284 100_1%_4
R1177 100_1%_4 VMA_CAS1# R1178 100_1%_4
R1263 100_1%_4 VMA_WE0# R1262 100_1%_4
R1180 100_1%_4 VMA_WE1# R1182 100_1%_4
+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA R1626 100_1%_4 VMA_CSA0#_0 R1627 100_1%_4
+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA R1628 100_1%_4 VMA_CSA0#_1 R1629 100_1%_4
R1630 100_1%_4 VMA_CSA1#_0 R1631 100_1%_4
R1632 100_1%_4 VMA_CSA1#_1 R1633 100_1%_4
B B
R1197 R1163 R1196 R1188
R1257 R1268 R1261 R1291 4.99K_1%_4 4.99K_1%_4 4.99K_1%_4 4.99K_1%_4
4.99K_1%_4 4.99K_1%_4 4.99K_1%_4 4.99K_1%_4

VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4


VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2

R1195 C1090 R1158 C1074 R1198 C1093 R1181 C1086


R1259 C1163 R1273 C1168 R1266 C1165 R1293 C1171 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4
4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4

VMA_CSA0#_1
VMA_CSA1#_1 VMA_CSA0#_1 <23,25>
VMA_CSA1#_1 <23,25>

VMA_CLK0 +1.5V_VGA +1.5V_VGA

R1286
80.6_1%_4

C1170
C1063
1u/6.3V_4
C1126
1u/6.3V_4
C1064
1u/6.3V_4
C1154
1u/6.3V_4
C1065
1u/6.3V_4
C1206
1u/6.3V_4
C1066
1u/6.3V_4
C1067
1u/6.3V_4
C1209
1u/6.3V_4
C1155
1u/6.3V_4
C1166
1u/6.3V_4
C1199
1u/6.3V_4
C1098
1u/6.3V_4
C1096
1u/6.3V_4
C1200
1u/6.3V_4
C1201
1u/6.3V_4
QBCON PN TOP BSQ
VMA_CLK0_COMM

0.01u/50V_4 +1.5V_VGA +1.5V_VGA Micron 2G AKD59GSTL00 AKD59GSTL01


R1281
80.6_1%_4
SAMSUNG 2G AKD5PGDT501 AKD5PGDT500
VMA_CLK0# Single Rank & Dual Rank :
A VMA_CLK1 80.6 ohm - PN: CS08062FB19
C1057
1u/6.3V_4
C1060
1u/6.3V_4
C1061
1u/6.3V_4
C1062
1u/6.3V_4
C1270
1u/6.3V_4
C1076
1u/6.3V_4
C1084
1u/6.3V_4
C1082
1u/6.3V_4
C1104
1u/6.3V_4
C1106
1u/6.3V_4
C1115
1u/6.3V_4
C1120
1u/6.3V_4
C1108
1u/6.3V_4
C1139
1u/6.3V_4
C1140
1u/6.3V_4
C1142
1u/6.3V_4
Hynix 2G AKD5PZDTW02 AKD5PZDTW01 A
PS: 40.2 ohm - CS04022FB28
R1179
80.6_1%_4
+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA
C1085
VMA_CLK1_COMM

0.01u/50V_4
R1185
80.6_1%_4
C1052
10U/6.3VS_6
C1053
10U/6.3VS_6
C1054
10U/6.3VS_6
C1055
10U/6.3VS_6
C1081
10U/6.3VS_6
C1127
10U/6.3VS_6
C1207
10U/6.3VS_6
C1208
10U/6.3VS_6
C1202
10U/6.3VS_6
C1203
10U/6.3VS_6
C1195
10U/6.3VS_6
C1196
10U/6.3VS_6
C1161
10U/6.3VS_6
C1156
10U/6.3VS_6
C1158
10U/6.3VS_6
C1164
10U/6.3VS_6
PROJECT : 0P1B
Quanta Computer Inc.
VMA_CLK1#
Size Document Number Rev
Custom
NB5 M1-70_S3_VRAM_DDR3L BGA96 1A

Date: Wednesday, March 08, 2017 Sheet 24 of 51


5 4 3 2 1
5 4 3 2 1

<23,24>
<23,24>
VMA_MA[15..0]
VMA_DM[7..0]
<23,24>
<23,24>
<23,24>
VMA_DQ[63..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0]
DDR3L 25
U1027 U1028 U1024 U1025

VREFC_VMA5 M8 E3 VMA_DQ14 VREFC_VMA6 M8 E3 VMA_DQ19 VREFC_VMA7 M8 E3 VMA_DQ62 VREFC_VMA8 M8 E3 VMA_DQ38


VREFD_VMA5 H1 VREFCA DQL0 F7 VMA_DQ8 VREFD_VMA6 H1 VREFCA DQL0 F7 VMA_DQ18 VREFD_VMA7 H1 VREFCA DQL0 F7 VMA_DQ59 VREFD_VMA8 H1 VREFCA DQL0 F7 VMA_DQ34
VREFDQ DQL1 F2 VMA_DQ13 VREFDQ DQL1 F2 VMA_DQ20 VREFDQ DQL1 F2 VMA_DQ60 VREFDQ DQL1 F2 VMA_DQ39
VMA_MA0 N3 DQL2 F8 VMA_DQ10 VMA_MA0 N3 DQL2 F8 VMA_DQ16 VMA_MA0 N3 DQL2 F8 VMA_DQ57 VMA_MA0 N3 DQL2 F8 VMA_DQ35
VMA_MA1 P7 A0 DQL3 H3 VMA_DQ15 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ22 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ61 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ36
D VMA_MA2 P3 A1 DQL4 H8 VMA_DQ11 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ17 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ56 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ33 D
VMA_MA3 N2 A2 DQL5 G2 VMA_DQ12 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ23 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ63 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ37
VMA_MA4 P8 A3 DQL6 H7 VMA_DQ9 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ21 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ58 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ32
VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7
VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA6 R8 A5
VMA_MA7 R2 A6 D7 VMA_DQ3 VMA_MA7 R2 A6 D7 VMA_DQ27 VMA_MA7 R2 A6 D7 VMA_DQ51 VMA_MA7 R2 A6 D7 VMA_DQ43
VMA_MA8 T8 A7 DQU0 C3 VMA_DQ5 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ31 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ52 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ47
VMA_MA9 R3 A8 DQU1 C8 VMA_DQ2 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ24 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ50 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ42
VMA_MA10 L7 A9 DQU2 C2 VMA_DQ6 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ30 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ55 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ46
VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ0 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ26 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ48 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ40
VMA_MA12 N7 A11 DQU4 A2 VMA_DQ7 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ29 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ53 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ45
VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ1 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ25 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ49 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ41
VMA_MA14 T7 A13 DQU6 A3 VMA_DQ4 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ28 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ54 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ44
VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7
A15 +1.5V_VGA A15 +1.5V_VGA A15 +1.5V_VGA A15 +1.5V_VGA

M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2


<23,24> VMA_BA0 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2
N8 D9 N8 D9 N8 D9 N8 D9
<23,24> VMA_BA1 M3 BA1 VDD#D9 G7 VMA_BA2 M3 BA1 VDD#D9 G7 VMA_BA2 M3 BA1 VDD#D9 G7 VMA_BA2 M3 BA1 VDD#D9 G7
<23,24> VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
<23,24> VMA_CLK0 K7 CK VDD#N9 R1 VMA_CLK0# K7 CK VDD#N9 R1 <23,24> VMA_CLK1 K7 CK VDD#N9 R1 VMA_CLK1# K7 CK VDD#N9 R1
<23,24> VMA_CLK0# CK VDD#R1 VMA_CKE0 CK VDD#R1 <23,24> VMA_CLK1# CK VDD#R1 VMA_CKE1 CK VDD#R1
K9 R9 K9 R9 K9 R9 K9 R9
<23,24> VMA_CKE0 CKE VDD#R9 +1.5V_VGA CKE VDD#R9 +1.5V_VGA <23,24> VMA_CKE1 CKE VDD#R9 +1.5V_VGA CKE VDD#R9 +1.5V_VGA

K1 A1 VMA_ODT0 K1 A1 K1 A1 VMA_ODT1 K1 A1
<23,24> VMA_ODT0 L2 ODT VDDQ#A1 A8 VMA_CSA0#_1 L2 ODT VDDQ#A1 A8 <23,24> VMA_ODT1 L2 ODT VDDQ#A1 A8 VMA_CSA1#_1 L2 ODT VDDQ#A1 A8
<23,24> VMA_CSA0#_1 CS VDDQ#A8 VMA_RAS0# CS VDDQ#A8 <23,24> VMA_CSA1#_1 CS VDDQ#A8 VMA_RAS1# CS VDDQ#A8
J3 C1 J3 C1 J3 C1 J3 C1
<23,24> VMA_RAS0# RAS VDDQ#C1 VMA_CAS0# RAS VDDQ#C1 <23,24> VMA_RAS1# RAS VDDQ#C1 VMA_CAS1# RAS VDDQ#C1
K3 C9 K3 C9 K3 C9 K3 C9
<23,24> VMA_CAS0# L3 CAS VDDQ#C9 D2 VMA_WE0# L3 CAS VDDQ#C9 D2 <23,24> VMA_CAS1# L3 CAS VDDQ#C9 D2 VMA_WE1# L3 CAS VDDQ#C9 D2
<23,24> VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 <23,24> VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_RDQS1 F3 VDDQ#F1 H2 VMA_RDQS2 F3 VDDQ#F1 H2 VMA_RDQS7 F3 VDDQ#F1 H2 VMA_RDQS4 F3 VDDQ#F1 H2
VMA_WDQS1 G3 DQSL VDDQ#H2 H9 VMA_WDQS2 G3 DQSL VDDQ#H2 H9 VMA_WDQS7 G3 DQSL VDDQ#H2 H9 VMA_WDQS4 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9
C C
VMA_DM1 E7 A9 VMA_DM2 E7 A9 VMA_DM7 E7 A9 VMA_DM4 E7 A9
VMA_DM0 D3 DML VSS#A9 B3 VMA_DM3 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3 VMA_DM5 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_RDQS0 C7 VSS#G8 J2 VMA_RDQS3 C7 VSS#G8 J2 VMA_RDQS6 C7 VSS#G8 J2 VMA_RDQS5 C7 VSS#G8 J2
VMA_WDQS0 B7 DQSU VSS#J2 J8 VMA_WDQS3 B7 DQSU VSS#J2 J8 VMA_WDQS6 B7 DQSU VSS#J2 J8 VMA_WDQS5 B7 DQSU VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9
<23,24> DRAM_RST_M RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1
VSS#T1 T9 VSS#T1 T9 VSS#T1 T9 VSS#T1 T9
VSS#T9 VSS#T9 VSS#T9 VSS#T9
J1 J1 J1 J1
L1 NC#J1/ODT1 B1 L1 NC#J1/ODT1 B1 L1 NC#J1/ODT1 B1 L1 NC#J1/ODT1 B1
J9 NC#L1/CS1 VSSQ#B1 B9 J9 NC#L1/CS1 VSSQ#B1 B9 J9 NC#L1/CS1 VSSQ#B1 B9 J9 NC#L1/CS1 VSSQ#B1 B9
NC#J9/CKE1 VSSQ#B9 D1 NC#J9/CKE1 VSSQ#B9 D1 NC#J9/CKE1 VSSQ#B9 D1 NC#J9/CKE1 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
VMA_ZQ5 L8 VSSQ#D8 E2 VMA_ZQ6 L8 VSSQ#D8 E2 VMA_ZQ7 L8 VSSQ#D8 E2 VMA_ZQ8 L8 VSSQ#D8 E2
L9 ZQ VSSQ#E2 E8 L9 ZQ VSSQ#E2 E8 L9 ZQ VSSQ#E2 E8 L9 ZQ VSSQ#E2 E8
NC#L9/ZQ1 VSSQ#E8 F9 NC#L9/ZQ1 VSSQ#E8 F9 NC#L9/ZQ1 VSSQ#E8 F9 NC#L9/ZQ1 VSSQ#E8 F9
Should be 240 VSSQ#F9 Should be 240 VSSQ#F9 Should be 240 VSSQ#F9 Should be 240 VSSQ#F9
Ohms +-1% G1 Ohms +-1% G1 Ohms +-1% G1 Ohms +-1% G1
VSSQ#G1 G9 VSSQ#G1 G9 VSSQ#G1 G9 VSSQ#G1 G9
R1506 VSSQ#G9 R1282 VSSQ#G9 R1436 VSSQ#G9 R1465 VSSQ#G9
240_1%_4 96-BALL 240_1%_4 96-BALL 240_1%_4 96-BALL 240_1%_4 96-BALL
SDRAM DDR3 SDRAM DDR3 INT SDRAM DDR3 SDRAM DDR3
H5TC4G63EFR-N0C H5TC4G63EFR-N0C H5TC4G63EFR-N0C H5TC4G63EFR-N0C

+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA


+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA
B B

R1468 R1448 R1469 R1431


R1499 R1516 R1250 R1509 4.99K_1%_4 4.99K_1%_4 4.99K_1%_4 4.99K_1%_4
4.99K_1%_4 4.99K_1%_4 4.99K_1%_4 4.99K_1%_4

VREFC_VMA7 VREFD_VMA7 VREFC_VMA8 VREFD_VMA8


VREFC_VMA5 VREFD_VMA5 VREFC_VMA6 VREFD_VMA6

R1471 C1317 R1451 C1288 R1467 C1303 R1438 C1278


R1502 C1425 R1517 C1444 R1248 C1146 R1513 C1435 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4
4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4 4.99K_1%_4 0.1u/16V_4

VMA_CLK0 +1.5V_VGA +1.5V_VGA

R1285
80.6_1%_4
QBCON PN TOP BSQ
C1369 C1385 C1392 C1393 C1395 C1398 C1397 C1434 C1437 C1401 C1188 C1187 C1078 C1080 C1133 C1370
C1167
VMA_CLK0_COMM_2
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
Micron 2G AKD59GSTL00 AKD59GSTL01
+1.5V_VGA +1.5V_VGA
R1280
0.01u/50V_4
SAMSUNG 2G AKD5PGDT501 AKD5PGDT500
80.6_1%_4

A
Hynix 2G AKD5PZDTW02 AKD5PZDTW01 A
VMA_CLK0# C1452 C1449 C1458 C1454 C1455 C1457 C1204 C1426 C1128 C1110 C1282 C1323 C1315 C1313 C1304 C1301
VMA_CLK1
Single Rank & Dual Rank : 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
80.6 ohm - PN: CS08062FB19
PS: 40.2 ohm - CS04022FB28
R1192
80.6_1%_4
+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA
C1094
VMA_CLK1_COMM_2

0.01u/50V_4
PROJECT : 0P1B
R1194
80.6_1%_4
C1414
10U/6.3VS_6
C1438
10U/6.3VS_6
C1440
10U/6.3VS_6
C1446
10U/6.3VS_6
C1422
10U/6.3VS_6
C1399
10U/6.3VS_6
C1415
10U/6.3VS_6
C1411
10U/6.3VS_6
C1353
10U/6.3VS_6
C1336
10U/6.3VS_6
C1347
10U/6.3VS_6
C1348
10U/6.3VS_6
C1299
10U/6.3VS_6
C1279
10U/6.3VS_6
C1265
10U/6.3VS_6
C1267
10U/6.3VS_6
Quanta Computer Inc.
Size Document Number Rev
VMA_CLK1# C
NB5 M1-70_S3_VRAM_DDR3L BGA96 1A

Date: Wednesday, March 08, 2017 Sheet 25 of 51


5 4 3 2 1
5 4 3 2 1

+3V +5V_HDMIC

26
+3V D3001 *BAV99W D3002 *BAV99W
2 2

3 CRT_R1 3 VGADDCCLK
<2> DDI1_HPD_CON

2
1 1
R3001 C3001
100K_1%_4 0.1u/16V_4
D3003 *BAV99W D3004 *BAV99W
2 2

1
3 CRT_G1 3 CRTVSYNC
D D

VCCK_V12
C3002 C3003 1 1

CIIC_SDA
CIIC_SCL
0.1u/16V_4 2.2u/10V_4

D3005 *BAV99W D3006 *BAV99W


2 2
+3V
3 CRT_B1 3 CRTHSYNC

33

32

31

30

29

28

27

26

25
2 1 INT_DDI1_AUXP_C 1 2 U3001
R3002 *1M_5%_4 R3003 *100K_5%_4 1 1

SMB_SDA

LDO_RSTB
EPAD

HPD

XI
EXT1.2V_CTRL

SMB_SCL

PVCC_33

VCCK_12
1 2 INT_DDI1_AUXN_C 2 1
R3005 *100K_5%_4 R3006 *1M_5%_4
D3007 *BAV99W
2
+3V 2
L3001 1 PBY160808T-600Y-N AVCC33 1 24
AVCC_33 GND 3 VGADDCSDA
1 2 INT_DDI1_AUXP_C C3004 0.1u/16V_4 RXAUXP 2 23 CRT_R 1 2
<2> INT_DDI1_AUXP AUX_P RED_P
R3004 *0_5%_4/S R3007 75_1%_4 1
1 2 INT_DDI1_AUXN_C C3005 0.1u/16V_4 RXAUXN 3 22 CRT_G 1 2
<2> INT_DDI1_AUXN AUX_N GREEN_P
R3008 *0_5%_4/S R3009 75_1%_4

<2> DDI1_TX0_P
C3006

C3007
0.1u/16V_4

0.1u/16V_4
VCCK_V12

RRX0P
4

5
AVCC_12

LANE0_P
RTD2166 VDD_DAC_33
BLUE_P
21

20
CRT_B

VDD_DAC_33 2
1
R3010
1
2
75_1%_4
+3V
L3002 PBY160808T-600Y-N
C3008 0.1u/16V_4 RRX0N 6 19 HSYNC 1 2 CRTHSYNC
<2> DDI1_TX0_N LANE0_N HSYNC R3011 47_5%_4 1 2 +5VCRT2 1 2 +5V_HDMIC
C3009 0.1u/16V_4 RRX1P 7 18 VSYNC 1 2 CRTVSYNC R3012 2.2K_5%_4
<2> DDI1_TX1_P LANE1_P VSYNC R3013 47_5%_4 D3008 RB500V-40
C3010 0.1u/16V_4 RRX1N 8 17

POL1/SPI_CEB
<2> DDI1_TX1_N LANE1_N HVSYNC_PWR +5V
VGADDCSDA
C C

VGA_SDA
VGA_SCL
SPI_CLK

VCC_33
SPI_SO
SPI_SI
C3011 C3012 C3013 1 2

POL2
0.1u/16V_4 0.1u/16V_4 4.7u/6.3V_4 R3014 2.2K_5%_4
VGADDCCLK

10

11

12

13

14

15

16
RTD2166-CG

+3V 1 2 VGADDCSDA
R3015 4.7K_5%_4
1 2 VGADDCCLK
R3016 4.7K_5%_4

SI
+3V

40 MIL
TP3001 TP3002 C3014 0.1u/16V_4 +5V_HDMIC
+3V 1 2
R3017 *4.7K_5%_4 SSM14 spec is 40V 1A

16
6
CRT_R 2
L3003 1 BLM15BB750SN1D CRT_R1 1 11
7
CRT_G 2
L3004 1 BLM15BB750SN1D CRT_G1 2 12 VGADDCSDA C3015 *470p/50V_4
8
CRT_B 2
L3005 1 BLM15BB750SN1D CRT_B1 3 13 CRTHSYNC C3016 2p/50V_4
+5V_HDMIC 9
4 14 CRTVSYNC C3023 2p/50V_4
B C3017 C3018 C3019 C3020 C3021 C3022 10 B
5 15 VGADDCCLK C3024 *470p/50V_4
CIIC_SCL, CIIC_SDA Connection 2p/50V_4 2p/50V_4 2p/50V_4 2p/50V_4 2p/50V_4 2p/50V_4

EP mode: Pin2, Pin3 connect to EC SMBUS

17
CRT CONN
ROM or EEPROM mode: connect to PCH SMBUS EMI CN3001
+3V +3V
IIC Protocol is used
1

DFDS15FR689
R3018 R3019 dsub-dhrd4-15k5200-15p
*4.7K_5%_4 *4.7K_5%_4
From PCH
2

1 2 CIIC_SDA
<10,17,18,33> SMB_RUN_DAT
R3020 *0_5%_4/S

1 2 CIIC_SCL
<10,17,18,33> SMB_RUN_CLK
R3021 *0_5%_4/S

+3V

From EC
5

A A

<10,18,37> MBDATA2 3 4
Q3001A *2N7002KDW
2

6 1 PROJECT : 0P1B
Quanta Computer Inc.
<10,18,37> MBCLK2
Q3001B *2N7002KDW

Size Document Number Rev

NB5
Custom 26 -- VRAM DDR3L - RANK1 1A

Date: Wednesday, March 08, 2017 Sheet 26 of 51


5 4 3 2 1
5 4 3 2 1

27
LID Switch eDP Conn. GS12401-1011-9H
CN3501

32
D D
51519-0300t-v01-30p-l
D3501 +3VLCD_CON
C3501 22P/50V_4 DFFC30FR149
<37> EMU_LID R3501 *0_4/SPN_BLON 2 1 BLON_CON
R3502 100K/F_4
RB500V-40

0.047U/16V_4

0.047U/16V_4
60mil 30
LVDS_BLON1 R3503 1K/F_4 29
INT_eDP_AUXP_C 28
INT_eDP_AUXN_C 27
26

C3503

C3502
INT_eDP_TXN0_C 25
LVDS_BLON1 R3504 100K/F_4 INT_eDP_TXP0_C 24
USBP7- R3505 *0_4/S USBP7-_C 23
USBP7+ R3506 *0_4/S USBP7+_C INT_eDP_TXN1_C 22
USBP_CAM- R3507 *0_4/SUSBP_CAM-_C INT_eDP_TXP1_C 21
USBP_CAM+ R3508 *0_4/SUSBP_CAM+_C 20
L3501 3 4 *MCM2012B900GBE USBP7-_C 19
TS USB Interface <12>
<12>
USBP7-
USBP7+
2 1 USBP7+_C 18
17
<2> ULT_EDP_HPD R3509 *0_4/S ULT_EDP_HPD_R
+VIN_BLIGHT 16
+5V_TS TS_INT# 15
2A / 80mils <37> TS_ON
+3V_TS
R3510 *0_4/S
14
+3V_CAM 13
+VIN_BLIGHT +3V_CAM 12
C +VIN
2 1 R9057 *0_4/S CABLE_NC C
1 2 USBP_CAM-_C 11
<12> USBP_CAM- USBP_CAM+_C 10
FUSE SMD 1.5A 24V POLY F1 C3504 0.1U/25V_4 4 3
<12> USBP_CAM+ 9
L3502 *MCM2012B900GBE
L3503 2 1 120/300MA DIGITAL_CLK_L 8
<28> DIGITAL_CLK DIGITAL_D1_L 7
C3505 0.01U/50V_4 L3504 2 1 120/300MA
<28> DIGITAL_D1 6
VADJ1
+VIN BLON_CON 5
C3506 C3507 4
+VIN_BLIGHT 3
*10P/50V_4 *10P/50V_4
2A/80mils 2
C3508 C3509 C3510 C3511 C3512 1

31
4.7U/25V_8 0.1U/25V_4 0.1U/25V_4 0.1U/25V_4
4.7U/25V_8 PIN11:NC NFL-C use
INT_eDP_TXP0_C
SI
<2> INT_eDP_TXP0 C3513 0.1U/16V_4
BRIGHT R3511 1K/F_4 VADJ1
C3514 0.1U/16V_4 INT_eDP_TXN0_C
<2> INT_eDP_TXN0

+3V_CAM C3515 0.1U/16V_4 INT_eDP_TXP1_C C3518 33P/50V_4


<2> INT_eDP_TXP1
R3512
R8560 *0_6/S +3V_CAM C3519 0.1U/16V_4 INT_eDP_TXN1_C 100K/F_4
+3V <2> INT_eDP_TXN1
+3V_TS +3V_TS
INT_eDP_AUXN_C
Need confirm
<2> INT_eDP_AUXN C3520 0.1U/16V_4

F3 8V 1.5A C3516 C3517 C3522 0.1U/16V_4 INT_eDP_AUXP_C


<2> INT_eDP_AUXP +3V
B 2 1 R8559 *0_6/S 10P/50V_4 4.7U/6.3V_4 B
C3521 Need confirm
*22U/6.3V_6 R3513 10_4 BRIGHT R3514 *1K_4 BRIGHT
PV
<2> PCH_DPST_PWM LVDS_BLON1
R3515 *1K_4
R3516 *0_4/S LVDS_BLON1

PV
<2> PCH_LVDS_BLON
R3517 *0_4/S DISP_ON
<2> PCH_DISP_ON
C3523
0.1U/16V_4
+3V

C3524
U3501
2.5A / 100mils +3VLCD_CON
1U/6.3V_4
L3505
+5V +5V_TS +5V_TS 4 1 2 1
VIN#1 VOUT
5 2
F4
2
*8V 1.5A
1 PV DISP_ON 3
VIN#2

EN
GND

MV
*0_6/S
C3525 C3526 C3527
C3528 0.01U/50V_4 0.1U/16V_4 10U/6.3V_6

*22U/6.3V_6
R3518 AL005245000

100K/F_4
A 先先先先先先
the Part is for FHD/先 A

C3529
0.1U/16V_4

<2,4,10,11,12,13,14,15,17,18,26,28,29,30,31,33,34,35,37,43,45> +3V PROJECT : 0P1B


<6,13,31,33,36,37,38,39>
<26,28,29,33,35,36,45>
+3VPCU
+5V
Quanta Computer Inc.
<35,38,39,40,41,43,44,46,47,48,50> +VIN
Size Document Number Rev

NB5
Custom 27 -- eDP CONN/LID/CAM/D-MIC/TS 1A

Date: Wednesday, March 08, 2017 Sheet 27 of 51


5 4 3 2 1
5 4 3 2 1

L4001
+5V_AVDD 1 2 +5V
Close to PIN1 >40mils trace HCB1005KF-181T15_4
SI C4001 C4002

28

1
L4002 1 2 +3V_DVDD 10U/6.3VS_6 0.1U/16V_4
+3V +3V_DVDD-IO *AZ2015-01H
HCB1005KF-181T15_4 +1.8V L4003 1 2
C4003

2
C4004 C4005 C4006
*HCB1005KF-181T15_4
Close to PIN26
1U/6.3V_4 10U/6.3VS_6 0.1U/16V_4 +3V L4004 1 2 AGND C581 need check! +5V
HCB1005KF-181T15_4 C4007 C4008 L4005 1 2 +3V +5V_AVDD
0.1U/16V_4 10U/6.3VS_6 *HCB1005KF-181T15_4 U4001
+1.5V_AVDD L4006 1 2 5 1
+1.8V Vout Vin
HCB1005KF-181T15_4
4
U4002 C4009 C4010 C4011 BYP C4012 C4013 C4014
10U/6.3VS_6 *2.2U/6.3V_6 *0.1U/16V_4 2 3 *0.1U/16V_4 *0.047U/10V_4 *1U/6.3V_4
GND EN
D
TO Digital MIC C4017 10P/50V_4 1
DVDD AVDD1
26
40 Close to PIN40 C4015
*1U/6.3V_4 *TPS793475DBVR
D

R4001 *0_4/S DMIC0 2 AVDD2 AGND HPA01091DBVR


<27> DIGITAL_D1 GPIO0/ DMIC-DATA AGND
<27> DIGITAL_CLK R4002 600 bead_4
PV DMIC_CLK_R 3
GPIO1 / DMIC-CLK AVSS1
AVSS2
25
38
AGND R4003
Vset=1.242V
*10K/F_4 +5V

Analog
C4016 10P/50V_4 R4004 100K/F_4
4 27 C4018 10U/6.3VS_6 AGND
DVSS LDO1-CAP 39 C4019 10U/6.3VS_6
ACZ_SDOUT_AUDIO 5 LDO2-CAP
<14> ACZ_SDOUT_AUDIO SDATA-OUT
R4005 *0_4/S HD_BCLK 6 28 C4020 0.1U/16V_4 +5V_AVDD
<14> BIT_CLK_AUDIO BCLK VREF
7 Close to PIN28
Close to PIN7 C4021 10U/6.3VS_6
LDO3-CAP
C4022 2.2U/6.3V_6 AGND
R4006 75/F_4 HD_SDIN0 8 32 HPOUT_L AGND SHIELD R4007
<14> ACZ_SDIN0 SDATA-IN HPOUT-L (PORT I)
10K/F_4
33 HPOUT_R AGND SHIELD
+3V_DVDD-IO 9 HPOUT-R (PORT I)
DVDD-IO
AGND SHIELD
24 AMP_BEEP AMP_BEEP_L AMP_BEEP_R2 AMP_BEEP_R
ACZ_SYNC_AUDIO 10 LINE2-L 23 C4023 0.1U/16V_4 R4008 100K/F_4 C4024 0.1U/16V_4
<14> ACZ_SYNC_AUDIO SYNC LINE2-R Q4001

Digital
11 DMN53D0L-7

3
<14> ACZ_RST#_AUDIO RESETB
C4025 *0.1U/16V_4 22 R4009 2
AMP_BEEP LINE1-L (PORTC) ACZ_SPKR <11,14>
12 21 C4026 10K/F_4
PCBEEP LINE1-R (PORTC) 0.01U/50V_4
C4027 2.2U/6.3V_6 34

1
CPVEE 20
MIC1-R (PORTB) 19
C4028 2.2U/6.3V_6 CAP- 35 MIC1-L (PORTB)
CBN 31
CAP+ 37 MIC1-VREFO-L 30 MUTE_LED_CNTL_L R4010 *0_4/S AGND
CBP MIC1-VREFO-R MUTE_LED_CNTL <33>
AGND
+3V_DVDD
36
CPVDD 18 MIC_R1 C4029 *4.7U/6.3V_4
C4030 4.7U/6.3V_4 MIC2-R (PORTF) 17 MIC_L1 C4031 4.7U/6.3V_4 R4011 1K/F_4 EXT_MIC_L
MIC2-L (PORTF)
C C
L_SPK+ 42
Close to Pin 34,35,36 SPK-L+ 29 VREFOUT_C EXT_MIC_L
R4012 2.2K_4
Close to CODEC

SPDIF-OUT/GPIO2
L_SPK- 43 MIC2-VREFO
SPK-L- 16
R_SPK- 44 MONO-OUT
SPK-R-
C4032 Close to Speaker EC4001 0.1U/16V_4

R_SPK+
*1U/6.3V_4 Speaker 4 ohm: 40mils CN4001
45

SenseA

SenseB
PVDD1

PVDD2

5
JDREF
SPK-R+ EC4002 0.1U/16V_4
PDB

AGND L_SPK+ L4007 1 2 PBY160808T-600Y-N(60,3A) L_SPK+_R


NC

L_SPK- L4008 1 2 PBY160808T-600Y-N(60,3A) L_SPK-_R 1 EC4003 0.1U/16V_4


ALC3227 x QFN48 R_SPK- L4009 1 2 PBY160808T-600Y-N(60,3A) R_SPK-_R 2
49

41

46

47

48

13

14

15
R_SPK+ L4010 1 2 PBY160808T-600Y-N(60,3A) R_SPK+_R 3 EC4004 0.1U/16V_4
+5V_DVDD 4
L4011 EC4005 0.1U/16V_4
+5V_DVDD Q4002

6
+5V
1 2
HCB1005KF-181T15_4 *DMN601K-7 C4034 C4035 C4036 C4037 SPEAK CONN
SENSE_A

1000P/50V_4

1000P/50V_4

1000P/50V_4

1000P/50V_4
0.1U/16V_4 C4033 Close to Pin 41 R4013 *20K/F_4 3 1 R4014 *0_4/S
AGND
10U/6.3VS_6 C4038
R4015 20K/F_4

2
AGND EXT_MIC_L
+5V_DVDD R4016 22K/F_4
SENSE_A_1 SENSE_A
Close to Pin 46 R4017 39.2K/F_4
0.1U/16V_4 C4039 place to near or under codec
10U/6.3VS_6 C4040
Close to codec C4041
R4018
R4019 *0_8/S
22K/F_4
4.7U/6.3V_4
PD#

HP_EAPD AGND
TP4001
AGND AGND
+1.8V

+3V_DVDD
R4020

B
*2.2K_4 Head Phone out B

Q4003 R4021
2

*MMBT3904 1K/F_4
ACZ_RST#_AUDIO 1 3

PD# EXT_MIC_L L4012 1 2 HCB1608KF-601T10 EXT_MIC_1

<37> VOLMUTE# 1
D4001
2
R4022
Audio JACK ESD
RB500V-40 10K/F_4
R4023 C4042
EXT_MIC_1 *22K_1%_4 1000p/50V_4
LINEOUT_L_C2

LINEOUT_R_C2 AGND AGND

SENSE_A
FOR EMI AGND C4043 1000p/50V_4
AGND SHIELD CN4002
ACZ_SDIN0 EC4006 *33P/50V_4 3
VC4001 VC4002 VC4003 VC4004 HPOUT_L R4025 30_1%_4 LINEOUT_L_C1 L4013 1 2 FCM1005KF-301T03 LINEOUT_L_C2 1
AGND SHIELD
*TVM0G140M900R_90p

*TVM0G140M900R_90p

*TVM0G140M900R_90p

*TVM0G140M900R_90p

ACZ_SDOUT_AUDIO EC4007 *10P/50V_4 HPOUT_R R4026 30_1%_4 LINEOUT_R_C1 L4014 1 2 FCM1005KF-301T03 LINEOUT_R_C2 2

AGND SHIELD 6
ACZ_SYNC_AUDIO EC4008 *10P/50V_4 C4044 1000p/50V_4
AGND
5
4
BIT_CLK_AUDIO EC4009 *33P/50V_4 SENSE_A SENSE_A
Audio_Combo_Jack

7
audio-2sj3095-102211f-6p

AGND AGND AGND AGND EC4010 AGND


*100p/50V_4
A R4027 A
*0_5%_4

AGND

AGND

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5
1A
28 -- Codec ALC3227-CG
Date: Wednesday, March 08, 2017 Sheet 28 of 51
5 4 3 2 1
5 4 3 2 1

HDMI CONN
EMI Solution
29
C_TX2_HDMI+ R4501 180_1%_4 C_TX2_HDMI-

C_TX1_HDMI+ R4502 180_1%_4 C_TX1_HDMI-


D D
C_TX0_HDMI+ R4503 180_1%_4 C_TX0_HDMI-
CN4501
C_IN_CLK R4504 180_1%_4 C_IN_CLK# 20
+3V C_TX2_HDMI+ 1 SHELL1
IN_D0 C4501 0.1u/16V_4 C_TX0_HDMI+ 2 D2+
<2> IN_D0 IN_D0# C4503 C_TX0_HDMI- C_TX2_HDMI- D2 Shield
0.1u/16V_4 3
<2> IN_D0# C_TX1_HDMI+ D2-
R4505 4
IN_D1 C4504 0.1u/16V_4 C_TX1_HDMI+ 1M_4 5 D1+
<2> IN_D1 D1 Shield
IN_D1# C4502 0.1u/16V_4 C_TX1_HDMI- C_TX1_HDMI- 6

2
<2> IN_D1# C_TX0_HDMI+ D1-
7 23
IN_D2 C4505 0.1u/16V_4 C_TX2_HDMI+ 1 3 HDMI_HPD R4506 20K/F_4 8 D0+SHELL2
<2> IN_D2 IN_D2# C4506 C_TX2_HDMI- <2> HDMI_HPD_CON C_TX0_HDMI- D0 Shield
0.1u/16V_4 9
<2> IN_D2# C_IN_CLK D0-
10
IN_CLK C4507 0.1u/16V_4 C_IN_CLK Q4501 11 CK+
<2> IN_CLK IN_CLK# C4508 C_IN_CLK# 2N7002K C_IN_CLK# CK Shield
0.1u/16V_4 12 22
<2> IN_CLK# D4501 CK- SHELL3
BAT54AW-L 13
1 5V_HSMBCK R4507 2.2K_5%_4 14 CE Remote
3 5V_HSMBDT R4508 2.2K_5%_4 HDMI_SCLK 15 NC
+5V_HDMIC DDC CLK
2 HDMI_SDATA 16
C4509 *10p/50V_4 17 DDC DATA
SSM14 spec is 40V 1A H=1.4mm(Max) C4510 *10p/50V_4 18 GND
+5V
40 mils F4500 8V 1.5A 19
HP DET
2 1 +5V_HDMIC 21
+5V SHELL4
HDMI_HPD HDMI_DET_C HDMI CONN
C
HDMI SMBus Isolation Close to HDMI connector C

+3V DGPU_CL_HDMIP R4509 470_1%_4C_TX2_HDMI+


R4510 470_1%_4C_TX2_HDMI- VC4501 C4511 VC4502 C4512
+3V R4511 Q4503 *TVM0G5R5M220R 0.1U/16V_4 *TVM0G5R5M220R 220p/50V_4
5

+3V 470_1%_4C_TX1_HDMI+

3
2.2K_4 2N7002K R4512
2 R4513 470_1%_4C_TX1_HDMI-
4 3 HDMI_SCLK
<2> SDVO_CLK
R4514 470_1%_4C_TX0_HDMI+
Q4502A 2N7002KDW R4515 470_1%_4C_TX0_HDMI-

1
2

R4516 470_1%_4C_IN_CLK U4501 U4502


R4517 *100K_1%_4 R4518 470_1%_4C_IN_CLK# C_TX2_HDMI+ 1 10 C_TX2_HDMI+ C_TX1_HDMI+ 1 10 C_TX1_HDMI+
1 6 HDMI_SDATA C_TX2_HDMI- 2 IN1 NC1 9 C_TX2_HDMI- C_TX1_HDMI- 2 IN1 NC1 9 C_TX1_HDMI-
<2> SDVO_DATA IN2 NC2 IN2 NC2
C4513 *0.1u/16V_4 3 8 3 8
R4519 C_TX0_HDMI+ 4 GND1 GND2 7 C_TX0_HDMI+ C_IN_CLK 4 GND1 GND2 7 C_IN_CLK
+3V Q4502B IN3 NC3 IN3 NC3
2.2K_4 C_TX0_HDMI- 5 6 C_TX0_HDMI- C_IN_CLK# 5 6 C_IN_CLK#
2N7002KDW Close to Q33 IN4 NC4 IN4 NC4
*AZ1045-04F(5V) *AZ1045-04F(5V)

B B

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 29 -- HDMI/AMP HPA022642RTJR 1A

Date: Wednesday, March 08, 2017 Sheet 29 of 51


5 4 3 2 1
5 4 3 2 1

LAN RTL8166EH/RTL8111HSH 30
LAN_XTAL1 R5001 10_5%_4 XTAL1

LAN_LED1
Y5000 TP5002
D LAN_LED2 D
1 3 XTAL2 if ISOLATEB pin pull-low,
TP5003
2 4 the LAN chip will not drive it's PCI-E outputs
(excluding PCIE_WAKE# pin )
25MHZ/30ppm +1.05V_LAN
For SWR mode support RTL8111HSH * Place Cc,Cd,Ce,Cf for RTL8111H(S)
Stuff: La, Ca ,Cb close to each VDD10 pin-- 3, 22, 8 , 30
SI C5001
12p/50V_4
C5002
12p/50V_4
LAN_AMBLED#
+3V
R5002 2.49K_1%_4
Ra LAN_WLED#
For LDO mode support RTL8166EH * Place Cg,Ch for RTL8111H(S) +3V_LAN R5003 0_5%_4 R5004
Rb 1K_5%_4
NA : La, Ca, Cb close to each VDD10 pin-- 22(reserved) R5005 *0_5%_4 LAN_WLED#

LAN_LED1
LAN_LED2
ISOLATEB

XTAL2
XTAL1
RSET
* Place Cq,Cr for RTL8166EH For GbE
close to each VDD10 pin-- 30(reserved) * Place Ra R5006
15K_1%_4
For 10/100

32
31
30
29
28
27
26
25
* Place Ce,Cd for RTL8166EH U5001
Power trace Layout 寬寬> 60mil * Place Rb

AVDD33

AVDD10_2
CKXTAL2
CKXTAL1
LED0
RSET

LED1/GPO
LED2(LED1)
+1.05V_LAN 33
close to each VDD10 pin-- 8 , 30 GND
+1.05V_LAN_REGOUT L5001 1
La 2 4.7uH_3.2x2.5x2 Add 9 GND VIAs with thermal PAD

MDI0+ 1 24 +1.05V_LAN_REGOUT
MDIP0 REGOUT(NC) +1.05V_LAN_REGOUT
PIN3 PIN8 PIN30 PIN22 PIN22 PIN22 PIN30 PIN30 MDI0- 2 23
MDIN0 VDDREG(VDD33) +3V_LAN
+1.05V_LAN 3 22 +1.05V_LAN
MDI1+ 4 AVDD10(NC) DVDD10(NC) 21 PCIE_WAKE#_R R5007 *0_5%_4/S
Ca Cb Cc Cd Ce Cf Cg Ch Cq Cr MDI1- 5 MDIP1 LANWAKEB 20 ISOLATEB
PCIE_WAKE# <4,36>
C5003 C5004 C5005 C5006 C5007 C5008 C5009 C5010 C5011 C5012 MDI2+ 6 MDIN1 ISOLATEB 19 R9047 *0_5%_4/S
MDIP2(NC) PERSTB PCIE_RXN6_LAN_L PLTRST# <4,19,34,36,37>
0.1u/16V_4 4.7U/6.3VS_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 1u/6.3V_4 0.1u/16V_4 *1u/6.3V_4 *0.1u/16V_4 MDI2- 7 18 C5013 0.1u/16V_4
MDIN2(NC) HSON PCIE_RXP6_LAN_L PCIE_RXN6_LAN <12>
8 17
AVDD10_1 RTL8166EH-CG
+1.05V_LAN C5014 0.1u/16V_4
HSOP PCIE_RXP6_LAN <12>

AVDD33(NC)
Update net name

REFCLK_N
MDIN3(NC)
MDIP3(NC)

REFCLK_P
CLKREQB
For GbE
C C

HSIN
HSIP
* Place RTL8111HSH-CG AL008111014
RTL8166EH-CG For 10/100
SI

9
10
11
12
13
14
15
16
R5008 360_5%_4 LAN_AMBLED
+3VLANVCC
* Place RTL8166EH-CG AL008166001
VC5504
*AVLC5S_4
TP8527
MDI3+
LAN_AMBLED# CLK_PCIE_LANN <13>
1 MDI3-
PCIE_TXN6_LAN CLK_PCIE_LANP <13>
+3V_LAN PCIE_TXP6_LAN PCIE_TXN6_LAN <12>
LAN_WLED * <13> PCIE_CLKREQ_LAN# PCIE_TXP6_LAN <12>
+3VLANVCC R5009 360_5%_4

VC5505
*AVLC5S_4
TP8528
LAN_WLED# 1

* Place Ci and Ck, close to each VDD33 pin-- 23, 32 for RTL8166EH For 10/100:Ua Ua For 10/100 stuff only & Close RJ45

5
U5002
* Place Cj and Ck, close to each VDD33 pin-- 11, 32 for RTL8111H(S)

5
MDI1+_1 1 16 MDI1+ MDI3-_1 R5010 *0_5%_4
TD1 TX16 MDI3+_1 R5011 *0_5%_4 C5015 *68p/50V_4
* For surge improvement, place Cm and Cn, close to each MDI1-_1 3 15 TRA_V_DAC MDI2-_1 R5012 *0_5%_4
VDD33 pin-- 11, 32(optional) TD3 CM15 MDI2+_1 R5013 *0_5%_4
LAN_MCTG1 2 14 MDI1-
+3VLANVCC +3V_LAN CT2 TX14
MDI0+_1 6 9 MDI0-
RD6 RX9
B MDI0-_1 TRA_V_DAC B
8 10
RD8 CT10
PIN23 PIN11 PIN32 PIN11 PIN32 LAN_MCTG0 7 11 MDI0+
CT7 RX11

12

13
C5016 C5017 C5018 C5019 C5020 C5021
*4.7U/6.3VS_4 *4.7U/6.3VS_4 *NS681684_10/100 0.01u/50V_4
Ci
*0.1u/16V_4
Cj
0.1u/16V_4 0.1u/16V_4
Ck Cm Cn 1st source:NS681684 DB0LE6LAN20
12

13 CN5001
RJ45
2nd source:N-3110M DB0Y11LAN00 LAN_WLED 9
LAN_WLED# 10 LED_WHT_P A1
LED_WHT_NA2
For Giga:Ub Ub MDI3-_1 8
U5003 MDI3+_1 7 RX1-
MDI2+ 2 23 MDI2+_1 MDI1-_1 6 RX1+ R5014
MDI2- 3 TD1+ MX1+ 22 MDI2-_1 MDI2-_1 5 RX0- *0_5%_6/S
PIN23 PIN23
For SWR mode support RTL8111HSH MDI3- 5 TD1- MX1- 20 MDI3-_1 MDI2+_1 4 TX1-
MDI3+ 6 TD2+ MX2+ 19 MDI3+_1 MDI1+_1 3 TX1+
Stuff Co, Cp 8 TD2- MX2- 17 MDI0-_1 MDI0-_1 2 RX0+ 14
C5022 C5023 MDI0-
4.7U/6.3VS_4 0.1u/16V_4 MDI0+ 9 TD3+ MX3+ 16 MDI0+_1 MDI0+_1 1 TX0- GND1
MDI1- 11 TD3- MX3- 14 MDI1-_1 TX0+ 13
Co Cp MDI1+ 12 TD4+ MX4+ 13 MDI1+_1 GND
TD4- MX4-
TRA_V_DAC 1 24 LAN_MCTG0 Ra R5016 75_1%_4 LAN_AMBLED 11
SI TRA_V_DAC
TRA_V_DAC
TRA_V_DAC
4
7
TCT1
TCT2
TCT3
MCT1
MCT2
MCT3
21
18
LAN_MCTG1
LAN_MCTG2
LAN_MCTG3
Rb
Rc
R5017
R5018
75_1%_4
75_1%_4
LAN_AMBLED# 12 LED_AMB_P B1
LED_AMB_N B2
R5015
*0_5%_6/S
10 15 Rd R5019 75_1%_4
TRA_V_DAC R9058 *0_5%_425 TCT4 MCT4 RJ45_CONN
R9059 *0_5%_4/S GND

For GiGA DB0LL1LAN00 For 10/100:Ra,Rb C5024


BOT:GST5009B LF,DB0Z06LAN00 For Giga:Ra,Rb,Rc,Rd 10p/3KV_1808

FCE :NS892407 ,DB0LL1LAN00

ESD2 ESD1
A MDI3+_1 1 6 MDI2+_1 MDI0-_1 1 6 MDI1-_1 A
2 1 6 5 2 1 6 5
MDI3-_1 2 5 MDI2-_1 +3V_LAN MDI0+_1 2 5 MDI1+_1 +3V_LAN
3 4 3 4
3 4 3 4
*IP4220CZ6_NC *IP4220CZ6_NC

For 10/100:ESD1
For Giga:ESD1,ESD2 PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
C
NB5 30 -- LAN RTL8166EH/RTL8111HSH 1A

Date: Wednesday, March 08, 2017 Sheet 30 of 51


5 4 3 2 1
5 4 3 2 1

+3VS5

USB3.0 R9045 +5V_USBP1

31
U5501
10K_4 +5VS5

5 1 C5501 *220u/6.3V_3528H1.9

+
VIN#1 VOUT
4 2 C5502 470p/50V_4
<31,37> USBPW_ON EN GND
C5505 3
VC5503 1U/6.3V_4 Fault
AVLC5S_4 R9046 10K_4
EM5213AJ-25
D D

USB 2.0/3.0 Combo


UART for Win7 WHQL DEBUG
C5503 0.1U/16V_4
C5504 470P/50V_4 USB 3.0
VC5501 *AVLC5S_4
PV La C5506 1000P/50V_4

+5V_USBP1 2A 1
CN5501
USB3.0 CONN
1 VBUS
USBP1- 1 2MCM2012B900GBEUSBP1-_C 2
<12> USBP1- USBP1+_C 2 D-
USBP1+ 4 3 3
+5V_USBP1 <12> USBP1+ 4 3 D+
5 4 GND
<12> USB30_RX1- L5501 5 SSRX-
6
<12> USB30_RX1+ 6 SSRX+
7
C5507 0.1U/16V_4 USB30_TX1-_C 8 7 GND
<12> USB30_TX1- USB30_TX1+_C 9 8 SSTX-
C5515 0.1U/16V_4
<12> USB30_TX1+ 9 SSTX+
C5509 C5510 C5511 C5512 C5513 C5514

13
12
11
10
22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6

13
12
11
10
USB ESD
USB 2.0/3.0 Combo USBP1-_C
USBP1+_C
USBP2-_C
USBP2+_C

C C5516 0.1U/16V_4 C
C5517 470P/50V_4 USB 3.0

1
VC5502 *AVLC5S_4
PV La C5518 1000P/50V_4

+5V_USBP1 2A 1
CN5502
USB3.0 CONN
1 VBUS
2MCM2012B900GBE USBP2-_C

3
USBP2- 1 2 C5519 C5520
<12> USBP2- USBP2+_C 2 D-
USBP2+ 4 3 3 AZ5315-02F.R7GR AZ5315-02F.R7GR
<12> USBP2+ 4 3 D+
5 4 GND
<12> USB30_RX2- L5502 5 SSRX-
6
<12> USB30_RX2+ 6 SSRX+
7
C5521 0.1U/16V_4 USB30_TX2-_C 8 7 GND
<12> USB30_TX2- USB30_TX2+_C 9 8 SSTX-
C5522 0.1U/16V_4
<12> USB30_TX2+ 9 SSTX+

13
12
11
10
U5503 U5504

13
12
11
10
USB30_RX1- 1 10 USB30_RX1- USB30_RX2- 1 10 USB30_RX2-
USB30_RX1+ 2 IN1 NC1 9 USB30_RX1+ USB30_RX2+ 2 IN1 NC1 9 USB30_RX2+
3 IN2 NC2 8 3 IN2 NC2 8
USB30_TX1-_C 4 GND1 GND2 7 USB30_TX1-_C USB30_TX2-_C 4 GND1 GND2 7 USB30_TX2-_C
USB30_TX1+_C 5 IN3 NC3 6 USB30_TX1+_C USB30_TX2+_C 5 IN3 NC3 6 USB30_TX2+_C
IN4 NC4 IN4 NC4
Update net name
PUSB3FR4 PUSB3FR4

Update net name

B B

Daughter Board
SI
C5523 *0.1U/16V_4
1
18 1
18
Place close to conn 2
2
+3VPCU 17
+5VS5 17
3
16 3
+3V 16
R5509 +3VPCU 4
10K_4 DEEP_PWRLED# 15 4
SATA_LED# 5 15
<12> SATA_LED# USBPW_ON 5
14
<31,37> USBPW_ON 14
6
DEEP_PWRLED#
USB2 <12> USBP3+ PV 4 3 USBP3+_C 13 6
13
3

1 2 USBP3-_C 7
<12> USBP3- L5503 MCM2012B900GBE 7
Q5501 12
PWR_LED# 2 4 3 USBP6+_C 8 12
<37> PWR_LED# DRC5144E0L
CR <12>
<12>
USBP6+
USBP6- L5504
1 2
*MCM2012B900GBE
USBP6-_C 11
9
8
11
C5524 10 9
1

0.1U/16V_4 10 22
22 21
19 21
USBP6+ R5512 *0_4/S USBP6+_C 20 19
USBP6- R5513 *0_4/S USBP6-_C 20
IO1

Update net name DB CONN


A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
C
NB5
1A
31 -- USB SW & TYPE-C -TPS25810
Date: Wednesday, March 08, 2017 Sheet 31 of 51
5 4 3 2 1
5 4 3 2 1

USB3 to SATA VL711 32


TP8502 TP8510

+3V_LDO_VL711

RST#_VL711
BUSYIND
SPI_CLK

PWRIND
+1.2V_SWR

SPI_CS
D RST#_VL711 D
R8501 1 2 *4.7K_4

SPI_Q
SPI_D
+3V_LDO_VL711
+3V_LDO_VL711
R8502 2 1 *0_8/S
+5V_VL711
+5VS5
U8502 +3V_LDO_VL711

49
48
47
46
45
44
43
42
41
40
39
38
37
SPI_CS_
PADGND
GND
SPI_D

PWRIND

RESET_
BUSYIND

VCC33_1
DCVCC12_2
DCVCC12_1
SPI_Q
SPI_CLK

DCVDD12FB
R8504
R8503 *10K_4
+1.2V_SWR *10K_4
1 36
TP8511 GPIO2 2 TESTEN DCGND 35 LX_VL711 1
L8501 2 *4.7uH U8501
TP8505 GPIO1 3 GPIO2 LX 34 * 1 SPI_CS 1 8
GPIO1 DCVDD5 +5V_VL711 TP8524 CS# VCC TP8525

1
SATA_RXP1_VL711 4 33 C8501 * 1 SPI_Q 2 7
SATA_RXN1_VL711 SARXP VCC33_2 GPIO6_VIA +3V_LDO_VL711 TP8523 SO HOLD# SPI_CLK
5 32 3 6 1
6 SARXN GPIO6 31 GPIO7_VIA *10U/6.3V/X5R_6 4 WP# SCLK 5 SPI_D 1
+1.2V_SWR

2
SATA_TXN1_VL711 7 SARXVDD12 *VL711 GPIO7 30 GPIO5_VIA TP8508 GND SI
SATA_TXP1_VL711 8 SATXN GPIO5 29 GPIO8_VIA TP8509 *MX25L512EMI-10G *
TP8526
9 SATXP GPIO8 28 GPIO9_VIA TP8512 *
+1.2V_SWR SATXVDD12 GPIO9
10 27
R8505 *11.8K/F_6 11 MVDD12_1 VDD12I 26
12 REXT DM 25 USBP-_VIA C8502
+5V_VL711 LDPVDD5 DP USBP+_VIA

LDOVDD33O

U3RXVDD12
U3TXVDD12
*0.1U/16V/X7R_4

MVDD12_2

U3RXGND
USB3RXN
USB3RXP
USB3TXN
USB3TXP
C8503 RST#_VL711 D8501 *TVUFB0201AC0

OSCXO
OSCXI

VCCU
*4.7U/10V/X5R_6

13
14
15
16
17
18
19
20
21
22
23
24
GPIO6_VIA R8564 *0_5%_4 +3V_LDO_VL711

GPIO7_VIA R9044 *0_5%_4

XTALO_VIA
+3V_LDO_VL711 +3V_LDO_VL711 ZERO_PWR_ODD <35,37>

XTALI_VIA

+1.2V_SWR

+1.2V_SWR
C8504
C C8505 *0.1U/16V/X7R_4 C
*4.7U/10V/X5R_6
SATA_HOST(Diff. Z = 85~115 ohm,SE=40 ohm)
<12> USB30_RX3-
C8506 *0.1U/16V/X7R_4 USB30_RX2-_R +1.2V_SWR Group Rf
C8509 *0.1U/16V/X7R_4 USB30_RX2+_R
<12> USB30_RX3+ USB30_TX2-_R SATA_TXP1_VL711 SATA_TXP2_ODD_COLAY
C8507 *0.1U/16V/X7R_4 C8508 R8510 *0_5%_4
<12> USB30_TX3- USB30_TX2+_R SATA_TXN1_VL711 SATA_TXN2_ODD_COLAY SATA_TXP2_ODD_COLAY <35>
C8510 *0.1U/16V/X7R_4 *0.1U/16V/X7R_4 R8512 *0_5%_4
<12> USB30_TX3+ SATA_TXN2_ODD_COLAY <35>
SATA_RXN1_VL711 R8514 *0_5%_4 SATA_RXN2_ODD_COLAY
SATA_RXN2_ODD_COLAY <35>
R8524 *0_5%_4/S USBP+_VIA SATA_RXP1_VL711 R8516 *0_5%_4 SATA_RXP2_ODD_COLAY
<12> USBP8+ SATA_RXP2_ODD_COLAY <35>
R8525 *0_5%_4/S USBP-_VIA
<12> USBP8-

+1.2V_SWR

C8515 C8516 C8517 C8518


*0.1U/16V/X7R_4 *0.1U/16V/X7R_4 *0.1U/16V/X7R_4 *0.1U/16V/X7R_4 X'tal 25MHz

SI XTALI_VIA

Y5001
+3V_LDO_VL711 +5V_VL711
1 3 XTALO_VIA
2 4

*25MHZ/30ppm
B B
C8519 C8524
*15P/50V_4 *15P/50V_4
C8520 C8523
*0.1U/16V/X7R_4 *0.1U/16V/X7R_4 C8521 C8522
*0.1U/16V/X7R_4 *4.7U/10V/X5R_6

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
C
NB5
1A
32 -- USB SW & TYPE-C -TPS25810
Date: Wednesday, March 08, 2017 Sheet 32 of 51
5 4 3 2 1
5 4 3 2 1

KEYBOARD Con.
<37> MY[0..17]
MY[0..17]

MX[0..7]
MX1
MX7
MX6
32
31
30
CN6001
KB CONN

32
31
33
33
Touch Pad Connector
4
Q6001A
2N7002KDW
3 TP_SMB_CLK
33
<37> MX[0..7] 30 <10,17,18,26> SMB_RUN_CLK
MY9 29
MX4 28 29 R6001 4.7K_4
MX5 27 28 Dual

5
MY0 26 27
26 +3V +3VSUS
MUTE_LED_CNTL_R1 MX2 25
25

2
D MX3 24 R6002 4.7K_4 D
MY5 23 24
22 23 1 6 TP_SMB_DATA

3
MY1
2 22 <10,17,18,26> SMB_RUN_DAT
Q6002 MX0 21
<28> MUTE_LED_CNTL 21
2N7002K MY2 20
MY4 19 20 Q6001B
MY7 18 19 2N7002KDW

1
R6003 MY8 17 18
10K_4 MY6 16 17
MY3 15 16 C6001 0.1U/16V_4
15 +3VSUS DFFC08FR115
MY12 14 +3VSUS R6004 4.7K_4 TPCLK
MY13 13 14 R6005 4.7K_4 TPDATA
MY14 12 13 196332-08041-3-8p-l
MY11 11 12
MY10 10 11 C6002 10P/50V_4
MY15 9 10 1 TP_CONN_8P
MY16 8 9 L6001 1 2 HCB1005KF-330T30 TPDAT-1 2 1
8 <37> TPDATA 2
MY17 7 <37> TPCLK L6002 1 2 HCB1005KF-330T30 TPCLK-1 3
6 7 C6003 10P/50V_4 4 3
R6006 200/F_6 CAPSLED#_R 5 6 TP_SMB_CLK 5 4
<37> CAPSLED# 5 5
MUTE_LED_CNTL_R1 R6007 200/F_6 MUTE_LED_CNTL_R 4 TP_SMB_DATA 6
3 4 TP_L 7 6
2 3 TP_R 8 7
LED_PW 1 2 34 9 8
+3V 1 34 9
C6004 C6005 10
10
*10P/50V_4 *10P/50V_4
50690-03201-v01-32p-l CN6002
DFFC32FR061 CN6003 dummy pin, please confirm need GND
TP_R 5
1
C 2 C
TP_L 3
4
6
TP Button_CONN

MY5 C6006 220P/50V_4


MY6 C6007 220P/50V_4

KEYBOARD PULL-UP
MY3 C6008 220P/50V_4
MY7 C6009 220P/50V_4 +5V

RP6001 MY8 C6010 220P/50V_4


FAN C6011 10U/6.3VS_6
+3VPCU 10 1 MY4 MY9 C6012 220P/50V_4
MY7 9 2 MY13 MY10 C6013 220P/50V_4 C6014 0.1U/16V_4
MY8 8 3 MY12 MY11 C6015 220P/50V_4
MY9 7 4 MY11

6
MY10 6 5 FAN1_PWM C6016 *220P/50V_4
<37> FAN1_PWM 4
+3VPCU *10P8R-8.2K MY1 C6019 220P/50V_4 FAN1 FAN1SIG C6017 *220P/50V_4
MY2 C6018 220P/50V_4 3
<37> FAN1SIG 2
RP6002 MY4 C6020 220P/50V_4
10 1 MY1 MY0 C6021 220P/50V_4 1
MY6 9 2 MY5

5
MY3 8 3 MY2 MX4 C6022 220P/50V_4 R6011 4.7K_4 FAN CONN
+3V
MY15 7 4 MY0 MX6 C6023 220P/50V_4
MY14 6 5 MX3 C6024 220P/50V_4
MX2 C6025 220P/50V_4
+3VPCU *10P8R-8.2K
Close to EC Side
R6012 *8.2K_4 MY16 MX7 C6026 220P/50V_4
B R6013 *8.2K_4 MY17 MX0 C6027 220P/50V_4 B
MX5 C6028 220P/50V_4
MX1 C6029 220P/50V_4

MY12 C6030 220P/50V_4


MY13 C6031 220P/50V_4
MY14 C6032 220P/50V_4
MY15 C6033 220P/50V_4
MY16 C6034 220P/50V_4
MY17 C6035 220P/50V_4

Power Button
CN6004
5
+3VPCU 1
<37> LID_EC# 2
NBSWON1# 3
<37> NBSWON1# 4
A 6 A
Power Button_CONN

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5
1A
33 -- KB/TP/FAN
Date: Wednesday, March 08, 2017 Sheet 33 of 51
5 4 3 2 1
5 4 3 2 1

TPM (2.0) +3V

D LAD0 R6501 *0_4 LAD0_T


PN:AL009665K05
26
U6501
10
C6503 *0.1U/16V_4
+3V

+3V
34 D
<10,36,37> LAD0 LAD1_T 23 LAD0 VDD_1 19
LAD1 R6502 *0_4
<10,36,37> LAD1 LAD2_T 20 LAD1 VDD_2 24
LAD2 R6506 *0_4
<10,36,37> LAD2 LAD3_T LAD2 VDD_3
LAD3 R6503 *0_4 17 5 C6504 C6501 C6502 R6504
<10,36,37> LAD3 CLK_PCI_TPM_R 21 LAD3 VSB
<10> CLK_PCI_TPM R6505 *0_4 *0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4 *4.7K_4
LCLK 4
LFRAME# R6507 *0_4 LFRAME#_T 22 GND_1 11
<10,36,37> LFRAME# LFRAME# GND_2
16 18
<4,19,30,36,37> PLTRST# 28 LRESET# GND_3 25 TPM_PP
SERIRQ 27 LPCPD# GND_4
<10,37> SERIRQ SERIRQ 6 R6508 *4.7K_4 +3V
9 GPIO 2
TEST/BADD GPIO2 R6509
15 7 TPM_PP *0_4
CLKRUN# PP 8
1 TESTI
3 NC_1 13
12 NC_2 XTALI/32K IN 14
NC_3 XTALO
*SLB9665 T2.0

C C

H1 H25 H24 H30


*H-TC276IBC197D154P2 *H-TC276IBC197D154P2 h-tc237ic170d130pt *PAD-BALL276-NP
1

1
H26 H27
*H-TC276IBC197D154P2 *H-TC276IBC197D154P2 H7 H8
*H-C237D130P2 *H-IC276BC315D154PB
1

1
B B

H28 H29
*H-TC276IBC197D154P2 *H-TC276IBC197D154P2 H4
*PAD-BALL276-NP H32 H2 H3 H31
*H-CT315B400SI178D158P2 *H-C237D130P2 *H-IC276BC315D154PB *H-IC276BC315D154PB
1

1
PAD1 PAD2
*SPAD-RE315X59NP *SPAD-RE537X138NP

1
A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
B
NB5
1A
34 -- TPM/G-Sensor/IR CAM
Date: Wednesday, March 08, 2017 Sheet 34 of 51
5 4 3 2 1
5 4 3 2 1

<2,4,10,11,12,13,14,15,17,18,26,27,28,29,30,31,33,34,37,43,45> +3V
<26,27,28,29,33,36,45>
<6,13,31,33,36,37,38,39>
+5V
+3VPCU
2nd SATA SSD

<12,35>

<12,35>
SATA_TXP2

SATA_TXN2
Group
R8553

R8552
Ra
*0_5%_4

*0_5%_4
SATA_TXP2_SDD_COLAY_R

SATA_TXN2_SDD_COLAY_R

SATA_RXN2_SDD_COLAY_R
CN7050
100 mils
SATA_TXP2_SDD_COLAY_R
Group
R8545
Rc
*0_5%_4 SATA_TXP2_SDD_COLAY
35
<12,35> SATA_RXN2 R8551 *0_5%_4
1 NGFF 2 +3V_SSD2 1.4A R7050 *0_8/S SATA_TXN2_SDD_COLAY_R R8544 *0_5%_4 SATA_TXN2_SDD_COLAY
D SATA_RXP2_SDD_COLAY_R CONFIG3 3V3#1 +3V D
<12,35> SATA_RXP2 R8550 *0_5%_4 3 4
5 GND#1 3V3#2 6 SATA_RXN2_SDD_COLAY_R R8543 *0_5%_4 SATA_RXN2_SDD_COLAY
7 GND#2 PWR_ON/OFF 8 C7052 C7051 C7050
9 USB_DP W_DISABLE 10 0.01U/50V_4 4.7U/6.3V_4 SATA_RXP2_SDD_COLAY_R R8542 *0_5%_4 SATA_RXP2_SDD_COLAY
USB_DN LED 0.1U/16V_4
11
Group Rb GND#3
CS PS
KEY B
<12> SATA_TXP3
R8537 0_5%_4 SATA_TXP2_SDD_COLAY
21 20 +3V
Group Rd
R8536 0_5%_4 SATA_TXN2_SDD_COLAY 23 CONFIG0 GPIO_5 22
<12> SATA_TXN3 25 WAKE_OUT_WWAN GPIO_6 24 SATA_TXP2_ODD_COLAY_R
R8557 0_5%_4
SATA_RXN2_SDD_COLAY 27 BODYSAR_DET GPIO_7 26 <12,35> SATA_TXP2
<12> SATA_RXN3 R8535 0_5%_4
29 GND#4 GPIO_10 28 R7051 R8556 0_5%_4 SATA_TXN2_ODD_COLAY_R
SATA_RXP2_SDD_COLAY 31 NC#1 GPIO_8 30 <12,35> SATA_TXN2
<12> SATA_RXP3 R8534 0_5%_4
33 NC#2 SIM_RST 32 10K_4 R8555 0_5%_4 SATA_RXN2_ODD_COLAY_R
GND#5 SIM_CLK <12,35> SATA_RXN2
35 34
37 NC#3 SIM_IO 36 R8554 0_5%_4 SATA_RXP2_ODD_COLAY_R
NC#4 SIM_PWR <12,35> SATA_RXP2
39 38 R7052 *0_4
SATA_RXP2_SDD_COLAY SATA_RXP3_SSD GND#6 NC#11 DEVSLP2 <12>
C8529 0.01u/50V_4 41 40
SATA_RXN2_SDD_COLAY C8528 0.01u/50V_4 SATA_RXN3_SSD 43 NC#5 GPIO_0 42
SATA_TXN2_SDD_COLAY C7053 0.01u/50V_4 SATA_TXN3_SSD
45
47
NC#6
GND#7
GPIO_1
GPIO_2
44
46
G35 added Group Re
SATA_TXP2_SDD_COLAY C7054 0.01u/50V_4 SATA_TXP3_SSD 49 NC#7 GPIO_3 48
51 NC#8 GPIO_4 50 SATA_TXP2_ODD_COLAY_R R8529 0_5%_4 SATA_TXP2_ODD_COLAY
53 GND#8 NC#12 52
55 NC#9 NC#13 54 SATA_TXN2_ODD_COLAY_R R8527 0_5%_4 SATA_TXN2_ODD_COLAY
57 NC#10 NC#14 56
59 GND#9 NC#15 58 SATA_RXN2_ODD_COLAY_R R8528 0_5%_4 SATA_RXN2_ODD_COLAY
61 ANT_TUNE0 NC#16 60
63 ANT_TUNE1 COEX3 62 SATA_RXP2_ODD_COLAY_R R8526 0_5%_4 SATA_RXP2_ODD_COLAY
65 ANT_TUNE2 COEX2 64
67 ANT_TUNE3 COEX1 66
R7057 *0_4/S PEDET2 69 Reset# SIM_DET 68
71 CONFIG_1 SSCLK 70 R7054 *0_8/S
GND#10 3V3#3 +3V
73 72
75 GND#11 3V3#4 74
CONFIG_2 3V3#5

76

77

78

79
WWAN_NGFF CONN

76

77

78

79
ngff-nfsb0-s6710-tph4-kb-smt
EC7052 EC7051 EC7050
DFHS75FR210 470p/50V/X7R_4 10U/6.3V_6 10U/6.3V_6

C C

SATA ODD +VIN

+5V

CN7001 +3V

1
S1 2 SATA_TXP2_ODD_C C7001 0.01u/50V_4 SATA_TXP2_ODD_COLAY
TXP 3 SATA_TXN2_ODD_C SATA_TXN2_ODD_COLAY SATA_TXP2_ODD_COLAY <32>
C7002 0.01u/50V_4 R7002 C7005
14 TXN SATA_TXN2_ODD_COLAY <32>
1M_5%_4 0.1u/16V_4
14 5 SATA_RXN2_ODD_C C7003 0.01u/50V_4 SATA_RXN2_ODD_COLAY
RXN SATA_RXN2_ODD_COLAY <32>
16 6 SATA_RXP2_ODD_C C7004 0.01u/50V_4 SATA_RXP2_ODD_COLAY R7001
SATA_RXP2_ODD_COLAY <32>

2
16 RXP

3
8 ZERO_ODD_DP# 10K_5%_4 R7003
DP ZERO_ODD_DP# <12>
9 2M_5%_4 Q7002
2

S7 +5V_1 10 2 PJA3404
P1 +5V_2 11 ZERO_ODD_DA# +5V_ODD 1 3
17 MD 1 ODD_EJECT# <37>
17 GND1 4 Q7001

1
15 GND2 7
15 GND3 2N7002K
12
GND4 13 ODD_DET
P6 GND5 C7006
SATA ODD 0.022u/25V_4
2.5A = 100mil
+5V_ODD +5V_ODD

C7007 C7008 C7009 C7010 C7011


10U/6.3VS_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4
PV ACIN <37,38>
R7100
5

22_5%_8
B B
ODD_DET 4 3
<12> ODD_DET
2N7002KDW Q7100A
ZERO_PWR_ODD <32,37>
2

3
1 6 ZERO_PWR_ODD 2 Q7003
2N7002KDW Q7100B 2N7002K

1
A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 35 -- SSD_ODD_EMMC_ASM1153 1A
1A
Date: Wednesday, March 08, 2017 Sheet 35 of 51
5 4 3 2 1
5 4 3 2 1

HDD 36
SATA HDD
HDD1 SATA_TXP1_C C7504 0.01U/50V_4
SATA_TXP1 <12>
D SATA_TXN1_C C7505 0.01U/50V_4 D
SATA_TXN1 <12>
1
GND1 2 SATA_TXP1_C SATA_RXN1_C C7506 0.01U/50V_4
TXP SATA_RXN1 <12>
3 SATA_TXN1_C
TXN 4 SATA_RXP1_C C7507 0.01U/50V_4
GND2 SATA_RXP1 <12>
5 SATA_RXN1_C
RXN 6 SATA_RXP1_C
RXP 7
GND3

8
3V01 9
3V02 10 R8563 *0_4/S DEVSLP0
3V03 DEVSLP0 <12>
11
GND4 12
GND5 13
24 GND6 14
hole2 5V01 +5V
15
23 5V02 16
hole1 5V03 17
GND7 18
RSVD 19 GPP_D9_R R8562 *0_4/S
GND8 GPP_D9 <14>
20
12V01 21
12V02 22
12V03 +5V
C7510 *10U/6.3VS_6

C166MP-12201-L
C7511 10U/6.3VS_4

C7512 0.1U/16V_4
C C

WLAN
+3VPCU +3VS5 +3V_WLAN_P
Mini Card
WLAN/BT(Option) +3V_WLAN_P
R7515
100mils +3V_WLAN_P Remove Net RF_LINK# and need check if
10K_4
Ra and Rb can be NI
1

Q7502 C7513 C7514 C7515 C7516 CN7503


2
R7516 200K_4 PJA3415 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 10U/6.3VS_4 Ra
1
NGFF 2 R7517 4.7K_4
GND_1 3.3Vaux_1 +3V_WLAN_P
3 4
100mils <12> USBP4+ USB_D+ 3.3Vaux_2
3

5 6 WLAN_LED# R7518 *0_4/S


+3V_AOCS <12> USBP4- USB_D- LED#1
7 8
3

B C7517 B
2 9 GND_2 PCM_CLK 10
<37> EC_AOCS
Q7503
0.022U/25V_4 C7518 11 SDIO CLK(O) PCM_SYNC 12
Rb
2N7002K SDIO CMDIO) PCM_IN
13 14
*0.1U/16V_4 15 SDIO DAT0(IO) PCM_OUT 16
1

17 SDIO DAT1(IO) LED#2 18


19 SDIO DAT2(IO) GND_11 20
21 SDIO DAT3(IO) UART Wake 22
23 SDIO Wake(I) UART Rx
SDIO Reset BT_OFF <14>

5
+3V_WLAN_P

Support Wake Function(Reserve) R7519 *10K_4 32


4
Q7504A
3 INT_BT_OFF#
2N7002KDW
33 UART Tx 34
GND_3 UART CTS RF_OFF_PCH <4>
2

2
35 36
<12> PCIE_TXP5_WLAN PETp0 UART RTS
37 38
<12> PCIE_TXN5_WLAN PETn0 Clink RESET
39 40 1 6 INT_RF_OFF#
41 GND_4 CLink DATA 42 Q7504B 2N7002KDW
<12> PCIE_RXP5_WLAN PERp0 CLink CLK
3 1 MINICAR_PME# 43 44
<4,30> PCIE_WAKE# <12> PCIE_RXN5_WLAN PERn0 COEX3
Q7505 *DRC5144E0L 45 46
47 GND_5 COEX2 48
<13> CLK_PCIE_WLANP REFCLKP0 COEX1
+3V_WLAN_P
0302 Reserved the MOSFET at CLKREQ# <13> CLK_PCIE_WLANN
49
REFCLKN0 SUSCLK(32KHz)
50
51 52 PLTRST#
even the current leakage test passed REQ_WLAN# 53 GND_6 PERST0# 54 INT_BT_OFF#
PLTRST# <4,19,30,34,37>
R7520 10K_4
for HP requested MINICAR_PME# 55 CLKREQ0# W_DISABLE2# 56 INT_RF_OFF# R7521 10K_4
PEWake0# W_DISABLE1# +3V_WLAN_P
57 58
R7522 *10K_4 59 GND_7 NFC I2C SM DATA 60
For EMI Suggestion 61 PETp1 NFC I2C SM CLK 62
CLK_24M_DEBUG EC7504 *33P/50V_4 63 PETn1 ALERT# 64 LAD0
GND_8 RESERVED LAD0 <10,34,37>
R7523 *0_4 65 66 LAD1
PERp1 UIM_SWP/PERST1# LAD1 <10,34,37>
67 68 LAD2
2

PCIE_WAKE# PERn1 UIM_POWER_SNK LAD2 <10,34,37>


EC7505 *220P/50V_4 69 70 LAD3 LAD3 <10,34,37>
3 1 REQ_WLAN# 71 GND_9 UIM_POWER_SRC 72
<13> PCIE_CLKREQ_WLAN# <10> CLK_24M_DEBUG Reserved1 3.3Vaux_3

GND_12
GND_13
A Q7506 *2N7002K <10,34,37> LFRAME# LFRAME# 73 74 A
75 Reserved2 3.3Vaux_4
GND_10

79
78
R7524 *0_4/S WLAN_NGFF CONN (E-Key)

79
78
76
77
PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5
1A
36 -- HDD/WLAN(NGFF)
Date: Wednesday, March 08, 2017 Sheet 36 of 51
5 4 3 2 1
5 4 3 2 1

+3VPCU_KBC R2100
TP8522

37

+3V_ECACC

+3V_VSTBY
+3V +3VPCU_KBC 2.2_5%_6 EC_WRST 1
C2001 0.1U/16V_4 +3VPCU
C2002 0.1U/16V_4 +3VPCU
C2003 0.1U/16V_4 C2004 0.1U/16V_4 Q2001 R2001 4.7K_4 *
+3V

3
C2005 0.1U/16V_4 METR3904-G
C2006 0.1U/16V_4 D2100 C2100 2 OVT_DETC 2 1 EC_PWROK R2002

114
121

106

127
C2007 0.1U/16V_4 0.1U/16V_4 D2001 *RB500V-40

11
26
50
92

74
*PDZ5.6B
U2000 100K_4

1
VCC

VSTBY_FSPI

AVCC
VSTBY_1
VSTBY_2
VSTBY_3
VSTBY_4
VSTBY_6

VSTBY_5

2
D LAD0 10 84 EC_AOCS R2003 10K_4 EC_WRST D
<10,34,36> LAD0 LAD0 EGCLK/WUI27/GPE3 EC_AOCS <36> +3VPCU
LAD1 9 83 VRON
<10,34,36> LAD1 LAD1 EGCS#/WUI26/GPE2 VRON <43> THRM_ALERT_HW#1
LAD2 8 C2008
<10,34,36> LAD2 LAD2 SUSACK#_EC
LAD3 7 82 TP8515
<10,34,36> LAD3 LAD3 EGAD/WUI25/GPE1
<4,19,30,34,36> PLTRST# PLTRST# 22 Open Drain need pu high 1U/6.3V_4
CLK_24M_KBC 13 LPCRST#/WUI4/GPD2 56 MY16
<10> CLK_24M_KBC LPCCLK KSO16/SMOSI/GPC3 MY16 <33>
LFRAME# 6 57 MY17 MY17 <33>
<10,34,36> LFRAME# LFRAME# KSO17/SMISO/GPC5 Q2002 *2N7002K
PV +3V
DC_PROCHOT_OFF
10K_4 R2004 TP2001 17
LPCPD#/WUI6/GPE6 LPC L80HLAT/BAO/WUI24/GPE0
L80LLAT/WUI7/GPE7
19
20
CRY1 R2005
EC_PWROK
*0_4/S AC_PRESENT_EC
EC_PWROK <4>
<4> 3 1
DGPU_OVT# <20> H_PROCHOT#
*0_4 R2006 DC_PROCHOT_OFF_R 126
5 GA20/GPB5 ODD_EJECT#
20160524 SERIRQ GPIO 122

2
<10,34> SERIRQ SERIRQ DTR1/SBUSY/GPG1/ID7 ODD_EJECT# <35>
SIO_EXT_SMI# 15 99 PCI_SERR#
<10> SIO_EXT_SMI# ECSMI#/GPD4 HMOSIGPH6/ID6 PCI_SERR# <10> ACIN <35,37,38> DGPU_PWROK <12,46,48,49>
SIO_EXT_SCI# 23 98 HWPG

3
<14> SIO_EXT_SCI# ECSCI#/GPD3 HMISO/GPH5/ID5 HWPG <4,39,40,41>
EC_WRST 14 97 ACIN *AVLC5S_4 VC2001 R2007 4.7K_4 H_PROCHOT#_EC 2 Q2003 C2009
WRST# HSCK/GPH4/ID4 +1.0V
EC_RCIN# 4 96 DGPU_PROCHOT_EC# TP2002 2N7002K *47P/50V_4
<10> EC_RCIN# KBRST#/GPB6 HSCE#/WUI19/GPH3/ID3
GPUT_CLK 16 95 MBDATA3 R2008
<20> GPUT_CLK PWUREQ#/BBO/GPC7 CTX1/WUI18/GPH2/SMDAT3/ID2 TP2003 DGPU_PROCHOT_EC# <20,37>

2
94 MBCLK3 C2010 220P/50V_4

1
CRX1/WUI17/GPH1/SMCLK3/ID1 93 CLKRUN# TP2004 *10K_4
CLKRUN#/WUI16/GPH0/ID0 CLKRUN# <10> For Gsensor 3 1
SUSWARN#_EC PM_THRMTRIP# <2>
BATSHIP 113 3 H_PECI (50ohm)
<38>
<33>
BATSHIP
LID_EC#
LID_EC#

TPDATA
123

86
CRX0/GPC0
TMA0/GPB2 IT8987 GPH7 TP8519

EC_PECI (50ohm)
Route on microstrip only
Spacing >18 mils
Q2004
METR3904-G
<33> TPDATA
TPCLK 85 PS2DAT0/TMB1/GPF1 117 EC_PECI_R R2009 33_4 Trace Length: <0.5 iches Trace Length: 0.4~6.125 iches
<33> TPCLK PS2CLK0/TMB0/GPF0 SMCLK2/WUI22/GPF6/PECI EC_PECI <2>
SUSB# 88 118 GPUT_DATA
<4> SUSB# DSWROK_EC 87 PS2DAT1/RTS0#/GPF3 SMDAT2/WUI23/GPF7 GPUT_DATA <20> For GPU thermal Adapter select for EC
PS/2 110
SI
<4> DSWROK_EC PS2CLK1/DTR0#/GPF2 SMCLK0/GPB3 MBCLK <38>
SLP_SUS#_EC 90 111
<4> SLP_SUS#_EC
89 PS2DAT2/WUI21/GPF5 SMDAT0/GPB4 MBDATA <38> for Battery charge/charge Ra Rb
<15,41,42> SLP_SUS_ON PS2CLK2/WUI20/GPF4 SM_BUS SMCLK1/GPC1
115
MBCLK2 <10,18,26> ADAPTER_SEL_EC R2011
For Touch-Pad 116 for DDR Thermal IC +3VPCU R2010 10K_4 2.94K_1%_4
SMDAT1/GPC2 MBDATA2 <10,18,26>

RSMRST# 119 ADAPTER_SEL_EC BOM


C <4> RSMRST#
MAINON 33 DSR0#/GPG6 Ra Rb C
<40,41,42,45> MAINON GINT/CTS0#/GPD5
UART 24 PWR_LED#
D2002 PWM0/GPA0 PWR_LED# <31>
25 MBATLED0# 150W
1 2 108 PWM1/GPA1 28 AC_LED_ON#
MBATLED0# <38> 10K(CS31002FB26) 100K(CS41002FB28) 3V
<11> GPIO33_EC RXD/SIN0/GPB0 PWM2/GPA2 AC_LED_ON# <38>
TS_ON 109 29 KB_LED_EN#
<27> TS_ON TXD/SOUT0/GPB1 PWM3/GPA3 TP2005
30 FAN1_PWM
RB500V-40 PWM4/GPA4 31 FAN2_PWM
FAN1_PWM <33> 120W 10K(CS31002FB26) 21.5K 2.25V
Close to BIOS USBPW_ON# 125 PWM5/GPA5 32 VOLMUTE#
TP2006
<31> USBPW_ON
R2012 15/F_4 BIOS_SPI_CLK 105 SSCE1#/GPG0 PWM6/SSCK/GPA6 34 CAPSLED#
VOLMUTE# <28> 90W 10K(CS31002FB26) 8.33K 1.5V
<10> PCH_SPI1_CLK_R FSCK/GPG7 PWM7/GPA7 CAPSLED# <33>
BIOS_RD# 103
65W 10K(CS31002FB26) 2.94K(CS22942FB01) 0.75V DIS
<10> PCH_SPI1_SO_R R2013 15/F_4
BIOS_WR# FMISO/GPG5 FLASH PWM TACH0/GPD6
47 FAN1SIG
FAN1SIG <33>
R2014 15/F_4 102 48 R2015 *0_4/S EC_RTC_RST 45W
<10> PCH_SPI1_SI_R
R2016 15/F_4 BIOS_CS# 101 FMOSI/GPG4 TACH1/TMA1/GPD7 EC_RTC_RST <13> NC 10K(CS31002FB26) 0V UMA
<10> PCH_SPI_CS0#_R FSCE#/GPG3
S5_ON 100
<39> S5_ON SSCE0#/GPG2 77 GPU_OVERT#_EC TP2007
<33> MY0
MY0
MY1
36
37 KSO0/PD0
DAC1/GPJ1
DAC0/GPJ0
76 EC_NVVDD_CORE1_EN TP2008 Adapter Type check +3VPCU
Change to 1SS355 as Current loss
<33> MY1 KSO1/PD1

1
MY2 38 120 TEMP_MBAT
<33> MY2 KSO2/PD2 TMR0/WUI2/GPC4 H_PROCHOT#_EC TEMP_MBAT <38>
MY3 39 124 D2003
<33> MY3 KSO3/PD3 TMR1/WUI3/GPC6
MY4 40 *1SS355
<33> MY4 KSO4/PD4
MY5 41
<33> MY5 KSO5/PD5
MY6 42 107 NBSWON1#
<33> MY6 NBSWON1# <33>

2
MY7 43 KSO6/PD6 PWRSW/GPE4 18 SUSC# AD_TYPE R2017 2K/F_4 R2018 100/F_4
<33> MY7 KSO7/PD7 RI1#/WUI0/GPD0 SUSC# <4> AD_ID <38>
MY8 44 WAKE UP 21 DNBSWON#
<33> MY8 KSO8/ACK# RI2#/WUI1/GPD1 DNBSWON# <4>

1
MY9 45 KBMX
<33> MY9 KSO9/BUSY
<33> MY10 MY10 46 35 SUSON SUSON <40,42,45> D2004 C2011 R2019
MY11 51 KSO10/PE WUI5/GPE5 112 LAN_POWER 7.15K/F_4 C2012
<33> MY11 KSO11/ERR# RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 LAN_POWER <45> PDZ5.6B
MY12 52 0.1U/25V_4 100P/50V_4
PV
<33> MY12 KSO12/SLCT
<33> MY13 MY13 53

2
MY14 54 KSO13
<33> MY14 KSO14
<33> MY15 MY15 55 66 GPI0 R9060 10K_4 +3V
MX0 58 KSO15 ADC0/GPI0 67 AD_TYPE
<33> MX0 KSI0/STB# ADC1/GPI1 SYS_I
B MX1 59 68 SYS_I <38> B
<33> MX1 KSI1/AFD# ADC2/GPI2 AD_AIR GPIO33_EC
MX2 60 A/D D/A 69 TP2100 +3V R2020 *10K_4
<33> MX2 KSI2/INIT# ADC3/GPI3 GPUT_CLK
MX3 61 70 R2021 *0_4/S R2022 4.7K_4 +3VPCU R2023 10K_4 NBSWON1#
<33> MX3 KSI3/SLIN# ADC4/WUI28/GPI4 THERMISTOR <6> GPUT_DATA
MX4 62 71 R2024 4.7K_4 R2025 4.7K_4 MBCLK
<33>
<33>
<33>
MX4
MX5
MX6
MX5
MX6
63
64
KSI4
KSI5
KSI6
ADC5/WUI29/GPI5
ADC6/WUI30/GPI6
ADC7/WUI31/GPI7
72
73
THERMISTOR_SHDN
ADAPTER_SEL_EC THERMISTOR_SHDN
EC_SRTC_RST
<6>
<13>
R2027 *4.7K_4 DGPU_PROCHOT_EC#
R2026
R2028
4.7K_4
47K/F_4
MBDATA
LID_EC#
S5_ON
SI
MX7 65 R2029 *4.7K_4 MBCLK2 R2030 10K_4
<33> MX7 KSI7 R2031 *4.7K_4 MBDATA2
81 EMU_LID
DAC5/RIG0#/GPJ5 THRM_ALERT_HW#1 EMU_LID <27>
TP8516 128 CLOCK 80
VCORE

GPJ6 DAC4/DCD0#/GPJ4
VSS_2

VSS_3
VSS_4
VSS_5
VSS_1

ZERO_PWR_ODD 2 79 FAN2SIG TP2010 R2032 100K_4 VRON R2033 10K_4 DNBSWON#


AVSS

<32,35> ZERO_PWR_ODD GPJ7 DAC3/GPJ3 +3VS5


78 TP_EN TP8514 R2034 100K_4 MAINON
DAC2/GPJ2 R2035 100K_4 SUSON
+3V_ECACC 1
L2001 2
*HCB1608KF-181T15_S0_6/S+3VPCU
1

27
49
91
104

75

12

L2002 1 2*HCB1608KF-181T15_S0_6/S AJ089870F01

IT8987E/BX C2013 C2014


C2015 1U/6.3V_4 1000P/50V_4 THERMISTOR_SHDN
IT8502_AGND 0.1U/16V_4 THERMISTOR
ADAPTER_SEL_EC CLK_24M_KBC *10_4 R2036 *10P/50V_4 C2016
+3V_VSTBY 1
L2003 2
*HCB1608KF-181T15_S0_6/S
+3V +3VPCU
IT8502_AGND C2017 C2019 C2020
HWPG C2021 0.1U/16V_4
C2018 *0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4

For HW Throttling
R2037 0.1U/16V_4
Check *10K_4

<35,37,38> ACIN CLOSE to EC Pin


SKL-H
5

DC_PROCHOT_OFF AC_PRESENT_EC H_PROCHOT#_EC H_PROCHOT# <2,4,10,11,12,13,14,15,17,18,26,27,28,29,30,31,33,34,35,43,45> +3V


*2N7002KDW
A <4,15,31,36,39,40,41,42,45,46,49> +3VS5 A
4 3 DGPU_PROCHOT_EC# <20,37> AC IN: <6,13,31,33,36,38,39> +3VPCU
6

Q2005B Q2006A
AC mode Operation H L H
2

2 5 Q2005A
AC remove:
*2N7002KDW *2N7002KDW
1 6 H_PROCHOT# <2,43> AC mode to DC mode L L L
PROJECT : 0P1B
1

Q2006B
*2N7002KDW DC mode recover
from PROCHOT L H H Quanta Computer Inc.
Size Document Number Rev
Custom
NB5
1A
37 -- EC (IT8987)
Date: Wednesday, March 08, 2017 Sheet 37 of 51
5 4 3 2 1
5 4 3 2 1

+3VPCU <6,13,31,33,36,37,38,39>

38
+5VPCU <39,45,49>
+BAT_RTC
+VIN <27,35,39,40,41,43,44,46,47,48,50>
+3VPCU <6,13,31,33,36,37,38,39>

ADP=65W 14"
CN1 N-channel MOS
D 51483-00801-V01_Header D

PQ1 PQ2 PQ3 PL1

7
AP0203GMT-HF AON7408 AON6414AL +BATCHG *Short_0805
9

PL2 +VA +VAD +PRWSRC CN2

D
*Short_0805 3 3 3

BBP26CC-B520Q-9H
D

S
1 J1-1 5 2 2 5 5 2 BATT+ 1
2 1 1 1 SMD 2
3

1
PL3 SMC 3

G
4

G
PR3455 PC4 *Short_0805 PC5 4
5 AD_ID PL4 3M_5%_4 PR3 PC10 0.1u/25V_4 0.1u/25V_4 B_TEMP_MBAT 5
6

4
PC7 *Short_0805 PC8 PD1 PC9 4.02K_1%_4 0.01u/50V_4 6

1
7 BATDIS_ID_DOD

P4SMAFJ20A
0.1u/25V_4 0.1u/25V_4 PC6 0.1u/50V_6 BQBATDRV PR4 PR5
8

2
2200p/50V_4 2 330_5%_4 330_5%_4
LED2

LED1

2
PQ95
10

PR3454 2N7002K PR1

3
AD_ID <37>

8
1M_5%_4 <37> MBDATA 200K_5%_4
BATDIS_G PR6
+VIN <37> MBCLK +3VPCU
EC11 Place this ZVS close to 0.01_1%_12
1000p/50V_4 DCIN CONN PR2
1 2 1K_1%_4
TEMP_MBAT <37>

1
Do Not add test pad on PC11 PC12
+5VPCU BATDIS_G signal PD2 *100p/50V_4 *100p/50V_4
+VAD *P4SMAFJ20A PC1 PC2
0.01u/50V_4 0.01u/50V_4
PR11 PR12 PD3 PD4

2
PR16 *Short_0201 *Short_0201 *PDZ5.6B *PDZ5.6B
2.43K_1%_6 Place this cap
close to EC
PR13 PR14 Place this ZVS close to

CSIP

CSIN
C 4.02K_1%_4 4.02K_1%_4 Far-Far away +VIN C

PQ5 REGN6V +VIN


METR3904-G PR18 PC13
3

PC21 75K_1%_4
0.1u/25V_4 2 MBATLED0# <37>
0.1u/25V_4
PC14 PC15 PC16 PC17 PC18 PC19 EC12
1

2200p/50V_4
PR19 0.1u/25V_4 0.1u/25V_4 1u/16V_4 10u/25V_8

4.7u/25V_8

0.1u/25V_4
*100K_1%_4

BQCMSRC

5
BQACDRV

16
2

1
D
+5VPCU
G

ACP

ACN

REGN
18 BQHIDRV 4
3 HIDRV PD6 S PQ6
CMSRC RB500V-40 EMB20N03V

1
2
3
PR25 REGN6V PR20 1 2
REGN6V
2.43K_1%_6 1_5%_6
4 PU9 17 BQB_2 PR22
ACDRV BQ24738HRGRR BTST PL5 0.01_1%_12 +BATCHG
PQ8 PR21 PC22 4.7uH_7x7x3
METR3904-G PR29 PR23 100K_1%_4 19 BQPHASE 0.047u/25V_4 1 2 BQLR 1 2
PHASE
3

PC27 75K_1%_4 100K_1%_4


2 5

1
0.1u/25V_4 ACIN
AC_LED_ON# <37> ACPRES

5
15 BQLODRV PQ7 PR24 PC24 PC25 PC23
LODRV EMB20N03V D 2.2_5%_6

10u/25V_8

10u/25V_8

0.1u/25V_4
1

PR32 G PD7
*100K_1%_4 PD40 <35,37> ACIN 14 4 *MEK500V-40
GND#1

2
BAS316 21 S PR27 PR28
2 1 BQVCC 20 GND#2 PC26 *Short_0201 *Short_0201
+VA VCC

1
2
3
B PC29 2200p/50V_4 B
PR26 0.1u/25V_4
2 1 22_5%_8 PC28 PR31
+BATCHG
0.47u/25V_6 10_1%_6
PD41 MBDATA PR30 8 13 BQSRP
BAS316 *Short_0402 SDA SRP CSOP
12 BQSRN PC30
MBCLK PR33 9 SRN 0.1u/25V_4 CSON

ACDET
*Short_0402 SCL 11 BQBATDRV PR34

IOUT
BATDRV

ILIM
5.6_1%_6
VIN>22.5V (AC OVP) PR35
430K_1%_4 Vacdet=2.4V 6 PC31

10

7
VIN>17.2V (Enable Charging) 0.1u/25V_4

BQIOUT
+BATCHG
VIN>15.2V (AC present) Ra
PR37 PR38 PC32
PR39
69.8K_1%_4 88.7K_1%_4 *0.1u/50V_6
PR40
SYS_I <37>
PR41 470_5%_8
100K_1%_4
+3VPCU PC33 300_5%_4 PC34

3
PR42 100p/50V_4 2200p/50V_4
2
3

1M_5%_4 PQ10
2 <37> BATSHIP
+PRWSRC PQ9 PR44 2N7002K
2N7002K 43.2K_1%_4

1
PR45
1

1M_5%_4 Place this R&C


MIN. BATV=7.2V close to EC
A A

PR47
3

75K_1%_4
2 PQ11
+VA
METR3904-G
PROJECT : 0P1B
1

PR48
3.9K_1%_4 Quanta Computer Inc.
Size Document Number Rev

NB5
Custom 1A
Charger (BQ24738H)
Date:Wednesday, March 08, 2017 Sheet 38 of 51
5 4 3 2 1
5 4 3 2 1

39
DC/DC +3VS5/+5VS5
+VIN <27,35,38,40,41,43,44,46,47,48,50>
+3VS5 <4,15,31,36,37,40,41,42,45,46,49>
+5VS5 <4,31,32,40,41,42,43,44,45,46,48> Do Not add test pad on LDO pin
+3VPCU <6,13,31,33,36,37,38>
PU10 +VIN_3VS5 +VIN
+5VPCU <38,45,49> +3VPCU SY8286BRAC
2
+3VS5 17 IN#1 3
D LDO IN#2 4 D
IN#3 5 PC36 PC37 PC38 PC39 PC40
PC41 IN#4 0.1u/25V_4 4.7u/25V_8 4.7u/25V_8 2200p/50V_4 0.1u/25V_4
PR49 2.2u/10V_4 7 +3.3 Volt +/- 5%
PR50 10K_1%_4 GND#1
*Short_0402 TDC:8A
SY8286BPG 9
<4,37,40,41> HWPG PG PR51 PC42 EDP:9A
1_5%_6 0.1u/25V_4
SY8286BBST_S
BS
1 SY8286BBST 7x7x3mm +3VS5
SY8286BLDOEN 11
+VIN EN2 PL7
PR57 6 SY8286BBSW 1 2
499K_1%_4 PR59 LX#1 19
150K_1%_4 LX#2 20 1.5uH_7x7x3
LX#3 PR53 PC45 PC46 PC47 PC48 +
*2.2_5%_6 PC44 22u/6.3V_8 22u/6.3V_8 *22u/6.3V_8 0.1u/16V_4 PC43
PR54 Vih>0.8V 22u/6.3V_8 *150u/6.3V_3528
*Short_0402 10
SY8286BEN 12 NC#1 16 PR55
<37,39> S5_ON EN1 NC#3 PC50 *Short_0201
*2200p/50V_4
PR56 PC49
1M_5%_4 *0.1u/16V_4

14 SY8286BVOUT
OUT
15
NC#2
13 SY8286BFB PR58 PC51

GND#2
GND#3
GND#4
C FF 1K_1%_4 470p/50V_4 C

8
18
21
Do Not add test pad on VCC & LDO pin
PU11 +VIN_5VS5 PL8 +VIN
+5VPCU SY8286CRAC *Short_0805
2
15 IN#1 3
LDO IN#2 4
IN#3 5 PC53 PC54 PC55 PC56 PC57
PC52 IN#4 0.1u/25V_4 4.7u/25V_8 4.7u/25V_8 2200p/50V_4 0.1u/25V_4
2.2u/10V_4 7
PR60 GND#1 +5 Volt +/- 5%
*Short_0402
HWPG SY8208CPG 9 TDC:8A
PG PR61 PC58
1_5%_6 0.1u/25V_4 EDP:9A
1 SY8208CBST SY8208CBST_S
B 11 BS PL9 +5VS5 B
+VIN EN2 2.2uH_7x7x3
PR3264 6 SY8208CSW 1 2
499K_1%_4 PR3268 LX#1 19
LX#2
150K_1%_4
LX#3
20 7x7x3mm
PR63 PC61 PC62 PC63 PC64 +
Vih>0.8V *2.2_5%_6 PC60 22u/6.3V_8 22u/6.3V_8 *22u/6.3V_8 0.1u/16V_4 PC59
PR64 22u/6.3V_8 *150u/6.3V_3528
1K_1%_4 10 PR65
SY8208CEN 12 NC#1 16 *Short_0201
<37,39> S5_ON EN1 NC#2 PC65
*2200p/50V_4
PR67 PC66
1M_5%_4 *0.1u/16V_4

14 SY8208CVOUT
OUT
17
VCC
13 SY8208CFB PR68 PC68
GND#2
GND#3
GND#4

PC67 FF 1K_1%_4 470p/50V_4


2.2u/10V_4
8
18
21

Do Not add test pad


on VCC & LDO pin

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5
Custom 1A
3/5VS5 (SY8208B/SY8208C)
Date:Wednesday, March 08, 2017 Sheet 39 of 51
5 4 3 2 1
1 2 3 4 5

40
+VIN <27,35,38,39,41,43,44,46,47,48,50>
+5VS5 <4,31,32,39,41,42,43,44,45,46,48>
+1.2VSUS <3,6,17,18,42>
DDR_VTT <17,18>

PR69
*Short_0402
<4,37,39,41> HWPG

A A
<37,42,45> SUSON
PR70
*Short_0402 PC69
PR71 *0.1u/16V_4
*Short_0402
PR72
<18> DDR_VTT_PG_CTRL_R
243K_1%_4

1P35V_PGOOD
<37,41,42,45> MAINON

1P35V_CS
1P35V_S3

1P35V_S5
PR73 PR74 +VIN_DDR PL10 +VIN
*Short_0402 PC70 499K_1%_4 *Short_0603 +1.2VSUS +/- 5%
1P35V_TON
*0.1u/16V_4 Countinue current:6A
PC75 PC76 PC71 PC72 PC73 Peak current:8A

10

13
7

9
PU12 2200p/50V_4 0.1u/25V_4
OCP minimum:12A

0.1u/25V_4

4.7u/25V_8

4.7u/25V_8
S3

S5

CS
PGOOD

TON

5
DDR_VTT
D
20 +1.2VSUS
VTT 1P35V_UGATE
G
17 4
2 DH S
VTTSNS

2
PC74 PR75 PC77 PQ12

1
2
3
10u/6.3V_6 18 1P35V_BOOT EMB20N03V PR76
1 BST PL11 +1.2VSUS_S
VTTGND *short-solderjumper-3
G5619RZ1U 2.2_5%_6 0.1u/25V_4 1uH_7x7x3

1
PR77 16 1P35V_PHASE 1 2
( 3mA ) LX
100_1%_4
1P35V_LGATE
DDR_VTTREF
4
VTTREF DL
15 7x7x3mm

5
B PR78 B
19 12 1P35V_VDD D *2.2_5%_6 PC80 PC81 PC82 PC83 PC84
+1.2VSUS VLDOIN VCC +5VS5
PC78 PC79 PR79

0.1u/16V_4
G

22u/6.3V_8

22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8
0.1u/16V_4 0.033u/25V_4 4 *Short_0201
S

VDDQSNS
PC86 PC87

VDDQSET
*10u/6.3V_6 1u/6.3V_4 PQ13 PC85

GND#1

GND#2

1
2
3
PGND
AON7752 *2200p/50V_4

VID
3

11

14

21
PR80
*Short_0201 Rds(on) 14m ohm

1P35V_VID

1P35V_FB
PR81
*Short_0201
1P35V_VDDQ
+5VS5

PR82
PR83 7.87K_1%_4
10K_1%_4

C C

+2.5VSUS +/- 3%
Countinue current:2A
+3VS5 PU13
G9661MF11U Peak current:3A
3 5
VIN NC OCP minimum:4A
PC88 PC89 +2.5VSUS
10u/6.3V_6 0.1u/16V_4
PR84 6
0_5%_4 VO
SUSON 2
VEN PC90 PC91
4 8 *10u/6.3V_6 0.1u/16V_4
+5VS5 VPP GND#1
PC92
ADJ

*0.1u/16V_4 1 9
PC93 POK GND#2
1u/6.3V_4
7

PR85
215K_1%_4
R1

D
PR87 R2 VO=(0.8(R1+R2)/R2) D
*Short_0402 PR86 R2<120Kohm
HWPG 100K_1%_4

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5 DDR4 (G5619RZ1U) 1A


1A
Date:Wednesday, March 08, 2017 Sheet 40 of 51
1 2 3 4 5
5 4 3 2 1

41
+VIN <27,35,38,39,40,43,44,46,47,48,50>
+3VS5 <4,15,31,36,37,39,40,42,45,46,49>
+5VS5 <4,31,32,39,40,42,43,44,45,46,48>
+1.0V_DEEP_SUS <9,13,15,42>
+1.8V_DEEP_SUS <9,15,49>
MAINON <37,40,41,42,45>
+1.5V

PR88
84.5K_1%_4

6
D PU8 +VIN_0.95V PL12 +VIN D
*Short_0603

TON
+5VS5 7
IN#1 22
IN#4
21
VCC (V1.00A+V1.00_MODPHY+VccPRIM_CORE)
PC94 PC95 PC96 PC97 PC98
2200p/50V_4 0.1u/25V_4
+1.0VS5 Volt +/- 5%

0.1u/25V_4

4.7u/25V_8

4.7u/25V_8
PC99
1u/6.3V_4
Countinue current:6A
PR90 PC100
Peak current:9A
20 1237BSTPCH
BST PL13 +1.0V_DEEP_SUS
PR91 0_5%_6 0.1u/25V_4 1uH_7x7x3
*Short_0402 10 1237LX 1 2
HWPG 1237PGPCH 1 LX#1
<4,37,39,40> HWPG PGOOD
LX#3
16 7x7x3mm
PR92 17 +
*Short_0201 LX#4 18 PR93 PC101 PC102 PC103 PC104 PC105
1237PFMPCH 3 LX#5 *2.2_5%_6 PR94 *220u/2V_7343H1.9

22u/6.3V_8

22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8
PFM *Short_0201 PC106
12

0.1u/16V_4
1237ENPCH 2 PGND#1 13
<15,37,42> SLP_SUS_ON EN PGND#2 14 PC107
PR95 PGND#3 15 *2200p/50V_4
*Short_0402 PC108 PGND#4 19
*0.1u/16V_4 PGND#5 4
AGND

C PR96 C
2.61K_1%_4
1237SSPCH 23 5 1237FBPCH 1237FBPCH_S
SS FB
Vout1=(1+R1/R2)*0.8
PC109 PR97
0.1u/16V_4 AOZ2260QI-18 10K_1%_4

+VIN +1.8V_DEEP_SUS
+1.8V_DEEP_SUS +/- 5%
+3VS5 PU15 Countinue current:1.0A
G9661MF11U +1.8V PR98
3 5 Peak current:3A +VIN 1M_5%_4 PC110
VIN NC

1
2
5
6
0.1u/16V_4
B B
PC111 PC112 +1.8V_DEEP_SUS PR100 3
*10u/6.3V_6 0.1u/16V_4 PR99 *22_5%_8
0.05A
PR101 6 1M_5%_4 PQ16 PQ14
*Short_0402 VO 2N7002K PR102 PC113 EMB32N03K

4
SLP_SUS_ON 2

3
1M_5%_4 2200p/50V_4
VEN PC114 PC115 2 2 +1.8V
4 8 *10u/6.3V_6 0.1u/16V_4 PQ17 PQ15
+5VS5 VPP GND#1
PC116 PR103 METR3904-G *2N7002K
ADJ

3
*0.1u/16V_4 1 9 75K_1%_4

1
PC119 POK GND#2 2 PR104
<37,40,41,42,45> MAINON
1u/6.3V_4 1M_5%_4 PC117 PC118
7

R1 PR105
*10u/6.3V_6 0.1u/16V_4

1
PR106
2 1 *100K_1%_4

PR108
R2 127K_1%_4

*Short_0402 PR371
HWPG 100K_1%_4

VO=(0.8(R1+R2)/R2)
R2<120Kohm

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 +1.0V/+1.8V_DEEP_SUS 1A

Date: Wednesday, March 08, 2017 Sheet 41 of 51


5 4 3 2 1
5 4 3 2 1

42
+1.0V <2,4,37,43>
+3VS5 <4,15,31,36,37,39,40,41,45,46,49>
+5VS5 <4,31,32,39,40,41,43,44,45,46,48>
+VCCIO <2,6>
+1.2VSUS <3,6,17,18,40>
+VCCSTPLL <2,4,5,6,9>
+1.0V_DEEP_SUS <9,13,15,41>
+1.2V_VCCPLL_OC <6>
MAINON <37,40,41,45>
Volume Segment
Vcc_STG: 0.04A
D
Volume Segment Vcc_IO: 3.4A D

Vcc_ST: 0.12A
+1.0V_DEEP_SUS <= 10ms full load ready
Vcc_PLL: 0.12A PU34
1
VIN#1 Imax:3.4A Imax:0.04A
<= 10ms, full load ready 2 +VCCIO +1.0V
PL14
VIN#2
(Vcc_ST+Vcc_PLL) PC120
9 8
*Short_0603
1u/6.3V_4
VIN#3 VOUT

Imax:0.24A
+1.0V_DEEP_SUS +VCCSTPLL
PC121 PC122 2015/10/26 updated
PL15 3 0.1u/16V_4 *10u/6.3V_6
+3VS5 VBIAS
*Short_0603

PC123
0.1u/16V_4
PC124 PC125
0.1u/16V_4 *10u/6.3V_6 PR109
*Short_0402 5
MAINON 4 GND
ON
AOZ1335DI
PC126
*0.1u/16V_4

C C

+3VS5

+1.2VSUS

PC127
*0.1u/16V_4
PC128
PR110 0.1u/16V_4

3
*0_5%_4 PR112
1 *47K_1%_4
<37,40,45> SUSON
2
4 2 PR116 <= 240us, full load ready
<15,37,41> SLP_SUS_ON 0_1%_6

PR111 3 PU17 PC129


PQ18
*DMG3414U-7
TDC:0.26A

1
*0_5%_4 *MC74VHC1G08DFT2G *1000p/50V_4

PL16 +1.2V_VCCPLL_OC
*Short_0603

PC130 PC131
B *0.1u/16V_4 *10u/6.3V_6 B

+1.2V_VCCPLL_OC

+5VS5
PR113
*22_5%_8

PR114

3
*1M_5%_4
PQ19A
5 *2N7002KDW
6

PR115

4
2 *2M_5%_4

PQ19B
*2N7002KDW
1

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 +1.0V/+VCCSTPLL 1A

Date: Wednesday, March 08, 2017 Sheet 42 of 51


5 4 3 2 1
1 2 3 4 5

43
PR3538
PR3537 100K_NTC_4_1% Place close to +VIN_VCCGT PL45 +VIN
+VIN
+1.0V
<27,35,38,39,40,41,44,46,47,48,50>
<2,4,37,42> PC522 PR3536 10_5%_4 GT Inductor *Short_0805 +VCC_GT
1000p/50V_4 2K_1%_4 CSN_GT 2 1
+VCCSA <6,44>
PR3539 PR3540
+VCC_CORE
+VCCGT <7>
<5,7>
100_1%_4 *Short_0402 PC523 PR3542 U-line 42 (15W)
PR3541 14K_1%_4 PC526 PC527 PC528 PC529 PC530 PC531 PC532 + +
+VCCGT TDC:12A

2200p/50V_4
1.65K_1%_4 2200p/50V_4 PC524 PC525 PC533 PC534

4.7u/25V_8

4.7u/25V_8

4.7u/25V_8

0.1u/25V_4

0.1u/25V_4
*4.7u/25V_8
1000p/50V_4 PR3546
Icc max:28A

0.015U/16V_4

100u/25V_D6.3H5.8

*100u/25V_D6.3H5.8
<7> VCCGT_SENSE

5
PC535 PR3545 7.5K_1%_6
<7> VSSGT_SENSE SWN_GT
1000p/50V_4 1K_1%_4 D L/L=3.1mV/A
G
PR3338 4 PQ27
+1.0V PR3543 PR3544 1_5%_6 S AON6414AL For Acoustic
A 100_1%_4 *Short_0402 PC537 PL46 +VCCGT A
+VCC_GT

1
2
3
PC536 0.22u/25V_6
SW_GT
0.15uH_7x7x3
1 2
DCR=1.9m-ohm+/-7%
1000p/50V_4

PR3547 PR3548 PR3549 PR3550 PC538 PR3551 PC539 7x7x3mm


U-line 22 (15W)

5
100_1%_4

+ PC540 +
*75_1%_4

*75_1%_4
45.3_1%_4

0.1u/16V_4 1K_1%_4 0.01u/50V_4 PQ28 PR3552 PC615 PC614


AON6760 D *2.2_5%_6 PC350 TDC:18A

22u/6.3V_8

22u/6.3V_8

*220u/2V_7343H1.9
PC542 PR3553 PR3554
Icc max:31A(22)

330u/2V_D5H4.2
G
Ra Rb 4 *Short_0201 *Short_0201
VR_SVID_DATA U22 34K 16.5K S
VR_SVID_ALERT# U42 40.2K 18.7K PC910 15p/50V_4 PC543 CSN_GT L/L=3.1mV/A

1
2
3
VR_SVID_CLK 1000p/50V_4 PR3555 *2200p/50V_4
H_PROCHOT# PC544 Ra Rb 11K_1%_4 SWN_GT
1000p/50V_4

31.6K_1%_4
PR3557 PC546
PC545 +VIN_VCC_CORE +VIN

COMP_GT 0.1u/16V_4
+VCC_CORE

16.5K_1%_4
PR3558 PR3559 PR3560 470p/50V_4
100_1%_4 *Short_0402 2.49K_1%_4
+VCCSA U-line 22(15W)

PR3556

ILIM_GT

TSENSE_GT
IOUT_GT
PC550 PC551 PC552 PC548 PC553 PC554 PC555 EC13
TDC:21A

CSN_GT_1
<6> VCCSA_SENSE

2200p/50V_4
PC547 PR3563 10u/25V_8

4.7u/25V_8

4.7u/25V_8

4.7u/25V_8

0.1u/25V_4

0.1u/25V_4
*4.7u/25V_8
VSN_GT

CSP_GT
VSP_GT

BST_GT

SW_GT
<6> VSSSA_SENSE

HG_GT

LG_GT
1000p/50V_4 1K_1%_4
Icc max:29A

5
PR3627 D L/L=2.4mV/A
PR3561 PR3562 PC549 1_5%_6 G
100_1%_4 *Short_0402 1000p/50V_4 4 PQ20

34

31

27

30

29

28

32

33

25

26

24

23

15
VSP_SA
PU32 S AON6414AL PL48 +VCC_CORE
<44> CSN_SA
PR3565 PC560 0.15uH_7x7x3 DCR=1.9m-ohm+/-7%

LG3/ICCMAX_1b
IOUT_1a

ILIM_1a

TSENSE_1a

COMP_1a

VSN_1a

VSP_1a

CSN_1a

CSP_1a

HG3

BST3

SW3

HG1

1
2
3
Place close to 10_5%_4 2200p/50V_4 PC559 1 2
B
VCCSA Inductor 1 2 14 SW1 PQ21 PQ110 B
BST1

5
49 AON6760 AON6760 7x7x3mm
VSP_1b 16 + PC564 + PC908
PR3564
SW 1
0.22u/25V_6 D D PR3567 PC613 PC414
PR3566 100K_NTC_4_1% VSN_SA48 2.2_5%_6

22u/6.3V_8

22u/6.3V_8
G G

*330u/2V_D5H4.2
*220u/2V_7343H1.9
VSN_1b PR3568
14K_1%_4 PC563 PC558 17 4 4 PR3569 PR3570
0.018u/16V_4 *390p/50V_4 CSN_SA_1 45 LG1/ROSC PR3628 S S *Short_0201 *Short_0201
PC909 CSN_1b *1_5%_6

1
2
3

1
2
3
1000p/50V_4 CSP_SA CSN_CORE1
NCP81236MNTXG
44 21 14K_1%_4 PC565
<44> SWN_SA CSP_1b HG2
Rc PC567 2200p/50V_4
PR3571 PC566 ILIM_SA 46 22 SWN_CORE1
7.5K_1%_6 150p/50V_4 PR3572 ILIM_1b BST2
PC568 32.4K_1%_4 COMP_SA 47 20 *0.22u/25V_6 SW2 Rk
COMP_1b SW 2 29.4K
Rc Rd PR3573 0.01u/50V_4 PC569 U22
U22 NA NA 1K_1%_4 470p/50V_4 IOUT_SA 43 19 PR3575 Rk U42 17.2K +VIN_VCC_CORE +VIN
IOUT_1b LG2/ICCMAX_1a
U42 32.4K 100K PR3574
102K_1%_4 Rd
+VCC_CORE

DIFFOUT_2ph/IccMax_2ph
PR3576 *Short_0402 40 10 CSP_CORE1 29.4K_1%_4
<44> PWM_SA
PR3577 PW M/ADDR_VBOOT CSP1_2ph U-line 42(15W)
51.1K_1%_4 DRON 39 8 CSREF_CORE PC570 PC571 PC572 PC573 PC574 PC579 PC575
<44> DRON
PR3578 *Short_0402 DRON CSREF_2ph 2200p/50V_4 0.1u/25V_4 TDC:42A

0.1u/25V_4
*4.7u/25V_8

*4.7u/25V_8

*4.7u/25V_8

*4.7u/25V_8
PR3579 VR_HOT# 35 9 CSP_CORE2
<2,37> H_PROCHOT# Icc max:64A

CSCOMP_2ph
VR_HOT# CSP2_2ph

5
TSENSE_2ph

PR3580 75_1%_4 SDIO 36


<5> VR_SVID_DATA SDIO

COMP_2ph
10_5%_4 PR3581 ALERT# 37 7 CSSUM_CORE PC578 D L/L=2.4mV/A
IOUT_2ph

<5> VR_SVID_ALERT#
VSN_2ph

ALERT# CSSUM_2ph
VSP_2ph

ILIM_2ph
VR_RDY

*Short_0402 SCLK 38

0.01u/50V_4
G
FB_2ph

<5> VR_SVID_CLK SCLK


12 18 4

EPAD
VRMP
PSYS

PR3582 +VIN PQ45

VCC
49.9_1%_4 VRMP PVCC S *AON6414AL
EN

PR3583 PL50 +VCC_CORE

1
2
3
1K_1%_4 PC580 *0.15uH_7x7x3 DCR=1.9m-ohm+/-7%
42

41

50

11

51

52

53
13
0.01u/50V_4 PR3585 +5VS5 1 2
PR3584 2.2_5%_6 PQ46 PQ111

5
C 10K_1%_4 *AON6760 *AON6760 7x7x3mm C
VR_EN

PSYS

TSENSE_CORE

VSP_CORE

VSN_CORE

IOUT_CORE

DIFFOUT_CORE

FB_CORE

COMP_CORE

ILIM_CORE

CSCOMP_CORE

PR3586 D D PR3587 PC415 PC416 + PC583


+3V +5VS5
*Short_0402 VR_RDY *2.2_5%_6

22u/6.3V_8

22u/6.3V_8
G G

*220u/2V_7343H1.9
IMVP_PWRGD
PR3588 PC584 PC581 4 4 PR3589 PR3590
<37> VRON S S
*Short_0402 1u/6.3V_4 Rh *Short_0201 *Short_0201

2.2u/10V_4
PMON

1
2
3

1
2
3
PR3592 PR3591 PC587 PR3629 PC586
20K_1%_4 *Short_0402 0_5%_4 *2200p/50V_4 CSN_CORE2
PC588
100p/50V_4 0.1u/16V_4 Rg Rh SWN_CORE2
PR3593 U22 0-ohm
*Short_0402 PR3594 U42 N/A PR3595 PR3596 Ri
+VCC_CORE PR3597 4.02K_1%_4 169K_1%_4
SWN_CORE1
10K_1%_4

100_1%_4
<5> VCC_SENSE PC589 Rg
<5> VSS_SENSE PR3599 1000p/50V_4 U22 10K PC590
*Short_0402 U42 19.1K 0.022u/16V_4 +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE
PR3598 PR3600
100_1%_4 1K_1%_4 PR3601 CSN_CORE1 Ri Rj
Re 10_1%_4 U22 169K NA
U42 169K 169K PC407 PC406 PC408 PC410
PC591 PR3602 PC592

22u/6.3V_8

22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8
TSENSE_GT TSENSE_CORE 2200p/50V_4 26.7K_1%_4 470p/50V_4 PR3603 CSN_CORE2
*10_1%_4
Re
PR3604 PR3605 U22 26.7K PC593
*Short_0402 *Short_0402 U42 25.5K *0.022u/16V_4 PR3606 Rj PR3607 Place close to
*4.02K_1%_4 *169K_1%_4
PR3612 PC594 PC595 SWN_CORE2 CORE1 Inductor
49.9_1%_4 330p/50V_4 15p/50V_4 PR3615
2

D 165K_1%_4 D
PR3608 PR3609 PR3610 PR3611 PC596
15K_5%_4 100K_NTC_4_1% 15K_5%_4 100K_NTC_4_1% PR3613

2
1K_1%_4
PR3614 2200p/50V_4 PR3618
1

Rf 3K_1%_4 PC597 PC598 PR3617 100K_NTC_4_1%

place close to place close to U22


Rf
102K
PR3616
102K_1%_4
470p/50V_4 *390p/50V_4 75K_1%_4
PROJECT : 0P1B
Quanta Computer Inc.

1
U42 154K
GT MOSFET VCORE MOSFET program IccMax_2ph
Size Document Number Rev
Custom
NB5 CPU VR IC (NCP81236) 1A

Date: Wednesday, March 08, 2017 Sheet 43 of 51


1 2 3 4 5
1 2 3 4 5

44
A A

+VIN_VCCSA PL51 +VIN


*Short_0805

PC599 PC600 PC601 PC602 PC603


VCCSA

2200p/50V_4
PR3619

4.7u/25V_8

4.7u/25V_8

0.1u/25V_4

0.1u/25V_4
5
1_5%_6
D
PU33 8 4
G VCCSA
PC604 S PQ103

DRVH
0.22u/25V_6 EMB20N03V PL52

1
2
3
+VCCSA
BST
1 0.47uH_7x7x3 DCR=4.2m ohm(max)
2
<43> PWM_SA PW M 7 1 2
B 3 SW B
<43> DRON EN
PR3620

5
*Short_0402 NCP81253MNTBG PQ104 PR3621 PC605 PC606 PC607 PC608 PC609 PC610
MDV1595SURH D *2.2_5%_6

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8
GND#2
GND#1
+5VS5 4 G PR3622 PR3623
VCC 5 4 *Short_0201 *Short_0201
DRVL S
PC611 9 6 PC612

1
2
3
2.2u/10V_4 *2200p/50V_4

CSN_SA <43>

SWN_SA <43>

C C

D D

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 +VCCSA (NCP81253) 1A

Date: Wednesday, March 08, 2017 Sheet 44 of 51


1 2 3 4 5
5 4 3 2 1

45
+3V <2,4,10,11,12,13,14,15,17,18,26,27,28,29,30,31,33,34,35,37,43>
+5V <26,27,28,29,33,35,36>
+VIN <27,35,38,39,40,41,43,44,46,47,48,50>
+3VS5 <4,15,31,36,37,39,40,41,42,46,49>
+5VS5 <4,31,32,39,40,41,42,43,44,46,48>
+3VSUS <33>
+5VPCU <38,39,49>
+3VLANVCC <30>

D D

+3VS5 +3VS5

5.2A PC265
0.1U/16V_4
PC266
0.1U/16V_4 0.67A

7
+3V PL24 PR292 +3VLANVCC

VIN1#1

VIN1#2

VIN2#1
VIN2#2
*Short_0805 *Short_0603
13 8
14 VOUT1#1 VOUT2#1 9
VOUT1#2 VOUT2#2
PC267 PC268 PC269 PC270
*10U/6.3V_6 0.1U/16V_4 11 0.1U/16V_4 *10U/6.3V_6
GND#1
15
4 GND#2
+5VPCU BIAS
PC271 PU20
APL3523AQBI-TRG
0.1U/16V_4
PR293 *Short_0402 3 5 PR294 *Short_0402
<37,40,41,42> MAINON EN1 EN2 LAN_POWER <37>

SS1

SS2
PC272 PC273

12

10
*0.1U/16V_4 *0.1U/16V_4

PC274 PC275
1000P/50V_4 1000P/50V_4
C C

+5VS5 +3VS5

5.1A PC276
0.1U/16V_4
PC277
0.1U/16V_4 0.04A

7
+5V PL25 PR295 +3VSUS

VIN1#1

VIN1#2

VIN2#1
VIN2#2
*Short_0805 *Short_0603
13 8
14 VOUT1#1 VOUT2#1 9
VOUT1#2 VOUT2#2
PC278 PC279 PC280 PC281
*10U/6.3V_6 0.1U/16V_4 11 0.1U/16V_4 *10U/6.3V_6
B
GND#1 B
15
4 GND#2
+5VPCU BIAS
PC282 PU21
APL3523AQBI-TRG
0.1U/16V_4
MAINON PR296 *Short_0402 3 5 PR297 *Short_0402 SUSON <37,40,42>

SS1

SS2
EN1 EN2

PC283 12 PC284

10
*0.1U/16V_4 *0.1U/16V_4

PC285 PC286
1000P/50V_4 1000P/50V_4

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev

NB5
Custom 1A
Load switch IC (APL3523A)
Date: Wednesday, March 08, 2017 Sheet 45 of 51
5 4 3 2 1
5 4 3 2 1

R17M-M1-70

+1.8V_VGA

VID Override table (VDD)


8899VCC PR3456
4.7_5%_4
+5VS5
46
PC448 8899PVCC PR3459 *Short_0402 +5VS5
PC449 SVC SVD Boot Voltage 2.2u/10V_4
PR3457 PR3458 *0.1u/16V_4
*10K_1%_4 *10K_1%_4 PC450
0 0 1.1V 2.2u/10V_4
+VIN_GPU
PR1209
D 0 1 1.0V PC451 4.7_5%_4 D

14

27

1
3662SVC 3662SVD
1 0 0.9V 0.1u/25V_4

VCC

PVCC

VIN
22 PR3465
1 1 0.8V NC 1_5%_6
PR1210 PR1208 24 3662UGATE1
UGATE1 3662UGATE1_G <47>
*10K_1%_4 *10K_1%_4 PR1201 PR1204
10K_1%_4 48.7K_1%_4
VREF_PINSET 3662SET1 11
SET1 PC452
PR1205 PR1206 0.1u/25V_4
10K_1%_4 2.94K_1%_4 23 3662BOOT1
BOOT1

PR3470 PR3471 PR3472


60.4K_1%_4 6.04K_1%_4 60.4K_1%_4 3662ISEN1P <47>
3662TSEN 10 25 3662LX1
VREF_PINSET TSEN PHASE1 3662LX1 <47>
3662ISEN1N <47>
1 2

PR3473 PR3474 PR3464 PR3475


10K_1%_4 23.7K_1%_4 100K_NTC_4_1% 3.3K_1%_4
PD16 26 3662LGATE1
LGATE1 3662LGATE1 <47>
RB500V-40 Put close to VGACORE
1 2 HOT SPOT PC453 0.47u/6.3V_4

PR3476 3662EN 32
<12,13,49> DGPU_PR_EN 10K_1%_4 PC454 EN

<48> 3662EN Vih=2V ISEN1P


7 3662ISEN1P_1 PR3477 357_1%_4
PC455
PU16
C 0.47u/6.3V_4 RT3662EBGQW 8 3662ISEN1N_1 PR3478 *Short_0402 C
ISEN1N

+3V_VGA PR3479 2.2_5%_6


0.1u/16V_4

R17M-M1-30 PR3481
PR3480 *2.2_5%_6 3662VDDIO 19 1_5%_6
+1.8V_VGA VDDIO 30 3662UGATE2
UGATE2 3662UGATE2_G <47>
R17M-M1-70
PC456 PC457
1u/6.3V_4 31 3662BOOT2
BOOT2 3662ISEN2P <47>
DGPU_PWROK PR3483 *Short_0201 3662PWROK 15 0.1u/25V_4
PW ROK 3662ISEN2N <47>

PR3484
PR3485 *Short_0201 3662SVC 16 29 3662LX2 3.3K_1%_4
<20> SVI2_CLK SVC PHASE2 3662LX2 <47>
PC458
0.47u/6.3V_4

PR3486 *Short_0201 3662SVD 17


<20> SVI2_DATA SVD PR3487 Unstuff
357_1%_4
PC459
PR3488 *Short_0201 3662SVT 18 28 3662LGATE2 0.1u/16V_4
<20> SVI2_SVT SVT LGATE2 3662LGATE2 <47>

PR3489
0_5%_4
5 3662ISEN2P_1 1 Phase setting
B DGPU_PWROK ISEN2P B
<12,37,48,49> DGPU_PWROK 3662ISEN2N_1
PR1207 6 PR3490 *10K_1%_2
PR3491 *Short_0201 3662PGOOD 20 ISEN2N PC460 PC461
+5VS5 stuff 1 Phase setting
+3VS5 PGOOD
10K_1%_4 39p/50V_4 270p/50V_4

+3VS5 PR3493
*10K_1%_4 PR3494 PR3495 PR3492
*Short_0402 3662VRHOT 9 56.2K_1%_4 10K_1%_4
<20> DGPU_OCP_L VRHOT_L 3 3662COMPA
COMP +VGA_CORE
Put close to
VGACORE hot sport R4
PHASE 1 R1 12
IMON 4 3662FBA PR3498
PR3497 FB 10_1%_4
1

6.98K_1%_4 PC462
PR3499 *100p/50V_4 VREF_PINSET
100K_NTC_4_1% 21 PR3500 *Short_0402 VGPU_CORE_SENSE_SRC
1 Phase setting 13 VSEN
VREF_PINSET
R1 R2
2

PC463 VGPU_CORE_SENSE <22>


PR3502 2 *82p/50V_4 VSS_GPU_SENSE <22>
R2 R3
GND

14K_1%_4 PR3504 RGND VSS_GPU_SENSE_SRC


PR3503 3.9_1%_4
R3 11K_1%_4 PR3506
33

10_1%_4
1 Phase setting
PC464
A
0.47u/6.3V_4
R4 A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 EC ENE KB9027B 1A

Date: Wednesday, March 08, 2017 Sheet 46of 51


5 4 3 2 1
5 4 3 2 1

47
D D

VGACORE ( R17M-M1-30_ 25W/38W(1ms) )


+VIN_GPU +VIN Countinue current:28A
Peak current=38A (1ms)
PHOCP_TDC=40A ( soft-start only)
PC465 PC466 PC467 PC468 PC469 PC470 + +
OCP_SPIKE=55A(1ms)

2200p/50V_4
0.1u/25V_4 PC907 PC294

4.7u/25V_8

4.7u/25V_8

*4.7u/25V_8

*4.7u/25V_8
D *100u/25V_D6.3H5.8 100u/25V_D6.3H5.8
Boot VID=0.9V
3662UGATE1_G
G
4
<46> 3662UGATE1_G S LL=1m V/A
DCR=4mohm

1
2
3
PQ96
AON6414AL PL40 +VGA_CORE
0.47uH_7x7x3
1 2
<46> 3662LX1

5
PR3507 + +
D *2.2_5%_6 PC348 PC349
C 330u/2V_D5H4.2 330u/2V_D5H4.2 C
G
4
<46> 3662LGATE1 S PR3508 PR3509
PQ100 *Short_0201 *Short_0201

1
2
3
AON6760 PC474
*2200p/50V_4

3662ISEN1P
<46> 3662ISEN1P

3662ISEN1N
<46> 3662ISEN1N

VGACORE ( R16M-M2-50_ 37W/56W(1ms) )


Countinue current:40A ( R16M-M2-50)
+VIN_GPU Peak current:56A (1mS) ( R16M-M2-50)
PHOCP_TDC=40A
OCP_SPIKE=75A(1ms)
PC475 PC476 PC477 PC478 PC479 PC480
Boot VID=0.9V
5

2200p/50V_4 0.1u/25V_4
4.7u/25V_8

4.7u/25V_8

*4.7u/25V_8

*4.7u/25V_8
D LL=1m V/A
3662UGATE2_G
G
4
B <46> 3662UGATE2_G S B
DCR=4mohm
1
2
3

PQ98
AON6414AL PL41 +VGA_CORE
0.47uH_7x7x3
1 2
<46> 3662LX2
5

PR3510 PC481 + + +
D *2.2_5%_6 0.1u/16V_4 PC351 PC482 PC483
G *330u/2V_D5H4.2 *220u/2V_7343H1.9 *220u/2V_7343H1.9
4
<46> 3662LGATE2 S PR3511 PR3512
PQ99 *Short_0201 *Short_0201
1
2
3

AON6760 PC485
*2200p/50V_4

3662ISEN2P
<46> 3662ISEN2P

3662ISEN2N
<46> 3662ISEN2N

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 EC ENE KB9027B 1A

Date: Wednesday, March 08, 2017 Sheet 47of 51


5 4 3 2 1
5 4 3 2 1

48
D D

PR3513 Vo Rton
127K_1%_4
+1.5V Volt +/- 5% 0.95V 82k

6
PU29 +VIN_1.35V PL42
*Short_0805
+VIN
Countinue current:6A
1V 84.5k

TON
+5VS5 7
IN#1 22 Peak current:7A
21 IN#4
VCC PC490 PC491 PC486 PC487 PC488 OCP minimum:9A 1.05V 95.3k
0.1u/25V_4 4.7u/25V_8 4.7u/25V_8 2200p/50V_4 0.1u/25V_4
PC489
1u/6.3V_4 +1.5V_VGA 1.35V 113k
PR3514 PC492
C 1_5%_6 0.1u/25V_4 1.5V 127k C
20 1237BST1.35V PR3515
BST PL43 +1.35V_VGA_S2 *short3720
PR3516 1uH_7x7x3
*Short_0402 10 1237LX1.35V 1 2
1237PG1.35V 1 LX#1
<12,37,46,49> DGPU_PWROK PGOOD 16
PR3518 LX#3 17 PR3517 PC494 PC495 PC496 PC497 PC498
*Short_0201 LX#4 18 *2.2_5%_6 0.1u/16V_4 22u/6.3V_8 22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8
1237PFM1.35V 3 LX#5 +
PFM
Vih=2.5V PR3519 PC493
12 *Short_0201 *150u/6.3V_3528
1237EN1.35V 2 PGND#1 13 PC499
<46> 3662EN EN PGND#2 14 *2200p/50V_4
PR3520 PGND#3 15
*Short_0402 PC500 PGND#4 19
*0.1u/16V_4 PGND#5 4
AGND

PR3521
10.5K_1%_4
1237SS1.35V 23 5 1237FB1.35V 1237FB1.35V_S
SS FB

PC501 PR3522 Vout1=(1+R1/R2)*0.8


0.1u/16V_4 AOZ2260QI-18 12K_1%_4

B B

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 EC ENE KB9027B 1A

Date: Wednesday, March 08, 2017 Sheet 48of 51


5 4 3 2 1
1 2 3 4 5 6 7 8

49
+0.95V +/- 3%
Countinue current:2A
Peak current:3A
A A
OCP minimum:4A
+1.0V_VGA +0.95V_VGA
PR3523
PC502 *2.2_5%_6

PR3525 *2200p/50V_4 PR3524


*Short_0402 PU30 PL44 +1.0V_VGA_S2 *Short_0603
4 1uH_2.5x2.0x1.2
<12,37,46,48> DGPU_PWROK PGOOD 1 1 2
LX#1
9 2
+3VS5 PVIN#1 LX#2
PR3527 10 3 PC506 PC503 PR3526 PC504 PC505 PC616
*Short_0603 PC507 PC508 PVIN#2 LX#3 *68p/50V_4 *22p/50V_4 *Short_0201 0.1u/16V_4 10u/6.3V_6 *10u/6.3V_6
0.01u/50V_4 10u/6.3V_6 PR3529 7
10_5%_6 NC
8 6
SVIN FB
Vih=1.6V R2 R1
11 5 PR3528
PC509 GND EN PR3530 6.65K_1%_4
1u/6.3V_4 11.3K_1%_4
RT8068AZQW V0=0.6*(R1+R2)/R2

PR3531
8.2K_1%_4
B B
DGPU_PR_EN <12,13,46>

PC510
0.47u/6.3V_4

+3V_VGA

+1.8V_VGA & +0.95V_VGA


PUT COLSE TO
+1.8V power. +VGA_CORE & +1.5_VGA

+1.8V_DEEP_SUS +3VS5

0.3A PC511
0.1u/16V_4
PC512
0.1u/16V_4 0.06A

7
+1.8V_VGA PR3532 +1.8V_VGA_S2 +3V_VGA_S2 PR3533 +3V_VGA

VIN1#1

VIN1#2

VIN2#1
VIN2#2
C *Short_0603 *Short_0603 C
13 8
14 VOUT1#1 VOUT2#1 9
VOUT1#2 VOUT2#2
PC513 PC514 PC515 PC516
*10u/6.3V_6 0.1u/16V_4 11 0.1u/16V_4 *10u/6.3V_6
GND#1
15
4 PU31 GND#2
+5VPCU BIAS
PD43 APL3523AQBI-TRG PD17
*RB500V-40 RB500V-40
1 2 1 2
PC517
DGPU_PR_EN 0.1u/16V_4 3 5 Vih=1.2V DGPU_PR_EN
EN1 EN2
SS1

SS2
Vih=1.2V
PR3534 PR3535
10K_1%_4 PC518 PC519 10K_1%_4
12

10

0.47u/6.3V_4 0.47u/6.3V_4

PC520 PC521
1000p/50V_4 1000p/50V_4

D D

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 EC ENE KB9027B 1A

Date: Wednesday, March 08, 2017 Sheet 49of 51


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

50
A A

B
EMI request for ISN EMI request for ISN B

+VIN +VIN +PRWSRC

EC50 EC49 EC48 EC47 EC46 EC22 EC33 EC44 EC5 EC6 EC77 EC88 EC99
*0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *10u/25V_8 *10u/25V_8 *10u/25V_8 10u/25V_8 *10u/25V_8 *10u/25V_8 *10u/25V_8 *10u/25V_8

C C

D D

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5
1A
EMI solution 1A
Date:Wednesday, March 08, 2017 Sheet 50 of 51
1 2 3 4 5 6 7 8
5 4 3 2 1

51
D D

C C

B B

A A

PROJECT : 0P1B
Quanta Computer Inc.
Size Document Number Rev
Custom
NB5 EC ENE KB9027B 1A

Date: Wednesday, March 08, 2017 Sheet 51of 51


5 4 3 2 1

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