Dayananda Sagar Institutions

Dept. Electronics And Communication

FROM
ADITHYA - 1D18EC003
PRESENTATION DATE : 22/04/2020 RAGHAVENDRA - 1DS18EC0016
23/04/2020 SIDDARTH - 1DS18EC043
G CHANDAN - 1DS19EC410
GEETHA S N - 1DS18EC003
CONTENTS
■ FLASH TYPE ADC (01 -08)
■ COUNTER TYPE ADC (09 -12)
■ SERVO TRACKING TYPE ADC (13 -16)
■ SUCCESSIVE APPROXIMATION TYPE ADC (17 -23)
COUNTER TYPE ADC

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OPERATION

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■ One of the simplest types of analog to digital converter is counter type ADC.
■ The input signal of ADC is connected to the signal input of its internal
comparator.
■ The ADC then systematically increases the voltage of the reference input of the
comparator until the reference becomes larger than the signal.
■ And the comparator output goes to 0.
■ Ex: consider an input signal is 4.78 volts. The initial comparator output would be
2.5 volts.
■ The comparator compares the two value then the result this is less than 4.78
then the next higher voltage (5.00 volts) is applied
■ The comparator compares the two value and says this is greater than 4.78 and
switches 0.
■ The digital output of the ADC is the number of times the ADC increase the
voltage after starting at the initial 2.5 volts.
■ This scheme is relatively simple, but as the number of ADC increases the time it
takes to scan through all possible values lower than input will grow quickly.
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COMPONENTS

■ This type of converter uses some type of counter as part of its operation.

■ Counter type contains the following elements:

1. Digital to analog converter Some type of counting mechanism
2. Comparator
3. Clock

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FEATURES
■ Use a clock to index the counter.

■ Use DAC to generate analog signal to compare against input.

■ Comparator is used to compare VIN and VDAC where VIN is

the signal to be digitized.

■ The input to the DAC is from the counter.

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ADVANTAGES
 Simple to understand and operate.
 Cost is less because of less complexity in design

DISADVANTAGES
 Speed is less because every time the counter has
to start from ZERO.
 There may be clash or aliasing effect if the next input
is sampled before completion of one operation.
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 FLASH TYPE ADC
■ Flash Type ADC is based on the principle of comparing analog input
voltage with a set of reference voltages.
■ To convert the analog input voltage into a digital signal of n-bit output,
(2n – 1) comparators are required.
■ The following figure shows 2- bit flash type ADC.

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CIRCUIT DIAGRAM

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 OPERATION

■ Consider first condition, where analog input voltage VA is less than (V/4). In
this case, the voltage at the non-inverting terminals of all the three
comparators is less than the respective voltages at inverting terminals and
hence the comparator outputs are C1C2C3 = 000.
■ This comparator outputs are applied to the further coding circuit to get the
digital outputs as B1B0 = 00
■ Similarly the digital outputs are calculated for other three conditions also.

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ADVANTAGE
■ It is the fastest type of ADC because the conversion is performed
simultaneously through a set of comparators, hence referred as
flash type ADC. Typical conversion time is 100ns or less.

■ The construction is simple and easier to design.

DISADVANTAGE
■ It is not suitable for higher number of bits.

■ To convert the analog input voltage into a digital signal of n-bit

output, (2n – 1) comparators are required. The number of
comparators required doubles for each added bit.
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SERVO TRACKING TYPE ADC
■ In counter type DAC, the counter has to come to zero for every conversion
which is a disadvantageous with respect to high conversion time. However the
input analog signal is continuous in signal amplitude with respect to time. I.e.
the difference between the two sampled analog values will be less, So for the
first analog sampled value if the counter has reached to its equal value the
counter has to be stopped there instead of coming to zero. The second analog
value will be slightly higher or lower than the previous sampled value so the
counter can increase or decrease the count for producing comparable analog
output from DAC.
■ To perform this operation instead of normal counter Up/Down counter is used
in tracking type ADC. After the first sampled value the up/down counter will
tracks the input analog value so that it is called tracking type of ADC. The
detailed block diagram of Tracking type ADC is shown in below figure.
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 OPERATION
■ The N bit up/down counter starts counting according to the clock pulse and
provides a digital input to the DAC. The DAC converts the digital input into
corresponding analog output which is applied to op-amp. The op-amp compares
the DAC analog output with the input analog sampled value, if the input value
greater than the DAC output it provides a clock pulse to increment the counter or
otherwise if it is lesser than the DAC output it provides a clock pulse to
decrement the counter. But normally for first sampled value the counter will
incremented to match to the analog value and for subsequent samples only the
counter may get decrement pulse.
■ When the DAC output is equal to the sampled value, the digital output will be
taken from the up/down counter directly. Here shift register is not needed to
capture the digital date because the counter will not go to reset state. Then
onwards for the next sample value, the counter will increment or decrement
according to the difference output of op-amp.
■ This is also called as Derivative counter type ADC because the counter output
depends difference to the previous and next sampled value like as differentiator.
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ADVANTAGES
 Shift register is not needed so the cost is less.
 Speed is high compared to digital ramp type as the counter will not reset

DISADVANTAGES
 Up/Down counter leads to complexity of the circuit.
 The digital output will never be constant because of differentiator effect.
I.e. for a constant analog value also the output will oscillating this is known
as bit bobble.
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SUCCESSIVE APPROXIMATION ADC

A successive approximation ADC is a

type of analog-to-digital converter that
converts a continuous analog waveform
into a discrete digital representation via
a binary search through all
possible quantization levels before finally
converging upon a digital output for each
conversion.

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BLOCK DIAGRAM

DAC = Digital-to-analog converter.

EOC = End of conversion.
SAR = Successive approximation
register.
S/H = Sample and hold circuit.
Vin = Input voltage.
Vref = Reference voltage.

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 ALGORITHM
The successive approximation analog-to-digital converter circuit typically
consists of four chief sub circuits.

 A sample and hold circuit to acquire the input voltage (Vin).

 An analog voltage comparator that compares Vin to the output of the
internal DAC and outputs the result of the comparison to the successive
approximation register (SAR).
 A successive approximation register sub circuit designed to supply an
approximate digital code of Vin to the internal DAC.
 An internal reference DAC that, for comparison with VREF, supplies
the comparator with an analog voltage equal to the digital code output of
the SARin.

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OPERATION
The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1.
This code is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the
comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the
comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1 and the
same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is
the digital approximation of the sampled input voltage and is finally output by the SAR at the end of the conversion
(EOC).
Mathematically, let Vin = xVref, so x in [−1, 1] is the normalized input voltage. The objective is to approximately
digitize x to an accuracy of 1/2n. The algorithm proceeds as follows:
■ Initial approximation x0 = 0.
■ ith approximation xi = xi−1 − s(xi−1 − x)/2i.
where, s(x) is the signum-function (sgn(x)) (+1 for x ≥ 0, −1 for x < 0). It follows using mathematical induction that
|xn − x| ≤ 1/2n.
As shown in the above algorithm, a SAR ADC requires:
■ An input voltage source Vin.
■ A reference voltage source Vref to normalize the input.
■ A DAC to convert the ith approximation xi to a voltage.
■ A comparator to perform the function s(xi − x) by comparing the DAC's voltage with the input voltage.
■ A register to store the output of the comparator and apply xi−1 − s(xi−1 − x)/2i. 20
 EXAMPLE
■ The ten steps to converting an analog input to 10 bit digital, using
successive approximation, are shown here for all voltages from 5 V to 0 V in
0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is
also 5 V all bits are set. As the voltage is decreased to 4.9 V, only some of
the least significant bits are cleared. The MSB will remain set until the input
is one half the reference voltage, 2.5 V.
■ The binary weights assigned to each bit, starting with the MSB, are 2.5,
1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125,
0.009765625, 0.0048828125. All of these add up to 4.9951171875,
meaning binary 1111111111, or one LSB less than 5.
■ When the analog input is being compared to the internal DAC output, it
effectively is being compared to each of these binary weights, starting with
the 2.5 V and either keeping it or clearing it as a result. Then by adding the
next weight to the previous result, comparing again, and repeating until all
the bits and their weights have been compared to the input, the end result, a
binary number representing the analog input, is found. 21
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 CHARGE – REDISTRIBUTION
■ One of the most common implementations of the successive approximation ADC, the charge-
redistribution successive approximation ADC, uses a charge scaling DAC. The charge scaling
DAC simply consists of an array of individually switched binary-weighted capacitors. The amount
of charge upon each capacitor in the array is used to perform the aforementioned binary search in
conjunction with a comparator internal to the DAC and the successive approximation register.
■ First, the capacitor array is completely discharged to the offset voltage of the comparator, VOS.
This step provides automatic offset cancellation(i.e. The offset voltage represents nothing but
dead charge which can't be juggled by the capacitors).
■ Next, all of the capacitors within the array are switched to the input signal, vIN. The capacitors
now have a charge equal to their respective capacitance times the input voltage minus the offset
voltage upon each of them.
■ In the third step, the capacitors are then switched so that this charge is applied across the
comparator's input, creating a comparator input voltage equal to −vIN.
■ Finally, the actual conversion process proceeds. First, the MSB capacitor is switched to VREF,
which corresponds to the full-scale range of the ADC. Due to the binary-weighting of the array the
MSB capacitor forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the
comparator is now −vIN plus VREF/2. Subsequently, if vIN is greater than VREF/2 then the
comparator outputs a digital 1 as the MSB, otherwise it outputs a digital 0 as the MSB. Each
capacitor is tested in the same manner until the comparator input voltage converges to the offset
voltage, or at least as close as possible given the resolution of the DAC. 23
THANKYOU

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