This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2019.2933276, IEEE
Transactions on Circuits and Systems II: Express Briefs
A 0.9-V Analog-to-Digital Acquisition Channel
for an IoT Water Management Sensor Node
Hugo Serra, Member, IEEE, Ivan Bastos, Member, IEEE, João L. A. de Melo, Member, IEEE,
João P. Oliveira, Member, IEEE, Nuno Paulino, Senior Member, IEEE, Elyes Nefzaoui, and Tarik Bourouina
Abstract—This paper presents an analog front-end (AFE)
specially developed for a water conductivity measurement system
for water network management applications. Water conductivity
is one of the best ways to detect a problem with the water in
the network. In order to trigger an alarm it is only required
to detect a 10 % variation, which allows to simplify the system
design. The proposed sensor uses four platinum micro-machined
electrodes, where a 6 kHz signal is applied to the outer electrodes
and a voltage signal is read in the inner ones. A programmable
switched-capacitor (SC) bandpass filter is included in the analog-
to-digital (A/D) channel to attenuate the interference from the
50 Hz power network, that shares the same environment with
the water network, and to allow using a square wave signal to
drive the sensor, thus simplifying the overall system. The resulting
sine wave is digitized using a passive continuous-time (CT) 2nd
order ∆Σ modulator. The output bitstream is decimated, using
a sinc filter, and the RMS value of the voltage is calculated. The
A/D acquisition channel was implemented in a 130 nm CMOS
technology, using a supply voltage of 0.9 V and a clock frequency
of 1 MHz (SC amplifier and SC bandpass filter) and 4 MHz (∆Σ
modulator). Measurement results show a SNDR of 44.4 dB for an
input signal of 6 kHz and an amplitude of -41 dBV. The channel
dissipates 386 µW and occupies an area of 0.27 mm2 .
Index Terms—Analog front-end, CMOS, conductivity sensor,
MEMS.
I. I NTRODUCTION
T HE scarcity of drinking water is pushing public water
distribution networks towards very high efficiency and
quality levels, which is demanding a significant reinforcement
in water monitoring and quality management systems. How-
ever, to increase the monitoring coverage of the water network,
it is necessary to deploy an increasing number of monitoring
nodes across the network. This requires the development of a
new type of easy to install and cheaper sensing node.
To monitor the state of the water network, it is necessary
to measure several key parameters at different locations. The
objective is to quickly detect a problem in a terminal pipe. This
can be achieved by detecting if a significant change occurs in
any of the relevant parameters, such as pressure, temperature
and water conductivity [1]. In particular, any sudden alteration
in the water conductivity can reveal a contamination problem
Hugo Serra, Ivan Bastos, João L. A. de Melo, João P. Oliveira, and Nuno
Paulino are with the Department of Electrical Engineering, Faculty of Sciences
and Technology, Universidade Nova de Lisboa, 2829-516 Caparica, Portugal,
and also with the Center for Technology and Systems (CTS/UNINOVA),
2829-516 Caparica, Portugal (e-mail: hugoaaserra@gmail.com).
Elyes Nefzaoui and Tarik Bourouina are with Université Paris-Est, ESY-
COM Lab, ESIEE-Paris, Noisy-Le-Grand, France.
Hugo Serra is now with Instituto de Telecomunicações, 1049-001 Lisboa,
Portugal.
This work was supported by project Proteus funded by the European
Union’s H2020 Programme (grant no. 644852), by FCT – Fundação para a
Ciência e a Tecnologia, CTS – Centre of Technology and Systems (reference
UID/EEA/00066/2019), and by project foRESTER (PCIF/SSI/0102/2017).
1549-7747 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
in the water pipe. In fact, when the water quality is compro-
mised, conductivity is one of the first water parameters that
signals a problem. Since the conductivity of drinking water
should be smaller than 2500 µS and in normal conditions is
below 800 µS, an accuracy of 10 % (250 µS) is enough to
detect a problem, relaxing the accuracy specifications for the
sensor. Therefore, most of the problems can be found out if a
10 % change in the conductivity of the water is detected. This
allows to simplify the design of the system.
To achieve a compact and low-cost solution, MEMS tech-
nology was used for the implementation of the conductivity
sensor. Among the available water sensor configurations, a
good candidate for MEMS fabrication, consists of a four
platinum electrodes arrangement involving two external ones
for signal excitation and two internal ones for sensing readout.
The AC signal injected between the external electrodes has
an optimum frequency range up to 10 kHz and the applied
voltage should be low (in the order of 10 mV), to reduce
electro-erosion of the platinum. At certain frequency values the
RMS voltage value of the inner electrodes is directly related
with the water conductivity level. The water temperature is
also measured by the water management system, in order to
correct/compensate the measured water conductivity value.
This paper presents an analog front-end (AFE) specially de-
veloped to drive and process the signals to and from the water
conductivity sensor. The block diagram of the sensor system
is shown in Fig. 1 which includes a digital-to-analog converter
(DAC) that applies an AC signal to a micro-fabricated set of
electrodes, a switched-capacitor (SC) amplifier, a SC bandpass
filter, a delta-sigma (∆Σ) analog-to-digital converter (ADC)
and a digital filter to calculate the RMS value of the measured
voltage from the micro fabricated electrodes.
FPGA Drms Ddec
DAC
n n
Clk
Voltage Clock RMS Decimation
Divider
Din
Divider Algorithm n Filter
1
G
ΔΣ
Dout
Modulator
Micro fabricated
electrodes inside
SC Amplifier Bandpass SC Filter
water pipe IC
Fig. 1. Simplified block diagram of the A/D acquisition channel proposed
for the water management sensor node.
II. A NALOG - TO -D IGITAL ACQUISITION C HANNEL
The simplified block diagram of the analog-to-digital (A/D)
acquisition channel, proposed for the water management sen-
sor node, is shown in Fig. 1. The system is divided into three
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2019.2933276, IEEE
Transactions on Circuits and Systems II: Express Briefs
2

main parts: the conductivity sensor; the A/D channel; and

Zm Zm
the digital-to-analog (D/A) channel. These parts are described VDAC
Re1 Re2
next. e1 Rw e2
Cdl1 Cdl2
Re3 Re4
A. Conductivity Sensor Cdl3 Cdl4
To establish an electrical connection to water it is necessary Vmeas
e3 e4
to use electrodes [2]. The charge transfer that can occur at Fig. 2. Equivalent electrical circuit of the impedance measurement using 4
the interface between the electrodes and the water, due to electrodes (based on [2], [3]).
oxidation reduction reactions, can cause the degradation of
the electrodes, due to corrosion. To reduce this problem, it B. Analog Channel Circuits
is important to keep the applied voltage across the electrodes The analog channel is composed by: a SC amplifier, which
low (around 10’s mV). Moreover, the resistance between the is used to sample and amplify the signal after the conductivity
electrode and the water (reaction resistance - Re ) varies non- sensor; a bandpass SC filter, which is used to attenuate the
linearly with the applied voltage and is larger for lower harmonics of the square wave and unwanted interference
voltages. Fortunately, a capacitance coupling between the signals; and a ∆Σ modulator, which is used to convert the
electrode and the water (Cdl ) also exists, this capacitance is in discrete-time sinusoid to the digital domain. These circuits
parallel with Re , which allows an AC signal (in the low kHz are described in more detail in the following sections.
range) to bypass Re . Using AC signals to measure the water
conductivity also minimizes the degradation of the electrodes 1) Programmable Switched-Capacitor Amplifier:
due to corrosion. The programmable SC amplifier [4] is shown in Fig. 3. Dur-
As shown in Fig. 2, a pair of electrodes (e1 and e2 ) in ing phase Φ2 , the input signal and the amplifier’s offset voltage
contact with water, exhibit an impedance that is composed by (Vos ) are stored. In phase Φ1 , the input signal is amplified and
the impedance due to the water and the parasitic impedance the offset voltage is canceled, as shown by the circuits transfer
of the electrodes (Rp and Cp in series, for clarity they are function (1), where capacitor C2 is a programmable capacitor
not shown). Since the objective is to determine a variation in bank in order to allow for gain programmability. The flicker
the water resistance (Rw ), it is important to select a frequency noise is also reduced since, at low frequencies, it resembles
value where the impedance across the electrodes is strongly an offset voltage. This is important, since the signal biasing
dependent on the value of Rw . For lower frequencies, the value the conductivity sensor is in the low kHz range, and at these
of this impedance is dominated by the high Re value and for frequencies the flicker noise is still significant.
high frequency values, the impedance is very small, due to Cp C1 −1/2
and Rp . A plot of the theoretical impedance across a pair of H(z) = Vout /Vin = z (1)
C2
electrodes in contact with water is presented in [2], where it is
concluded that the largest variation in the measured impedance Due to the sensing of the offset voltage (Vos ), during phase
(Zm ), due to the variation of Rw , occurs in the low kHz. Φ2 , the following circuit needs to acquire the amplifier’s output
In this frequency range and for water acceptable to human during phase Φ1 . The gain block is implemented using a folded
consumption (which has a conductivity value smaller than cascode transconductance amplifier and the circuit’s common-
2500 µS/cm), the impedance of the electrodes (Re1,2 //Cdl1,2 ) mode voltage is set using a conventional SC common-mode
is smaller than the water resistance. By adding an inner feedback circuit.
C2 Ф2
pair of electrodes to the sensor, e3 and e4 , as shown in
Vcm
Fig. 2, it is possible to use the ADC to measure the voltage Ф1
Ф2
division of the voltage applied to e1 and e2 , between the water Ф2 C1
Vin +
conductivity and the impedance of the outer electrodes-water Vout +
interface (Re1,2 // Cdl1,2 ). Since uncontaminated water has a Ф1 Vos
Vout −
lower conductance, any increase in the conductivity, due to Vin −
Ф2 C1
contamination, results in a decrease in the measured voltage Ф2
Ф1
across e3 and e4 . This approach maximizes the voltage that Vcm
C2 Ф2
needs to be digitized under normal conditions, i.e, clean water
(close to the maximum voltage applied), thus simplifying the Fig. 3. Programmable SC amplifier using offset compensation.
specifications of the A/D channel. Within the range of water
conductivities suitable for human consumption (500 µS/cm to 2) Programmable Bandpass Switched-Capacitor Filter:
2500 µS/cm), the input amplifier does not require a very large The programmable bandpass SC biquad filter [5], which
input impedance nor a large gain. is shown in Fig. 4, is based on the continuous-time (CT)
A further simplification can be me made by applying a bandpass Sallen-Key topology [6], replacing the resistors with
square wave signal instead of a sinusoidal signal. This will parallel SC branches. This architecture is capable of imple-
result in a 1-bit DAC that is built using only CMOS inverters menting bandpass filtering functions using a low-gain amplifier
in series with a resistor. The square wave signal will be filtered (< 2). Due to the low gain, the circuit is sensitive to the
by the bandpass filter, resulting in a sine wave at the input of effects of the parasitic capacitances. Since the top and bottom
the ADC. plate parasitic capacitances of the capacitors are substantially

1549-7747 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2019.2933276, IEEE
Transactions on Circuits and Systems II: Express Briefs
3

different, the differential capacitors (C1 , C2 , C4 , C5 , and C7 ) 1) Square Wave Generator:

are implemented using two capacitors in anti-parallel, allowing The square wave signal biasing the conductivity sensor is
both sides of the differential circuit to see, approximately, the generated in the same manner as the clock signals for the
same parasitic capacitance. The input common-mode voltage analog circuits. The amplitude of the square wave is attenuated
(Vcm ) of the amplifier is set through the switched network to the desired value using a resistive voltage divider, as shown
formed by capacitor C4 . in Fig. 6. Since the required amplitude is small (10 mV),
Ф2 Ф1 capacitor C1 is used to reduce noise and also to provide a small
Ф1 Ф2 degree of filtering to the square wave. The signal’s amplitude
C3 C6
Vin + can be adjusted by varying potentiometer R1 . Note that the
Ф1 Ф2
Vcm accuracy of the measurement is not affected by variations in
Vout +
G the amplitude, since the reference of the ADC is also obtained
C1 C2 C5 C4 C7 Vout −
Vcm
Ф1 Ф2 from the same voltage.
Vin −
Ф1 Ф2 C3 C6
Clock Din
R1
Clk Dout
Ф2 Ф1 Divider
R2
Fig. 4. Programmable bandpass SC biquad filter using a low-gain amplifier. FPGA C1

To achieve programmability in the filter’s gain, center Fig. 6. Resistive voltage divider used to attenuate the square wave’s amplitude.
frequency (fc ), and quality factor (Qp ), capacitors C1 , C2 , and
2) Cascaded Integrator-Comb Decimation Filter:
C5 were made programmable using a bank of capacitors.
The decimation of the ∆Σ’s bitstream is performed using a
3) Continuous-Time Delta-Sigma Modulator: third-order CIC decimation filter, which is shown in Fig. 7.
The schematic of the second-order 1-bit CT ∆Σ modulator Dout Integrator Stage
is shown in Fig. 5 and uses a similar approach to the one k1
Σ z-1 k2 k3 Σ z-1 k2 k3 Σ z-1 k2
described in [7]. The loop filter uses passive RC integrators - k1
plus an open-loop low-gain amplifier as an interstage gain.
Vdec Σ - z-M Σ - z-M Σ - z-M
Resistor R3 adds a zero to the loop, which helps stabilize + + +
the closed-loop system with only one feedback path. At high
Comb Stage
frequencies, this resistor works as a resistive voltage divider,
acting as a feedforward path in the second integrator stage. The Fig. 7. Block diagram of the third-order CIC decimation filter.
comparator is implemented using a pre-amplification stage, where, M is the decimation factor. The gain k2 is used to
a regenerative latch, and a D flip-flop. The pre-amplification avoid
Pn the −i
integrator stages from saturating and is given by
stage is used to reduce the input-referred offset and to attenuate 2 , where n should have the lowest possible value
i=1
the regenerative latch’s kickback noise. Since this architecture without impacting the signal’s SNDR. The gain k2 is achieved
only uses differential pairs (resistive loaded common-source using binary shifts and k1 is a power of two, high enough to
amplifier) and positive feedback in the comparator, to provide reduce the error due to the loss of bits from the binary shifts
the required gain, these circuits can be designed to have low and high enough to use most of the width of the registers.
power dissipation and work at lower supply voltages. The gain k3 is a negative power of two and is used to reduce
the width necessary for the computing registers of the CIC
R1
Vin − R2 decimation filter. The filter’s transfer function is shown in (2).
R3 1-bit 2 
k1 k2 z −1 k3 k2 z −1
  3
Dout + HCIC = 1 − z −M (2)
C1 C2 Vx 1 − k2 z −1 1 − k2 z −1
Dout −
R3 Fs
Vin +
The values used in the CIC decimation filter’s parameters
R2
R1 are shown in Table I, where cells with multiple values repre-
sent the value for each stage.
Fig. 5. Second-order 1-bit continuous-time ∆Σ modulator.
TABLE I
CIC DECIMATION FILTER PARAMETERS
C. Digital Channel Circuits
Registers width (bits)
M k1 k2 k3
The digital circuits were synthesized in Verilog and pro- Integrator Stages Comb Stages
grammed into a Digilent Cmod S6 board, that features a 64 212 0.992188 2−5 , 2−7 18 18, 17, 16
Spartan 6 field-programmable gate array (FPGA). The clock
signals for the analog circuits are generated using the FPGA 3) Root Mean Square Algorithm:
global clock signal (8 MHz) and counters to create clock The RMS algorithm used to obtain an approximate value to
signals with the appropriate frequency. The remaining digital the decimated bitstream’s RMS voltage is divided into three
circuits are a square wave generator, a cascaded integrator- parts: the sum of nsamples (128) squared decimated samples
comb (CIC) decimation filter, and a root mean square (RMS) (Vdec sum ), the division of this sum by nsamples , and the square
algorithm, which are described next. root of the resulting value. The square root is calculated using

1549-7747 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2019.2933276, IEEE
Transactions on Circuits and Systems II: Express Briefs
4

a bitwise binary search algorithm and determines the closest B. Analog Channel Measurement Results
integer value less than or equal to the real RMS value, i.e.: The SC amplifier, the bandpass SC biquad filter and the
$s
∆Σ modulator, presented in the previous section, were im-
$s % %
Vdec sum Xnsamples Vdec 2
Vrms = ⇔ Vrms = (3) plemented in a standard 130 nm CMOS technology, using
nsamples i=1 nsamples
a supply voltage of 0.9 V and clock frequencies (Fs ) of
The algorithm begins by setting the most significant bit 1 MHz (SC amplifier and bandpass SC filter) and 4 MHz
position and calculating its square value, if it is larger than (∆Σ modulator). The individual performance of each block
the input, the bit is left at ’0’, otherwise it is set in the in the analog channel is summarized in Table II.
variable. This process continues for each bit, decreasing in
TABLE II
bit significance, until all bits have been determined. Using I NDIVIDUAL PERFORMANCE OF THE ANALOG CHANNEL BLOCKS
this approach, the algorithm takes nbits /2 cycles to calculate
Programmable SC Amplifier
the RMS of a register, where nbits represents the width of the
Fs (MHz) GBW (MHz) Gain (dB) Power (µW) Area (mm2 )
register containing the sum of the square decimated samples. 1.0 16.1 18.4 ∼ 37.9 123.0 0.03
Once a new RMS value is calculated, the output is updated. Programmable Bandpass SC Filter
fc (kHz) Qp Fs (MHz) Gain (dB) Power (µW) Area (mm2 )
III. M EASUREMENT R ESULTS 3.9 ∼ 7.1 0.9 ∼ 6.9 1.0 -6.4 ∼ 12.6 256.4 0.10
A. Conductivity Sensor Measurement Results Continuous-Time ∆Σ Modulator
The frequency response of the conductivity sensor, which Fs (MHz) Peak SNDR (dB) FoM (fJ/step) Power (µW) Area (mm2 )
4.0 63.5 116 5.86 0.14
is shown in Fig. 8(b), was measured for different water con-
ductivity values, to determine the best frequency value for the
signal driving the sensor, i.e., the frequency where the variation The die photo of the analog channel is shown in Fig. 9.
between water conductivity and sensor conductance is most The AFE circuits were connected to the digital part of the
linear. The conductivity range used is between 500 µS/cm system, implemented in the FPGA, using a custom PCB. The
(clean water) and 2500 µS/cm (contaminated water), which is board has a level shifter IC to reduce the amplitude of the
the recommended range for drinking water. The conductivity clock signals, going from the FPGA to the analog channel,
values shown in Fig. 8(b) were obtained using distilled water from 3.3 V to 0.9 V. In the same manner, one of the outputs
and different quantities of a contaminant. To have a base of the ∆Σ modulator also goes through the level shifter, in
of reference, the water’s conductivity was measured using a the opposite direction, to elevate its voltage.
147.2 µm
commercial conductivity meter, while the conductance was ΔΣ Modulator

measured by the fabricated conductivity sensor, described in

209.2 µm
Section II-A and shown in Fig. 8(a).
487.2 µm

SC Bandpass Filter
204.5 µm

SC
Amplifier

291.7 µm 487.2 µm

Fig. 9. Die photo of the analog channel.

The analog channel’s measured SNDR, as a function of the

input signal amplitude, is shown in Fig. 10. In this case, the
(a)
input signal was generated by an audio test system (Audio
0.6
555 uS/cm Precision ATS-2) with a frequency of 6.02 kHz.
0.5 1077 uS/cm
1539 uS/cm 50.0
Conductance (S)

0.4 2100 uS/cm

2540 uS/cm 40.0
0.3
SNDR (dB)

0.2 30.0

0.1 20.0

0.0 10.0
100 101 102 103 104 105
Frequency (Hz) 0.0
-80 -70 -60 -50 -40 -30 -20
(b)
Input Signal Amplitude (dBV)
Fig. 8. Conductivity sensor: (a) photo of sensor chip and (b) measured
conductance frequency response for different water conductivity levels. Fig. 10. Measured SNDR of the analog channel at 6.02 kHz.

These results show that the most linear variation, between The measured output spectrum of the analog channel’s
the sensor’s measured conductance and the water’s conductiv- bitstream, for an input signal of -41 dBV, at 6.02 kHz, is
ity, is in the frequency range between 200 Hz up to 10 kHz. shown in Fig. 11.

1549-7747 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2019.2933276, IEEE
Transactions on Circuits and Systems II: Express Briefs
5

TABLE III
P ERFORMANCE COMPARISON OF SENSING INTERFACES
This Work TCSI’17 [8] TBCAS’17 [9] JSEN’15 [10] ASSCC’14 [11] JSSC’14 [12] IJEC’12 [13]
Technology (µm) 0.13 0.35 0.35 0.35 0.13 0.35 0.35
Supply Voltage (V) 0.9 3 3.3 3.3 1.2 3.3 3.3
Power (mW) 0.386 2.19 0.150/0.170 19.14 0.012 1.65 0.820
fin (kHz) 3.9 ∼ 7.1 10 < 100 0.041 ∼ 16.34 0.9 ∼ 2.8 1 ∼ 16 1
Fs (MHz) 1/4 2 40 (fin = 10 mHz) 56 22.8 ∼ 89.6 0.512 ∼ 8 0.025
Chip Area (mm2 ) 0.27 2.37 0.07 1.12 0.6 9 1.32
ADC Type CT ∆Σ CT ∆Σ MDC/PDC No SAR BP ∆Σ BP ∆Σ
Sensor Type Conductivity Salinity EIS Salinity EIS Impedance CTD

0 26
SNR = 44.67 dB Trendline µ = 22.50 µV-1
-20 SNDR = 44.40 dB σ = 0.16 µV-1
SFDR = 55.20 dB 22

1/Voltage (1/µV)
Power (dBFS)

-40 µ = 18.23 µV-1

σ = 0.19 µV-1
µ = 20.69 µV-1
-60 18 σ = 0.25 µV-1
µ = 15.13 µV-1
-80 σ = 0.09 µV-1
14
-100 µ = 13.15 µV-1 y = 0.0046 x + 12.1
σ = 0.21 µV-1 R² = 0.9666
-120 10
102 103 104 105 106 0 500 1000 1500 2000 2500
Frequency (Hz) Conductivity (µS/cm)

Fig. 11. Measured output spectrum of the analog channel’s bitstream for a Fig. 13. Voltage measured at the output of the proposed acquisition channel,
-41 dBV input at 6.02 kHz (216 points FFT). using the fabricated conductivity sensor, for different water conductivity levels.

C. Analog-to-Digital Channel Measurement Results
The measured signal at the input of the ∆Σ modulator, the
decimated bitstream, and its RMS value (implemented using
the FPGA), when driving the sensor with a square wave signal,
are shown in Fig. 12. The RMS value returned by the FPGA
is approximately the same as the one obtained from sine wave
at the input of the ∆Σ modulator (∼28 mV).
(a) (b)
Fig. 12. Measured signal at the input of ∆Σ modulator (SC filter output) and:
(a) decimated bitstream, (b) bitstream’s RMS value, obtained from the FPGA.
The acquisition channel was measured, ten times, for dif-
ferent water conductivity values. The results are shown in
Fig. 13, where the x-axis represents the water conductivity,
measured by a commercial conductivity meter (providing a
base of reference) and the y-axis represents the 1/Voltage of
the signal’s amplitude, measured at the output of the system
described in this paper, using the fabricated conductivity
sensor. The resulting plot should be as linear as possible.
A performance comparison between the proposed acquisi-
tion channel and other sensing interfaces is show in Table III.
IV. C ONCLUSION
This paper presented an AFE developed to measure the con-
ductivity of water for water network management applications.
Measurement results show that the analog channel has a peak
SNDR of 48.9 dB and that the FPGA correctly decimates and
calculates the RMS value of the measured signal read from the
sensor. The trendline from the measured voltage, for different
conductivity levels, shows a good variation in the acquisition
channel output voltage with the conductivity value (R2 = 0.97).
R EFERENCES
[1] Proteus. (2018) AdaPtative micROfluidic and nano-enabled smart
systems for waTEr qUality Sensing (PROTEUS). H2020 grant No.
644852. [Online]. Available: http://www.proteus-sensor.eu/
[2] A. Hyldgård, D. Mortensen, K. Birkelund et al., “Autonomous multi-
sensor micro-system for measurement of ocean water salinity,” Sens.
Actuators A: Phys., vol. 147, no. 2, pp. 474–484, Oct. 2008.
[3] X. Huang, R. W. Pascal, K. Chamberlain et al., “A miniature, high preci-
sion conductivity and temperature sensor system for ocean monitoring,”
IEEE Sensors J., vol. 11, no. 12, pp. 3246–3252, Dec. 2011.
[4] R. Gregorian, K. W. Martin, and G. C. Temes, “Switched-capacitor
circuit design,” Proc. IEEE, vol. 71, no. 8, pp. 941–966, Aug. 1983.
[5] H. Serra, J. P. Oliveira, and N. Paulino, “A 0.9-V programmable second-
order bandpass switched-capacitor filter for IoT applications,” IEEE
Trans. Circuits Syst. II: Exp. Briefs, vol. 65, no. 10, pp. 1335–1339,
Oct. 2018.
[6] R. P. Sallen and E. L. Key, “A practical method of designing RC active
filters,” IRE Trans. Circuit Theory, vol. 2, no. 1, pp. 74–85, Mar. 1955.
[7] J. L. A. de Melo, N. Paulino, and J. Goes, “Continuous-time delta-sigma
modulators based on passive RC integrators,” IEEE Trans. Circuits
Syst. I: Reg. Papers, vol. 65, no. 11, pp. 3662–3674, Nov. 2018.
[8] C. T. Chiang, “A CMOS seawater salinity to digital converter for IoT
applications of fish farms,” IEEE Trans. Circuits Syst. I: Reg. Papers,
vol. 64, no. 9, pp. 2591–2597, Sep. 2017.
[9] T. A. Chen, W. J. Wu, C. L. Wei et al., “Novel 10-bit impedance-to-
digital converter for electrochemical impedance spectroscopy measure-
ments,” IEEE Trans. Biomed. Circuits Syst., vol. 11, no. 2, pp. 370–379,
Apr. 2017.
[10] C. T. Chiang and C. W. Chang, “Design of a calibrated salinity
sensor transducer for monitoring salinity of ocean environment and
aquaculture,” IEEE Sensors J., vol. 15, no. 9, pp. 5151–5157, Sep. 2015.
[11] J. Gu, H. Yao, K. Wang et al., “A 10µA on-chip electrochemical
impedance spectroscopy system for wearables/implantables,” in IEEE
Asian Solid-State Circuits Conf., Nov. 2014, pp. 309–312.
[12] M. Crescentini, M. Bennati, and M. Tartagni, “A high resolution
interface for Kelvin impedance sensing,” IEEE J. Solid-State Circuits,
vol. 49, no. 10, pp. 2199–2212, Oct. 2014.
[13] M. Crescentini, M. Bennati, and M. Tartagni, “Design of inte-
grated and autonomous conductivity–temperature–depth (CTD) sensors,”
AEU—Int. J. Electron. Commun., vol. 66, no. 8, pp. 630–635, Aug. 2012.

1549-7747 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.