Interfacing Logic Families

Interfacing between Logic Devices

 In order to interface between logic devices

 Must consider the voltage levels of the driving and load devices.

 Must consider the current sourced and sunk by the driving and load

devices, respectively.
 Interfacing between Logic Devices

 Voltage:
 The VOH of the driving device must be greater than the VIH of the load device.
 The VOL of the driving device must be less than the VIL of the load device.
 Noise Margin

 Current:
 The driving device sources current for one or more load devices.
 Must consider the fan-out limit for the driving device.
 Interfacing Logic Families

• Suppose we want to connect the output of a TTL gate to the input of a CMOS gate.

• A TTL HIGH output may be as low as 2.4 V.

• But CMOS expects at least 3.3 V for a HIGH.

• Problem: The CMOS gate may interpret the TTL gate’s HIGH output as a LOW.

• Solution? See next slide.

 Interfacing Logic Families
• TTL to CMOS
– Pull-up resistor

When the TTL output is high, its output transistors are not trying to pull current into the output pin from the positive side of the power

supply. As far as the pull-up resistor is concerned, its lower terminal is connected to an approximately open circuit. Therefore, since

practically no current flows through the resistor, there's no voltage drop and the lower terminal of the resistor is at the same voltage as

the top, which is Vdd.

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 TTL/CMOS Interfacing
TTL: CMOS :
VOL = 0.7 V, VIL = 2.3,
VOH = 3.3V) VIH = 3.4V

TTL CMOS

1. We do have a problem when TTL drives CMOS.

2. TTL driving HC (high speed CMOS) doesn’t work unless the TTL high output happens to be higher and the
CMOS high input threshold happens to be lower by a total of 1V.

3. To drive CMOS inputs properly from TTL outputs, the CMOS device should be TTL compatible (i.e. use
HCT, VHCT, FCT)
TTL/CMOS Interfacing

 CMOS has very high input impedance so almost no current is required

in either state!
 So TTL can drive CMOS with no problems if we are considering fan-
out (up to 15 gates)

TTL CMOS
 Interfacing Logic Families

• CMOS to TTL –

40
 Interfacing Logic Families

• CMOS to TTL –

41
 CMOS/TTL Interfacing

 For example : HC or HCT driving TTL

CMOS TTL

VOL max C  0.33V  VIL max T  0.8V √

VOH min C  3.84V  VIH min T  2.0V √
 CMOS/TTL Interfacing

 TTL driving HC or VHC

TTL CMOS
VOL max T  0.55V  VIL max C  1.5V √
VOH min T  2.7V  VIH min C  3.85V X
TTL can’t drive HC or VHC directly.
Current levels when interfacing CMOS to TTL: (a) CMOS IOH and (b) CMOS IOL

√ X
Using the 4050B CMOS buffer to supply sink and source current to two standard TTL loads.

√
 Comparison of Digital IC Families

Performance Ratings 74HC 4000B 74 74S 74LS 74AS 74ALS ECL

Power Dissipation/gate (mW)

Static 2.5x10-3 1x10-3 10 20 2 8 1.2 40

@ 100kHz 0.17 0.1 10 20 2 8 1.2 40

Propagation Delay (nSec) 8 50 9 3 9.5 1.7 4 1

Speed Power Product 1.4 5 90 10 19 13.6 4.8 40

@ 100kHz

Max Clock rate (MHz) 40 12 35 12.5 45 200 70 300

Voltage Parameters

Worst Case Noise Margin 0.9 1.5 0.4 0.3 0.3 0.3 0.4 0.25

All of the performance ratings are for a

NAND gate in each series.
 Comparison of TTL Series Characteristics
74 74L 74H 74S 74LS 74AS 74
ALS
Performance Propagation 9 33 6 3 9.5 1.7 4
Ratings Delay (nSec)

Power 10 1 23 20 2 8 1.2
Dissipation
(mW)
Speed Power 90 33 138 60 19 13.6 4.8
(pJ)

Max Clock 35 3 50 125 45 200 70

rate (MHz)

Fan-out 10 20 10 20 20 40 20
(same series)

Voltage VOH(min) 2.4 2.4 2.4 2.7 2.7 2.5 2.5

Parameters

VOL(max) 0.4 0.4 0.4 0.5 0.5 0.5 0.4

VIH(min) 2.0 2.0 2.0 2.0 2.0 2.0 2.0

VIL(max) 0.8 0.7 0.8 0.8 0.8 0.8 0.8

All of the performance ratings are for a NAND gate in each series.
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