Chapter 6

Interfacing and communication

I/O Fundamental

# I/O devices cannot connect directly to the CPU because:

1. The formats required for different devices are different.
 some require single piece of data.
 Some require a block of data
 Some expect data sequentially
 Some expect data in parallel
2. Incompatibilities in speed make synchronization difficult.

# Therefore, there must be:

 A means to individually address different devices.
 A way in which peripheral device can initiate communication with CPU.
Eg, enable response to unexpected input.

# Input Output Technique

 Handshaking - provide some status bits in a secondary input port to indicate
that a device is ready to accept or transmit data. For example, a one in a
single bit in an I/O port can tell the CPU that a printer is ready to accept more
data, a zero would indicate that the printer is busy and the CPU should not
send new data to the printer.

 direct control – CPU controls the device by reading/writing data lines directly.

 programmed I/O – data transferred through an I/O port and controlled by

software.

 Direct memory access (DMA)– Used to transfer data from disk and tapes to
memory. Used to transfer large amount of data. If amount of data is small,
better use PIO. CPU commands device which transfers data directly to/from
memory. Advantages: Release the CPU from doing data transfer and High
speed disk transfer.

 I/O channels – device has specified processor which interprets special

command set. CPU asks device to execute entire I/O program.

 polled I/O – Microprocessor checking each device in rotation at frequent

intervals to see if it needs service. The CPU will be busy checking each device
in rotation at frequent intervals. The computer time spent in polling is largely
wasted. Not efficient when the processor needs to perform other tasks. Need
better system that allow processor to be free to continue normal sequential

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 execution and only stop to deal with a peripheral when it specially needed
attention. So that, interrupt system has been design to satisfy the requirement
for external input control and freeing the CPU from waiting for events to occur.

Interrupt

# Interrupt is a call for the microprocessor to interact or service the interrupting unit. The
interrupt will cause the computer to suspend the program being executed and jump into
a special interrupt processing program.
# There are many circumstances under which it would be desirable to interrupt the normal
flow of a program in the computer to react to special event. Example:
 User command from keyboard
 Command from other external input
 Abnormal situation – power failure
 Execution of an illegal instruction
 Completion signaling of an I/O task

# Advantages of Interrupt
 Allow computer to take special actions when required.
 Used to time-share the CPU between several different programs at once.
 Satisfy the requirement for external input control.
 Provides the desirable feature of freeing the CPU from waiting for events to occur.

Interrupt service

# The messages sent through the IRQ (Interrupt ReQuest) lines is known as interrupt.
# The interrupt will cause the computer to suspend the program being executed and jump
to a special interrupt processing program.
# Interrupt handler program – action taken by the processor when an interrupt occurs. Also
known as interrupt routine.
# When interrupt occurs, the processor will then execute the interrupt routine called for.
# The process of determining the appropriate course of action by the interrupt handler
program (interrupt routine) is known as servicing the interrupt.

# There are 4 distinct steps that microprocessor takes after an interrupt.

1. The microprocessor finished the current instruction, until the end of an instruction
cycle.
2. Normal operation is suspended.
i. All the pertinent information about the program being suspended is
saved/preserved in a known part of memory. Either in a special area associated
with the program (process control block) or in a part of memory known as stack
area.
ii. Pertinent information including:
 Location of the last instruction executed.
 Values of data in various registers that contain pieces of information
relate to the algorithm being carried out when the interrupt occurred.
iii. The contents of the registers and the status of microprocessor in general must
be preserved so that it can again resume operation when the interrupt has been
serviced.

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 3. The microprocessor jumps to the location in memory where the interrupt service
routine has been stored and executes the routine. The address of the routine may
be fixed in the microprocessor design.
4. When interrupt routine complete its task, it would return control to the interrupted
program.
i. The processor returns from an interrupt. The return includes restoring the
microprocessor to its exact condition before the interrupt occurred.

ii. All registers were restored to their original values. The information they
contained must be retrieved from memory and placed back in their respective
registers.

iii. Finally, the program counter (PC) is loaded with retrieval address of instruction
that would have been executed if an interrupt had not occurred.

iv. The original program would resume execution exactly where it left off.

Usage of interrupt

# The way in which an interrupt is used depends on the nature of the device.
# There are several different ways in which interrupt are used:
 As an external event notifier, ex: printer out of paper
 As a completion signal. Ex: printer completes a job.
 As a means of allocating CPU time. Ex. To handle more than one program those
are sharing the CPU.
 As an abnormal event indicator. Ex: computer execute illegal instruction, ex:
divide by zero, and hardware error detected.

Multiple interrupt and prioritization

# There are many different input and output devices and event indicators connected to
interrupt lines.
# Multiple interrupts will occur from time to time. Two different processing method used for
determining which device initiated interrupt:
 Vectored interrupt
 Polling

# Multiple interrupt can be handled by assigning priorities to each interrupt – handle top
priority first.
# Most computer system allows the system manager to establish priorities for various
interrupt.
# There are three methods used to establish priorities:
i) Logical way
ii) Hardware or software
iii) Assigning a priority number to each interrupts.

i) Logical way
 Highest priority are reserved for time sensitive situation.
- Power failure, external event.
 Lower priority usually for task completion interrupts.

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ii) Hardware or software

 Highest priority devices are placed closest to the CPU.

 Connecting most critical devices to the interrupt pin with the highest priority.
 Used chips that perform a prioritizing function.
- All peripheral devices are connected to the interrupt controller chip.
- Sends the interrupt on to the microprocessor along with the address of the
interrupt routine to execute.

Vectored Interrupt

# Address of the interrupting device is included as a part of the interrupt. When the
interrupt request occurs, the microprocessor will automatically load the program counter
with the assigned address. Assigned address contains the address of the routine to be
executed. The interrupt will then check the assigned address to get the interrupt routine.

# Example: Assume that assigned interrupt address is FFFAH and FFFBH

Hex Address

Program 1000
Counter 1001
1002
1003 Interrupt 1
1003
occurs
1004

2000
2001
2002

2030

FFFA 0 0 1 0 0 0 0 0 20 (Hi)
FFFB 0 0 0 0 0 0 0 0
FFFC 00 (Lo)
FFFD
FFFE
FFFF

Figure 4.7(a): Program is interrupted while working at location 1003h

# The microprocessor is executing the normal program sequence.

# On the instruction located at 1003, interrupt 1 is received.
# Interrupt caused the microprocessor to check assigned address.
# Vectored address FFFA and FFFB contains the address of interrupt routine(ex 2000h).
# Address routine, 2000h loaded into program counter address register and routine is executed .
# At the end of subroutine, processor returns to the next sequential address in the normal
routine.

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Types of interrupt

# Interrupt can be divided into TWO categories:

 Maskable – interrupt that can be selectively disabled. interrupt that not be accepted.
 Non-maskable- interrupt that never disabled. interrupt that will always be
acknowledged and accepted. example: power failure.

# Most interrupt can be temporary disable by program instruction when a program is

performing a critical task that would be negatively affected if an interrupt were to occur.
# These interrupt can then be disabled or masked, so the microprocessor does not accept
them.
# The various interrupts can be masked by assigning each interrupt possible a bit position
in an interrupt mask register.

CPU-Memory-I/O Architecture
# There are five basic components involved in the interface between the CPU and the I/O
peripheral:

1. CPU
2. I/O peripheral device
3. Memory. Except for single pieces of input and output that can be transferred
directly from a register.
4. One or more I/O modules. The I/O module(s) acts as an interface between
the CPU or memory and one or more I/O device. The primary role of the I/O
module is to receive commands from the CPU and to provide the control of
the I/O device or devices so as to execute those commands.
5. Buses – connecting various components together.

I/O MODULES

# I/O module is an entity within a computer responsible for the control of one or more
external devices and for exchange of data between those devices and main memory or
CPU.

# Functions of I/O modules:

 Control and timing, to coordinate the flow of traffic between internal resources
and external devices.
 CPU communication
It involves:
 Command decoding to interpret and differentiate between control signal
sent through control bus and it associate data/parameter send through
the data bus.
 Data are exchanged over the data bus.

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  Status reporting. I/O modules must report on BUSY or READY
condition, or /and on various error conditions.
 Address recognition for each peripheral devices

 Device communication. I/O module must be able to communicate commands,

status information, and data.
 Data buffering. For devices with much slower rate, I/O module must be able to
buffer the data and then sent them to the peripheral device at its data rate.
Also data are buffered so as not to tie up the memory in slow transfer
operation.
 Error detection including mechanical and electrical malfunctions reported by
the devices. Also report on unintentional changes to bit pattern as it is
transmitted from device to I/O modules.

3.3.1 Bus
# The physical connection to transfer data from one location to another location in
the computer system. Ex : (CPU, memory, registers, peripheral, inside CPU)
# The capacity of a bus is determined by how many bits can travel through the
circuitry at one time. The greater the capacity of a bus, the more powerful and
faster the operation. Newer bus lines can move 32-bits or 64-bits at one time
through the circuitry.
# Defined as a group of electrical conductors that carry computer signals
from one location to another. The electrical conductors may be wires, or
they may be conductors on a printed circuit- known as line. Each line
carries a single electrical signal. The signal might be:
1. bit of a memory address
2. sequence of data bits
3. Timing control that turns a device on and off at the proper time.
4. power to a module
# Bus line can be grouped into four general categories :
1. data – carry the “data” that is being moved from one location to another.
2. address – carry the data address to specify the recipient of data
3. control – provide control for the proper synchronization and operation.
4. power – provide required power for plug-in peripheral interface card.

# Buses connected modules together in two ways:

1. point-to-point bus – carry signals from a specific sources to a specific
destination. Ex: the cable that connects the parallel or serial port in a personal
computer to a printer. Point-to-point buses intended for connection to a plug-in
device are often called ports. Addressing is not required since the destination
is already known.

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 2. multipoint bus (also known as multidrop/broadcast bus) – used to connect
several points together. The signals produced by a source on the bus are
“broadcast” to every other point on the bus. Ex: the bus in an Ethernet
network : the signal being sent by a particular computers received by every
other computer connected to the network. Requires addressing signals on
the bus to identify the desired destination that is being addressed by source at
particular time.

# Backplane (also known as system bus or external bus) – the bus is used to carry
computer signals that connect the CPU with memory and/or with a set of plug-in
module cards in the same physical package. One common method of connecting a CPU
to memory and I/O modules is to mount the CPU and its related components on a
printed circuit board known as motherboard. The backplane in this case is a part of the
printed circuit wiring on the motherboard.

# Bus interface bridge – the interface between different buses. It support different buses to
communicate each other.

# Types of buses:
1. Internal buses inside CPU (generally don’t have name)
2. The external CPU buses – connect CPU and memory
3. ISA (Industry Standard Architecture) bus - developed for the IBM Personal
Computer. First was an 8-bit wide data path; then it was 16-bits wide. Slow for many
of today’s applications. Still widely used.
4. peripheral control interface (PCI) bus - The most recently developed category of
buses called local buses. Originally developed to meet video demands of graphical
user interfaces. The most widely used local bus. High-speed 32-bit or 64-bit bus.
Twenty times faster than ISA buses.
5. AGP (Accelerated Graphic Processor) bus - The newest bus. Over twice as fast as
the PCI bus. Dedicated to the acceleration of graphics performance. Widely used for
graphics and 3-D animations. Replaces the PCI bus for transfer of video data.

# Bus protocol – is an agreement between two or more entities that establishes a clear,
common path of communication and understanding between them. A bus protocol is
simply a specification that spell out the meaning of each line and each signal on each
line for this purpose. Ex: both the CPU and memory would have to agree, for example,
that a “0” on the particular line means “memory read” and a “1” on the line means
“memory write”.

3.3.2 Bus architecture and characteristics

# There are two basic I/O system architectures in common use: bus architecture and
channel architecture.

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Bus architecture
# The system bus in a bus architecture consist of number of different interconnected
buses. The various buses in a PC are interconnected by bus interface (also known as
expansion bus / bus bridge).
# Bus interface expand the flexibility of the system bus architecture by converting the bus
signals from one bus to another so that different types pf buses can be used together.
These other bus types can then be used to connect to specific devices, such as disks or
terminal.
# Buses are characterized primarily by their configuration, width, speed, and their
particular use. Buses are also generally characterized as parallel or serial.

Characteristics Parallel bus Serial bus

A bus in which there is an A bus in which data is
individual line for each bit of data, transferred sequentially,
address and control being used. one bit at a time using a
Definition
All the bits being transferred on single data line pair.
the bus can be transferred
simultaneously.
Expensive because require large Cheap because require
Cost
number of lines only a line
High throughput because all the Low throughput because
bits of a data word are transferred data is transferred
Throughput
at once sequentially, one bit at a
time
Used for internal and short Used for longer
Usage
external distances distances

# Virtually every bus internal to the computer is a parallel bus, since the high speed is
essential to computer operation, particularly between the CPU and memory, but also
between the CPU and high-speed devices such as disk and graphic display modules.

Channel architecture
# The channel architecture is based on a separate I/O processor known as a channel
subsystem. The I/O processor (channel subsystem) acts as a separate computer just for
I/O operations, thus freeing the computer CPU for other task.
# The channel subsystem executes its own set off instruction (stored in memory) known as
channel control words, independent of CPU.

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# The channel subsystem is made up of subchannels, each of which is connected through
a control unit module an individual device by one or more channel paths. The control unit
module serves the same role as a device controller
# A CPU initiate s an I/O operation by issuing a START SUBCHANNEL command to the
channel subsystem. The START SUBCHANNEL command specifies the subchannel
number, which identifies the device, and the particular channel program to be executed.
The channel subsystem attempts to identify an available channel path and initiates data
transfer. If there is no available channel path, the channel subsystem simply holds the
request until a path become available. In this way, the channel subsystem frees the CPU
from having keep track of the status of the of the I/O operation.
# Physically, the channel subsystem is connected to the CPU by a bus, and the various
control units and I/O devices are also connected by bus.

PORT (External Interface)

# Port is simply a connecter (connecting socket on the back of the system unit) at the end
of a bus into which a device can plugged.

# To control external devices that connected to the port, specific device control is built into
a controller within the device itself and into computer the computer software program
(called device driver) that control I/O from these devices.

# Some common ports are:

1. Serial - used to connect devices that need to send data over a long distance. Used to
connect mouse, keyboard, and modem devices to the system unit. Sends data one bit at
a time.

2. Parallel - used to connect external devices that need to send data over a short distance.
Used to connect printers to the system unit. Typically sends eight bits of data
simultaneously across eight parallel wires.

3 AGP (Accelerated Graphics Port) - Used to connect monitor. Support high speed
graphics and other video input.

4. USB (Universal Serial Bus) - one port can be used to connect several devices to the
system unit. Faster than serial or parallel ports. Expected to replace serial and parallel
ports.

5. HPSB (High Performance Serial Bus) also known as FireWire Ports/IEEE 1394 - used to
connect high-speed printers or video cameras. Uses a daisy-chain configuration, with up
to 63 devices connected off a single port.33 times faster than USB port. The newest type
of port.

6. Small Computer System Interface (SCSI) - Built in 1980’s SCSI-1 provides for 8 data
lines and operates at a clock speed of 5 MHz, or a data rate of 5 Mbytes/sec. It allows up
to 7 devices to be daisy-chained and hooked to the host system.

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Stack

# The stack is a special memory buffer used as a holding area for addresses and data.
However, computers do not generally provide special memory for stack use. Instead, the
programmer sets aside one or more blocks of regular memory for this purpose. (The
STACKS command, sometimes seen in PC MS-DOS CONFIG.SYS files, can also be
used to assign blocks of memory for stack use.)

# Each location on the stack is pointed to by the Stack pointer. The stack pointer holds the
address of the last data element to be added to, or pushed on the stack. The last value
added to a stack is also the first one to be removed, or popped from the stack, so we call
it a LIFO structure (“Last In First Out”).

# Ex: the stack containing one value, 0006, on the left side of the following illustration. The
stack pointer (notated by SP) points to the most recently added (Push) value. When we
push new value on the stack, SP is decremented by two to points to the last value
pushed.

(Low Memory) (Low Memory) (Low Memory)

10F5
10F5
10F5 10F6
10F6
10F6 10F7
10F7 SP
10F7 10F8
10F8
00
10F8
10F9 SP A5
10F9 10F9
10FA 00 10FA 00
10FA
10FB 06 06
10FB
SP
Before After
Before (High Memory) (High Memory)
(High Memory)

# We use Push instruction to add the value on the stack, ex:

mov ax, 00A5 ; move 00A5h to AX

push ax ; push AX on the stack 10FB

# The Push instruction does not change the content of AX; instead, it copies the
contents of AX onto the stack.

# let’s assume that the BX and CX registers contain the values 0001 and 0002. The
following instruction push them on the stack:

push bx ; push BX on the stack; 0001

push cx ; push CX on the stack;0002

# Now that 0001 and 0002 have been pushed on the stack, it appears as follow:

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# A pop operation removes a value from the stack and places it in a register or variable.
After the value is popped from the stack, the stack pointer is incremented by two to point
to the previous value on the stack: Ex:

pop ax ; pop the top of the stack into AX

(Low Memory)

10F2 (AX = 0002)

10F3
SP
10F4
10F5 00
10F6 01
10F7 00
10F8 A5
10F9 00
10FA 06

After
(High Memory)

# After the POP has taken place, AX contains the number that was at the top o the stack
(0002). The stack pointer has moved up and is now pointing at 0001.

# There are two standard uses of stacks:

1. A stack makes an excellent temporary save area for registers if we need to preserve
their value. We can then use the registers as a scratch area and restore them when
finished.
2. When a subroutine is called, the program saves a return address on the stack, the
location in the program to which the subroutine is to return.

Given the segment of the program and content of registers(address and data are given in
hexadecimal) below:

PUSH AX;
PUSH BX;
PUSH CX; (A)

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POP BX;
POP AX;
PUSH DX;
POP CX; (B)

AX = 1234, BX = 5678, CX= 9ABC, DX=DEFF and stack pointer register = 10FF

a. 1. Build a stack diagram and show the content of SP when the program execute
until (A).

2. When the program continues, build another stack until (B).

b. Show the content of the register: AX, BX, and CX after the execution of the
instruction is finished.

[12 Marks]

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