Semiconductor Process

Technology, Equipment, Materials

& Manufacturing

• Jo De Boeck
• Arco Krijgsman
 Semiconductor Process Technology, Equipment,
Materials & Manufacturing
Overall SRA Process Oct 18
Core
Nov 20
Core team
team + comm.

Apr ‘17 May ‘17 Jun ‘17 Jul ‘17 Aug ‘17 Sep ‘17 Oct ‘17 Nov ‘17 Dec ‘17 Jan ‘18

April 19 May 4 June 9 July 4 July 18 Aug 25 Sep 7 Sep 29 Oct 12 Beg Nov. Dec 5-6 Dec 18 End Jan
Core team Kick-off Core team Core team Core Core Core team Core Core team (no mtg) EFECS (no mtg (no mtg)
1st meeting & chapter & chapter team team & chapter team & chapter Workshops Except if
leaders leaders leaders leaders needed)
Dec 7th
Core team
& chapters
leaders

Second draft
Outline & teams First draft for comments Final version
definition
by community

Over 250 experts

across core team Team, V1 – Major V2 – For V3 – For V4 – Publicly V5 – Final Final
half page review by review by draft for version
+ 10 chapter teams & « Game
challenges
assoc. assoc.
available review by
identified for comments assoc.
Changers » expert councils. mgt + Preliminary mgt
description Topic & Major bodies input bodies
2
Challenges To ECSEL MASP
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Overall SRA structure

3
 Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Chapter contributors
Name Organization Country Name Organization Country Name Organization Country
Advanced Mask Technology
Markus Bender Center DE Lothar Pfitzner Friedrich-Alexander-Universität DE François Brunier SOITEC FR

Michael Heuken AIXTRON DE Anne Van den Bosch IMEC BE Claudia Caligiore STMicroelectronics IT

Ilan Englard Applied Materials NL Jo de Boeck IMEC BE Philippe Vialletelle STMicroelectronics FR

Arco Krijgsman ASML NL Stefan DeGendt IMEC BE Guy Garry Thales Research and TechnologyFR
Jérôme
Frans List ASML NL Francis Balestra IMEP FR Bourderionnet Thales Research and TechnologyFR

Gerold Alberga ASML NL Pietro Siciliano IMM-CNR IT Olaf Kievit TNO NL

Joost van Hees ASML NL Dana Cristea IMT Bucharest RO Mart Graef TU Delft NL

Thomas Fleischmann Bosch DE Christian Meyne Infineon Technologies DE Cian O'Murchu Tyndall National Institute IRL

Jochen Kinauer camLine DE Johann Massoner Infineon Technologies AT Rainer Pforr Zeiss DE

Carlo Reita CEA FR Klaus Pressel Infineon Technologies DE

Thomas Ernst CEA FR Wolfgang Dettmann Infineon Technologies DE

Livio Baldi ENI2 IT Laurent Roux Ion Beam Services FR

George
Frank de Jong FEI NL Nikolakopoulos Luleå University of Technology SE

Gerhard Domann FhG ISC DE Anton Köck Materials Center Leoben AT

Martin
Schellenberger Fraunhofer-Gesellschaft DE Soenke Habenicht Nexperia DE

Michael Scholles Fraunhofer-Gesellschaft DE Jan Driessen NXP Semiconductors NL

4
Georg Schwalb Siltronic DE
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Core team structure
Role Team members

Coordinators Jo de Boeck / Arco Krijgsman

Overall editing Livio Baldi
Topic Lead Performance System in System on Chip Semicon
scaling Package Equipment &
Manufacturing
Klaus Pressel / Rainer Pforr /
Francis Balestra
Thomas Fleischmann Ilan Englard

Overall editing: Topic leads:

• Secure overall integrity & consistency of the • Represent the contributors on this topic in the core
team
document
• Make sure the contributions from all contributors are
taken into the ECS agenda
• Make sure the roadmap timeline matches
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Workshop session September 26th 2017
1. Developing advanced, logic and
memory technology for nanoscale
integration and application-driven
performance
2. More than Moore and
Heterogeneous System-on-Chip (SoC)
Integration;
3. Advanced smart System-in-
Package (SiP) applications
4. Maintaining world leadership in
Semiconductor Equipment, Materials
and Manufacturing solutions.

IMEP ASML IMEC Tyndall National FhG ISC ASML Zeiss TNO ASML
Institute
Francis Balestra Gerold Alberga Stefan DeGendt Cian O'Murchu Gerhard Domann Frans List Rainer Pforr Olaf Kievit Arco Krijgsman

FR NL BE IRL DE NL DE NL NL

Applied Materials TU Delft Bosch Infineon Infineon CEA

Technologies Technologies
Ilan Englard Mart Graef Thomas Klaus Pressel Christian Meyne Thomas Ernst
Fleischmann
NL NL DE DE DE FR
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Setting the scene I/O BAN DW ITH
1 Mbp/s 10 Mbp/s 1 Gbp/s 100 Gbp/s 1 Tbp/s

POW ER IOT personal/home gateway

Data center/cloud
500 Watt
1 TByte
(mains level)

100 Watt 1 TByte

DATA STORAGE
IOT sensor nodes
IOT interfaces
1 Watt
(battery level) - High-performance mobile (low power) 100 GByte
- High performance CPU/GPU
- Mass Storage
100mWatt - Hi-speed communication (Optical IO)
(battery level) 10 GByte

100µW - Ultra-low-power, cost-sensitive design 100 MByte

(ambient level) - Sensor and sensor integration

10 Mop/s 10 Gop/s 100 Gop/s 1 Top/s 1 Pop/s

PERFORMAN CE
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Major Challenges
1. Developing advanced, logic
and memory technology for
nanoscale integration and
application-driven
performance;
2. More than Moore and
Heterogeneous System-on-
Chip (SoC) Integration;
3. Advanced smart System-in-
Package (SiP) applications;
4. Maintaining world leadership
in Semiconductor Equipment,
Materials and Manufacturing
solutions.
 Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Major Challenge 1
Developing advanced logic and memory technology for nanoscale integration and
application-driven performance
As already evidenced in the latest versions of IRDS (International Roadmap for Devices and Systems), device
density and switching speed are no more the single performance indicator for logic devices. Low power
(stand-by and operational) and high operating temperature are of greater importance for European critical
applications like Health, IoT and Automotive/Industrial.

2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030

CMOS technology platform generations

'Developing advanced logic
and memory technology for
nanoscale integration and

22 nm FDX implementation (Strained PFET, in-situ doped RSD(Gen1), Gate first)

Major Challenge 1:

FINFET implementation >N7 / 12nm FDx (Strained CMOS), in situ doped RSD(Gen2), dual STI)
application-driven
performance'

<N7 horizontal Gate-All-Around NW/ 10 nm FDX (Gate Last, SAC)

<N5 Vertical GAA
Beyond CMOS & new compute paradigm options down-select and implement Spin transistors, Steep sub-Vt slope (FeFET, TFET, NEMS), alternative materials: TMD's, others
Integrated (embedded NVM) memory systems incl. new storagr architectures for smart systems, IoT and new compute paradigms
STT-MRAM / ReRAM / PCM / other
Wafer based process technologies for 3D integration (cfr also Challenge 3) including (monolithic) 3D-IC
implementation pilots
 Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Major Challenge 2
More than Moore and Heterogeneous System-on-Chip (SoC) Integration
The realization of smart electronic components and systems for European critical applications requires
complementing logic and memories with additional features, which are non-scalable with Moore’s Law, to
handle the functions of sensing, actuation, communication, data protection and power management. These
heterogeneous functionalities can be integrated on the same System-on-Chip, such as for embedded memories,
and for analogue and Smart Power, or realized as discrete components for SiP integration. Advanced
technologies, processes and materials need to be developed for innovative More-than-Moore solutions. They
enable innovative emerging applications, while leveraging synergies with processing and manufacturing
technologies of More-Moore devices.
2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030

Technology platform for integrated application defined sensors, including packaging

Heterogeneous System-on-Chip

implementation pilots
'More than Moore and

Process technology platforms for new RF and mm-wave integrated device options, incl. radar (SiGe/BiCMOS, FDX, CMOS), photonics options, as well as packaging
Major Challenge 2:

(SoC) Integration'

implementation pilots
Process technology platforms for biomedical devices for minimally invasive healthcare
implementation pilots
Process technology platforms for power electronics
e.g. higher P density & freq., wide-gap, new CMOS/IGBT processes, integrated logic, uni-& bipolar, higher V-classes, lateral to vertical arch as well as packaging

Process technology exploration for functional integration of novel materials (e.g. Graphene, TMD's, FerroElectric, Magnetic, e.a. ) implemented in existing pilot line
implementation pilots
 Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Major Challenge 3
Advanced smart System-in-Package (SiP) applications
Advanced SiP technologies are required to deliver the functionality in meeting the demanding specifications
and boundary conditions of major electronic component applications. The integration of more functionality in
smaller volume requires new assembly and packaging materials, compatible chip/package interfaces, as well
as heterogeneous integration of chips with different functionalities like MEMS/sensors, power chips,
processors, or memory. Special focus must be on electrical capabilities and temperature constraints keeping
robustness and reliability for the applications.

2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030

Process technology for multi-chip embedding (molded, PCB, flexible substrate, silicon)
Multi-die embedding (molded, la implementation pilots next gen systems / new applications
'Heterogeneous System-in-
Package (SiP) integration'

… in flexible substrates implementation pilots next gen systems / new applications

Major Challenge 3:

Process technology for heterogeneous and (2.5 & 3D) SiP integration
wafer level, interposer (Si), various technologies, e.g. GaN, SiC, Logic & power embedding, intelligent power modules, optical interc.
SiP Technologies (thin wafer/die handling, dicing, stacking) next gen systems / new applications
Si interposer (TSV), passive, RF-SiP (glass) and sensor integration next gen systems / new applications
Continuous improvement of (i) Materials aspects, (ii) Thermal management
(iii) high temperature package (iv) Characterization & modleing, (v) Reliability & failure analysis & test
continuous improvements continuous improvements
iv) Characterization & modleing, (v) Reliability & failure analysis & test, but needs parallel ongoing basic reseach
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Major Challenge 4
Maintaining world leadership in Semiconductor Equipment, Materials and
Manufacturing solutions

Supply the European ECS manufacturing companies with ‘best-in-class’ equipment and materials, and
flexible, agile and competitive semiconductor manufacturing solutions in the domains More Moore (MM),
More than Moore (MtM) and System in Package, and by this the European application sector to compete
on the world markets with top quality products.
 Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Major Challenge 4
Maintaining world leadership in Semiconductor Equipment, Materials and
Manufacturing solutions
2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030

More Moore: Equipment & Materials for sub-10nm semiconductor devices & systems manufacturing
Equipment & materials for 7nm node °
Equipment & materials for 5nm node °
Equipment & materials for 3nm node °
Equipment & materials for sub 3nm node °
Metrology & inspection equipment for 7nm node
Semiconductor Equipment, Materials
'Maintaining world leadership with

Metrology & inspection for 5nm node

and Manufacturing solutions.'

Metrology & inspection equipment for 3nm node

Metrology & inspection equipment for sub 3nm node
Major Challenge 4:

Equipment , Materials, Metrology & inspection for Beyond CMOS & new compute paradigm options
More than Moore and Heterogeneous SoC & SiP integration equipment and materials
Equipment enabling Heterogeneous Integration
Innovative materials enabling Heterogeneous Integration (on chip & package level)
Specific equipments and materials enabling innovative MTM devices and heterogeneous integration
Defend and extend Europe’s world leadership positions in Semiconductor Equipment, Materials and Manufacturing
E&M for further miniaturization and higher functional density for MTM
solutions. Upgrade MTM technologies to 300mm wafers and heterogeneous SiP integration
Supply the European
Manufacturing ECS manufacturing companies with ‘best-in-class’ equipment and materials, and flexible, agile and
technologies
competitive semiconductor
Upgrade automation,manufacturing
APC and integration solutions
of new sensorsin the
and domains
hybrid solutions More Moore (MM), More than Moore (MtM) and

System in Package, and by this the European application sector to compete on the world markets with top quality
Control of variability in manufacturing
products. Advanced diagnostic and decision support systems (supervision, scheduling, agility)
Knowledge management (inter fab flows, fast diagnosis)
FICS migration toward distributed architecture BYOD / Apps
R&I funding instrument landscape

NATIONAL CROSS BORDER COOPERATION

NATIONAL EUREKA ECSEL-JU H2020

Develop & Maintain Trans-National
Critical Mass Programmes
National contract National Priorities
National contract
ECS Programmes Innovation & Infrastructure
National & European European Priorities
Priorities EC contract
EC contract & National
contract

NATIONAL FUNDING
EUROPEAN FUNDING
 ECS-related R&I funding
programme information
Available in the Exhibition Hall ECSEL 2018 RIA and IA calls:
• Calls open: 21/02/2018
• Project Outline deadline:
26/04/2018
• Full Project Proposal deadline:
20/09/2018

Based on ECS SRA

Open, closing date PO deadline

Open, deadline for PO
February 15th 2018 March 12th 2018
February 13th, 2017

Call opens Dec 11th 2017 PO deadline

Call closure March 12th 2018
PO deadline March 9th 2018
April 23rd, 2018
Call open, cut-off
date March 1st, 2018
15
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
The floor is yours!
• Questions?
• Feedback?
• Inputs?

16
Semiconductor Process
Technology, Equipment,
Materials & Manufacturing

Pitches
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Pitched ideas
Idea Name Presenter Organization Poster/Pitch

Next GaN Michael Salter Acreo Swedish ICT AB Pitch

LUniHar Christian Hedayat Fraunhofer ENAS-PB Pitch

Nano-R, MSP-X & MSP-R Anton Koeck Materials Center Leoben Pitch
Forschung GmbH (MCL)
INTELLIGENT Martin Landgraf Fraunhofer IPMS Pitch

LAMP Anneliese Poenninger EV Group Poster

PLIANTLY Jacques Perocheau LCP'S Engineering Poster

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NextGaN
Next generation, high power, high
efficiency III-N components through
innovations in material and process
technologies

Michael Salter – michael.salter@ri.se

NextGaN
Challenges and objectives
• Develop novel scalable and adaptive III-N
material technology for improvements in high-
power electronic components
• Novel approaches to reducing defect density
of III-N wafers to allow for vertical power
transistors in the 600V – 1200 V category
• Addressing SRA Energy Challenge 1:
Ensuring sustainable power generation and
energy conversion
• Enable increased efficiency, cost-effective
energy conversion, transport and utilization of
electric power
Technical goals
• Develop low-dislocation density Ga(Al)N
wafer technology
• Nanowire-based low-dislocation density GaN and
Al(Ga)N wafters
• GaN and Al(Ga)N epitaxy with hot-wall MOCVD on
SiC, GaN and Al(Ga)N wafers
• Develop defect reduction and efficient doping
in hetero- and homo-epitaxy
• Design, fabricate and demonstrate vertical III-
N power devices
• Design, fabricate and assess vertical III-N JBS
diodes and switches
NextGaN
Current Partners Desired Partners
• ON Semiconductor, ABB (LE) • Power electronic device manufacturing
• SweGaN, Hexagem (SME) companies
• Linköping, Lund, Chalmers (University) • Power electronic subsystem companies
• RISE (RTO) • Power equipment and Energy OEMs
• Passive component manufactures
• University and RTOs
• Other national power consortiums/projects

Contact
• michael.salter@ri.se, +46 703 55 5838
Nano-R
Fabrication and Reliability of Nanodevices based on 0D, 1D,
& 2D Nanomaterials

Anton Köck – anton.koeck@mcl.at

Nano-R
Challenges and objectives
• Novel nanomaterials enable entirely new
applications (Graphene, MoS2, nanowires,
quantum dots…)
• How to fabricate and integrate such
nanomaterials on CMOS based devices ?
• How to fabricate new “Si-less” nanodevices ?
• How to analyse the nanodevices ?
Technical goals
• Fabrication and integration technologies
• Lot of reliability issues !!!
• E.g. electrical contacts
• Novel analysis tools and technologies from
macro to nano along production chain
Nano-R
Partners Economical impact (optional)
• Materials Center Leoben (MCL) • Entirely new sensor devices
• University of Oxford • Entirely new light emitting devices
• KTH Stockholm • Energy storage & energy harvesting
• ETH Zürich • Ultra low power devices for IoT and
• EVGroup wearables

• Etc.

• Which call….?

Contact Expected Duration / budget (optional)

• Anton Köck, +43(0)3842-45922-505 • 48 months, XXXX k€
MSP-R
Multi Sensor Platform – Reliability of 3D-integrated Multi
Sensor Systems

Anton Köck – anton.koeck@mcl.at

MSP-R
Challenges and objectives
• The project is based on the MSP-project
• 3D-integration of 57 nano-based sensor
devices !
• Focus on specific combinations of sensor
devices
Technical goals
• 3D-integration technologies
• 3D-integration in more (than 2) layers !
• Overmolding of 3D-integrated system
• Reliability issues !!! Analysis tools and technologies
from macro to nano along production chain !
Project idea name
Partners Economical impact (optional)
• Materials Center Leoben • Reliable multi-sensor system capable for IoT-
• Holst Center imec Netherlands applications
• Ams AG • Multi-sensor systems for wearables, smart
• Infineon phones, wristband devices
• Besi • Consumer Electronics
• Boschman • Smart Home, Smart Building, Smart Cities,…
• Etc.

• ECSEL-project

Contact Expected Duration / budget (optional)

• Anton Köck, +43(0)3842-45922-505 • 36 months, 10000 k€
MSP-Xtreme
Multi Sensor Platform - Extreme Miniaturisation & Integration
for IoT Applications

Anton Köck – anton.koeck@mcl.at

MSP-Xtreme
Challenges and objectives
• The project is based on the MSP-project
• 57 integrated sensor devices !
• 3D-integration of nanotechnology based
sensors for environmental monitoring
• Development of energy autonomous system
Technical goals
• Ultra-low power sensing devices
• Energy harvesting (Perovskite or Quantum
Dots) & Energy storage (Super-Cap)
• Wireless transmission
• Reliability issues !!! Advanced analysis tools
and technologies from macro to nano along
production chain !
Project idea name
Partners Economical impact (optional)
• Materials Center Leoben (MCL) • Energy autonomous multi-sensor system
• Holst Center imec Netherlands capable for IoT-applications

• University Barcelona • Consumer electronics, wearables

• University of Oxford • Smart Home, Smart Building, Smart Cities

• TNO (Solliance Solar Research)

• Etc.

• ICT-Call ICT-07-2018 Electronic Smart System

Contact Expected Duration / budget (optional)

• Anton Köck, +43(0)3842-45922-505 • 36 months, 6000 k€
INTELLIGENT
New BEOL based Non-Volatile Memory
for low-power applications

Martin Landgraf – Fraunhofer IPMS, Dresden, Germany

- Funding Project Management -
 INTELLIGENT
Introduction of new functional layers into general
electronics for non-volatile memory technologies
M9
New BEOL based Non-Volatile Memory
M8
Introduction of HfO based ferroelectric layers into
the BEoL on FeFET basis (1T-1C integration)
M7

Advantages:
Standard CMOS • Low power (< 4V program/erase)
M6 • Small size (bitcell footprint)
• Low cost (few additional litho layers only)
M5

M4
• independent integration from FEoL
(use standard CMOS baseline)
M3

M2 Application fields:
M1
• low power embedded memory solutions (e.g. IoT,
Standard CMOS baseline metering, data logging, self-powered systems)
NMOS PMOS
from Waferfab
INTELLIGENT
Introduction of new functional layers into general
electronics for non-volatile memory technologies

Standard FeFET Search for following partners:

Project Goal
• System integrators and end user with need
for embedded NVM in low-power application

• Partner for array design & simulations

FE material Expected Duration / Budget

FE material separated in
in Front-End Back-End
36 months / tbd

Contact
martin.landgraf@ipms.fraunhofer.de (funding project management)
konrad.seidel@ipms.fraunhofer.de (group manager NVM)
PLIANTLY
Pilot Line for Advanced GaN
Power Technology
Challenges and objectives
Emerging applications and market will require
an important volume of power semiconductor
technologies (5G / MIMO, SATCOM). We also
expect important needs for mixing GaN/SiC with
Si RF & Digital technologies for very integrated
3D modules associated to 5G / Telecom and
Secure applications. Other specific needs will
appear in Automotive (AVAS), Medical ... , all
requiring new industrial capabilities to
manufacture with a high level quality and yield
advanced GaN Technologies. Considering these
trends, the object of this project is focused on
the development of a GaN / SiC industrial pilot
line fully connected to the heterogeneous
integration with Silicon technologies.
LAMP
Large Surface Nano Imprint
Lithography
Semiconductor Process
Technology, Equipment,
Materials &
Manufacturing
Semiconductor Process Technology,
Equipment, Materials & Manufacturing
Contact Information

 Jo DeBoeck  Arco Krijgsman

 Imec  ASML
 Jo.DeBoeck@imec.be  Arco.Krijgsman@asml.com

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