High Performance, ISM Band,

FSK/ASK Transceiver IC
Data Sheet ADF7020
FEATURES −3 dBm IIP3 in high linearity mode
Low power, low IF transceiver On-chip VCO and fractional-N PLL
Frequency bands On-chip 7-bit ADC and temperature sensor
431 MHz to 478 MHz Fully automatic frequency control loop (AFC) compensates
862 MHz to 956 MHz for ±25 ppm crystal at 862 MHz to 956 MHz or±50 ppm at
Data rates supported 431 MHz to 478 MHz
0.15 kbps to 200 kbps, FSK Digital RSSI
0.15 kbps to 64 kbps, ASK Integrated Tx/Rx switch
2.3 V to 3.6 V power supply Leakage current of <1 μA in power-down mode
Programmable output power APPLICATIONS
−16 dBm to +13 dBm in 0.3 dBm steps
Low cost wireless data transfer
Receiver sensitivity
Remote control/security systems
−119 dBm at 1 kbps, FSK
Wireless metering
−112 dBm at 9.6 kbps, FSK
Keyless entry
−106.5 dBm at 9.6 kbps, ASK
Home automation
Low power consumption
Process and building control
19 mA in receive mode
Wireless voice
26.8 mA in transmit mode (10 dBm output)

FUNCTIONAL BLOCK DIAGRAM

RSET CREG[1:4] ADCIN MUXOUT

ADF7020
RLNA LDO(1:4) TEMP TEST MUX
OFFSET SENSOR
CORRECTION

LNA
RFIN FSK/ASK DATA
IF FILTER RSSI MUX 7-BIT ADC DEMODULATOR SYNCHRONIZER
RFINB

GAIN

OFFSET
CORRECTION CE
AGC
CONTROL DATA CLK
Tx/Rx
CONTROL DATA I/O
FSK MOD GAUSSIAN Σ-∆
CONTROL FILTER MODULATOR AFC
CONTROL INT/LOCK

DIVIDERS/ DIV P N/N + 1

RFOUT MUXING
SLE

SERIAL SDATA
PORT SREAD
VCO
CP SCLK
PFD
DIV R OSC CLK
DIV
05351-001

VCOIN CPOUT OSC1 OSC2 CLKOUT

Figure 1.

Rev. E Document Feedback

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ADF7020
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
Timing Characteristics ..................................................................... 8
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Frequency Synthesizer ................................................................... 15
Reference Input ........................................................................... 15
Choosing Channels for Best System Performance ................. 17
Transmitter ...................................................................................... 18
RF Output Stage .......................................................................... 18
Modulation Schemes.................................................................. 18
Receiver ............................................................................................ 20
RF Front End ............................................................................... 20
RSSI/AGC .................................................................................... 21
FSK Demodulators on the ADF7020 ....................................... 21
FSK Correlator/Demodulator ................................................... 21
Linear FSK Demodulator .......................................................... 23
AFC .............................................................................................. 23
Automatic Sync Word Recognition ......................................... 24
Applications Information .............................................................. 25
LNA/PA Matching ...................................................................... 25
Image Rejection Calibration ..................................................... 26
Rev. E | Page 2 of 47
Data Sheet
Transmit Protocol and Coding Considerations ..................... 27
Device Programming after Initial Power-Up ............................. 27
Interfacing to Microcontroller/DSP ........................................ 27
Power Consumption and battery lifetime calculations ......... 28
Serial Interface ................................................................................ 31
Readback Format........................................................................ 31
Registers ........................................................................................... 32
Register 0—N Register............................................................... 32
Register 1—Oscillator/Filter Register ...................................... 33
Register 2—Transmit Modulation Register (ASK/OOK
Mode) ........................................................................................... 34
Register 2—Transmit Modulation Register (FSK Mode) ..... 35
Register 2—Transmit Modulation Register (GFSK/GOOK
Mode) ........................................................................................... 36
Register 3—Receiver Clock Register ....................................... 37
Register 4—Demodulator Setup Register ............................... 38
Register 5—Sync Byte Register ................................................. 39
Register 6—Correlator/Demodulator Register ...................... 40
Register 7—Readback Setup Register ...................................... 41
Register 8—Power-Down Test Register .................................. 42
Register 9—AGC Register ......................................................... 43
Register 10—AGC 2 Register.................................................... 44
Register 11—AFC Register ....................................................... 44
Register 12—Test Register......................................................... 45
Register 13—Offset Removal and Signal Gain Register ....... 46
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
Data Sheet
REVISION HISTORY
9/2016—Rev. D to Rev. E
Changes to General Description Section ....................................... 4
Changes to Interfacing to Microcontroller/DSP Section and
Figure 37 ...........................................................................................27
8/2012—Rev. C to Rev. D
Added EPAD Notation ...................................................................11
Changed CP-48-3 Package to CP-48-5 Package ..........................47
Updated Outline Dimensions ........................................................47
Changes to Ordering Guide ...........................................................47
5/2011—Rev. B to Rev. C
Added Exposed Pad Notation to Outline Dimensions ..............47
Changes to Ordering Guide ...........................................................47
8/2007—Rev. A to Rev. B
Changes to Features .......................................................................... 1
Changes to General Description ..................................................... 4
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 8
Changes to Reference Input Section .............................................15
Changes to N Counter Section ......................................................16
Changes to Choosing Channels for Best Performance Section 17
Changes to Table 5 ..........................................................................20
Changes to FSK Correlator Register Settings Section ................22
Added Image Rejection Calibration Section ...............................26
Added Figure 41 ..............................................................................30
Changes to Readback Format Section ..........................................31
Changes to Register 9—AGC Register Comments Section .......43
Added Register 12—Test Register Comments Section ..............45
Rev. E | Page 3 of 47
ADF7020
4/2006—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Table 1 ............................................................................ 5
Changes to Figure 24 ...................................................................... 17
Changes to the Setting Up the ADF7020 for GFSK Section ..... 19
Changes to Table 6 .......................................................................... 21
Changes to Table 9 .......................................................................... 23
Changes to External AFC Section................................................. 23
Deleted Maximum AFC Range Section ....................................... 23
Added AFC Performance Section ................................................. 24
Changes to Internal Rx/Tx Switch Section .................................. 25
Changes to Figure 32 ...................................................................... 25
Changes to Transmit Protocol and Coding Considerations
Section .............................................................................................. 26
Added Text Relating to Figure 37 ................................................. 27
Changes to Figure 41 ...................................................................... 31
Changes to Register 1—Oscillator/Filter Register
Comments ........................................................................................ 31
Changes to Figure 42 ...................................................................... 32
Changes to Register 2—Transmit Modulation Register
(FSK Mode) Comments ................................................................. 33
Changes to Figure 44 ...................................................................... 34
Changes to Register 2—Transmit Modulation Register
(GFSK/GOOK Mode) Comments ................................................ 34
Changes to Register 4—Demodulator Setup Register
Comments ........................................................................................ 36
Changes to Figure 51 ...................................................................... 41
Changes to Figure 53 ...................................................................... 42
Changes to Ordering Guide ........................................................... 45
6/2005—Revision 0: Initial Version
ADF7020
GENERAL DESCRIPTION
The ADF7020 is a low power, highly integrated FSK/ASK/OOK
transceiver designed for operation in the license-free ISM bands
at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed
Japanese RFID band at 950 MHz. A Gaussian data filter option
is available to allow either GFSK or G-ASK modulation, which
provides a more spectrally efficient modulation. In addition to
these modulation options, the ADF7020 can also be used to
perform both MSK and GMSK modulation, where MSK is a
special case of FSK with a modulation index of 0.5. The modula-
tion index is calculated as twice the deviation divided by the
data rate. MSK is spectrally equivalent to O-QPSK modulation
with half-sinusoidal Tx baseband shaping, so the ADF7020 can
also support this modulation option by setting up the device in
MSK mode.
This device is suitable for circuit applications that meet the
European ETSI-300-220, the North American FCC (Part 15),
or the Chinese Short Range Device regulatory standards. A
complete transceiver can be built using a small number of
external discrete components, making the ADF7020 very
suitable for price-sensitive and area-sensitive applications.
The transmitter block on the ADF7020 contains a VCO and
low noise fractional-N PLL with an output resolution of
<1 ppm. This frequency agile PLL allows the ADF7020 to be
used in frequency-hopping spread spectrum (FHSS) systems.
The VCO operates at twice the fundamental frequency to
reduce spurious emissions and frequency-pulling problems.
Rev. E | Page 4 of 47
Data Sheet
The transmitter output power is programmable in 0.3 dB steps
from −16 dBm to +13 dBm. The transceiver RF frequency and
modulation are programmable using a simple 3-wire interface.
The device operates with a power supply range of 2.3 V to 3.6 V
and can be powered down when not in use.
A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable
features, including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application.
The receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.
An on-chip ADC provides readback of an integrated temperature
sensor, an external analog input, the battery voltage, or the RSSI
signal, which provides savings on an ADC in some applications.
The temperature sensor is accurate to ±10°C over the full operating
temperature range of −40°C to +85°C. This accuracy can be
improved by doing a 1-point calibration at room temperature
and storing the result in memory.
Data Sheet ADF7020

SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All
measurements are performed using the EVAL-ADF7020DBZ1 through EVAL-ADF7020DBZ3 using the PN9 data sequence, unless
otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions
RF CHARACTERISTICS
Frequency Ranges (Direct Output) 862 870 MHz VCO adjust = 0, VCO bias = 10
902 928 MHz VCO adjust = 3, VCO bias = 10
928 956 MHz VCO adjust = 3, VCO bias = 12, VDD = 2.7 V to 3.6 V
Frequency Ranges (Divide-by-2 Mode) 431 440 MHz VCO adjust = 0, VCO bias = 10
440 478 MHz VCO adjust = 3, VCO bias = 12
Phase Frequency Detector Frequency RF/256 24 MHz
TRANSMISSION PARAMETERS
Data Rate
FSK/GFSK 0.15 200 kbps
OOK/ASK 0.15 64 1 kbps
OOK/ASK 0.3 100 kbaud Using Manchester encoding
Frequency Shift Keying
GFSK/FSK Frequency Deviation 2, 3 1 110 kHz PFD = 3.625 MHz
4.88 620 kHz PFD = 20 MHz
Deviation Frequency Resolution 100 Hz PFD = 3.625 MHz
Gaussian Filter BT 0.5
Amplitude Shift Keying
ASK Modulation Depth 30 dB
PA Off Feedthrough in OOK Mode −50 dBm
Transmit Power 4 −20 +13 dBm VDD = 3.0 V, TA = 25°C
Transmit Power Variation vs. ±1 dB From −40°C to +85°C
Temperature
Transmit Power Variation vs. VDD ±1 dB From 2.3 V to 3.6 V at 915 MHz, TA = 25°C
Transmit Power Flatness ±1 dB From 902 MHz to 928 MHz, 3 V, TA = 25°C
Programmable Step Size
−20 dBm to +13 dBm 0.3125 dB
Integer Boundary −55 dBc 50 kHz loop BW
Reference −65 dBc
Harmonics
Second Harmonic −27 dBc Unfiltered conductive
Third Harmonic −21 dBc
All Other Harmonics −35 dBc
VCO Frequency Pulling, OOK Mode 30 kHz rms DR = 9.6 kbps
Optimum PA Load Impedance 5 39 + j61 Ω FRF = 915 MHz
48 + j54 Ω FRF = 868 MHz
54 + j94 Ω FRF = 433 MHz
RECEIVER PARAMETERS
FSK/GFSK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz,
LNA and PA matched separately 6
Sensitivity at 1 kbps −119.2 dBm FDEV = 5 kHz, high sensitivity mode 7
Sensitivity at 9.6 kbps −112.8 dBm FDEV = 10 kHz, high sensitivity mode
Sensitivity at 200 kbps −100 dBm FDEV = 50 kHz, high sensitivity mode
OOK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz
Sensitivity at 1 kbps −116 dBm High sensitivity mode
Sensitivity at 9.6 kbps −106.5 dBm High sensitivity mode

Rev. E | Page 5 of 47
ADF7020 Data Sheet
Parameter Min Typ Max Unit Test Conditions
LNA and Mixer, Input IP37
Enhanced Linearity Mode −3 dBm Pin = −20 dBm, 2 CW interferers
Low Current Mode −5 dBm FRF = 915 MHz, F1 = FRF + 3 MHz
High Sensitivity Mode −24 dBm F2 = FRF + 6 MHz, maximum gain
Rx Spurious Emissions8 −57 dBm <1 GHz at antenna input
−47 dBm >1 GHz at antenna input
AFC
Pull-In Range at 868 MHz/915 MHz ±50 kHz IF_BW = 200 kHz
Pull-In Range at 433 MHz ±25 kHz IF_BW = 200 kHz
Response Time 48 Bits Modulation index = 0.875
Accuracy 1 kHz
CHANNEL FILTERING Desired signal 3 dB above the input sensitivity level,
CW interferer power level increased until BER = 10−3,
image channel excluded
Adjacent Channel Rejection 27 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
(Offset = ±1 × IF Filter BW Setting)
Second Adjacent Channel Rejection 50 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
(Offset = ±2 × IF Filter BW Setting)
Third Adjacent Channel Rejection 55 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
(Offset = ±3 × IF Filter BW Setting)
Image Channel Rejection 30 dB Image at FRF = 400 kHz
(Uncalibrated)
Image Channel Rejection (Calibrated) 50 dB Image at FRF = 400 kHz
CO-CHANNEL REJECTION −2 dB
Wideband Interference Rejection 70 dB Swept from 100 MHz to 2 GHz, measured as channel
rejection
BLOCKING Desired signal 3 dB above the input sensitivity level,
CW interferer power level increased until BER = 10−2
±1 MHz 60 dB
±5 MHz 68 dB
±10 MHz 65 dB
±10 MHz (High Linearity Mode) 72 dB
Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10−3
LNA Input Impedance 24 − j60 Ω FRF = 915 MHz, RFIN to GND
26 − j63 Ω FRF = 868 MHz
71 − j128 Ω FRF = 433 MHz
RSSI
Range at Input −110 to dBm
−24
Linearity ±2 dB
Absolute Accuracy ±3 dB
Response Time 150 μs See the RSSI/AGC section
PHASE-LOCKED LOOP
VCO Gain 65 MHz/V 902 MHz to 928 MHz band,
VCO adjust = 0, VCO_BIAS_SETTING = 10
130 MHz/V 860 MHz to 870 MHz band, VCO adjust = 0
65 MHz/V 433 MHz, VCO adjust = 0
Phase Noise (In-Band) −89 dBc/Hz PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,
FRF = 915 MHz, VCO_BIAS_SETTING = 10
Phase Noise (Out-of-Band) −110 dBc/Hz 1 MHz offset
Residual FM 128 Hz From 200 Hz to 20 kHz, FRF = 868 MHz
PLL Settling 40 μs Measured for a 10 MHz frequency step to within
5 ppm accuracy, PFD = 20 MHz, LBW = 50 kHz

Rev. E | Page 6 of 47
Data Sheet ADF7020
Parameter Min Typ Max Unit Test Conditions
REFERENCE INPUT
Crystal Reference 3.625 24 MHz
External Oscillator 3.625 24 MHz
Load Capacitance 33 pF See crystal manufacturer’s specification sheet
Crystal Start-Up Time 2.1 ms 11.0592 MHz crystal, using 33 pF load capacitors
1.0 ms Using 16 pF load capacitors
Input Level CMOS levels See the Reference Input section
ADC PARAMETERS
INL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C
DNL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C
TIMING INFORMATION
Chip Enabled to Regulator Ready 10 µs CREG = 100 nF
Chip Enabled to RSSI Ready 3.0 ms See Table 11 for more details
Tx to Rx Turnaround Time 150 µs + Time to synchronized data out, includes AGC settling;
(5 × TBIT) see the AGC Information and Timing section
LOGIC INPUTS
Input High Voltage, VINH 0.7 × V
VDD
Input Low Voltage, VINL 0.2 × V
VDD
Input Current, IINH/IINL ±1 µA
Input Capacitance, CIN 10 pF
Control Clock Input 50 MHz
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − V IOH = 500 µA
0.4
Output Low Voltage, VOL 0.4 V IOL = 500 µA
CLKOUT Rise/Fall 5 ns
CLKOUT Load 10 pF
TEMPERATURE RANGE, TA −40 +85 °C
POWER SUPPLIES
Voltage Supply
VDD 2.3 3.6 V All VDD pins must be tied together
Transmit Current Consumption FRF = 915 MHz, VDD = 3.0 V,
PA is matched to 50 Ω
−20 dBm 14.8 mA Combined PA and LNA matching network as on
−10 dBm 15.9 mA EVAL-ADF7020DBZ1 through EVAL-ADF7020DBZ3
boards, VCO_BIAS_SETTING = 12
0 dBm 19.1 mA
10 dBm 28.5 mA
10 dBm 26.8 mA PA matched separately with external antenna
switch, VCO_BIAS_SETTING = 12
Receive Current Consumption
Low Current Mode 19 mA
High Sensitivity Mode 21 mA
Power-Down Mode
Low Power Sleep Mode 0.1 1 µA
1
Higher data rates are achievable, depending on local regulations.
2
For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.
3
For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.
4
Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5
For matching details, see the LNA/PA Matching section and the AN-764 Application Note.
6
Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
7
See Table 5 for a description of different receiver modes.
8
Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

Rev. E | Page 7 of 47
ADF7020 Data Sheet

TIMING CHARACTERISTICS
VDD = 3 V ± 10%, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, not production tested.

Table 2.
Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments
t1 >10 ns SDATA to SCLK setup time
t2 >10 ns SDATA to SCLK hold time
t3 >25 ns SCLK high duration
t4 >25 ns SCLK low duration
t5 >10 ns SCLK to SLE setup time
t6 >20 ns SLE pulse width
t8 <25 ns SCLK to SREAD data valid, readback
t9 <25 ns SREAD hold time after SCLK, readback
t10 >10 ns SCLK to SLE disable time, readback

TIMING DIAGRAMS
t3 t4

SCLK

t1 t2

DB1 DB0 (LSB)

SDATA DB31 (MSB) DB30 DB2 (CONTROL BIT C2) (CONTROL BIT C1)

t6

SLE

05351-002
t5

Figure 2. Serial Interface Timing Diagram

t1 t2

SCLK

SDATA R7_DB0

(CONTROL BIT C1)

SLE

t3
t10

SREAD X RV16 RV15 RV2 RV1

05351-003

t9
t8
Figure 3. Readback Timing Diagram

Rev. E | Page 8 of 47
Data Sheet ADF7020
±1 × DATA RATE/32 1/DATA RATE

RxCLK

RxDATA DATA

05351-004
Figure 4. RxData/RxCLK Timing Diagram

1/DATA RATE

TxCLK

TxDATA DATA

FETCH SAMPLE

05351-005
NOTES
1. TxCLK ONLY AVAILABLE IN GFSK MODE.

Figure 5. TxData/TxCLK Timing Diagram

Rev. E | Page 9 of 47
ADF7020
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND1
Analog I/O Voltage to GND
Digital I/O Voltage to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
MLF θJA Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
1
GND = GND1 = RFGND = GND4 = VCO GND = 0 V.
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
Rating
or any other conditions above those indicated in the operational
−0.3 V to +5 V
section of this specification is not implied. Operation beyond
−0.3 V to AVDD + 0.3 V
the maximum operating conditions for extended periods may
−0.3 V to DVDD + 0.3 V
affect product reliability.
−40°C to +85°C This device is a high performance RF integrated circuit with an
−65°C to +125°C ESD rating of <2 kV, and is ESD sensitive. Proper precautions
150°C should be taken for handling and assembly.
26°C/W
260°C
ESD CAUTION
40 sec
Rev. E | Page 10 of 47
Data Sheet ADF7020

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCO GND

MUXOUT
CPOUT
CREG3
CVCO
GND1

OSC1
OSC2
VDD3
GND

GND
VDD
48
47
46
45
44
43
42
41
40
39
38
37
VCOIN 1 36 CLKOUT
CREG1 2 35 DATA CLK
VDD1 3 34 DATA I/O
RFOUT 4 33 INT/LOCK
RFGND 5 32 VDD2
RFIN 6
ADF7020 31 CREG2
RFINB 7 TOP VIEW 30 ADCIN
(Not to Scale)
RLNA 8 29 GND2
VDD4 9 28 SCLK
RSET 10 27 SREAD
CREG4 11 26 SDATA
GND4 12 25 SLE

13
14
15
16
17
18
19
20
21
22
23
24
FILT_I
FILT_I

FILT_Q
FILT_Q

TEST_A
MIX_Q
MIX_Q
MIX_I
MIX_I

GND4

GND4

CE

05351-006
NOTES
1. EXPOSED PAD MUST BE CONNECTED TO GROUND.

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
2 CREG1 Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
3 VDD1 Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as
possible to this pin. All VDD pins should be tied together.
4 RFOUT The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The
output should be impedance matched to the desired load using suitable components. See the Transmitter
section.
5 RFGND Ground for Output Stage of Transmitter. All GND pins should be tied together.
6 RFIN LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
7 RFINB Complementary LNA Input. See the LNA/PA Matching section.
8 RLNA External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
9 VDD4 Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5%
tolerance.
11 CREG4 Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND
for regulator stability and noise rejection.
12 GND4 Ground for LNA/MIXER Block.
13 to 18 MIX_I, MIX_I, Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
MIX_Q, MIX_Q, unconnected.
FILT_I, FILT_I
19, 22 GND4 Ground for LNA/MIXER Block.
20, 21, 23 FILT_Q, FILT_Q, Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
TEST_A unconnected.
24 CE Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when
CE is low, and the part must be reprogrammed once CE is brought high.
25 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the fourteen latches. A latch is selected using the control bits.
26 SDATA Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high
impedance CMOS input.

Rev. E | Page 11 of 47
ADF7020 Data Sheet
Pin No. Mnemonic Description
27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The
SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
28 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
29 GND2 Ground for Digital Section.
30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V
to 1.9 V. Readback is made using the SREAD pin.
31 CREG2 Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between
this pin and ground for regulator stability and noise rejection.
32 VDD2 Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to
this pin.
33 INT/LOCK Bidirectional Pin. In output mode (interrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has
found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to
lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked,
NRZ data can be reliably received. In this mode, a demodulation lock can be asserted with minimum delay.
34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply.
35 DATA CLK In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the
center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data
from the microcontroller into the transmit section at the exact required data rate. See the Gaussian
Frequency Shift Keying (GFSK) section.
36 CLKOUT A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used
to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
37 MUXOUT This pin provides the LOCK_DETECT signal, which is used to determine if the PLL is locked to the correct
frequency. Other signals include REGULATOR_READY, which is an indicator of the status of the serial
interface regulator.
38 OSC2 The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.
39 OSC1 The reference crystal should be connected between this pin and OSC2.
40 VDD3 Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a
0.01 μF capacitor.
41 CREG3 Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be
placed between this pin and ground for regulator stability and noise rejection.
42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 μF capacitor.
44 to 47 GND, GND1, Grounds for VCO Block.
VCO GND
48 CVCO A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.
EP Exposed Pad. The exposed pad must be connected to ground.

Rev. E | Page 12 of 47
Data Sheet ADF7020

TYPICAL PERFORMANCE CHARACTERISTICS

CARRIER POWER –0.28dBm ATTEN 0.00dB MKR1 10.0000kHz MKR4 3.482GHz
REF –70.00dBc/Hz –87.80dBc/Hz REF 10dBm ATTEN 20dB SWEEP 16.52ms (601pts)
10.00 PEAK 1
dB/DIV log
1 10dB/DIV

REF LEVEL
10.00dBm

05351-007

05351-010
1kHz FREQUENCY OFFSET 10MHz START 100MHz STOP 10.000GHz
RES BW 3MHz VBW 3MHz SWEEP 16.52ms (601pts)

Figure 7. Phase Noise Response at 868.3 MHz, VDD = 3.0 V, ICP = 1.5 mA Figure 10. Harmonic Response, RFOUT Matched to 50 Ω, No Filter

10 ∆ Mkr1 1.834GHz
PRBS PN9 REF 15dBm ATTEN 30dB –62.57dB
DR = 7.1kbps
NORM 1R
FDEV = 4.88kHz
20 log
RBW = 300kHz
10dB/DIV
SIGNAL LEVEL (dBm)

30

MARKER ∆
FSK 1.834000000GHz
40 –62.57dB

LgAv
50
W1 S2 1
S3 FC
60 AA
GFSK £(f):
FTun
Swp
70
05351-008

913.28 913.30 913.32 913.36 913.38

FREQUENCY (MHz)

05351-011
START 800MHz STOP 5.000GHz
#RES BW 30kHz VBW 30kHz SWEEP 5.627s (601pts)

Figure 8. Output Spectrum in FSK and GFSK Modulation Figure 11. Harmonic Response, Murata Dielectric Filter

0 10
–5 200kHz FILTER BW
–10
0
–15
ATTENUATION LEVEL (dB)

–20
SIGNAL LEVEL (dBm)

–10
–25
–30
ASK
–35 –20
OOK
–40
–45 150kHz FILTER BW
–30
–50
100kHz FILTER BW
–55
–40
–60
–65
GOOK
–70 –50
05351-012

–400 –300 –200 –100 0 100 200 300 400 500 600 899.60 899.80 900.00 900.20 900.40 900.60 900.80
05351-009

–350 –250 –150 –50 50 150 250 350 450 550 FREQUENCY (MHz)
IF FREQ (kHz)

Figure 9. IF Filter Response Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps

Rev. E | Page 13 of 47
ADF7020 Data Sheet
20 0
DATA RATE = 1kbps FSK
9µA 3.0V, +25°C IF BW = 100kHz
15 –1 DEMOD BW = 0.77kHz
11µA
10
–2
5
PA OUTPUT POWER

–3
5µA
0 2.4V, +85°C
7µA –4

BER
–5 3.6V, –40°C
–5
–10
–6
–15

–20 –7

–25 –8

05351-013
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61

–124
–123
–122
–121
–120
–119
–118
–117
–116
–115
–114
–113
–112
–111
–110
–109
–108
–107
–106

05351-016
PA SETTING
RF INPUT LEVEL (dBm)

Figure 13. PA Output Power vs. Setting Figure 16. BER vs. VDD and Temperature

80 0

70 –1
200.8k
60 DATA RATE
–2
LEVEL OF REJECTION (dB)

50
–3
1.002k 9.760k
40 DATA RATE DATA RATE
–4
BER

30
–5
20

–6
10

0 –7

–10 –8
05351-014

–99
–98
–97
–96
–95
–94
–93
–92
–91
–90
–122
–121
–120
–119
–118
–117
–116
–115
–114
–113
–112
–111
–110
–109
–108
–107
–106
–105
–104
–103
–102
–101
–100
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100

05351-017
FREQUENCY OF INTERFERER (MHz) RF INPUT LEVEL (dBm)

Figure 14. Wideband Interference Rejection; Wanted Signal (880 MHz) at 3 dB Figure 17. BER vs. Data Rate (Combined Matching Network) Separate LNA
above Sensitivity Point Interferer = FM Jammer (9.76 kbps, 10 kHz Deviation) and PA Matching Paths Typically Improve Performance by 2 dB

20 –60

–65
0
ACTUAL INPUT LEVEL
–70
LINEAR AFC OFF
–20 –75
SENSITIVITY (dBm)
RSSI LEVEL (dB)

–80
–40
RSSI READBACK LEVEL –85 CORRELATOR
–60 AFC ON
–90

–80 –95 CORRELATOR LINEAR AFC ON

AFC OFF
–100
–100
–105

–120 –110
05351-015

–120 –100 –80 –60 –40 –20 0 20

05351-018
0
10
20
30
40
50
60
70
80
90
–90
–80
–70
–60
–50
–40
–30
–20
–10

100
110
–110
–100

RF INPUT (dB)
FREQUENCY ERROR (kHz)

Figure 15. Digital RSSI Readback Linearity Figure 18. Sensitivity vs. Frequency Error with AFC On/Off

Rev. E | Page 14 of 47
Data Sheet ADF7020

FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 19) can use
an inexpensive quartz crystal as the PLL reference. The oscillator
circuit is enabled by setting R1_DB12 high. It is enabled by default
on power-up and is disabled by bringing CE low. Errors in the
crystal can be corrected using the automatic frequency control
(see the AFC section) feature or by adjusting the fractional-N
value (see the N Counter section). A single-ended reference
(TCXO, CXO) can also be used. The CMOS levels should be
applied to OSC2 with R1_DB12 set low.
OSC1 OSC2
05351-019
R Counter
The 3-bit R counter divides the reference input frequency by an
integer ranging from 1 to 7. The divided-down signal is presented
as the reference clock to the phase frequency detector (PFD).
The divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. Every doubling of the PFD gives a 3 dB benefit
in phase noise, as well as reducing occurrences of spurious
components. The R register defaults to R = 1 on power-up.
PFD [Hz] = XTAL/R
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various digital
points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB[29:31].
Regulator Ready

CP2 CP1
Figure 19. Oscillator Circuit on the ADF7020
Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. PCB track capacitance
values might vary from 2 pF to 5 pF, depending on board
layout. Thus, calculate CP1 and CP2 using:
Regulator ready is the default setting on MUXOUT after the
transceiver has been powered up. The power-up time of the
regulator is typically 50 μs. Because the serial interface is
powered from the regulator, the regulator must be at its
nominal voltage before the ADF7020 can be programmed. The
status of the regulator can be monitored at MUXOUT. When
the regulator ready signal on MUXOUT is high, programming
of the ADF7020 can begin.
DVDD

1
CL   CPCB
1 1
 REGULATOR READY
CP1 CP2
DIGITAL LOCK DETECT
Where possible, choose capacitors that have a low temperature ANALOG LOCK DETECT
coefficient to ensure stable frequency operation over all R COUNTER OUTPUT
MUX CONTROL MUXOUT

conditions. N COUNTER OUTPUT

CLKOUT Divider and Buffer PLL TEST MODES

Σ-∆ TEST MODES
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 20, and supplies a divided

05351-021
down 50:50 mark-space signal to the CLKOUT pin. An even
DGND
divide from 2 to 30 is available. This divide number is set in
Figure 21. MUXOUT Circuit
R1_DB[8:11]. On power-up, the CLKOUT defaults to
divide-by-8. Digital Lock Detect
DVDD Digital lock detect is active high. The lock detect circuit is
CLKOUT located at the PFD. When the phase error on five consecutive
ENABLE BIT
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
OSC1 DIVIDER ÷2 CLKOUT
1 TO 15 Because no external components are needed for digital lock
05351-020

detect, it is more widely used than analog lock detect.

Figure 20. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at fCLK.
Analog Lock Detect
This N-channel open-drain lock detect should be operated with
an external pull-up resistor of 10 kΩ nominal. When a lock has
been detected, this output is high with narrow low going pulses.

Rev. E | Page 15 of 47
ADF7020 Data Sheet
Voltage Regulators N Counter
The ADF7020 contains four regulators to supply stable voltages The feedback divider in the ADF7020 PLL consists of an 8-bit
to the part. The nominal regulator voltage is 2.3 V. Each integer counter and a 15-bit Σ-Δ fractional-N divider. The
regulator should have a 100 nF capacitor connected between integer counter is the standard pulse-swallow type common in
CREGx and GND. When CE is high, the regulators and other PLLs. This sets the minimum integer divide value to 31. The
associated circuitry are powered on, drawing a total supply fractional divide value gives very fine resolution at the output,
current of 2 mA. Bringing the chip-enable pin low disables the where the output frequency of the PLL is calculated as
regulators, reduces the supply current to less than 1 μA, and
 FRACTIONAL _ N 
erases all values held in the registers. The serial interface f OUT  PFD   INTEGER _ N  
 215 
operates off a regulator supply; therefore, to write to the part,
the user must have CE high and the regulator voltage must be REFERENCE IN

stabilized. Regulator status (CREG4) can be monitored using 4÷R PFD/

CHARGE VCO
the regulator ready signal from MUXOUT. PUMP

Loop Filter
The loop filter integrates the current pulses from the charge 4÷N

pump to form a voltage that tunes the output of the VCO to the
THIRD-ORDER
desired frequency. It also attenuates spurious levels generated by Σ-∆ MODULATOR

05351-023
the PLL. A typical loop filter design is shown in Figure 22.
FRACTIONAL-N INTEGER-N

Figure 23. Fractional-N PLL

CHARGE VCO
PUMP OUT The maximum N divide value is the combination of the
INTEGER_N (maximum = 255) and the FRACTIONAL_N
05351-022

(maximum = 32767/32768) and puts a lower limit on the

Figure 22. Typical Loop Filter Configuration
In FSK, the loop should be designed so that the loop bandwidth
(LBW) is approximately one and a half times the data rate.
Widening the LBW excessively reduces the time spent jumping
between frequencies, but it can cause insufficient spurious
attenuation.
For ASK systems, a wider LBW is recommended. The sudden
large transition between two power levels can result in VCO
pulling and can cause a wider output spectrum than is desired.
By widening the LBW to more than 10 times the data rate, the
amount of VCO pulling is reduced, because the loop settles
quickly back to the correct frequency. The wider LBW can
restrict the output power and data rate of ASK-based systems
compared with FSK-based systems.
Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtaining accurate FSK/GFSK modulation.
For GFSK, it is recommended that an LBW of 1.0 to 1.5 times
the data rate be used to ensure that sufficient samples are
taken of the input data while filtering system noise. The free
design tool ADIsimSRD Design Studio™ can be used to design
loop filters for the ADF7020. It can also be used to view the
effect of loop filter bandwidth on the spectrum of the
transmitted signal for different combinations of modulation
type, data rates, and modulation indices.
minimum usable PFD.
PFDMIN [Hz] = Maximum Required Output Frequency/(255 + 1)
For example, when operating in the European 868 MHz to
870 MHz band, PFDMIN equals 3.4 MHz. In the majority of
cases, it is advisable to use as high a value of PFD as possible
to obtain best phase noise performance.
Voltage Controlled Oscillator (VCO)
To minimize spurious emissions, the on-chip VCO operates
from 1724 MHz to 1912 MHz. The VCO signal is then divided
by 2 to give the required frequency for the transmitter and the
required LO frequency for the receiver.
The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO Adjust Bits
R1_DB[20:21].
The VCO is enabled as part of the PLL by the PLL Enable bit,
R0_DB28.
A further frequency divide-by-2 block is included to allow
operation in the lower 433 MHz and 460 MHz bands. To enable
operation in these bands, R1_DB13 should be set to 1. The
VCO needs an external 22 nF between the VCO and the
regulator to reduce internal noise.

Rev. E | Page 16 of 47
Data Sheet ADF7020
VCO Bias Current CHOOSING CHANNELS FOR BEST SYSTEM
VCO bias current can be adjusted using Bit R1_DB19 to PERFORMANCE
Bit R1_DB16. To ensure VCO oscillation, the minimum bias The fractional-N PLL allows the selection of any channel within
current setting under all conditions is 0xA. 868 MHz to 956 MHz (and 433 MHz using divide-by-2) to a
resolution of <300 Hz. This also facilitates frequency-hopping
VCO BIAS
R1_DB[16:19] TO N systems.
DIVIDER
Careful selection of the XTAL frequency is important to achieve
LOOP FILTER VCO ÷2 MUX TO PA
÷2 best spurious and blocking performance. The architecture of
220µF fractional-N causes some level of the nearest integer channel to
CVCO PIN couple directly to the RF output. This phenomenon is often
referred to as integer boundary spurious. If the desired RF channel

05351-024
VCO SELECT BIT and the nearest integer channel are separated by a frequency of
Figure 24. Voltage-Controlled Oscillator (VCO) less than the PLL loop bandwidth (LBW), the integer boundary
spurs are not attenuated by the loop.
Integer boundary spurs can be significantly reduced in amplitude
by choosing XTAL values that place the wanted RF channel
away from integer multiples of the PFD.

Rev. E | Page 17 of 47
ADF7020 Data Sheet

TRANSMITTER
RF OUTPUT STAGE
The PA of the ADF7020 is based on a single-ended, controlled
current, open-drain amplifier that has been designed to deliver
up to 13 dBm into a 50 Ω load at a maximum frequency of
956 MHz.
The PA output current and, consequently, the output power are
programmable over a wide range. The PA configurations in
FSK/GFSK and ASK/OOK modulation modes are shown in
Figure 25 and Figure 26, respectively. In FSK/GFSK modulation
mode, the output power is independent of the state of the
DATA I/O pin. In ASK/OOK modulation mode, it is dependent
on the state of the DATA I/O pin and Bit R2_DB29, which
selects the polarity of the TxData input. For each transmission
mode, the output power can be adjusted as follows:
The PA is equipped with overvoltage protection, which makes it
robust in severe mismatch conditions. Depending on the applica-
tion, one can design a matching network for the PA to exhibit
optimum efficiency at the desired radiated output power level
for a wide range of different antennas, such as loop or mono-
pole antennas. See the LNA/PA Matching section for details.
PA Bias Currents
Control Bits R2_DB[30:31] facilitate an adjustment of the PA
bias current to further extend the output power control range,
if necessary. If this feature is not required, the default value of
7 μA is recommended. The output stage is powered down by
resetting Bit R2_DB4. To reduce the level of undesired spurious
emissions, the PA can be muted during the PLL lock phase by
toggling this bit.

 FSK/GFSK MODULATION SCHEMES

The output power is set using Bits R2_DB[9:14]. Frequency Shift Keying (FSK)
 ASK Frequency shift keying is implemented by setting the N value
The output power for the inactive state of the TxData input for the center frequency and then toggling this with the TxData
is set by Bits R2_DB[15:20]. The output power for the line. The deviation from the center frequency is set using
active state of the TxData input is set by Bits R2_DB[9:14]. Bits R2_DB[15:23]. The deviation from the center frequency
 OOK in Hz is
The output power for the active state of the TxData input PFD  Modulation Number
is set by Bits R2_DB[9:14]. The PA is muted when the TxData FSK DEVIATION [Hz] 
214
input is inactive.
where Modulation Number is a number from 1 to 511
R2_DB[30:31]
2 (R2_DB[15:23]).
Select FSK using Bits R2_DB[6:8].
6
IDAC R2_DB[9:14]

RFOUT
R2_DB4
+ R2_DB5
4R PFD/ PA STAGE
DIGITAL CHARGE VCO
LOCK DETECT PUMP
RFGND
05351-025

FSK DEVIATION
FROM VCO FREQUENCY
Figure 25. PA Configuration in FSK/GFSK Mode ÷N

–fDEV
THIRD-ORDER
+fDEV Σ-∆ MODULATOR
DATA I/O ASK/OOK MODE
05351-027

R2_DB29 TxDATA
FRACTIONAL-N INTEGER-N
R2_DB[30:31]
Figure 27. FSK Implementation
6
6 R2_DB[9:14]
IDAC
6
R2_DB[15:23]

RFOUT 0
R2_DB4
+ R2_DB5
DIGITAL
RFGND LOCK DETECT
05351-026

FROM VCO

Figure 26. PA Configuration in ASK/OOK Mode

Rev. E | Page 18 of 47
Data Sheet
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied
by the transmitted spectrum by digitally prefiltering the TxData.
A TxCLK output line is provided from the ADF7020 for
synchronization of TxData from the microcontroller. The
TxCLK line can be connected to the clock input of a shift
register that clocks data to the transmitter at the exact data rate.
Setting Up the ADF7020 for GFSK
To set up the frequency deviation, set the PFD and the modulation
control bits.
PFD × 2m
GFSK DEVIATION [Hz] =
212
where m is GFSK_MOD_CONTROL, set using R2_DB[24:26].
To set up the GFSK data rate,
PFD
DR [bps] =
DIVIDER _ FACTOR × INDEX _ COUNTER
The INDEX_COUNTER variable controls the number of
intermediate frequency steps between the low and high frequency.
It is usually possible to achieve a given data rate with various
combinations of DIVIDER_FACTOR and INDEX_COUNTER.
Choosing a higher INDEX_COUNTER can help in improving
the spectral performance.
Rev. E | Page 19 of 47
ADF7020
Amplitude Shift Keying (ASK)
Amplitude shift keying is implemented by switching the output
stage between two discrete power levels. This is accomplished
by toggling the DAC, which controls the output level between
two 6-bit values set up in Register 2. A 0 TxData bit sends
Bits R2_DB[15:20] to the DAC. A high TxData bit sends
Bits R2_DB[9:14] to the DAC. A maximum modulation depth
of 30 dB is possible.
On-Off Keying (OOK)
On-off keying is implemented by switching the output stage to
a certain power level for a high TxData bit and switching the
output stage off for a zero. For OOK, the transmitted power for
a high input is programmed using Bits R2_DB[9:14].
Gaussian On-Off Keying (GOOK)
Gaussian on-off keying represents a prefiltered form of OOK
modulation. The usually sharp symbol transitions are replaced
with smooth Gaussian filtered transitions, the result being a
reduction in frequency pulling of the VCO. Frequency pulling
of the VCO in OOK mode can lead to a wider than desired BW,
especially if it is not possible to increase the loop filter BW >
300 kHz. The GOOK sampling clock samples data at the data
rate (see the Setting Up the ADF7020 for GFSK section).
ADF7020 Data Sheet

RECEIVER
RF FRONT END The LNA has two basic operating modes: high gain/low noise
The ADF7020 is based on a fully integrated, low IF receiver mode and low gain/low power mode. To switch between these
architecture. The low IF architecture facilitates a very low external two modes, use the LNA_MODE bit, R6_DB15. The mixer is
component count and does not suffer from power line-induced also configurable between a low current and an enhanced
interference problems. linearity mode using the MIXER_LINEARITY bit, R6_DB18.

Figure 28 shows the structure of the receiver front end. The Based on the specific sensitivity and linearity requirements
many programming options allow users to trade off sensitivity, of the application, it is recommended to adjust control bits
linearity, and current consumption against each other in the LNA_MODE (R6_DB15) and MIXER_LINEARITY (R6_DB18),
way best suitable for their applications. To achieve a high level as outlined in Table 5.
of resilience against spurious reception, the LNA features a The gain of the LNA is configured by the LNA_GAIN field,
differential input. Switch SW2 shorts the LNA input when R9_DB[20:21], and can be set by either the user or the
transmit mode is selected (R0_DB27 = 0). This feature facilitates automatic gain control (AGC) logic.
the design of a combined LNA/PA matching network, avoiding IF Filter Settings/Calibration
the need for an external Rx/Tx switch. See the LNA/PA
Out-of-band interference is rejected by means of a fourth-order
Matching section for details on the design of the matching
Butterworth polyphase IF filter centered around a frequency of
network.
200 kHz. The bandwidth of the IF filter can be programmed
I (TO FILTER)
between 100 kHz and 200 kHz by using Control Bits R1_DB[22:23]
RFIN
Tx/Rx SELECT
SW2 LNA
and should be chosen as a compromise between interference rejec-
(R0_DB27) LO
RFINB
tion, attenuation of the desired signal, and the AFC pull-in range.
Q (TO FILTER) To compensate for manufacturing tolerances, the IF filter
LNA MODE
(R6_DB15) should be calibrated once after power-up. The IF filter calibration
MIXER LINEARITY
LNA CURRENT (R6_DB18) logic requires that the IF filter divider in Bits R6_DB[20:28] be set
(R6_DB[16:17])
as dependent on the crystal frequency. Once initiated by setting
LNA GAIN
(R9_DB[20:21]) Bit R6_DB19, the calibration is performed automatically without
05351-028

LNA/MIXER ENABLE
(R8_DB6)
Figure 28. ADF7020 RF Front End
The LNA is followed by a quadrature down conversion mixer,
that converts the RF signal to the IF frequency of 200 kHz. It
is important to consider that the output frequency of the
synthesizer must be programmed to a value 200 kHz below
the center frequency of the received channel.
any user intervention. The calibration time is 200 μs, during
which the ADF7020 should not be accessed. It is important not
to initiate the calibration cycle before the crystal oscillator has
fully settled. If the AGC loop is disabled, the gain of IF filter can
be set to three levels using the FILTER_GAIN field, R9_DB[20:21].
The filter gain is adjusted automatically, if the AGC loop is
enabled.

Table 5. LNA/Mixer Modes

Sensitivity
LNA Mode LNA Gain Value Mixer Linearity (DR = 9.6 kbps, Rx Current Input IP3
Receiver Mode (R6_DB15) (R9_DB[20:21]) (R6_DB18) fDEV = 10 kHz) Consumption (mA) (dBm)
High Sensitivity Mode (Default) 0 30 0 −110.5 21 −24
RxMode2 1 10 0 −104 20 −13.5
Low Current Mode 1 3 0 −94 19 −5
Enhanced Linearity Mode 1 3 1 −88 19 −3
RxMode5 1 10 1 −98 20 −10
RxMode6 0 30 1 −107 21 −20

Rev. E | Page 20 of 47
Data Sheet ADF7020
RSSI/AGC This wait time can be adjusted to speed up this settling by
The RSSI is implemented as a successive compression log amp adjusting the appropriate parameters.
following the baseband channel filtering. The log amp achieves AGC _ WAIT _ TIME 
±3 dB log linearity. It also doubles as a limiter to convert the AGC _ DELAY  SEQ _ CLK
signal-to-digital levels for the FSK demodulator. The RSSI itself XTAL
is used for amplitude shift keying (ASK) demodulation. In ASK
AGC Settling =
mode, extra digital filtering is performed on the RSSI value.
AGC_WAIT_TIME × Number of Gain Changes
Offset correction is achieved using a switched capacitor integrator
in feedback around the log amp. This uses the baseband offset Thus, in the worst case, if the AGC loop has to go through all
clock divide. The RSSI level is converted for user readback and 5 gain changes, AGC_DELAY =10, SEQ_CLK = 200 kHz, AGC
digitally controlled AGC by an 80-level (7-bit) flash ADC. This Settling = 10 × 5 μs × 5 = 250 μs. Minimum AGC_WAIT_TIME
level can be converted to input power in dBm. needs to be at least 25 μs.
OFFSET RSSI Formula (Converting to dBm)
CORRECTION
INPUT_POWER [dBm] = −120 dBm + (READBACK_CODE +
FSK GAIN_MODE_CORRECTION) × 0.5
1 A A A LATCH DEMOD

where:
FWR FWR FWR FWR CLK RSSI READBACK_CODE is given by Bit RV7 to Bit RV1 in the
ASK
DEMOD readback register (see the Readback Format section).
ADC
GAIN_MODE_CORRECTION is given by the values in Table 6.
05351-029

R
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained
NOTES
1. FWR = FULL WAVE RECTIFIER from the readback register.
Figure 29. RSSI Block Diagram
Table 6. Gain Mode Correction
RSSI Thresholds Gain Mode
When the RSSI is above AGC_HIGH_THRESHOLD, the gain LNA Gain (LG2, LG1) Filter Gain (FG2, FG1) Correction
is reduced. When the RSSI is below AGC_LOW_THRESHOLD, H (1,1) H (1,0) 0
the gain is increased. A delay (AGC_DELAY) is programmed M (1,0) H (1,0) 24
to allow for settling of the loop. The user programs the two M (1,0) M (0,1) 45
threshold values (recommended defaults of 30 and 70) and the M (1,0) L (0,0) 63
delay (default of 10). The default AGC setup values should be L (0,1) L (0,0) 90
adequate for most applications. The threshold values must be EL (0,0) L (0,0) 105
chosen to be more than 30 apart for the AGC to operate An additional factor should be introduced to account for losses
correctly. in the front-end matching network/antenna.
Offset Correction Clock
FSK DEMODULATORS ON THE ADF7020
In Register 3, the user should set the BB offset clock divide bits
The two FSK demodulators on the ADF7020 are
R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz.
 FSK correlator/demodulator
BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE)
 Linear demodulator
where BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
Select these using the demodulator select bits, R4_DB[4:5].
AGC Information and Timing
AGC is selected by default, and operates by selecting the appropriate FSK CORRELATOR/DEMODULATOR
LNA and filter gain settings for the measured RSSI level. It is The quadrature outputs of the IF filter are first limited and then
possible to disable AGC by writing to Register 9 if entering one fed to a pair of digital frequency correlators that perform band-
of the modes listed in Table 5 is desired, for example. The time pass filtering of the binary FSK frequencies at (IF + fDEV) and
for the AGC circuit to settle and, therefore, the time to take an (IF − fDEV). Data is recovered by comparing the output levels
accurate RSSI measurement is typically 150 μs, although this from each of the two correlators. The performance of this
depends on how many gain settings the AGC circuit has to frequency discriminator approximates that of a matched filter
cycle through. After each gain change, the AGC loop waits detector, which is known to provide optimum detection in the
for a programmed time to allow transients to settle. presence of additive white Gaussian noise (AWGN).

Rev. E | Page 21 of 47
ADF7020 Data Sheet
FREQUENCY CORRELATOR SLICER
The discriminator BW is controlled in Register 6 by
IF RxDATA

SYNCHRONIZER
I

DEMOD FILTER
Bit R6_DB[4:13] and is defined as

POST

DATA
LIMITERS DEMOD _ CLK  K
DISCRIMINATOR _ BW 
Q RxCLK
800  10 3
IF – fDEV IF + fDEV

0
where:

05351-030
DEMOD_CLK is as defined in the Register 3—Receiver Clock
R6_DB[4:13] R6_DB[14] R3_DB[8:15]
Register section, second comment.
Figure 30. FSK Correlator/Demodulator Block Diagram
K = Round(200 × 103/FSK Deviation)
Postdemodulator Filter To optimize the coefficients of the FSK correlator, two addi-
A second-order, digital low-pass filter removes excess noise from tional bits, R6_DB14 and R6_DB29, must be assigned. The
the demodulated bit stream at the output of the discriminator. value of these bits depends on whether K (as defined above) is
The bandwidth of this postdemodulator filter is programmable odd or even. These bits are assigned according to Table 7 and
and must be optimized for the user’s data rate. If the bandwidth Table 8.
is set too narrow, performance is degraded due to intersymbol
interference (ISI). If the bandwidth is set too wide, excess noise Table 7. When K Is Even
degrades the receiver’s performance. Typically, the 3 dB bandwidth K K/2 R6_DB14 R6_DB29
of this filter is set at approximately 0.75 times the user’s data rate, Even Even 0 0
using Bits R4_DB[6:15]. Even Odd 0 1

Bit Slicer Table 8. When K Is Odd

The received data is recovered by the threshold detecting the K (K + 1)/2 R6_DB14 R6_DB29
output of the postdemodulator low-pass filter. In the correlator/ Odd Even 1 0
demodulator, the binary output signal levels of the frequency Odd Odd 1 1
discriminator are always centered on 0. Therefore, the slicer
threshold level can be fixed at 0, and the demodulator perform- Postdemodulator Bandwidth Register Settings
ance is independent of the run-length constraints of the transmit
The 3 dB bandwidth of the postdemodulator filter is controlled
data bit stream. This results in robust data recovery, which does
by Bits R4_DB[6:15] and is given by
not suffer from the classic baseline wander problems that exist in
the more traditional FSK demodulators. 210  2π  fCUTOFF
POSTDEMOD_BW_SETTING 
Frequency errors are removed by an internal AFC loop that DEMOD _ CLK
measures the average IF frequency at the limiter output and where fCUTOFF is the target 3 dB bandwidth in Hz of the post-
applies a frequency correction value to the fractional-N demodulator filter. This should typically be set to 0.75 times the
synthesizer. This loop should be activated when the frequency data rate (DR).
errors are greater than approximately 40% of the transmit
Some sample settings for the FSK correlator/demodulator are
frequency deviation (see the AFC section).
DEMOD_CLK = 5 MHz
Data Synchronizer
DR = 9.6 kbps
An oversampled digital PLL is used to resynchronize the fDEV = 20 kHz
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate. Therefore,
See the Register 3—Receiver Clock Register Comments section fCUTOFF = 0.75 × 9.6 × 103 Hz
for a definition of how to program. The clock recovery PLL can POSTDEMOD_BW_SETTING = 211 π 7.2 × 103 Hz/(5 MHz)
accommodate frequency errors of up to ±2%. POSTDEMOD_BW_SETTING = Round(9.26) = 9
FSK Correlator Register Settings and
To enable the FSK correlator/demodulator, Bits R4_DB[5:4] should K = Round(200 kHz)/20 kHz) = 10
be set to 01. To achieve best performance, the bandwidth of the DISCRIMINATOR_BW = (5 MHz × 10)/(800 × 103) = 62.5 =
FSK correlator must be optimized for the specific deviation 63 (rounded to the nearest integer)
frequency that is used by the FSK transmitter.

Rev. E | Page 22 of 47
Data Sheet ADF7020
Table 9. Register Settings1 ASK/OOK Operation
Setting Name Register Address Value ASK/OOK demodulation is activated by setting Bits R4_DB[4:5]
POSTDEMOD_BW_SETTING R4_DB[6:15] 0x09 to 10.
DISCRIMINATOR_BW R6_DB[4:13] 0x3F
Digital filtering and envelope detecting the digitized RSSI input
DOT_PRODUCT R6_DB14 0
via MUX 1, as shown in Figure 31, performs ASK/OOK
RXDATA_INVERT R6_DB29 1
demodulation. The bandwidth of the digital filter must be
1
The latest version of the ADF7020 configuration software can aid in optimized to remove any excess noise without causing ISI in the
calculating register settings. received ASK/OOK signal.
LINEAR FSK DEMODULATOR The 3 dB bandwidth of this filter is typically set at approximately
Figure 31 shows a block diagram of the linear FSK demodulator. 0.75 times the user data rate and is assigned by R4 _DB[6:15] as
MUX 1 SLICER
ADC RSSI OUTPUT 7 210  2  f CUTOFF
POSTDEMOD _ BW _ SETTING 
DEMOD _ CLK
LEVEL RxDATA
I
IF where fCUTOFF is the target 3 dB bandwidth in Hz of the
AVERAGING
FILTER

LIMITER
postdemodulator filter.
DETECTOR
ENVELOPE

Q It is also recommended to adjust the peak response factor to 6

FREQUENCY in Register 10 for robust operation over the full input range.
FREQUENCY READBACK
LINEAR DISCRIMINATOR AND This improves the receiver’s AM immunity performance.
AFC LOOP
05351-031

R4_DB[6:15]
Figure 31. Block Diagram of Frequency Measurement System and
ASK/OOK/Linear FSK Demodulator
This method of frequency demodulation is useful when very
short preamble length is required, and the system protocol
cannot support the overhead of the settling time of the internal
feedback AFC loop settling.
A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a
combined averaging filter and envelope detector. The demodu-
lated FSK data is recovered by threshold-detecting the output of
the averaging filter, (see Figure 31). In this mode, the slicer
output shown in Figure 31 is routed to the data synchronizer
PLL for clock synchronization. To enable the linear FSK
demodulator, set Bits R4_DB[4:5] to 00.
The 3 dB bandwidth of the postdemodulation filter is set in the
same way as the FSK correlator/demodulator, which is set in
R4_DB[6:15] and is defined as
210  2  f CUTOFF
POSTDEMOD _ BW _ SETTING 
DEMOD _ CLK
where fCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter. DEMOD_CLK is as defined in the
Register 3—Receiver Clock Register section, second comment.
AFC
The ADF7020 supports a real-time AFC loop, which is used to
remove frequency errors that can arise due to mismatches between
the transmit and receive crystals. This uses the frequency
discriminator block, as described in the Linear FSK Demodulator
section (see Figure 31). The discriminator output is filtered and
averaged to remove the FSK frequency modulation, using a
combined averaging filter and envelope detector. In FSK mode,
the output of the envelope detector provides an estimate of the
average IF frequency.
Two methods of AFC, external and internal, are supported on
the ADF7020 (in FSK mode only).
External AFC
The user reads back the frequency information through the
ADF7020 serial port and applies a frequency correction value to
the fractional-N synthesizer’s N divider.
The frequency information is obtained by reading the 16-bit
signed AFC_READBACK, as described in the Readback Format
section, and applying the following formula:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215
Note that while the AFC_READBACK value is a signed number,
under normal operating conditions, it is positive. The frequency
error can be calculated from
FREQ_ERROR [Hz] = FREQ_RB (Hz) − 200 kHz
Thus, in the absence of frequency errors, the FREQ_RB value is
equal to the IF frequency of 200 kHz.

Rev. E | Page 23 of 47
ADF7020
Internal AFC
The ADF7020 supports a real-time internal automatic
frequency control loop. In this mode, an internal control
loop automatically monitors the frequency error and adjusts
the synthesizer N divider using an internal PI control loop.
The internal AFC control loop parameters are controlled in
Register 11. The internal AFC loop is activated by setting
R11_DB20 to 1. A scaling coefficient must also be entered,
based on the crystal frequency in use. This is set up in
Bits R11_DB[4:19] and should be calculated using
AFC_SCALING_COEFFICIENT = (500 × 224)/XTAL
Therefore, using a 10 MHz XTAL yields an AFC scaling
coefficient of 839.
AFC Performance
The improved sensitivity performance of the Rx when AFC is
enabled and in the presence of frequency errors is shown in
Figure 18. The maximum AFC frequency range is ±50 kHz,
which corresponds to ±58 ppm at 868 MHz. This is the total
error tolerance allowed in the link. For example, in a point-to-
point system, AFC can compensate for two ±29 ppm crystals or
one ±50 ppm crystal and one ±8 ppm TCXO.
AFC settling typically takes 48 bits to settle within ±1 kHz. This
can be improved by increasing the postdemodulator bandwidth
in Register 4 at the expense of Rx sensitivity.
When AFC errors have been removed using either the internal
or external AFC, further improvement in the receiver’s sensi-
tivity can be obtained by reducing the IF filter bandwidth using
Bits R1_DB[22:23].
Rev. E | Page 24 of 47
Data Sheet
AUTOMATIC SYNC WORD RECOGNITION
The ADF7020 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7020. In receive mode, this
preprogrammed word is compared to the received bit stream
and, when a valid match is identified, the external pin
INT/LOCK is asserted by the ADF7020.
This feature can be used to alert the microprocessor that a valid
channel has been detected. It relaxes the computational require-
ments of the microprocessor and reduces the overall power
consumption. The INT/LOCK is automatically deasserted again
after nine data clock cycles.
The automatic sync/ID word detection feature is enabled by
selecting Demodulator Mode 2 or Demodulator Mode 3 in the
demodulator setup register. Do this by setting Bits R4_DB[25:23] =
010 or 011. Bits R5_DB[4:5] are used to set the length of the
sync/ID word, which can be 12, 16, 20, or 24 bits long. The
transmitter must transmit the MSB of the sync byte first and the
LSB last to ensure proper alignment in the receiver sync byte
detection hardware.
For systems using forward error correction (FEC), an error
tolerance parameter can also be programmed that accepts a
valid match when up to three bits of the word are incorrect. The
error tolerance value is assigned in Bits R5_DB[6:7].
Data Sheet ADF7020

APPLICATIONS INFORMATION
LNA/PA MATCHING A first-order implementation of the matching network can be
obtained by understanding the arrangement as two L type
The ADF7020 exhibits optimum performance in terms of matching networks in a back-to-back configuration. Due to the
sensitivity, transmit power, and current consumption only if its asymmetry of the network with respect to ground, a compromise
RF input and output ports are properly matched to the antenna between the input reflection coefficient and the maximum
impedance. For cost-sensitive applications, the ADF7020 is differential signal swing at the LNA input must be established.
equipped with an internal Rx/Tx switch that facilitates the use The use of appropriate CAD software is strongly recommended
of a simple combined passive PA/LNA matching network. for this optimization.
Alternatively, an external Rx/Tx switch, such as the Analog
Devices ADG919, can be used. It yields a slightly improved Depending on the antenna configuration, the user may need a
receiver sensitivity and lower transmitter power consumption. harmonic filter at the PA output to satisfy the spurious emission
requirement of the applicable government regulations. The
External Rx/Tx Switch harmonic filter can be implemented in various ways, such as
Figure 32 shows a configuration using an external Rx/Tx switch. a discrete LC pi or T-stage filter. Dielectric low-pass filter
This configuration allows an independent optimization of the components, such as the LFL18924MTC1A052 (for operation
matching and filter network in the transmit and receive path in the 915 MHz and 868 MHz band) by Murata Manufacturing,
and is, therefore, more flexible and less difficult to design than Co., Ltd., represent an attractive alternative to discrete designs.
the configuration using the internal Rx/Tx switch. The PA is Application Note AN-917 describes how to replace the Murata
biased through Inductor L1, while C1 blocks dc current. Both dielectric filter with an LC filter if desired.
elements, L1 and C1, also form the matching network, which
The immunity of the ADF7020 to strong out-of-band interference
transforms the source impedance into the optimum PA load
can be improved by adding a band-pass filter in the Rx path.
impedance, ZOPT_PA.
Apart from discrete designs, SAW or dielectric filter components,
VBAT
such as the SAFCH869MAM0T00 or SAFCH915MAL0N00,
L1 both by Murata, are well suited for this purpose. Alternatively,
C1 PA_OUT
OPTIONAL PA the ADF7020 blocking performance can be improved by
LPF
selecting the high linearity mode, as described in Table 5.
ANTENNA ZOPT_PA
ZIN_RFIN Internal Rx/Tx Switch
OPTIONAL CA RFIN Figure 33 shows the ADF7020 in a configuration where the internal
BPF
(SAW) Rx/Tx switch is used with a combined LNA/PA matching network.
LA LNA
RFINB This is the configuration used in the EVAL-ADF7020DBZ1
through EVAL-ADF7020DBZ3 evaluation boards. For most
ADG919
ZIN_RFIN applications, the slight performance degradation of 1 dB to 2 dB
05351-032

CB
Rx/Tx – SELECT ADF7020 caused by the internal Rx/Tx switch is acceptable, allowing the
user to take advantage of the cost saving potential of this
Figure 32. ADF7020 with External Rx/Tx Switch
solution. The design of the combined matching network must
ZOPT_PA depends on various factors, such as the required compensate for the reactance presented by the networks in the
output power, the frequency range, the supply voltage range, Tx and the Rx paths, taking the state of the Rx/Tx switch into
and the temperature range. Selecting an appropriate ZOPT_PA consideration.
helps to minimize the Tx current consumption in the application. VBAT
Application Note AN-767 contains a number of ZOPT_PA values
L1
for representative conditions. Under certain conditions, however, it C1 PA_OUT
is recommended that a suitable ZOPT_PA value be obtained by PA

means of a load-pull measurement. ANTENNA ZOPT_PA

OPTIONAL
BPF OR LPF ZIN_RFIN
Due to the differential LNA input, the LNA matching network
CA RFIN
must be designed to provide both a single-ended-to-differential
conversion and a complex conjugate impedance match. The LA LNA
network with the lowest component count that can satisfy these RFINB

requirements is the configuration shown in Figure 32, which

consists of two capacitors and one inductor. ZIN_RFIN
05351-033

CB
ADF7020
Figure 33. ADF7020 with Internal Rx/Tx Switch

Rev. E | Page 25 of 47
ADF7020
The procedure typically requires several iterations until an
acceptable compromise is reached. The successful implementation
of a combined LNA/PA matching network for the ADF7020 is
critically dependent on the availability of an accurate electrical
model for the PC board. In this context, the use of a suitable
CAD package is strongly recommended. To avoid this effort,
however, a small form-factor reference design for the ADF7020
is provided, including matching and harmonic filter components.
Gerber files and schematics are available on the product page at:
www.analog.com/ADF7020.
IMAGE REJECTION CALIBRATION
The image channel in the ADF7020 is 400 kHz below the desired
signal. The polyphase filter rejects this image with an asymmetric
frequency response. The image rejection performance of the
receiver is dependent on how well matched the I and Q signals
are in amplitude, and how well matched the quadrature is between
them (that is, how close to 90º apart they are.) The uncalibrated
Data Sheet
The magnitude of the phase adjust is set by using the IR_PHASE_
ADJUST bits (R10_DB[24:27]). This correction can be applied
to either the I channel or Q channel, by toggling bit (R10_DB28).
The magnitude of the I/Q gain is adjusted by the IR_GAIN_
ADJUST bits (R10_DB[16:20]). This correction can be applied
to either the I or Q channel using bit (R10_DB22), while the
GAIN/ATTENUATE bit (R10_DB21) sets whether the gain
adjustment defines a gain or attenuation adjust.
The calibration results are valid over changes in the ADF7020
supply voltage. However, there is some variation with temperature.
A typical plot of variation in image rejection over temperature
after initial calibrations at +25°C, −40°C, and +85°C is shown in
Figure 34. The internal temperature sensor on the ADF7020 can
be used to determine if a new IR calibration is required.
60
CAL AT +25°C
50

image rejection performance is approximately 30 dB. However,

IMAGE REJECTION (dB)

it is possible to improve this performance by as much as 20 dB 40 CAL AT +85°C
CAL AT –40°C
by finding the optimum I/Q gain and phase adjust settings.
30
Calibration Procedure and Setup
VDD = 3.0V
The image rejection calibration works by connecting an external IF BW = 25kHz
20
WANTED SIGNAL: INTERFERER SIGNAL:
RF signal to the RF input port. The external RF signal should be RF FREQ = 430MHz RF FREQ = 429.8MHz
MODULATION = 2FSK MODULATION = 2FSK
set at the image frequency and the filter rejection measured by 10 DATA RATE = 9.6kbps, DATA RATE = 9.6kbps,
PRBS9 PRBS11
monitoring the digital RSSI readback. As the image rejection is fDEV = 4kHz fDEV = 4kHz
improved by adjusting the I/Q Gain and phase, the RSSI LEVEL= –100dBm
0

05351-058
–60 –40 –20 0 20 40 60 80 100
reading reduces.
TEMPERATURE (°C)

Figure 34. Image Rejection Variation with Temperature after Initial

Calibrations at +25°C, −40°C, and +85°C
ADF7020
RFIN
EXTERNAL
SIGNAL MATCHING RFINB LNA
SOURCE POLYPHASE
GAIN ADJUST

IF FILTER
RSSI/
LOG AMP

7-BIT ADC
PHASE ADJUSTMENT

I Q

FROM LO SERIAL
INTERFACE

PHASE ADJUST
REGISTER 10 4 RSSI READBACK
GAIN ADJUST
REGISTER 10

MICROCONTROLLER
05351-059

I/Q GAIN/PHASE ADJUST AND

RSSI MEASUREMENT
ALGORITHM

Figure 35. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller

Rev. E | Page 26 of 47
Data Sheet ADF7020
TRANSMIT PROTOCOL AND CODING DEVICE PROGRAMMING AFTER INITIAL POWER-UP
CONSIDERATIONS Table 10 lists the minimum number of writes needed to set up
the ADF7020 in either Tx or Rx mode after CE is brought high.
SYNC ID

05351-034
PREAMBLE WORD FIELD DATA FIELD CRC Additional registers can also be written to tailor the part to a
particular application, such as setting up sync byte detection or
Figure 36. Typical Format of a Transmit Protocol
enabling AFC. When going from Tx to Rx or vice versa, the
A dc-free preamble pattern is recommended for FSK/GFSK/ user needs to write only to the N Register to alter the LO by
ASK/OOK demodulation. The recommended preamble pattern 200 kHz and to toggle the Tx/Rx bit.
is a dc-balanced pattern such as a 10101010… sequence.
Preamble patterns with longer run-length constraints such as Table 10. Minimum Register Writes Required for Tx/Rx Setup
11001100… can also be used. However, this results in a longer Mode Register
synchronization time of the received bit stream in the receiver. Tx Reg. 0 Reg. 1 Reg. 2
Rx (OOK) Reg. 0 Reg. 1 Reg. 3 Reg. 4 Reg. 6
The remaining fields that follow the preamble header do not
Rx (G/FSK) Reg. 0 Reg. 1 Reg. 3 Reg. 4 Reg. 6
have to use dc-free coding. For these fields, the ADF7020 can
Tx ↔Rx Reg. 0
accommodate coding schemes with a run-length of up to
several bytes without any performance degradation, for example Figure 39 and Figure 40 show the recommended programming
several bytes of 0x00 or 0xFF. To help minimize bit errors when sequence and associated timing for power-up from standby mode.
receiving these long runs of continuous 0s or 1s, it is important INTERFACING TO MICROCONTROLLER/DSP
to choose a data rate and XTAL combination that minimizes the
error between the actual data rate and the on-board CDR_CLK/32. Low level device drivers are available for interfacing the
For example, if a 9.6 kbps data rate is desired, then using an ADF7020 to the Analog Devices ADuC841 analog micro-
11.0592 MHz XTAL gives a 0% nominal error between the controller, or the Blackfin® ADSP-BF533 DSP, using the hardware
desired data rate and CDR_CLK/32. Application Note AN-915 connections shown in Figure 37 and Figure 38.
gives more details on supporting long run lengths on the ADuC841 ADF7020
ADF7020. MISO DATA I/O
MOSI
The ADF7020 can also support Manchester-encoded data for SCLOCK DATA CLK
the entire protocol. Manchester decoding needs to be done on SS
the companion microcontroller, however. In this case, the P3.7 CE
P3.2/INT0 INT/LOCK
ADF7020 should be set up at the Manchester chip or baud
P2.4 SREAD
rate, which is twice the effective data rate. P2.5 SLE
GPIO

05351-035
P2.6 SDATA
P2.7 SCLK

Figure 37. ADuC841 to ADF7020 Connection Diagram

ADSP-BF533 ADF7020
SCK SCLK
MOSI SDATA
MISO SREAD
PF5 SLE
RSCLK1 DATA CLK
DT1PRI DATA I/O
DR1PRI
RFS1 INT/LOCK
PF6 CE
05351-036

VDDEXT VDD
GND GND

Figure 38. ADSP-BF533 to ADF7020 Connection Diagram

Rev. E | Page 27 of 47
ADF7020 Data Sheet
POWER CONSUMPTION AND BATTERY LIFETIME Using a sequenced power-on routine like that illustrated in
CALCULATIONS Figure 39 can reduce the IAVG_ON current and, hence, reduce the
overall power consumption. When used in conjunction with a
Average Power Consumption can be calculated using
large duty-cycle or large tOFF, this can result in significantly
Average Power Consumption = (tON × IAVG_ON + tOFF × increased battery life. Analog Devices, Inc., free design tool,
IPOWERDOWN)/(tON + tOFF) ADIsimSRD Design Studio, can assist in these calculations.
ADF7020 I DD

19mA TO
22mA

14mA

XTAL
t0

3.65mA

2.0mA

AFC
t10

REG. AGC/
READY WR0 WR1 VCO WR3 WR4 WR6 RSSI CDR RxDATA TIME
t1 t2 t3 t4 t5 t6 t7 t8 t9 t11

05351-037
tON tOFF

Figure 39. Rx Programming Sequence and Timing Diagram

Table 11. Power-Up Sequence Description

Parameter Value Description Signal to Monitor
t0 2 ms Crystal starts power-up after CE is brought high. This typically depends CLKOUT pin
on the crystal type and the load capacitance specified.
t1 10 μs Time for regulator to power up. The serial interface can be written to after MUXOUT pin
this time.
t2, t3, t5, 32 × 1/SPI_CLK Time to write to a single register. Maximum SPI_CLK is 25 MHz.
t6, t7
t4 1 ms The VCO can power-up in parallel with the crystal. This depends on the CVCO pin
CVCO capacitance value used. A value of 22 nF is recommended as a
trade-off between phase noise performance and power-up time.
t8 150 μs This depends on the number of gain changes the AGC loop needs to Analog RSSI on TEST_A pin
cycle through and AGC settings programmed. This is described in more (Available by writing 0x3800 000C)
detail in the AGC Information and Timing section.
t9 5 × BIT_PERIOD This is the time for the clock and data recovery circuit to settle. This typically
requires 5-bit transitions to acquire sync and is usually covered by the
preamble.
t10 48 × BIT_PERIOD This is the time for the automatic frequency control circuit to settle. This
typically requires 48-bit transitions to acquire lock and is usually covered by
an appropriate length preamble.
t11 Packet Length Number of bits in payload by the bit period.

Rev. E | Page 28 of 47
Data Sheet ADF7020

ADF7020 I DD
15mA TO
30mA

14mA

3.65mA

2.0mA

REG.
READY WR0 WR1 XTAL + VCO WR2 TxDATA TIME
t1 t2 t3 t4 t5 t12

05351-038
tON tOFF

Figure 40. Tx Programming Sequence and Timing Diagram

Rev. E | Page 29 of 47
ADF7020 Data Sheet
LOOP FILTER

XTAL

REFERENCE

VDD
CVCO
CAP

48
47
46
45
44
43
42
41
40
39
38
37
VCO GND

OSC1
OSC2
GND

GND
VDD
CPOUT

MUXOUT
GND1

CREG3
CVCO

VDD3
VDD

MICROCONTROLLER
1 36
VCOIN CLKOUT

Tx/Rx SIGNAL
MATCHING 2 PIN 1 35

INTERFACE
CREG1 INDICATOR DATA CLK
3 34
VDD VDD1 DATA I/O

TO
T-STAGE LC 4 33
ANTENNA FILTER RFOUT INT/LOCK
CONNECTION 5 32
RFGND VDD2 VDD
6 31
RFIN ADF7020 CREG2
7 30
RFINB TOP VIEW ADCIN
8 29

MICROCONTROLLER
RLNA (Not to Scale) GND2

CONFIGURATION
9 28
VDD VDD4 SCLK

INTERFACE
10 27
RSET SREAD

TO
11 26
CREG4 SDATA
12 25
GND4 SLE

TEST_A
FILT_Q
FILT_Q
MIX_Q
MIX_Q
FILT_I
FILT_I
GND4

GND4
MIX_I
MIX_I

CE

TO MICROCONTROLLER
CHIP ENABLE
21
13
14
15
16
17
18
19
20

22
23
24
RLNA RSET
RESISTOR RESISTOR

05351-056
Figure 41. Application Circuit

Rev. E | Page 30 of 47
Data Sheet ADF7020

SERIAL INTERFACE
The serial interface allows the user to program the fourteen
32-bit registers using a 3-wire interface (SCLK, SDATA, and
SLE). Signals should be CMOS compatible. The serial interface
is powered by the regulator and, therefore, is inactive when CE
is low.
Data is clocked into the register, MSB first, on the rising edge
of each clock (SCLK). Data is transferred to one of fourteen
latches on the rising edge of SLE. The destination latch is
determined by the value of the four control bits (C4 to C1).
These are the bottom four LSBs, DB3 to DB0, as shown in the
timing diagram in Figure 3.
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and setting the readback enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin (see Figure 42), starting with the MSB first. The
data appearing at the first clock cycle following the latch
operation must be ignored. The last (eighteenth) SCLK edge
puts the SREAD pin back in three-state.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprising Bit RV1 to Bit RV16 and is scaled according to the
following formula:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215
In the absence of frequency errors, the FREQ_RB value is equal
to the IF frequency of 200 kHz. Note that, for the AFC readback
to yield a valid result, the down-converted input signal must not
fall outside the bandwidth of the analog IF filter. At low input
signal levels, the variation in the readback value can be improved
by averaging.
RSSI Readback
The RSSI readback operation yields valid results in Rx mode
with ASK or FSK signals. The format of the readback word is
shown in Figure 42. It comprises the RSSI level information
(Bit RV1 to Bit RV7), the current filter gain (FG1, FG2), and the
current LNA gain (LG1, LG2) setting. The filter and LNA gain
are coded in accordance with the definitions in Register 9. With
the reception of ASK modulated signals, averaging of the
measured RSSI values improves accuracy. The input power can
be calculated from the RSSI readback value as outlined in the
RSSI/AGC section.
Battery Voltage/ADCIN/Temperature Sensor Readback
These three ADC readback values are valid by just enabling the
ADC in Register 8 without writing to the other registers. The
battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV1 to Bit RV7. This also
applies for the readback of the voltage at the ADCIN pin and
the temperature sensor. From the readback information, the
battery, ADCIN voltage or temperature can be obtained using
VBATTERY = (BATTERY_VOLTAGE_READBACK)/21.1
VADCIN = (ADCIN_VOLTAGE_READBACK)/42.1
Temperature = −40°C + (68.4 −
TEMPERATURE_SENSOR_READBACK) × 9.32
Silicon Revision Readback
The silicon revision word is coded with four quartets in BCD
format. The product code (PC) is coded with three quartets
extending from Bit RV5 to Bit RV16. The revision code (RV) is
coded with one quartet extending from Bit RV1 to Bit RV4. The
product code for the ADF7020 should read back as PC = 0x200.
The current revision code should read as RV = 0x8.
Filter Calibration Readback
The filter calibration readback word is contained in Bit RV1 to
Bit RV8 and is for diagnostic purposes only. Using the automatic
filter calibration function, accessible through Register 6, is
recommended. Before filter calibration is initiated, decimal 32
should be read back as the default value.

READBACK MODE READBACK VALUE

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AFC READBACK RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1

RSSI READBACK X X X X X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1

BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK X X X X X X X X X RV7 RV6 RV5 RV4 RV3 RV2 RV1

SILICON REVISION RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
05351-039

FILTER CAL READBACK 0 0 0 0 0 0 0 0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1

Figure 42. Readback Value Table

Rev. E | Page 31 of 47
ADF7020 Data Sheet

REGISTERS
REGISTER 0—N REGISTER
ENABLE
Tx/Rx
ADDRESS
PLL

MUXOUT 8-BIT INTEGER-N 15-BIT FRACTIONAL-N BITS

DB31

DB30

DB29

PLE1 DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(0)

C2(0)

C1(0)
M15

M14

M13

M12

M11

M10
TR1
M3

M2

M1

M9

M8

M7

M6

M5

M4

M3

M2

M1
N8

N7

N6

N5

N4

N3

N2

N1
TRANSMIT/ FRACTIONAL
TR1 RECEIVE M15 M14 M13 . M3 M2 M1 DIVIDE RATIO
0 TRANSMIT 0 0 0 . 0 0 0 0
1 RECEIVE 0 0 0 . 0 0 1 1
0 0 0 . 0 1 0 2
PLE1 PLL ENABLE
. . . . . . . .
0 PLL OFF . . . . . . . .
1 PLL ON . . . . . . . .
M3 M2 M1 MUXOUT 1 1 1 . 1 0 0 32,764
1 1 1 . 1 0 1 32,765
0 0 0 REGULATOR READY (DEFAULT) 1 1 1 . 1 1 0 32,766
0 0 1 R DIVIDER OUTPUT 1 1 1 . 1 1 1 32,767
0 1 0 N DIVIDER OUTPUT
0 1 1 DIGITAL LOCK DETECT
1 0 0 ANALOG LOCK DETECT
1 0 1 THREE-STATE
1 1 0 PLL TEST MODES
1 1 1 Σ-∆ TEST MODES

N COUNTER
N8 N7 N6 N5 N4 N3 N2 N1 DIVIDE RATIO
0 0 0 1 1 1 1 1 31
0 0 1 0 0 0 0 0 32
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
1 1 1 1 1 1 0 1 253

1 1 1 1 1 1 1 0 254

05351-040
1 1 1 1 1 1 1 1 255

Figure 43. Register 0—N Register

Register 0—N Register Comments

 The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and controls the state of the internal Tx/Rx switch.
XTAL FRACTIONAL _ N
 f OUT   ( INTEGER _ N  )
R 215
 If operating in 433 MHz band, with the VCO band bit set, the desired frequency, fOUT, should be programmed to be twice the desired
operating frequency, due to removal of the divide-by-2 stage in the feedback path.

Rev. E | Page 32 of 47
Data Sheet ADF7020
REGISTER 1—OSCILLATOR/FILTER REGISTER

IF FILTER BW

VCO BAND
CURRENT

DOUBLER
ENABLE
ADJUST

XOSC

XTAL
CLOCKOUT ADDRESS

VCO

CP
VCO BIAS DIVIDE R COUNTER BITS

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(0)

C2(0)

C1(1)
VA2

VA1

VB4

VB3

VB2

VB1

CP2

CP1

CL4

CL3

CL2

CL1
IR2

IR1

D1

R3

R2

R1
V1

X1
FREQUENCY X1 XTAL OSC RF R COUNTER
VA2 VA1 OF OPERATION 0 OFF R3 R2 R1 DIVIDE RATIO
0 0 850 TO 920 1 ON 0 0 1 1
0 1 860 TO 930 0 1 0 2
1 0 870 TO 940 . . . .
1 1 880 TO 950 VCO Band . . . .
V1 (MHz)
. . . .
0 862 TO 956 1 1 1 7
1 431 TO 478
VCO BIAS
VB4 VB3 VB2 VB1 CURRENT
XTAL
0 0 0 0 0.125mA
D1 DOUBLER
0 0 0 1 0.375mA
0 DISABLE
0 0 1 0 0.625mA ENABLED
1
. . . .
1 1 1 1 3.875mA
CLKOUT
CL4 CL3 CL2 CL1 DIVIDE RATIO
FILTER 0 0 0 0 OFF
CP2 CP1 ICP (mA)
IR2 IR1 BANDWIDTH 0 0 0 1 2
0 0 100kHz 0 0 0.3 0 0 1 0 4
0 1 150kHz 0 1 0.9 . . . . .
1 0 200kHz 1 0 1.5 . . . . .

05351-041
1 1 NOT USED 1 1 2.1 . . . . .
1 1 1 1 30

Figure 44. Register 1—Oscillator/Filter Register

Register 1—Oscillator/Filter Register Comments

 The VCO Adjust Bits R1_DB[20:21] should be set to 0 for operation in the 862 MHz to 870 MHz band and set to 3 for operation in
the 902 MHz to 928 MHz band.
 The VCO bias setting should be 0xA for operation in the 862 MHz to 870 MHz and 902 MHz to 928 MHz bands. All VCO gain
numbers are specified for these VCO Adjust and Bias settings.

Rev. E | Page 33 of 47
ADF7020 Data Sheet
REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)

UNTIL LOCK
COUNTER

MUTE PA

ENABLE
INVERT
TxDATA

INDEX
GFSK MOD MODULATION ADDRESS

PA
PA BIAS CONTROL MODULATION PARAMETER POWER AMPLIFIER SCHEME BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(0)

C2(1)

C1(0)
MC3

MC2

MC1

MP1
PA2

PA1

PE1
DI1

IC2

IC1

D9

D8

D7

D6

D5

D4

D3

D2

D1

P6

P5

P4

P3

P2

P1

S3

S2

S1
PE1 POWER AMPLIFIER

IC2 IC1 MC3 MC2 MC1 0 OFF

1 ON
X X X X X

MUTE PA UNTIL
DI1 MP1 LOCK DETECT HIGH
0 TxDATA 0 OFF
1 TxDATA 1 ON

PA2 PA1 PA BIAS S3 S2 S1 MODULATION SCHEME

0 0 5µA 0 0 0 FSK
0 1 7µA 0 0 1 GFSK
1 0 9µA 0 1 0 ASK
1 1 11µA 0 1 1 OOK
1 1 1 GOOK

POWER AMPLIFIER OUTPUT LOW LEVEL POWER AMPLIFIER OUTPUT HIGH LEVEL
D6 D5 . D2 D1 P6 . . P2 P1
X X . X X OOK MODE 0 . . X X PA OFF
0 X . X X PA OFF 0 . . 0 0 –16.0dBm
0 0 . 0 0 –16.0dBm 0 . . 0 1 –16 + 0.45dBm
0 0 . 0 1 –16 + 0.45dBm 0 . . 1 0 –16 + 0.90dBm
0 . . 1 0 –16 + 0.90dBm . . . . . .

05351-042
. . . . . . . . . . . .
. . . . . . 1 1 . 1 1 13dBm
1 1 . 1 1 13dBm

Figure 45. Register 2—Transmit Modulation Register (ASK/OOK Mode)

Register 2—Transmit Modulation Register (ASK/OOK Mode) Comments

 See the Transmitter section for a description of how the PA bias affects the power amplifier level. The default level is 9 μA.
If maximum power is needed, program this value to 11 μA.
 See Figure 13.
 D7, D8, and D9 are don’t care bits.

Rev. E | Page 34 of 47
Data Sheet ADF7020
REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)

UNTIL LOCK
COUNTER

MUTE PA

ENABLE
INVERT
TxDATA

INDEX
GFSK MOD MODULATION ADDRESS

PA
PA BIAS CONTROL MODULATION PARAMETER POWER AMPLIFIER SCHEME BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(0)

C2(1)

C1(0)
MC3

MC2

MC1

MP1
PA2

PA1

PE1
DI1

IC2

IC1

D9

D8

D7

D6

D5

D4

D3

D2

D1

P6

P5

P4

P3

P2

P1

S3

S2

S1
PE1 POWER AMPLIFIER

IC2 IC1 MC3 MC2 MC1 0 OFF

1 ON
X X X X X

MUTE PA UNTIL
DI1 FOR FSK MODE, MP1 LOCK DETECT HIGH
0 TxDATA D9 . D3 D2 D1 F DEVIATION
0 OFF
1 TxDATA 0 . 0 0 0 PLL MODE 1 ON
0 . 0 0 1 1 × fSTEP
0 . 0 1 0 2 × fSTEP
PA2 PA1 PA BIAS 0 . 0 1 1 3 × fSTEP
. . . . . . S3 S2 S1 MODULATION SCHEME
0 0 5µA 1 . 1 1 1 511 × fSTEP 0 0 0 FSK
0 1 7µA 0 0 1 GFSK
1 0 9µA 0 1 0 ASK
1 1 11µA 0 1 1 OOK
1 1 1 GOOK

POWER AMPLIFIER OUTPUT LEVEL

P6 . . P2 P1
0 . . X X PA OFF
0 . . 0 0 –16.0dBm
0 . . 0 1 –16 + 0.45dBm
0 . . 1 0 –16 + 0.90dBm

05351-043
. . . . . .
. . . . . .
1 1 . 1 1 13dBm

Figure 46. Register 2—Transmit Modulation Register (FSK Mode)

Register 2—Transmit Modulation Register (FSK Mode) Comments

 fSTEP = PFD/214.
 When operating in the 431 MHz to 478 MHz band, fSTEP = PFD/215.
 PA bias default = 9 μA.

Rev. E | Page 35 of 47
ADF7020 Data Sheet
REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)

UNTIL LOCK
COUNTER

MUTE PA

ENABLE
INVERT
TxDATA

INDEX
GFSK MOD MODULATION ADDRESS

PA
PA BIAS CONTROL MODULATION PARAMETER POWER AMPLIFIER SCHEME BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(0)

C2(1)

C1(0)
MC3

MC2

MC1

MP1
PA2

PA1

PE1
DI1

IC2

IC1

D9

D8

D7

D6

D5

D4

D3

D2

D1

P6

P5

P4

P3

P2

P1

S3

S2

S1
D7 . D3 D2 D1 DIVIDER_FACTOR PE1 POWER AMPLIFIER
0 . 0 0 0 INVALID 0 OFF
0 . 0 0 1 1 1 ON
0 . 0 1 0 2
0 . 0 1 1 3
. . . . . . MUTE PA UNTIL
DI1 1 . 1 1 1 127 MP1 LOCK DETECT HIGH
0 TxDATA 0 OFF
1 TxDATA 1 ON

PA2 PA1 PA BIAS GAUSSIAN – OOK S3 S2 S1 MODULATION SCHEME

D9 D8 MODE
0 0 5µA 0 0 0 FSK
0 1 7µA 0 0 NORMAL MODE 0 0 1 GFSK
1 0 9µA 0 1 OUTPUT BUFFER ON 0 1 0 ASK
1 1 11µA 1 0 BLEED CURRENT ON 0 1 1 OOK
1 1 BLEED/BUFFER ON 1 1 1 GOOK

IC2 IC1 INDEX_COUNTER

0 0 16 POWER AMPLIFIER OUTPUT LEVEL
0 1 32 P6 . . P2 P1
1 0 64 0 . . X X PA OFF
1 1 128 0 . . 0 0 –16.0dBm
0 . . 0 1 –16 + 0.45dBm
0 . . 1 0 –16 + 0.90dBm
. . . . . .
MC3 MC2 MC1 GFSK_MOD_CONTROL . . . . . .
0 0 0 0 1 1 . 1 1 13dBm
0 0 1 1

05351-044
. . . .
1 1 1 7

Figure 47. Register 2—Transmit Modulation Register (GFSK/GOOK Mode)

Register 2—Transmit Modulation Register (GFSK/GOOK Mode) Comments

 GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/212.
 When operating in the 431 MHz to 478 MHz band, GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/213.
 Data Rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR).
 PA Bias default = 9 μA.

Rev. E | Page 36 of 47
Data Sheet ADF7020
REGISTER 3—RECEIVER CLOCK REGISTER

CLOCK DIVIDE

CLOCK DIVIDE
BB OFFSET
DEMOD
ADDRESS
SEQUENCER CLOCK DIVIDE CDR CLOCK DIVIDE BITS

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(0)

C2(1)

C1(1)
OK2

OK1

BK2

BK1
SK8

SK7

SK6

SK5

SK4

SK3

SK2

SK1

FS8

FS7

FS6

FS5

FS4

FS3

FS2

FS1
SK8 SK7 . SK3 SK2 SK1 SEQ_CLK_DIVIDE BK2 BK1 BBOS_CLK_DIVIDE
0 0 . 0 0 1 1 0 0 4
0 0 . 0 1 0 2 0 1 8
. . . . . . . 1 x 16
1 1 . 1 1 0 254
1 1 . 1 1 1 255
OK2 OK1 DEMOD_CLK_DIVIDE
0 0 4
0 1 1
1 0 2
1 1 3

FS8 FS7 . FS3 FS2 FS1 CDR_CLK_DIVIDE

0 0 . 0 0 1 1
0 0 . 0 1 0 2
. . . . . . .

05351-045
1 1 . 1 1 0 254
1 1 . 1 1 1 255

Figure 48. Register 3—Receiver Clock Register

Register 3—Receiver Clock Register Comments

 Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where
XTAL
BBOS _ CLK 
BBOS _ CLK _ DIVIDE
 The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where
XTAL
DEMOD _ CLK 
DEMOD _ CLK _ DIVIDE
 Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where
DEMOD _ CLK
CDR _ CLK 
CDR _ CLK _ DIVIDE
Note that this can affect your choice of XTAL, depending on the desired data rate.
 The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to
40 kHz for ASK.
XTAL
SEQ _ CLK 
SEQ _ CLK _ DIVIDE

Rev. E | Page 37 of 47
ADF7020 Data Sheet
REGISTER 4—DEMODULATOR SETUP REGISTER

SYNC WORD MATCH

DEMOD LOCK/

SELECT
DEMOD
ADDRESS
DEMODULATOR LOCK SETTING POSTDEMODULATOR BW BITS
DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DW10 DB15

DW9 DB14

DW8 DB13

DW7 DB12

DW6 DB11

DW5 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(1)

C2(0)

C1(0)
DW4

DW3

DW2

DW1
LM2

LM1

DS2

DS1
DL8

DL7

DL6

DL5

DL4

DL3

DL2

DL1
DEMODULATOR
DS2 DS1 TYPE
0 0 LINEAR DEMODULATOR
0 1 CORRELATOR/DEMODULATOR
1 0 ASK/OOK
1 1 INVALID

DEMOD MODE LM2 LM1 DL8 DEMOD LOCK/SYNC WORD MATCH INT/LOCK PIN
0 0 0 0 SERIAL PORT CONTROL – FREE RUNNING –
1 0 0 1 SERIAL PORT CONTROL – LOCK THRESHOLD –
2 0 1 0 SYNC WORD DETECT – FREE RUNNING OUTPUT
3 0 1 1 SYNC WORD DETECT – LOCK THRESHOLD OUTPUT
4 1 0 X INTERRUPT/LOCK PIN LOCKS THRESHOLD INPUT
5 1 1 DL8 DEMOD LOCKED AFTER DL8–DL1 BITS –

MODE5 ONLY

DL8 DL7 . DL3 DL2 DL1 LOCK_THRESHOLD_TIMEOUT

. 0 0 0
0 0 0
. 0 1 1
0 0 0
. 1 0 2
0 0 0
. . . .
. . .

05351-046
. 1 0 254
1 1 1
1 1 1 1 1 255

Figure 49. Register 4—Demodulator Setup Register

Register 4—Demodulator Setup Register Comments

 Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to
allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints greater than 7, when using the linear
demodulator.
211  π  fCUTOFF
 POSTDEMOD_BW =
DEMOD_CLK
where the cutoff frequency (fCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate.
 For Mode 5, Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK
where SEQ_CLK is defined in the Register 3—Receiver Clock Register section.

Rev. E | Page 38 of 47
Data Sheet ADF7020
REGISTER 5—SYNC BYTE REGISTER

TOLERANCE

SYNC BYTE
MATCHING

LENGTH
CONTROL
SYNC BYTE SEQUENCE BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(1)

C2(0)

C1(1)
MT2

MT1

PL2

PL1
SYNC BYTE
PL2 PL1 LENGTH
0 0 12 BITS
0 1 16 BITS
1 0 20 BITS
1 1 24 BITS

MATCHING
MT2 MT1 TOLERANCE
0 0 0 ERRORS
0 1 1 ERROR

05351-047
1 0 2 ERRORS
1 1 3 ERRORS

Figure 50. Register 5—Sync Byte Register

Register 5—Sync Byte Register Comments

 Sync byte detect is enabled by programming Bits R4_DB[25:23] to 010 or 011.
 This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK
pin goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine
data bits.
 The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte
detection hardware.
 Choose a sync byte pattern that has good autocorrelation properties, for example, 0x123456.

Rev. E | Page 39 of 47
ADF7020 Data Sheet
REGISTER 6—CORRELATOR/DEMODULATOR REGISTER

LNA MODE
LINEARITY
IF FILTER

PRODUCT
CURRENT
RxDATA
INVERT

MIXER
Rx ADDRESS

DOT
LNA
CAL
RESET IF FILTER DIVIDER DISCRIMINATOR BW BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

TD10 DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(0)

C3(1)

C2(1)

C1(0)
ML1

LG1
CA1

DP1
FC9

FC8

FC7

FC6

FC5

FC4

FC3

FC2

FC1

TD9

TD8

TD7

TD6

TD5

TD4

TD3

TD2

TD1
RI1

LI2

LI1
CA1 FILTER CAL DP1 DOT PRODUCT
0 NO CAL 0 CROSS PRODUCT
1 CALIBRATE 1 DOT PRODUCT

ML1 MIXER LINEARITY LG1 LNA MODE

0 DEFAULT 0 DEFAULT
RxDATA 1 HIGH 1 REDUCED GAIN
RI1 INVERT
0 RxDATA LI2 LI1 LNA BIAS
1 RxDATA 0 0 800µA (DEFAULT)

RxRESET
FILTER CLOCK
0 NORMAL OPPERATION FC9 . FC6 FC5 FC4 FC3 FC2 FC1 DIVIDE RATIO
1 DEMOD RESET
0 . 0 0 0 0 0 1 1
0 . 0 0 0 0 1 0 2
. . . . . . . . .
. . . . . . . . .
RxRESET . . . . . . . . .
0 NORMAL OPPERATION . . . . . . . . .
1 CDR RESET 1 . 1 1 1 1 1 1 511

05351-048
Figure 51. Register 6—Correlator/Demodulator Register

Register 6—Correlator/Demodulator Register Comments

 See the FSK Correlator/Demodulator section for an example of how to determine register settings.
 Nonadherence to correlator programming guidelines results in poorer sensitivity.
 The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The
formula is XTAL/FILTER_CLOCK_DIVIDE.
 The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is
set high.
 DISCRIMINATOR_BW = (DEMOD_CLK × K)/(800 × 103). See the FSK Correlator/Demodulator section. Maximum value = 600.
 When LNA mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when
linearity is a concern. See Table 5 for details of the different Rx modes.

Rev. E | Page 40 of 47
Data Sheet ADF7020
REGISTER 7—READBACK SETUP REGISTER
READBACK ADC CONTROL
SELECT MODE BITS

DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RB3 RB2 RB1 AD2 AD1 C4(0) C3(1) C2(1) C1(1)

RB3 READBACK AD2 AD1 ADC MODE

0 DISABLED 0 0 MEASURE RSSI
1 ENABLED 0 1 BATTERY VOLTAGE
1 0 TEMP SENSOR
1 1 TO EXTERNAL PIN
RB2 RB1 READBACK MODE
0 0 AFC WORD
0 1 ADC OUTPUT

05351-049
1 0 FILTER CAL
1 1 SILICON REV

Figure 52. Register 7—Readback Setup Register

Register 7—Readback Setup Register Comments

 Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or
the voltage at the external pin in Rx mode, AGC function in Register 9 must be disabled. To read back these parameters in Tx mode,
the ADC must first be powered up using Register 8 because this is off by default in Tx mode to save power. This is the recommended
method of using the battery readback function because most configurations typically require AGC.
 Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.
 See the Readback Format section for more information.

Rev. E | Page 41 of 47
ADF7020 Data Sheet
REGISTER 8—POWER-DOWN TEST REGISTER

SWITCH ENABLE
INTERNAL Tx/Rx
PA ENABLE

LNA/MIXER
Rx MODE

ENABLE

ENABLE

ENABLE

ENABLE

ENABLE

ENABLE
DEMOD

FILTER

SYNTH
LOG AMP/ CONTROL

VCO
ADC
RSSI BITS

DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

PD7 SW1 LR2 LR1 PD6 PD5 PD4 PD3 PD2 PD1 C4(1) C3(0) C2(0) C1(0)

PD7 PA (Rx MODE) PLE1 LOOP

0 PA OFF (FROM REG 0) PD2 PD1 CONDITION
1 PA ON 0 0 0 VCO/PLL OFF
0 0 1 PLL ON
0 1 0 VCO ON
SW1 Tx/Rx SWITCH 0 1 1 PLL/VCO ON
0 DEFAULT (ON) 1 X X PLL/VCO ON
1 OFF

LR2 LR1 RSSI MODE PD3 LNA/MIXER ENABLE

X 0 RSSI OFF 0 LNA/MIXER OFF
X 1 RSSI ON 1 LNA/MIXER ON

PD6 DEMOD ENABLE PD4 FILTER ENABLE

0 DEMOD OFF 0 FILTER OFF
1 DEMOD ON 1 FILTER ON

PD5 ADC ENABLE

05351-050
0 ADC OFF
1 ADC ON

Figure 53. Register 8—Power-Down Test Register

Register 8—Power-Down Test Register Comments

 For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.
 It is not necessary to write to this register under normal operating conditions.

Rev. E | Page 42 of 47
Data Sheet ADF7020
REGISTER 9—AGC REGISTER

CONTROL
CURRENT

SEARCH
FILTER

GAIN
DIGITAL FILTER LNA ADDRESS

AGC
TEST IQ GAIN GAIN AGC HIGH THRESHOLD AGC LOW THRESHOLD BITS

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(1)

C3(0)

C2(0)

C1(1)
GC1

GH7

GH6

GH5

GH4

GH3

GH2

GH1
GS1
FG2

FG1

LG2

LG1

GL7

GL6

GL5

GL4

GL3

GL2

GL1
FI1

FI1 FILTER CURRENT GS1 AGC SEARCH AGC LOW

GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD
0 LOW 0 AUTO AGC
1 HIGH 1 HOLD SETTING 0 0 0 0 0 0 1 1
0 0 0 0 0 1 0 2
0 0 0 0 0 1 1 3
FG2 FG1 FILTER GAIN GC1 GAIN CONTROL 0 0 0 0 1 0 0 4
0 0 8 0 AUTO . . . . . . . .
0 1 24 1 USER . . . . . . . .
1 0 72 . . . . . . . .
1 1 INVALID 1 0 0 1 1 1 0 78
1 0 0 1 1 1 1 79
1 0 1 0 0 0 0 80

AGC HIGH
GH7 GH6 GH5 GH4 GH3 GH2 GH1 THRESHOLD
0 0 0 0 0 0 1 1
0 0 0 0 0 1 0 2
0 0 0 0 0 1 1 3
LG2 LG1 LNA GAIN 0 0 0 0 1 0 0 4
0 0 <1 . . . . . . . .
0 1 3 . . . . . . . .
1 0 10 . . . . . . . .
1 0 0 1 1 1 0 78

05351-051
1 1 30
1 0 0 1 1 1 1 79
1 0 1 0 0 0 0 80

Figure 54. Register 9—AGC Register

Register 9—AGC Register Comments

 This register does not need to be programmed in normal operation. Default AGC_LOW_THRESHOLD = 30, default
AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details. Default register setting = 0xB2 31E9.
 AGC high and low settings must be more than 30 apart to ensure correct operation.
 LNA gain of 30 is available only if LNA mode, R6_DB15, is set to 0.

Rev. E | Page 43 of 47
ADF7020 Data Sheet
REGISTER 10—AGC 2 REGISTER

GAIN/ATTENUATE
RESERVED
SELECT

SELECT
I/Q PHASE ADDRESS
I/Q

I/Q
ADJUST I/Q GAIN ADJUST AGC DELAY LEAK FACTOR PEAK RESPONSE BITS
SIQ2 DB28

DB27

DB26

DB25

DB24

DB23

SIQ1 DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(1)

C3(0)

C2(1)

C1(0)
GC5

GC4

GC3

GC2

GC1

GL7

GL6

GL5

GL4
UD1

DH4

DH3

DH2

DH1
PH4

PH3

PH2

PH1

PR4

PR3

PR2

PR1
R1

IF DB21 = 0, THEN GAIN

IS SELECTED.
IF DB21 = 1, THEN DEFAULT = 0xA
ATTENUATE IS SELECTED
DEFAULT = 0xA DEFAULT = 0x2
SIQ2 SELECT IQ SIQ2 SELECT IQ

05351-052
0 PHASE TO I CHANNEL 0 GAIN TO I CHANNEL
1 PHASE TO Q CHANNEL 1 GAIN TO Q CHANNEL

Figure 55. Register 10—AGC 2 Register

Register 10—AGC 2 Register Comments

 This register is not used under normal operating conditions.
 For ASK/OOK modulation, the recommended settings for operation over the full input range are peak response = 2, leak factor = 10
(default), and AGC delay =10 (default). Bit DB31 to Bit DB16 should be cleared. For bit-rates below 4 kbps the AGC_WAIT_TIME
can be increased by setting the AGC_DELAY to 15. The SEQ_CLK should also be set at a minimum.

REGISTER 11—AFC REGISTER

DB20 AFC ENABLE

CONTROL
AFC SCALING COEFFICIENT BITS
DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(1)

C3(0)

C2(1)

C1(1)
AE1

M16

M15

M14

M13

M12

M11

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1

INTERNAL
AE1 AFC
05351-053

0 OFF
1 ON

Figure 56. Register 11—AFC Register

Register 11—AFC Register Comments

 See the Internal AFC section to program the AFC scaling coefficient bits.
 The AFC scaling coefficient bits can be programmed using the following formula:
AFC_SCALING_COEFFICIENT = Round((500 × 224)/XTAL)

Rev. E | Page 44 of 47
Data Sheet ADF7020
REGISTER 12—TEST REGISTER
DB31 PRESCALER

OSC TEST

COUNTER
SOURCE
LD HIGH

RESET
FORCE
ANALOG TEST DIGITAL Σ-∆ ADDRESS
MUX MANUAL FILTER CAL TEST MODES TEST MODES PLL TEST MODES BITS
DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(1)

C3(1)

C2(0)

C1(0)
PRE

QT1

CS1

SF6

SF5

SF4

SF3

SF2

SF1

CR1

T9

T8

T7

T6

T5

T4

T3

T2

T1
P PRESCALER DEFAULT = 32. INCREASE CR1 COUNTER RESET
0 4/5 (DEFAULT) NUMBER TO INCREASE BW 0 DEFAULT
1 8/9 IF USER CAL ON 1 RESET

CS1 CAL SOURCE

05351-054
0 INTERNAL
1 SERIAL IF BW CAL

Figure 57. Register 12—Test Register

Register 12—Test Register Comments Programming the test register, Register 12, enables the test DAC. In
This register does not need to be written to in normal operation. correlator mode, this can be done by writing to Digital Test
The default test mode is 0x0000 000C, which puts the part in Mode 7 or 0x0001C00C.
normal operation. To view the test DAC output when using the linear demodu-
Using the Test DAC on the ADF7020 to Implement lator, the user must remove a fixed offset term from the signal
Analog FM Demodulation and Measuring of SNR using Register 13. This offset is nominally equal to the IF
frequency. The user can determine the value to program by
The test DAC allows the output of the postdemodulator filter
using the frequency error readback to determine the actual IF
for both the linear and correlator/demodulators (see Figure 30
and then programming half this value into the offset removal
and Figure 31) to be viewed externally. It takes the 16-bit filter
field. It also has a signal gain term to allow the usage of the
output and converts it to a high frequency, single-bit output
maximum dynamic range of the DAC.
using a second-order Σ-Δ converter. The output can be viewed
on the CLKOUT pin. This signal, when filtered appropriately, Setting Up the Test DAC
can then be used to  Digital test modes = 7: enables the test DAC, with no offset
 Monitor the signals at the FSK/ASK postdemodulator filter removal (0x0001 C00C).
output. This allows the demodulator output SNR to be  Digital test modes = 10: enables the test DAC, with offset
measured. Eye diagrams can also be constructed of the removal (needed for linear demodulation only, 0x02 800C).
received bit stream to measure the received signal quality. The output of the active demodulator drives the DAC, that is, if
 Provide analog FM demodulation. the FSK correlator/demodulator is selected, the correlator filter
While the correlators and filters are clocked by DEMOD_CLK, output drives the DAC.
CDR_CLK clocks the test DAC. Note that although the test The evaluation boards for the ADF7020 contain land patterns
DAC functions in a regular user mode, the best performance is for placement of an RC filter on the CLKOUT line. This is
achieved when the CDR_CLK is increased up to or above the typically designed so that the cut-off frequency of the filter is
frequency of DEMOD_CLK. The CDR block does not function above the demodulated data rate.
when this condition exists.

Rev. E | Page 45 of 47
ADF7020 Data Sheet
REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER
PULSE CONTROL
TEST DAC GAIN TEST DAC OFFSET REMOVAL EXTENSION KI KP BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4(1)

C3(1)

C2(0)

C1(1)
PE4

PE3

PE2

PE1
KI DEFAULT = 3 KP DEFAULT = 2

PE4 PE3 PE2 PE1 PULSE EXTENSION

0 0 0 0 NORMAL PULSE WIDTH
0 0 0 1 2 × PULSE WIDTH
0 0 1 0 3 × PULSE WIDTH
. . . . .

05351-055
. . . . .
. . . . .
1 1 1 1 16 × PULSE WIDTH

Figure 58. Register 13—Offset Removal and Signal Gain Register

Register 13—Offset Removal and Signal Gain Register Comments

 Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low
signal. The offset can be removed, up to a maximum of 1.0, and gained to use the full dynamic range of the DAC:
DAC_INPUT = (2TEST_DAC_GAIN) × (Signal − TEST_DAC_OFFSET_REMOVAL/4096)
 Ki (default) = 3. Kp (default) = 2.

Rev. E | Page 46 of 47
Data Sheet ADF7020

OUTLINE DIMENSIONS
7.00 0.30
BSC SQ 0.23
PIN 1 0.18 PIN 1
INDICATOR INDICATOR
37 48
36 1

0.50
BSC EXPOSED 4.25
PAD
4.10 SQ
3.95

25 12
24 13
0.45 0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF

08-16-2010-B
PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.

Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

7 mm × 7 mm Body, Very Very Thin Quad
(CP-48-5)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option2
ADF7020BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-48-5
ADF7020BCPZ-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-48-5
EVAL-ADF70xxMBZ2 Evaluation Platform
EVAL-ADF7020DBZ1 902 MHz to 928 MHz Daughter Board
EVAL-ADF7020DBZ2 860 MHz to 870 MHz Daughter Board
EVAL-ADF7020DBZ3 430 MHz to 445 MHz Daughter Board
1
Z = RoHS Compliant Part.
2
Formerly CP-48-3 package.

©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05351-0-9/16(E)

Rev. E | Page 47 of 47