A B C D E

1 1

2
Compal Confidential 2

VIWZ1/VIWZ2 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N14P-GV2

2012-12-26
3 3

LA-9063P
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 1 of 62
A B C D E
 A B C D E

U4 HM76@ U4 HM70@ ZZZ 14@

Compal confidential VIWZ1
LA9063
File Name : VIWZ1/VIWZ2 LS9061P PWR/B
PCH-HM76
SA00005FH70
PCH-HM70
SA00005MQ80
DA_PCB
DA8000XJ000
LS9062P USB/B
Page23-32 ZZZ6 15@

LA9063
1
nVIDIA N14P-GV2 VIWZ2 1

DA_PCB
DA8000XJ100 LS9065P PWR/B
VRAM 128Mb*16 Intel LS9062P USB/B
DDR3*4 1GB LS9063P ODD/B
Ivy Bridge LS9064P LED/B
PCI-E x8 DDR3 SO-DIMM *2
VRAM 256Mb*16 Socket-rPGA988B BANK 0, 1, 2, 3
DDR3*4 2GB 37.5mm*37.5mm
Page12-13

Dual Channel Up to 8GB

HDMI Page35 Page5-11DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
Connector DDR3 1600MHz(1.5V)
100MHz
Page34 2.7GT/s FDI *8 DMI *4
CRT
2 Connector Intel Audio Codec 2 channel speaker Page41
2

Page33 AZALIA Realtek

LVDS LVDS Panther Point ALC259-VC2
Int. Digital MIC array
Page41
Connector eDP HM70 / HM76 (Combine with webcam)
Page41
Page45 USB 3.0 FCBGA 989 Combo Jack*1 Page43
USB2.0 25mm*25mm USB2.0 *14
USB3.0 *1(Left) Camera Conn.Page33
include USB2.0*1 PCI-E x1 *6
SATA *6 BlueTooth Conn.
Page40
Page14-22
SPIROM
BIOS Page14
3 LPC BUS Card Reader Page44 3

Realtek
Page42 Reltek
RTL8111F(GLAN) EC RTS5178 for SDR50
SDXC/MMC
RTL8105E-VD(10/100) ENE KB9012
Page37

RJ-45 Page38 USB2.0 *2(Right)

Page 43
Connector Touch Pad Int. KBD
Page43
Page43
PCI-E(WLAN)
Mini PCIE Full size Slot *1
Mini PCIE Half size Slot *1 Thermal Sensor SSD Page36

EMC1403 Page39
WLAN Page36
SATA HDD
4 Page40 4

SATA ODD Page40

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 2 of 62
A B C D E
 A B C D E

SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+V1.05S_VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 +5VALW +1.5V +VCC_CORE 1
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +VCC_GFXCORE_AXG
+1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
State +0.75VS Vcc 3.3V +/- 5%
Board ID PCB Revision
+1.05VS Ra/Rc/Re 100K +/- 5%
0 LA-9061P 1.0 Board ID Porject Phase
Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1 LA-9061P 0.3 Z-series
0 0 0 V 0 V 0 V MP
2 LA-9061P 0.2 Z-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
3 LA-9061P 0.1 Z-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
4 LA-9063P 0.2 Z-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
S0
5 LA-9063P 0.2 15_TS Re-flash
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
6 Reserved
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
7 Reserved
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
S3 Reserved
O O O X 7 NC 2.500 V 3.300 V 3.300 V MP

S5 S4/AC O O USB Port Table BOM Structure Table

X X
3 External BTO Item BOM Structure
2 USB 2.0 Port USB Port 2
S5 S4/ Battery only O GPU:N14P-GV2 GV2@
X X X
0 USB Port (Left Side) USB3.0 OPTIMUS part OPT@
EHCI1 UHCI0
S5 S4/AC & Battery 1 Touch Screen integrate Graphic part UMA@
don't exist X X X X USB3.0 2 Blue Tooth GPU:N14P-GV2 Strap GV2@
Address UHCI1
EC SM Bus1 address EC SM Bus2 address 3 Camera GPU:N14P-GV2 GC6 function GC6@
4 OPTIMUS no support GCLK OPTNOGCLK@
UHCI2
Device Device Address 5 OPTIMUS support GCLK OPTGCLK@
Smart Battery 0001 011X b Thermal Sensor EMC1403 1001_101xb
EHCI1
6 Support Green CLK GCLK@
USB Charger 1010 111X b
UHCI3
7 not Support Green CLK NOGCLK@
8 USB Port (Right Side USB-BD) Support Green CLK 244 GCLK244@
PCH SM Bus address UHCI4
9 USB Port (Right Side USB-BD) Support Green CLK 304 GCLK304@
Device Address 10 Mini Card(WLAN) Cardreader CR@
DDR DIMM0 1001 000Xb
EHCI2 UHCI5
11 Card Reader Support HP Woofer woofer@
DDR DIMM2 1001 010Xb 12 Gastube Gastube@
UHCI6
13 EC RESET function RESET@
NV-GPU SM Bus address HDMI HDMI@
BlueTooth BT@
Device Address Connector ME@
3 3

Internal thermal sensor 1001 111Xb (0x9E)

45 LEVEL 45@
10/100 LAN 8105@
GIGA LAN GIGA@
Deep Sleep S3 DS3@
SMBUS Control Table GPU BOM Structure Table Not Support Deep Sleep S3 NODS3@
ISCT AOAC@
Thermal BOM Structure N14P-GV2
WLAN Sensor PCH TP ISCT not support NOAOAC@
SOURCE VGA BATT KB9012 SODIMM WWAN OPT@ V
Camera CMOS@
OPTNOGCLK@ V
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X X GV2@ V
For Z490 (14")
For Z590 (15")
14@
15@
+3VALW
GC6@ Select
SMB_EC_CK2
SMB_EC_DA2
KB9012 X X X X X X V
+3VS
X Unpop
USB Charger
@
CHG@
+3VALW
SMBCLK
SMBDATA
PCH
+3VALW
X X X V
+3VS
V
+3VS
X X V
+3VS
not USBCharger
Keyboard Back Light
NOCHG@
KBL@
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X X Touch Screen
HM76 by PCH
TS@
HM76@
SML1CLK
4 SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X V
+3VS
X X HM70 by PCH
Cardreader RTS5178
HM70@
RTS5178@ 4

Cardreader RTS5170 RTS5170@

for 14" Touch Screen TS_14@
for 15" Touch Screen TS_15@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 3 of 62
A B C D E
 5 4 3 2 1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13x GPIO) Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 I H GC6_FB_CLAMP Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

D D
GPIO1 OUT - MEM_VDD_CTL N13P-GL
64bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1GB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) GDDR3

GPIO3 OUT H Panel Power Enable

Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO4 OUT H Panel Back-Light On/Off (PWM)
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG/PCI_DEVID[5] PEX_PLL_EN_TERM
GPIO5 OUT - RESERVED ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO6 OUT L GC6_FB_REQ
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO7 OUT - 3DVision STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO8 I/O L Thermal Catastrophic Over Temperature
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO9 OUT L Thermal Alert STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO10 OUT - Memory VREF Control

GPIO11 OUT - PWM_VID

C C

GPIO12 IN AC Power Detect Input (10K pull low)

GPIO13 OUT - PSI

GPIO14 OUT N/A

GPIO15 IN

GPIO16 OUT N/A

GPIO17 IN N/A

GPIO18 IN

GPIO19 IN N/A

B
+3VS_VGA B

+VGA_CORE

tNVVDD >0
+1.5VS_VGA
tFBVDDQ >0

+1.05VS_VGA
tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A A

Tpower-off <10ms

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title
1.all GPU power rails should be turned off within 10ms
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 4 of 62
5 4 3 2 1
 5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
+V1.05S_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils

1
R1
- typical impedance = 14.5 mohms
D D
24.9_0402_1%

JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
<16> DMI_CRX_PTX_N1 B25
A25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
<16> DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N14
B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N13
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
<16> DMI_CRX_PTX_P1 B26 J35 PCIE_CRX_GTX_N12 PEG Static Lane Reversal - CFG2 is for the 16x
A24 DMI_RX[1] PEG_RX#[3] J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2

DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PCIE_CRX_GTX_N5 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
G22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
<16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
F20 B33 PCIE_CRX_GTX_N1
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]

PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_CRX_GTX_N0
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] L35 PCIE_CRX_GTX_P14
PEG_RX[1] K34 PCIE_CRX_GTX_P13
A21 PEG_RX[2] H35 PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
C H19 H32 PCIE_CRX_GTX_P11 C
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P4
PEG_RX[11] D34 PCIE_CRX_GTX_P3
A22 PEG_RX[12] E31 PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P1
<16> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
eDP_COMPIO and ICOMPO signals E20 B32 PCIE_CRX_GTX_P0
<16> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
G18
should be shorted near balls <16> FDI_CTX_PRX_P3
B20 FDI0_TX[3] M29 PCIE_CTX_GRX_C_N15 C1 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N[0..15] <23>
and routed with typical <16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N14 C2 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N14
<16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
impedance <25 mohms D19 M31 PCIE_CTX_GRX_C_N13 C3 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N13
<16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PCIE_CTX_GRX_C_N12 C4 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N12
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 PCIE_CTX_GRX_C_N11 C5 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N11
J18 PEG_TX#[4] K31 PCIE_CTX_GRX_C_N10 C6 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N10
+V1.05S_VCCP <16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
<16> FDI_FSYNC1
J17 K28 PCIE_CTX_GRX_C_N9 C7 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N9
FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N8 C8 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N8
H20 PEG_TX#[7] J28 PCIE_CTX_GRX_C_N7 C9 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N7
<16> FDI_INT FDI_INT PEG_TX#[8] H29 PCIE_CTX_GRX_C_N6 C10 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N6
PEG_TX#[9]
1

<16> FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N5

R7 H17 FDI0_LSYNC PEG_TX#[10] E29 PCIE_CTX_GRX_C_N4 C12 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N4
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C13 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N3
PEG_TX#[12] D28 PCIE_CTX_GRX_C_N2 C14 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N2
PEG_TX#[13] F26 PCIE_CTX_GRX_C_N1 C15 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N1
2

PEG_TX#[14] E25 PCIE_CTX_GRX_C_N0 C16 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N0

EDP_COMP A18 PEG_TX#[15]
B eDP_COMPIO PCIE_CTX_GRX_P[0..15] <23> B
A17 M28 PCIE_CTX_GRX_C_P15 C17 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P15
B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_C_P14 C18 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P14
eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_C_P13 C19 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P13
PEG_TX[2] L31 PCIE_CTX_GRX_C_P12 C20 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P12
C15 PEG_TX[3] L28 PCIE_CTX_GRX_C_P11 C21 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P11
D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_C_P10 C22 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P10
eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_C_P9 C23 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P9
eDP

PEG_TX[6] J29 PCIE_CTX_GRX_C_P8 C24 @ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P8

C17 PEG_TX[7] J27 PCIE_CTX_GRX_C_P7 C25 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P7
F16 eDP_TX[0] PEG_TX[8] H28 PCIE_CTX_GRX_C_P6 C26 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P6
C16 eDP_TX[1] PEG_TX[9] G28 PCIE_CTX_GRX_C_P5 C27 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P5
G15 eDP_TX[2] PEG_TX[10] E28 PCIE_CTX_GRX_C_P4 C28 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P4
eDP_TX[3] PEG_TX[11] F28 PCIE_CTX_GRX_C_P3 C29 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P3
C18 PEG_TX[12] D27 PCIE_CTX_GRX_C_P2 C30 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P2
E16 eDP_TX#[0] PEG_TX[13] E26 PCIE_CTX_GRX_C_P1 C31 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P1
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE_CTX_GRX_C_P0 C32 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P0
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

A A

Security Classification Compal Secret Data

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 5 of 62
5 4 3 2 1
 5 4 3 2 1

JCPU1B
R10;R11 put on U4 side
D D
R02
A28 CLK_CPU_DMI_R R10 1 @ 2 0_0402_5%
C26 BCLK A27 CLK_CPU_DMI <15>
CLK_CPU_DMI#_R R11 1 @ 2 0_0402_5%

MISC

CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# R02 CLK_CPU_DMI# <15>

AN34
SKTOCC# A16 R12 2 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK A15 R13 2 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP

T48 H_CATERR# AL33

CATERR#
R9 1
62_0402_5%

THERMAL
AN33 R8 H_DRAMRST#
<42> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

R15

DDR3
MISC
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
<42,48> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 2 R17 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
AN32 DDR3 Compensation Signals
<19> H_THRMTRIP# THERMTRIP#

+V1.05S_VCCP
AP29 XDP_PRDY# T97
PRDY# AP27 XDP_PREQ# T98
PREQ# XDP_TMS R20 2 1 51_0402_5%
AR26 XDP_TCK XDP_TDI R21 2 1 51_0402_5% PU/PD for JTAG signals
C R02 TCK AR27 XDP_TMS XDP_TDO R23 2 @ 1 51_0402_5% C

PWR MANAGEMENT
TMS

JTAG & BPM

R22 1 @ 2 0_0402_5% H_PM_SYNC_R AM34 AP30 XDP_TRST#
<16> H_PM_SYNC PM_SYNC TRST# XDP_TCK 2 1 51_0402_5%
R24
AR28 XDP_TDI XDP_TRST# R25 2 1 51_0402_5%
TDI AP26 XDP_TDO
R26 1 @ 2 0_0402_5% H_CPUPWRGD_R AP33 TDO
<19> H_CPUPWRGD UNCOREPWRGOOD
2

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

DBR# +3VS
R27 1 2 PM_DRAM_PWRGD_R V8
130_0402_5% SM_DRAMPWROK
10K_0402_5%
AT28 XDP_BPM#0 T49
BPM#[0] AR29 XDP_BPM#1 T90
1

BPM#[1] AR30 XDP_BPM#2 T91

BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3 T92
RESET# BPM#[3] AP32 XDP_BPM#4 T93
BPM#[4] AR31 XDP_BPM#5 T94
BPM#[5] AT31 XDP_BPM#6 T95
BPM#[6] AR32 XDP_BPM#7 T96
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
+3VALW

1 Buffered reset to CPU

C33
0.1U_0402_16V7K
+1.5V_CPU_VDDQ
2 +3VS
B B
1

1 @ 2
<16> SYS_PWROK
R880 0_0402_5% R30
U1 200_0402_5% +V1.05S_VCCP
1
C34
5

0.1U_0402_16V7K
2

1 R161 2 1
P

+3VS B 2
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
2 O 75_0402_5%
<16> PM_DRAM_PWRGD A
G

5
74AHC1G09GW_TSSOP5 R34 U2
3

43_0402_1% 1 3V

P
BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
Y 2 PCH_PLTRST#
A PCH_PLTRST# <18>

G
SN74LVC1G07DCKR_SC70-5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 6 of 62
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D
<13> DDR_B_D[0..63]

AB6 AE2
<12> DDR_A_D[0..63] SA_CLK[0] AA6 M_CLK_DDR0 <12> SB_CLK[0] AD2 M_CLK_DDR2 <13>
DDR_A_D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR_B_D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
D C6 SA_DQ[4] SA_CLK[1] AB5 M_CLK_DDR1 <12> A8 SB_DQ[4] SB_CLK[1] AD1 M_CLK_DDR3 <13> D
DDR_A_D5 DDR_B_D5
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
DDR_A_D23 K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> DDR_B_D23 K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR_A_D24 M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> DDR_B_D24 M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
DDR_A_D30 N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> DDR_B_D30 M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
M_ODT1 <12> M_ODT3 <13>

DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5

DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13> C
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
AN11 SA_DQ[48] D4 DDR_A_DQS[0..7] <12> AJ11 SB_DQ[48] C7 DDR_B_DQS[0..7] <13>
DDR_A_D49 DDR_A_DQS0 DDR_B_D49 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
B <12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 B
DDR_A_MA8 DDR_B_MA8
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3
DDR_A_MA9 DDR_B_MA9
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 DDR_A_MA10 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 DDR_A_MA14 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5 DDR_B_MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

+1.5V
1

R37
1K_0402_5%

R38
2

1K_0402_5%
S

H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
2

Q2
R39 LBSS138LT1G_SOT-23-3
G
2

4.99K_0402_1%
1

A A
NODS3@
1 2
<15> DRAMRST_CNTRL_PCH
R40 0_0402_5%
R02 1 @ 2 DRAMRST_CNTRL_R
<10> DRAMRST_CNTRL
R92 0_0402_5%
1 2
<42> DRAMRST_CNTRL_EC
R65 DS3@ 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title
For Deep S3 Eiffel used 0.01u PROCESSOR(3/7) DDRIII
C35
0.047U 16V K X7R 0402
Module design used 0.047u THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 7 of 62

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R41
1K_0402_1%

2
D D

Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

AH27 PAD T13 CFG2
AK28 VCC_DIE_SENSE AH26 R02 R93 1 @ 2 0_0402_5%
socket pin map definition
AK29 CFG[0] VSS_DIE_SENSE
CFG2 AL26 CFG[1]
0:Lane Reversed
CFG4
AL27
AK26
AL29
CFG[2]
CFG[3]
CFG[4] RSVD28
L7
AG7
*
CFG5 CFG4
CFG6 AL30 CFG[5] RSVD29 AE7
CFG[6] RSVD30

1
CFG7 AM31 AK2
AM32 CFG[7] RSVD31
AM30 CFG[8] W8 @ R42

CFG
AM28 CFG[9] RSVD32 1K_0402_1%
+VCC_GFXCORE_AXG AM26 CFG[10]

2
AN28 CFG[11] AT26
+VCC_CORE AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
CFG[14] RSVD35
2

AM27
R252 AK31 CFG[15]
AN29 CFG[16]
49.9_0402_1% CFG[17]
2

Display Port Presence Strap

R253
1

49.9_0402_1% T8
C RSVD37 J16 C
1 : Disabled; No Physical Display Port
VCC_AXG_VAL_SENSE AJ31 RSVD38 H16 CFG4 * attached to Embedded Display Port
1

R82 1 @ 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16

VCC_VAL_SENSE AJ33 VSSAXG_VAL_SENSE RSVD40
R88 1 2 100_0402_1% VSS_VAL_SENSE AH33 VCC_VAL_SENSE
@
VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Need PWR add new circuit on 1.05V(refer CRB) AJ26 AR35
RSVD5 RSVD_NCTF1 AT34

RESERVED
RSVD_NCTF2 AT33
VSS_AXG_VAL_SENSE RSVD_NCTF3 AP35 CFG6
RSVD_NCTF4 AR34
RSVD_NCTF5 CFG5
VSS_VAL_SENSE

1
F25 GV2@ @
F24 RSVD8 R43 R44
RSVD9
2

F23 1K_0402_1% 1K_0402_1%

R255 R257 D24 RSVD10 B34
G25 RSVD11 RSVD_NCTF6 A33
49.9_0402_1% 49.9_0402_1%

2
G24 RSVD12 RSVD_NCTF7 A34
E23 RSVD13 RSVD_NCTF8 B35 for N14P_GV2 GPU 11/13
1

D23 RSVD14 RSVD_NCTF9 C35

C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
INTEL 12/28 recommand RSVD21 RSVD52 PCIE Port Bifurcation Straps
A30
to add RC120, RC121, RC122, RC123 C29 RSVD22
Please place as close as JCPU1 RSVD23
11: (Default) x16 - Device 1 functions 1 and 2 disabled
B J20
RSVD24
BCLK_ITP
BCLK_ITP#
AN35
AM35 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
B18
RSVD25 disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2
2 enabled)
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13

B1 CFG7
KEY

1
@ R45
1K_0402_1%

TYCO_2013620-2_IVY BRIDGE

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 8 of 62
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER +V1.05S_VCCP

+VCC_CORE

QC=94A 8.5A
DC=53A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12

PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44 +V1.05S_VCCP
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
1
CORE SUPPLY

Y34 VCC51
Y33 VCC52 C99
Y32 VCC53 0.1U_0402_16V7K
VCC54

1
Y31 2
Y30 VCC55 R46
Y29 VCC56
VCC57 75_0402_5%
Y28
Y27 VCC58
VR_SVID_CLK series-resistors close to VR

2
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_5%
SVID

V33 VCC62 VIDALERT# AJ30 R02 R48 1 2 0_0402_5% VR_SVID_ALRT# <55>

H_CPU_SVIDCLK @
V32 VCC63 VIDSCLK AJ28 R02 R49 1 2 0_0402_5% VR_SVID_CLK <55>
H_CPU_SVIDDAT @
V31 VCC64 VIDSOUT VR_SVID_DAT <55>
V30 VCC65
V29 VCC66 2 1 130_0402_5%
VCC67
R50 +V1.05S_VCCP 0.1uF on power side
V28
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83

1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
100_0402_1%
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils
SENSE LINES

2
R27 VCC88 AJ35 VCCSENSE_R R02 R52 1 @ 2 0_0402_5%
R26 VCC89 VCC_SENSE AJ34 VSSSENSE_R R02 R53 1 2 0_0402_5% VCCSENSE <55>
@
P35 VCC90 VSS_SENSE VSSSENSE <55>
P34 VCC91
VCC92

1
P33
P32 VCC93 B10 R54
P31 VCC94 VCCIO_SENSE A10 1 VCCIO_SENSE <53>
VSSIO_SENSE_L R74 2VSSIO_SENSE 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO 10_0402_1%
P29 VCC96 @

2
P28 VCC97
VCC98 R74 & R79 put together +V1.05S_VCCP
P27
P26 VCC99 R79
A VCC100 2 1 A
VSSIO_SENSE_L <53>
10_0402_1%

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 9 of 62
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ
@ J1 Q6

1
1 2 D LBSS138LT1G_SOT-23-3
2 DRAMRST_CNTRL
R02 PAD-OPEN 4x4m +VREF_DQ_DIMMA G DRAMRST_CNTRL <7>
R668 1 @ 2 0_0402_5% +VREF_DQ_DIMMB R670@ S

3
<25,46,51,54> SUSP 1 2 0_0402_5%~D +V_DDR_REFA_R
1 2 0_0402_5%~D +V_DDR_REFB_R
U3 R671@
AP4800BGM-HF_SO-8

1
+VSB 8 1 AP4800

1
7 2 D
D 6 3 Id=9.6A DRAMRST_CNTRL 2 R353 R64 D

1
5 G 1K_0402_1% 1K_0402_1%
R56 S @ @

2
82K_0402_5% Q9

4
LBSS138LT1G_SOT-23-3

2
R885 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RUN_ON_CPU1.5VS3 1 2
15K_0402_1% 1

1
D +VCC_GFXCORE_AXG
2 Q4 C97
G 2N7002K_SOT23-3 0.047U_0603_25V7M

1
S 2

3
R616
10_0402_1%

2
VCC_AXG_SENSE <55>

+VCC_GFXCORE_AXG JCPU1G
POWER Q5-orignal part
AP2302GN-HF_SOT23-3
AT24 AK35
SB523020210

SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 +1.5V_CPU_VDDQ
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <55>
AT21
VAXG3

1
AT20
AT18 VAXG4 R626
VAXG5

1
AT17 10_0402_1%
AR24 VAXG6
AR23 VAXG7 R67
+V_SM_VREF should

2
AR21 VAXG8 1K_0402_1%
AR20 VAXG9 have 20 mil trace width

2
AR18 VAXG10 AL1 +V_SM_VREF_CNT
C
AR17 VAXG11 SM_VREF C
VAXG12

1
AP24 1

VREF
AP23 VAXG13
AP21 VAXG14 C98 R78
AP20 VAXG15 B4 +V_DDR_REFA_R 0.1U_0402_16V7K 1K_0402_1%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R 2

2
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21 +1.5V_CPU_VDDQ
AN18 VAXG22

DDR3 -1.5V RAILS

AN17 VAXG23 +1.5V +1.5V_CPU_VDDQ
AM24 VAXG24 AF7

GRAPHICS
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1
AM20 AC7 1 1 1 1 1 1
VAXG28 VDDQ4

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 + C123
VAXG29 VDDQ5

330U_2.5V_M
AM17 AC1
AL24 VAXG30 VDDQ6 Y7
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2
AL21 VAXG32 VDDQ8 Y1
AL20 VAXG33 VDDQ9 U7 C96
AL18 VAXG34 VDDQ10 U4 0.1U_0402_16V7K
AL17 VAXG35 VDDQ11 U1 1 2
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4 C95
AK21 VAXG38 VDDQ14 P1 0.1U_0402_16V7K
AK20 VAXG39 VDDQ15 1 2
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
B B
AJ18 VAXG46
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26
SA RAIL

VAXG49 VCCSA2 1 1 1 1 1

10U_0603_6.3V6M
C124

10U_0603_6.3V6M
C125

10U_0603_6.3V6M
C126

10U_0603_6.3V6M
C127
AH23 L26
AH21 VAXG50 VCCSA3 J26 + C128 @
AH20 VAXG51 VCCSA4 J25 330U_D2_2.5VY_R9M
AH18 VAXG52 VCCSA5 J24 2 2 2 2
AH17 VAXG53 VCCSA6 H26 2
VAXG54 VCCSA7 H25
VCCSA8
1.8V RAIL

H23 +3VS
+1.8VS R20 80mil VCCSA_SENSE +VCCSA_SENSE <52>
@ J14 1.5A

2
1 2 +1.8VS_VCCPLL B6
1 2 A6 VCCPLL1 C22 R75
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <52>

10U_0603_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

1 1 1 A2 C24 10K_0402_5%
JUMP_43X79 VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <52>

1
2 2 2 A19 H_VCCP_SEL R02 R77 1 @ 2 0_0402_5%
VCCIO_SEL

TYCO_2013620-2_IVY BRIDGE

A A

Security Classification Compal Secret Data

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 10 of 62
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
D D
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
C
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 C
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
B B
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W35 H1 VSS221
AL10 VSS64 VSS145 W34 G35 VSS222
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80

A A
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 11 of 62
5 4 3 2 1
 5 4 3 2 1

+1.5V

+VREF_DQ_DIMMA +1.5V +1.5V

1
3A@1.5V
<7> DDR_A_D[0..63]
R70
1K_0402_1% DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1
<7> DDR_A_DQS#[0..7]

2
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 <7> DDR_A_MA[0..15]

2.2U_0603_6.3V6K

0.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
1

C134

C133
1 1 DDR_A_D1 7 8
9 DQ1 VSS3 10 DDR_A_DQS#0
R71 DDR_A_DM0 11 VSS4 DQS#0 12 DDR_A_DQS0
1K_0402_1% 13 DM0 DQS0 14
D 2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 D
2

DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7

19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28 DDR_A_DM1
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <7,13>
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46 DDR_A_DM2
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
DDR_A_DM3 63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26

C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
105 106 Layout Note:
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1 +1.5V (10uF_0603_6.3V)*8
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
DDR_A_BS1 <7> Place near DIMM
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 112
<7> DDR_A_WE# DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# (0.1uF_402_10V)*4
WE# S0# DDR_CS0_DIMMA# <7>

1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118 R72
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 1K_0402_1%
A13 ODT1 M_ODT1 <7>
DDR_CS1_DIMMA# 121 122
<7> DDR_CS1_DIMMA# S1# NC2 +1.5V
123 124

2
125 VDD17 VDD18 126 +VREF_CA
NCTEST VREF_CA

0.1U_0402_16V7K
127 128
VSS27 VSS28

C135

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36 1 EVT Check

1
C136
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37

10U_0603_6.3V6M
C139

10U_0603_6.3V6M
C140

10U_0603_6.3V6M
C141

10U_0603_6.3V6M
C142

10U_0603_6.3V6M
C143

10U_0603_6.3V6M
C144

0.1U_0402_16V7K
C145

0.1U_0402_16V7K
C146

0.1U_0402_16V7K
C147

0.1U_0402_16V7K
C148
133 134 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4 R73 + C149 @
B DDR_A_DQS4 137 DQS#4 DM4 138 2 1K_0402_1% 220U_6.3V_M B
139 DQS4 VSS31 140 DDR_A_D38 2

2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DDR_A_DM5 153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
VSS37 VSS38 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
DQ43 DQ47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DQ48 DQ52 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_A_D49 165 166 DDR_A_D53
167 DQ49 DQ53 168 Place near DIMM
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6
DQS#6 DM6 VTT(0.75V) =
DDR_A_DQS6 171 172 7/28 Update connect GND directly
173 DQS6 VSS43 174 DDR_A_D54
VSS44 DQ54 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178 +0.75VS
DQ51 VSS45 VREF =
179 180 DDR_A_D60 DDR_A_DM0
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 DDR_A_DM1
DQ56 DQ61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184 DDR_A_DM2
185 DQ57 VSS47 186 DDR_A_DQS#7 DDR_A_DM3
VSS48 DQS#7 VDDSPD (3.3V)=

1U_0402_6.3V6K
C152
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
189 DM7 DQS7 190 DDR_A_DM5
VSS49 VSS50 1*0402 0.1uf 1*0402 2.2uf 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 DDR_A_DM7
1 R81 2 195 DQ59 DQ63 196
10K_0402_5% 197 VSS51 VSS52 198 2
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,36,43> Layout Note:
2.2U_0603_6.3V6K

0.1U_0402_16V7K

A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 <13,15,36,43> Place near DIMM
C155

C156

1 1 203 204 +0.75VS

VTT1 VTT2
1
10K_0402_5%
R83

205 206 0.65A@0.75V

G1 G2
2 2 LCN_DAN06-K4806-0103
ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 12 of 62
5 4 3 2 1
 5 4 3 2 1

+1.5V
+VREF_DQ_DIMMB 3A@1.5V
<7> DDR_B_D[0..63]

1
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
R84
1K_0402_1% JDIMM2
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS 4 DDR_B_D4
<7> DDR_B_MA[0..15]

2
DDR_B_D0 5 VSS DQ4 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS

2.2U_0603_6.3V6K

0.1U_0402_16V7K
9 10 DDR_B_DQS#0
VSS DQS0#
1

C158
1 1 DDR_B_DM0 11 12 DDR_B_DQS0
13 DM0 DQS0 14
VSS VSS

C157
R85 DDR_B_D2 15 16 DDR_B_D6
1K_0402_1% DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
D 2 2 19 DQ3 DQ7 20 D
2

DDR_B_D8 21 VSS VSS 22 DDR_B_D12

DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS VSS 28 DDR_B_DM1
DDR_B_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <7,12>
31 32
DDR_B_D10 33 VSS VSS 34 DDR_B_D14
For Arranale only +VREF_DQ_DIMMB DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
supply from a external 1.5V voltage divide 37 DQ11 DQ15 38
circuit. DDR_B_D16 39 VSS VSS 40 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS VSS 46 DDR_B_DM2
DDR_B_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D22
DDR_B_D18 51 VSS DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDR_B_D28
DDR_B_D24 57 VSS DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_B_DQS#3
DDR_B_DM3 63 VSS DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS VSS 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS VSS

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
77 VDD VDD 78 DDR_B_MA15
C DDR_B_BS2 79 NC A15 80 DDR_B_MA14 C
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD VDD 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD VDD 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD VDD 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 106
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# <7> +1.5V
111 112 Layout Note:
<7> DDR_B_WE# DDR_B_WE# 113 VDD VDD 114 DDR_CS2_DIMMB# (10uF_0603_6.3V)*8
DDR_B_CAS# 115 WE# S0# 116 M_ODT2
DDR_CS2_DIMMB# <7> Place near DIMM
<7> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>

1
117 118
DDR_B_MA13 119 VDD VDD 120 M_ODT3 R86 (0.1uF_402_10V)*4
A13 ODT1 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122 1K_0402_1%
123 S1# NC 124
125 VDD VDD 126 +VREF_CB

2
TEST VREF_CA

0.1U_0402_16V7K
127 128
VSS VSS +1.5V

2.2U_0603_6.3V6K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

C159

C160
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

1
133 134
VSS VSS

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_B_DQS#4 135 136 DDR_B_DM4
DQS4# DM4

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
DDR_B_DQS4 137 138 R87
DQS4 VSS 2 2

C163

C164

C165

C166

C167

C168

C169

C170

C171

C172
139 140 DDR_B_D38 1K_0402_1% 1 1 1 1 1 1 1 1 1 1
DDR_B_D34 141 VSS DQ38 142 DDR_B_D39

2
B DDR_B_D35 143 DQ34 DQ39 144 B
145 DQ35 VSS 146 DDR_B_D44
DDR_B_D40 147 VSS DQ44 148 DDR_B_D45 2 2 2 2 2 2 2 2 2 2
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_B_DQS#5
DDR_B_DM5 153 VSS DQS5# 154 DDR_B_DQS5
DM5 DQS5 VDDQ(1.5V) =
155 156
DDR_B_D42 157 VSS VSS 158 DDR_B_D46
DQ42 DQ46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 159 160 DDR_B_D47
161 DQ43 DQ47 162
VSS VSS 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
VSS VSS VTT(0.75V) = Layout Note:
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 171 DQS6# DM6 172 3*0805 10uf 4*0402 1uf Place near DIMM
173 DQS6 VSS 174 DDR_B_D54
DDR_B_D50 175 VSS DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_B_D60
VSS DQ60 1*0402 0.1uf +0.75VS
DDR_B_D56 181 182 DDR_B_D61 1*0402 2.2uf
DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS VDDSPD (3.3V)=
185 186 DDR_B_DQS#7 DDR_B_DM0
DDR_B_DM7 187 VSS DQS7# 188 DDR_B_DQS7 DDR_B_DM1
DM7 DQS7 1*0402 0.1uf
189 190 1*0402 2.2uf DDR_B_DM2
VSS VSS

1U_0402_6.3V6K
C174

1U_0402_6.3V6K
C176
DDR_B_D58 191 192 DDR_B_D62 DDR_B_DM3
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63 DDR_B_DM4
DQ59 DQ63 1 1
195 196 DDR_B_DM5
1 R95 2 197 VSS VSS 198 DDR_B_DM6
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3 DDR_B_DM7
VDDSPD SDA SMB_DATA_S3 <12,15,36,43> 2 2
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,36,43>
2.2U_0603_6.3V6K

0.1U_0402_16V7K

R97 10K_0402_5% 203 204 +0.75VS

VTT VTT
C177

C178

1 1 0.65A@0.75V
A 205 206 A
207 GND1 GND2 208
Layout Note:
BOSS1 BOSS2 Place near DIMM
2 2
LCN_DAN06-K4406-0103
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 13 of 62
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT
NOGCLK@
Y1
R99 1 2
1K_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT
1 2 R03 1 1 R03
C180 NOGCLK@ C181

1
1 18P_0402_50V8J 18P_0402_50V8J
C179 CLRP1 NOGCLK@ NOGCLK@
1U_0402_6.3V6K SHORT PADS 2 2

2
R02
2 Remove R176
D D
close to Y1

R182 1 2 GCLK_32K
GCLK_32K <44>
0_0402_5%
CMOS GCLK@
U4A

SHORT PADS
CLRP2
+RTCVCC
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <36,42>

1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <36,42>

LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 <36,42>EC and Mini card debug port
R102 1 2 330K_0402_5% PCH_INTVRMEN 1U_0402_6.3V6K C37 LPC_AD3

2
1 2 2 D20 FWH3 / LAD3 LPC_AD3 <36,42>
PCH_RTCRST#
R103 20K_0402_5% RTCRST# D36 LPC_FRAME#
INTVRMEN 1 2 PCH_SRTCRST# G22 FWH4 / LFRAME# LPC_FRAME# <36,42>
R100 20K_0402_5% SRTCRST# E36 +3VS
H Integrated VRM enable
* 1 LDRQ0#

1
SHORT PADS
CLRP3
SM_INTRUDER# K22 K36 2 1 10K_0402_5%

RTC
L Integrated VRM disable R104
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0402_6.3V6K PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <42>

2
2 INTVRMEN SERIRQ

AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <36>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <36>
AP7 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K@2 1 C184 SATA_ITX_DRX_N0

SATA 6G
SATA0TXN SATA_ITX_DRX_N0 <36> SSD
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K@2 1 C185 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 <36>
HDA_SYNC SATA0TXP CAP on Conn, side
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10 SATA_DTX_R_IRX_N1 0_0402_5%1 HM76@ 2 R311 SATA_DTX_C_IRX_N1
<41> HDA_SPKR SPKR SATA1RXN SATA_DTX_C_IRX_N1 <40>
LOW= Disable (Default) AM8 SATA_DTX_R_IRX_P1 0_0402_5%1 HM76@ 2 R312 SATA_DTX_C_IRX_P1
* HDA_RST# K34
HDA_RST#
SATA1RXP
SATA1TXN
AP11 SATA_ITX_R_DRX_N1 0.01U_0402_16V7K 2 1 C198 SATA_ITX_C_DRX_N1 0_0402_5% 2 @ 1 R5593 SATA_ITX_DRX_N1
SATA_DTX_C_IRX_P1 <40>
SATA_ITX_DRX_N1 <40>HDD
AP10 SATA_ITX_R_DRX_P1 0.01U_0402_16V7K 2 1 C199 SATA_ITX_C_DRX_P1 0_0402_5% 2 @ 1 R5594 SATA_ITX_DRX_P1 SATA_ITX_DRX_P1 <40>
SATA1TXP CAP on Conn, side
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<41> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <40>
AD5 SATA_DTX_C_IRX_P2 ODD
SATA2RXP SATA_DTX_C_IRX_P2 <40>
R106 2 @ 1 1K_0402_5% HDA_SDOUT G34 AH5 SATA_ITX_C_DRX_N2
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_N2 <40>
SATA2TXP SATA_ITX_C_DRX_P2 <40>
Low = Disabled (Default) C34
* HDA_SDIN2 AB8

IHDA
High = Enabled [Flash Descriptor Security Overide] SATA3RXN
R02 A34 AB10
R109 HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1
HM70 Disable SATA Port 1,3
0_0402_5%
ME_FLASH 1 @ 2 HDA_SDOUT A36 SATA3TXP
+3V_PCH <42> ME_FLASH HDA_SDO Y7 SATA_DTX_R_IRX_N4 0_0402_5%1 HM70@ 2 R318 SATA_DTX_C_IRX_N1

SATA
SATA4RXN Y5 SATA_DTX_R_IRX_P4 0_0402_5%1 HM70@ 2 R315 SATA_DTX_C_IRX_P1
R108 2 1 1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 SATA4RXP AD3 SATA_ITX_R_DRX_N4 0.01U_0402_16V7K 2 1 C229 SATA_ITX_C_DRX_N1
HDA_DOCK_EN# / GPIO33 SATA4TXN HDD
AD1 SATA_ITX_R_DRX_P4 0.01U_0402_16V7K 2 1 C237 SATA_ITX_C_DRX_P1
10K_0402_5% 2 R264 @1 N32 SATA4TXP
+3V_PCH HDA_DOCK_RST# / GPIO13
This signal has a weak internal pull-down Y3
SATA5RXN Y1
On Die PLL VR is supplied by SATA5RXP
1.5V when smapled high AB3
2 R110 1 PCH_JTAG_TCK J3 SATA5TXN AB1
*1.8V when sampled low
Needs to be pulled High for Chief River platfrom
JTAG_TCK SATA5TXP
51_0402_5% PCH_JTAG_TMS H7 Y11 R111
JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA

JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS JTAG_TDI SATAICOMPI

8MB SPI ROM FOR ME

R112 PCH_JTAG_TDO H1
33_0402_5% JTAG_TDO AB12 R113 +1.05VS_SATA3
SATA3RCOMPO
& Non-share ROM.
1 2 HDA_BIT_CLK 49.9_0402_1%
<41> HDA_BITCLK_AUDIO
2
G

R114 Q10 AB13 SATA3_COMP 1 2

33_0402_5% LBSS138LT1G_SOT-23-3 SATA3COMPI
1 2 HDA_SYNC_R 3 1 HDA_SYNC
<41> HDA_SYNC_AUDIO
R116 SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
S

33_0402_5% SPI_CLK SATA3RBIAS R115 +3VS

2

B 1 2 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% R02 B

<41> HDA_RST_AUDIO# SPI_CS0#
R118 R878 R291
33_0402_5% 1M_0402_5% SPI_SB_CS1# T1 0_0402_5% U6 R02
SPI_CS1#
SPI

1 2 HDA_SDOUT P3 SATALED# 2 R117 1 10K_0402_5% SPI_SB_CS1# 1 @ 2 CS1# 1 8 R199

<41> HDA_SDOUT_AUDIO SATALED# +3VS CS# VCC 7
SPI_SO_R 1 2 SPI_SO1 2 SPI_HOLD#1 0_0402_5%
1

SPI_SI V4 V14 PCH_GPIO21 2 R119 1 10K_0402_5% SPI_WP#1 3 SO HOLD# 6 SPI_CLK1 1 @ 2 SPI_CLK_PCH_R

SPI_MOSI SATA0GP / GPIO21 +3VS WP# SCLK 5
R188 4 SPI_SI1 1 2 SPI_SI
SPI_SO_R U3 P1 BBS_BIT0_R 2 R187 1 10K_0402_5% 33_0402_5% GND SI R196
check with vender SPI_MISO SATA1GP / GPIO19 +3VS
33_0402_5%
Del Q10 check with codec 16M W25Q16BVSSIG SOIC 8P
PANTHER-POINT_FCBGA989
VDDIO using 3VALW +3VS

SPI_CLK_PCH_R R266 1 2 SPI_WP#1

3.3K_0402_5%
U6 Rersver 4M+2M Solution
1

R221 1 2 SPI_HOLD#1 +3VS

R124 3.3K_0402_5%
33_0402_5% R127 1 2 SPI_WP# C191 0.1U_0402_16V7K
@ 3.3K_0402_5% R02 1 2
R130
R124;c190 close to U4.T3 pin
2

R129 1 2 SPI_HOLD# 0_0402_5% U5 R02

3.3K_0402_5% SPI_SB_CS0# 1 @ 2 CS# 1 8 R132
C190 SPI_SO_R 1 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD# 0_0402_5%
SPI_WP# 3 SO HOLD# 6 SPI_CLK_PCH 1 @ 2 SPI_CLK_PCH_R
22P_0402_50V8J WP# SCLK
@ 33_0402_5% 4 5 SPI_SI_R 1 2 SPI_SI
R131 GND SI R133
W25Q32BVSSIG_SO8 33_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC, XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 14 of 62
5 4 3 2 1
 5 4 3 2 1

U4B
Q60A
2N7002KDWH_SOT363-6
PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
<37> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,36,43>
LAN PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPI011 2 R134 1
<37> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 +3V_PCH
C192 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N1 AV32 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
<37> PCIE_PTX_C_DRX_N1
C193 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1

2
<37> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK

<36> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34

PERN2 SMBDATA
C9 PCH_SMBDATA
+3V_PCH
1 2 1
+3VS
2 DIMM2

5
PCIE_PRX_DTX_P2 BF34 R135 R138
WLAN
<36>
<36>
PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BB32 PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C195 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<36> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,36,43>

SMBUS
A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
2N7002KDWH_SOT363-6
BJ36 PERN3 C8 PCH_SML0CLK
PERP3 SML0CLK Q60B
D AV34 2 R139 1 D
PETN3 +3V_PCH
AU34 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
BF36 2 R140 1 10K_0402_5% 2N7002KDWH_SOT363-6
PERN4 +3V_PCH
BE36 6 1 EC_SMB_CK2
AY34 PERP4 C13 EC_SMB_CK2 <23,39,42>
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 2.2K_0402_5%
PETP4 E14 SML1CLK 1 R141 2 VGA

2
BG37 SML1CLK / GPIO58

PCI-E*
BH37 PERN5
PERP5 SML1DATA / GPIO75
M16 SML1DATA
+3V_PCH
1 2
+3VS EC

5
AY36 R142
BB36 PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
BJ38 EC_SMB_DA2 <23,39,42>
BG38 PERN6 2N7002KDWH_SOT363-6
AU36 PERP6 M7

Controller
PETN6 CL_CLK1 Q61B
AV36 +3V_PCH
HM70 not support PETP6 +3V_PCH
PCIE port 5-8

Link
BG40 T11
PERN7 CL_DATA1

2
BJ40
AY40 PERP7
PETN7

2
BB40 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 R02 2.2K_0402_5% 2.2K_0402_5%

1
BC38 PERN8 R144 0_0402_5%
AW38 PERP8 1 @ 2

1
AY38 PETN8 CLK_REQ_VGA# <23> PCH_SML0CLK
PETP8
R02 M10 PEG_CLKREQ#_R PCH_SML0DATA
R153 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R Y40 PEG_A_CLKRQ# / GPIO47
<37> CLK_PCIE_LAN# 1 2 0_0402_5% CLK_PCIE_LAN_R Y39 CLKOUT_PCIE0N R02
LAN R154 @
<37> CLK_PCIE_LAN R02 CLKOUT_PCIE0P AB37 CLK_PCIE_VGA#_R R146 1 2 0_0402_5% CLK_PCIE_VGA#
@
C 1 2 0_0402_5% CLKREQ_LAN#_R J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA_R R148 1 2 0_0402_5% CLK_PCIE_VGA CLK_PCIE_VGA# <23> C
R151 @ @

CLOCKS
<37> CLKREQ_LAN# 2 1 10K_0402_5% PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P R02 CLK_PCIE_VGA <23>
+3V_PCH R152
R02
R149 1 @ 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#
<36> CLK_PCIE_WLAN1# 1 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI CLK_CPU_DMI# <6>
R150 @
<36> CLK_PCIE_WLAN1 R02 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN
R156 1 @ 2 0_0402_5% CLKREQ_WLAN#_R M1
<36> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
R158 2 1 10K_0402_5% AM12
+3VS CLKOUT_DP_N AM13
AA48 CLKOUT_DP_P
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
R147 2 1 10K_0402_5% PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R157 1 2 10K_0402_5%
+3VS PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%

Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_DMI2 R160 1 2 10K_0402_5%
CLKOUT_PCIE3P CLKIN_GND1_P
R301 2 1 10K_0402_5% PCH_GPIO25 A8
+3V_PCH PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5%
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
R165 2 1 10K_0402_5% PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
+3V_PCH PCIECLKRQ4# / GPIO26 CLKIN_SATA_P

V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5% R02

V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P Remove R1381
R168 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
+3V_PCH PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18> close to Y2
B B
AB42 V47 XTAL25_IN 0_0402_5% 2 1 R1382 GCLK_PCH_25MHZ
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT GCLK_PCH_25MHZ <44>
GCLK@
CLKOUT_PEG_B_P XTAL25_OUT
R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN
+3V_PCH PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
V40 XCLK_RCOMP
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P
R172 2 110K_0402_5% PCH_GPIO45 T13
+3V_PCH PCIECLKRQ6# / GPIO45 27M_SSC
V38 K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

CLKOUT_PCIE7P F47
R174 2 1 10K_0402_5% PCH_GPIO46 K12 CLKOUTFLEX1 / GPIO65
+3V_PCH PCIECLKRQ7# / GPIO46 H47
T52 CLKOUT_ITPXDP_N AK14 CLKOUTFLEX2 / GPIO66 XTAL25_IN
T53 CLKOUT_ITPXDP_P AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19> XTAL25_OUT 1 NOGCLK@2
BIOS Request SKU ID R169 1M_0402_5%
PANTHER-POINT_FCBGA989
3 4
OSC NC
2 1
NC OSC
Y2 NOGCLK@
1 25MHZ_10PF_7V25000014 1
C196 C197
12P_0402_50V8J 12P_0402_50V8J
NOGCLK@ NOGCLK@
2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 15 of 62
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <5>
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
<5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
<5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3 DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
<5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <5>
U15 DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <5>

DMI
FDI
MC74VHC1G08DFT2G_SC70-5 BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
3

DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6

<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
1 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
G

<55> VGATE A <5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>

4 SYS_PWROK DMI_CRX_PTX_P2 AY18
PCH_PWROK 2 Y SYS_PWROK <6> <5> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AU18 DMI2TXP
B <5> DMI_CRX_PTX_P3 DMI3TXP
P

AW16 FDI_INT
FDI_INT FDI_INT <5>
5

+V1.05S_VCCP BJ24 AV12 FDI_FSYNC0

DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5> +RTCVCC
R180 @
100K_0402_1% 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
+3VS R177 49.9_0402_1%
*

1
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
2

C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C

R178 750_0402_1% R179
4mil width and place BB10 FDI_LSYNC1 DSWODVREN - On Die DSW VR Enable 330K_0402_5%
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH H Enable
L Disable

2
A18 DSWODVREN
DSWVRMEN
R20 R181 1 NODS3@2 0_0402_5% PCH_RSMRST#_R

System Power Management

1
<42> SUSACK# R304 1 @ 2 0_0402_5% SUSACK#_R C12 E22 PCH_DPWROK R267 1 2 0_0402_5% DPWROK_EC
DPWROK_EC <42>
SUSACK# DPWROK DS3@ R183
For Deep S3 R02 330K_0402_5%
2 1 SYS_RST# K3 B9 WAKE# R185 1 @ 2 0_0402_5% For Deep S3 +3VS
+3VS SYS_RESET# WAKE# PCIE_WAKE# <36,37> @
10K_0402_5% R184 1 2 10K_0402_5%
+3V_PCH

2
R186 @ R189 8.2K_0402_5%
SYS_PWROK P12 N3 PM_CLKRUN# 1 2
SYS_PWROK CLKRUN# / GPIO32
AEPWROK can be connect to R299 10K_0402_5%
PWROK if iAMT disable PCH_PWROKR02 1 @ 2 PCH_POK L22 G8 SUS_STAT# T74 2 1
<42> PCH_PWROK PWROK SUS_STAT# / GPIO61
R190 0_0402_5%

1 @ 2 APWROK L10 N14

<42> PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK <42>
PCH_POK R02 1 @ 2 APWROK R302 0_0402_5%
R191 0_0402_5%
PM_DRAM_PWRGD B13 D10
<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <42>

R02 1 @ 2 PCH_RSMRST#_R C21 H4

<42> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <42>
R193 0_0402_5%
+3V_PCH R20
R1455 2 @ 1 0_0402_5% SUSWARN#_R K16 F4
<42> SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <42>
R192 2 1 300_0402_5% PM_DRAM_PWRGD For Deep S3 Can be left NC
B R02 1 @ 2 PBTN_OUT#_R E20 G10 SLP_A# T99 B
<42> PBTN_OUT# PWRBTN# SLP_A#
when IAMT is not
R198 0_0402_5% R20 support on the
R194 2 1 10K_0402_5% SUSWARN#_R R1447 0_0402_5% platfrom
D29 1 2 AC_PRESENT_R H20 G16 SLP_SUS#_R 2 @ 1
<42,49> ACIN ACPRESENT / GPIO31 SLP_SUS# SLP_SUS# <42,46>
R5574 2 NODS3@1 200K_0402_5% AC_PRESENT_R
CH751H-40PT_SOD323-2 For Deep S3
R197 2 1 10K_0402_5% PCH_RSMRST#_R 2 R200 1 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
10K_0402_5%

2 R201 1 RI# A10 K14 PCH_GPIO291 2 Can be left NC if no use

+3V_PCH RI# SLP_LAN# / GPIO29 +3V_PCH
10K_0402_5% R261 @ integrated LAN.
10K_0402_5%
PANTHER-POINT_FCBGA989

For Deep S3

+3VALW

R195 1 DS3@ 2 200K_0402_5% AC_PRESENT_R

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI,FDI,PM,
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 16 of 62
5 4 3 2 1
 5 4 3 2 1

+3VS

U4D

1
D R523 R234 J47 AP43 D
<33> PCH_ENBKL L_BKLTEN SDVO_TVCLKINN
2.2K_0402_5% 2.2K_0402_5% M45 AP45 +3VS
<33> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
P45 AM42
<33> PCH_PWM

2
L_BKLTCTL SDVO_STALLN AM40
SDVO_STALLP

1
EDID_CLK EDID_CLK T40
+3VS <33> EDID_CLK K47 L_DDC_CLK AP39
EDID_DATA EDID_DATA HDMI@ R202 R203HDMI@
<33> EDID_DATA L_DDC_DATA SDVO_INTN AP40 2.2K_0402_5% 2.2K_0402_5%
2.2K_0402_5%1 R204 2 CTRL_CLK T45 SDVO_INTP
2.2K_0402_5%1 R205 2 CTRL_DATA P39 L_CTRL_CLK

2
L_CTRL_DATA
2 R206
2.37K_0402_1% 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB <35>
AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB <35>
LVD_VREF AE48
AE47 LVD_VREFH AT49
LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40
DDPB_HPD TMDS_B_HPD# <35>
AK39
<33> LVDS_ACLK# LVDSA_CLK#

LVDS
AK40 AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 0.1U_0402_16V7K
<33> LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK <35>
AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 0.1U_0402_16V7K HDMI D2
AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCHHDMI@ 1 2 HDMI_TX2+_CK <35>
C202 0.1U_0402_16V7K
<33> LVDS_A0# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH HDMI@ 1 2 HDMI_TX1-_CK <35>
C203 0.1U_0402_16V7K HDMI D1
<33> LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK <35>

Digital Display Interface

AK47 AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 0.1U_0402_16V7K HDMI
C <33> LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0_PCH HDMI@ 1 2 HDMI_TX0-_CK <35> C
C205 0.1U_0402_16V7K HDMI D0
LVDSA_DATA#3 DDPB_2P HDMI_TX0+_CK <35>
AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 0.1U_0402_16V7K
AN47 DDPB_3N AV49 TMDS_B_CLK_PCH 1 2 HDMI_CLK-_CK <35>
HDMI@ C207 0.1U_0402_16V7K HDMI CLK
<33> LVDS_A0 AM49 LVDSA_DATA0 DDPB_3P HDMI_CLK+_CK <35>
<33> LVDS_A1 LVDSA_DATA1
AK49
<33> LVDS_A2 AJ47 LVDSA_DATA2 P46 CAP move on Conn, side
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
AF40
<33> LVDS_BCLK# LVDSB_CLK#
AF39 AP47
<33> LVDS_BCLK LVDSB_CLK DDPC_AUXN AP49
AH45 DDPC_AUXP AT38
<33> LVDS_B0# AH47 LVDSB_DATA#0 DDPC_HPD
<33> LVDS_B1# AF49 LVDSB_DATA#1 AY47
<33> LVDS_B2# LVDSB_DATA#2 DDPC_0N
AF45 AY49
LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
<33> LVDS_B0 AH49 LVDSB_DATA0 DDPC_1P BA47
+3VS <33> LVDS_B1 AF47 LVDSB_DATA1 DDPC_2N BA48
<33> LVDS_B2 LVDSB_DATA2 DDPC_2P
AF43 BB47
DAC_BLU LVDSB_DATA3 DDPC_3N BB49
<34> DAC_BLU DDPC_3P
R208 2 1 150_0402_1%
1

DAC_GRN
<34> DAC_GRN
B R559 R524 R209 2 1 150_0402_1% N48 M43 B
2.2K_0402_5% 2.2K_0402_5% DAC_RED P49 CRT_BLUE DDPD_CTRLCLK M36
<34> DAC_RED CRT_GREEN DDPD_CTRLDATA
R210 2 1 150_0402_1% T49
CRT_RED
2

AT45
DDPD_AUXN

CRT
CRT_DDC_CLK CRT_DDC_CLK T39 AT43
<34> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA CRT_DDC_DATA M40 BH41
<34> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
BB43
M47 DDPD_0N BB45
<34> CRT_HSYNC M49 CRT_HSYNC DDPD_0P BF44
<34> CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
CRT_IREF T43 DDPD_2N BE42
T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N
1

BG42
R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989
2

A A

Security Classification Compal Secret Data

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 17 of 62
5 4 3 2 1
 5 4 3 2 1

+3VS

U4E
RP2 AY7
8 1 PCI_PIRQA# RSVD1 AV7
7 2 PCI_PIRQD# BG26 RSVD2 AU3
6 3 PCI_PIRQC# BJ26 TP1 RSVD3 BG4
5 4 PCI_PIRQB# BH25 TP2 RSVD4
BJ16 TP3 AT10
8.2K_8P4R_5% BG16 TP4 RSVD5 BC8
RP1 AH38 TP5 RSVD6
D TP6 D
8 1 PCH_GPIO2 AH37 AU2
7 2 DGPU_PWR_EN_R AK43 TP7 RSVD7 AT4
6 3 PCH_GPIO4 AK45 TP8 RSVD8 AT3
5 4 ODD_DA#_R C18 TP9 RSVD9 AT1
N30 TP10 RSVD10 AY3
8.2K_8P4R_5% H3 TP11 RSVD11 AT5
AH12 TP12 RSVD12 AV3
AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
R213 1 2 8.2K_0402_5% PCH_GPIO5 Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
R225 1 2 8.2K_0402_5% PCH_WL_OFF# L24 TP17 RSVD17 BB3
AB46 TP18 RSVD18 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 TP19 RSVD19 BE8
TP20 RSVD20

RSVD
BD4
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53
PPT EDS DOC#474146 RSVD21 BF6
RSVD22
R259 1 2 8.2K_0402_5% DGPU_PWR_EN1 B21 AV5
M20 TP21 RSVD23 AV10
R212 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R AY16 TP22 RSVD24
BG46 TP23 AT8
R214 1 @ 2 8.2K_0402_5% DGPU_HOLD_RST#_R TP24 RSVD25
HM70 not support USB3 port 3,4 AY5
RSVD26 BA2
USB30_RX_N1 BE28 RSVD27
<45> USB30_RX_N1 USB3Rn1
T1833 USB30_RX_N2 BC30 AT12
T1829 USB30_RX_N3 BE32 USB3Rn2 RSVD28 BF3
C Boot BIOS Strap bit1 BBS1 USB3Rn3 RSVD29 C
T1825 USB30_RX_N4 BJ32
USB30_RX_P1 BC28 USB3Rn4
Boot BIOS <45> USB30_RX_P1 USB3Rp1 USB DEBUG=PORT1 AND PORT9
T1834 USB30_RX_P2 BE30
Destination T1832 USB30_RX_P3 BF32 USB3Rp2
Bit11 Bit10 USB3Rp3
T1826 USB30_RX_P4 BG32 C24 USB20_N0
USB3Rp4 USBP0N USB20_N0 <45>
0 1 Reserved USB30_TX_N1 AV26 A24 USB20_P0 LEFT USB (USB 3.0)
<45> USB30_TX_N1 USB3Tn1 USBP0P USB20_P0 <45>
GNT1#/ T1835 USB30_TX_N2 BB26 C25 USB20_N1
USB3Tn2 USBP1N USB20_N1 <43>
1 0 Reserved T1831 USB30_TX_N3 AU28 B25 USB20_P1 Touch Screen
GPIO51 T1827 USB30_TX_N4 AY30 USB3Tn3 USBP1P C26 USB20_N2
USB20_P1 <43>
USB3Tn4 USBP2N USB20_N2 <40>
1 1 SPI (Default) USB30_TX_P1 AU26 A26 USB20_P2 Bluetooth
* <45> USB30_TX_P1
T1836 USB30_TX_P2 AY26 USB3Tp1
USB3Tp2
USBP2P
USBP3N
K28 USB20_N3
USB20_P2
USB20_N3
<40>
<33>
0 0 LPC T1830 USB30_TX_P3 AV28 H28 USB20_P3 USB Camera
USB3Tp3 USBP3P USB20_P3 <33>
T1828 USB30_TX_P4 AW30 E28
USB3Tp4 USBP4N D28
USBP4P C28
USBP5N A28
USBP5P C29
DGPU_PWR_EN_R 1 @ 2 NVDD_PWR_EN USBP6N B29
HM70 not support USB port 4,5,6,7,12,13
R319 0_0402_5% PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P

PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 <43>
PCI_PIRQD# G38 K30 USB20_P8
PIRQD# USBP8P USB20_P8 <43> (CR-B/D USB)
G30 USB20_N9
R02 1 USBP9N USB20_N9 <43>
GPIO55 @ 2 DGPU_HOLD_RST#_R C46 E30 USB20_P9
<23> DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 <43> (CR-B/D USB)

USB
R553 0_0402_5% DGPU_PWR_EN1 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 <36>
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% R02 1 @ 2 DGPU_PWR_EN_R E40 A30 USB20_P10
<23,25,42> DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 <36> WLAN
B R691 0_0402_5% L32 USB20_N11 B
USBP11N USB20_N11 <44>
PCH_GPIO51 D47 K32 USB20_P11
GNT1# / GPIO51 USBP11P USB20_P11 <44> CARD READER
PCH_GPIO53 E42 G32
PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32
A16 swap overide Strap/Top-Block <36> PCH_WL_OFF# GNT3# / GPIO55 USBP12P
Swap Override jumper C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
Low=A16 swap PIRQE# / GPIO2
override/Top-Block R715 1 @ 2 0_0402_5% ODD_DA#_R G40
<40> ODD_DA# PIRQF# / GPIO3
PCI_GNT3# Swap Override enabled PCH_GPIO4 C42 C33 USBRBIAS 1 R218 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
High=Default * PIRQH# / GPIO5 USB_OC0# Share with USB_OC4#
B33
Within 500 mils due to same power switch +3V_PCH
K10 USBRBIAS
<42> PCI_PME# PME# 10K_1206_8P4R_5% RP3
R692 1 @ 2 0_0402_5% DGPU_PWR_EN1 PCH_PLTRST# C6 A14 USB_OC0# USB_OC5# 4 5
<54> NVDD_PWR_EN <6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <45>
K20 USB_OC1# USB_OC2# 3 6
OC1# / GPIO40 B17 USB_OC2# USB_OC7# 2 7
22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 OC2# / GPIO41 C16 USB_OC3# USB_OC0# 1 8
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
<42> CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <43>
22_0402_5% 2 @ 1 R173 CLK_PCI_DB_R J48 A16 USB_OC5# USB_OC6# 4 5
<36> CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
K42 D14 USB_OC6# USB_OC1# 3 6
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7# USB_OC4# 2 7
1 @ 2 CLKOUT_PCI4 OC7# / GPIO14 USB_OC3# 1 8
R222 0_0402_5%
PANTHER-POINT_FCBGA989 10K_1206_8P4R_5% RP4

A A
3

1 PCH_PLTRST#
G

4 A
<23,36,37,42> PLT_RST# Y 2
B
P

Security Classification Compal Secret Data

1

1 U7 @
5

MC74VHC1G08DFT2G_SC70-5 2012/12/26 2012/07/11 Title

C208 @
Issued Date Deciphered Date
0.1U_0402_16V7K
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
+3VS AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
2

R223 Custom 1.0

100K_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 18 of 62
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS

2
10K_0402_5%

10K_0402_5%
PCH_GPIO69 Function PCH_GPIO70 Function
HM70@ GV2@
R702
0 HM76 by PCH R703 0 UMA
1 HM70 by PCH 1 N14P-GV2

1
PCH_GPIO69 PCH_GPIO70

2
10K_0402_5%
R707
HM76@ R705
200K_0402_5%
UMA@
D +3V_PCH D

1
Weak internal pull-high
1 R235 2 10K_0402_5% EC_SMI#

U4F +3VS

1 R233 2 10K_0402_5% PCH_GPIO0 T7 C40 PCH_GPIO68 10K_0402_5%1 2 R224

+3VS BMBUSY# / GPIO0 TACH4 / GPIO68
1 R227 2 10K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69
GPIO28 TACH1 / GPIO1 TACH5 / GPIO69
On-Die PLL Voltage Regulator 1 R228 2 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS +3VS
+3VS TACH2 / GPIO6 TACH6 / GPIO70
This signal has a weak internal pull up
EC_SCI# E38 A40 PCH_GPIO71 10K_0402_5%2 1 R704
<42> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71

2
H On-Die voltage regulator enable
* L On-Die PLL Voltage Regulator disable <42> EC_SMI# EC_SMI# C10
GPIO8
R236
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 R229 1 @ 2 10K_0402_5% PCH_GPIO12 C4
+3V_PCH LAN_PHY_PW R_CTRL / GPIO12

1
R230 1 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
GPIO15 A20GATE GATEA20 <42>
<42> EC_LID_OUT# AU16
mSATA_DET#
<36> mSATA_DET# PECI
+3VS R231 1 2 10K_0402_5% U2
R02 SATA4GP / GPIO16 P5 KBRST# KBRST# R226 1 2 10K_0402_5%
* Deep S4,S5 wake event signal RCIN# KBRST# <42>
R297 1 @ 2 0_0402_5%
RTC alarm,Power BTN,GPIO27 <46,54> DGPU_PWROK

GPIO
1 2 10K_0402_1% DGPU_PWROK_R D40 AY11
+3VS R232 @
TACH0 / GPIO17 PROCPW RGD H_CPUPWRGD <6>

CPU/MISC
PU on power side
PCH_GPIO27 (Have internal Pull-High) +3VS R238 1 2 10K_0402_5% BT_DISABLE T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# H_THRMTRIP# <6>
C
SCLOCK / GPIO22 THRMTRIP# R239 390_0402_5% C
Deep S4,S5 wake event signal <36> BT_DISABLE ODD_EN E8 T14
<40> ODD_EN GPIO24 INIT3_3V#
+3VALW For DS3 PCH_GPIO27 E16 AY1
PCH_THRMTRIP#_R <23>
DS3@ GPIO27 DF_TVS INIT3_3V
R5530 2 1 10K_0402_5% R241 1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
+3V_PCH GPIO28 AH8
<36,40> PCH_BT_ON# 1 R242 2 10K_0402_5% K1 TS_VSS1
PCH_BT_ON#
+3VS STP_PCI# / GPIO34 +1.8VS
R245 1 @ 2 10K_0402_5% PCH_GPIO27 AK11
1 R243 2 10K_0402_5% PCH_GPIO35 K4 TS_VSS2
R03 GPIO35 AH10
TS_VSS3
DMI Termination Voltage
INTEL_BT_OFF# V8
<36> INTEL_BT_OFF# SATA2GP / GPIO36

1
AK10 Set to Vcc when HIGH
PCH_GPIO37 M5 TS_VSS4
SATA3GP / GPIO37
NV_CLE
+3VS Set to Vss when LOW R216
+3VS PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1

2
1

R247 1 2 10K_0402_5% PCH_GPIO39 M3 NV_CLE R217 2 1 1K_0402_5%

+3VS SDATAOUT0 / GPIO39 H_SNB_IVB# <6>
R244 @ R250 @
10K_0402_5% 10K_0402_5% R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT
SDATAOUT1 / GPIO48 VSS_NCTF_15
PU,Do not pull low
R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
+3VS
2

PCH_GPIO37 INTEL_BT_OFF# SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16

R251 1 2 10K_0402_5% PCH_GPIO57 D6 BH3
+3V_PCH GPIO57 VSS_NCTF_17
1

BH47
R881 VSS_NCTF_18
10K_0402_5% R547 A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
10K_0402_5%
2

A44 BJ44
2

B VSS_NCTF_2 VSS_NCTF_20 B
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21

NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
BIOS Request SKU ID
A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
+3VS A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 C2
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26
2

1
10K_0402_5%

10K_0402_5%

BD1 D1
VSS_NCTF_9 VSS_NCTF_27
BD49 D49
R711 R246 VSS_NCTF_10 VSS_NCTF_28
UMA@ UMA@ BE1 E1
1

VSS_NCTF_11 VSS_NCTF_29
PCH_GPIO38 BE49 E49
VSS_NCTF_12 VSS_NCTF_30
PCH_GPIO67 BF1 F1
PCH_GPIO67 <15> VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32
2

1
10K_0402_5%

10K_0402_5%

OPT@ R708 R298 OPT@ PANTHER-POINT_FCBGA989

PCH_GPIO38 PCH_GPIO67 Function

1

A A

0 0 Optimus
1 1 UMA Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 19 of 62
5 4 3 2 1
 5 4 3 2 1

L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
+V1.05S_VCCP U4G POWER +3VS PCH Power Rail Table
@ J2 1300mA L1 1_0603_1% Refer to CPU EDS R1.5
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] 1mA VCCADAC
VCCCORE[2] 1 1 1 S0 Iccmax

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212
1 1 1 1 AD21 Voltage Rail Voltage Current (A)

CRT
VCCCORE[3]

10U_0603_6.3V6M
C209
PAD-OPEN 4x4m AD23 U47 C213 C214 C215
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_16V7K 10U_0603_6.3V6M

VCC CORE
AF23 VCCCORE[5] 2 2 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7] R02
AG24 VCCCORE[8] AK36 +VCCA_LVDS R295 2 @ 1 0_0603_5%
VCCCORE[9] 1mA VCCALVDS V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]

LVDS
AJ26 AM37 L2
AJ27 VCCCORE[14] VCCTX_LVDS[1] 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[15]
Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
+V1.05S_VCCP AJ31 VCCCORE[16] VCCTX_LVDS[2] 0.1uH inductor, 200mA
VCCCORE[17] 1 1 1
AP36 VccADAC 3.3 0.001
60mA VCCTX_LVDS[3] C216 C217 C218
R02 AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
R254 2 @ 1 0_0603_5% +1.05VS_VCCDPLLEXPAN19 VCCTX_LVDS[4] 2 2 2
VCCIO[28]
VccADPLLA 1.05 0.075
R02
T47 +VCCAPLLEXP BJ22 R256 +3VS VccADPLLB 1.05 0.075
VCCAPLLEXP 0_0603_5%
This pin can be left as no connect in V33 +3VS_VCC3_3_6 2 @ 1
AN16 VCC3_3[6]

HVCMOS
VccCore 1.05 1.3
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16] V34 C219
VCC3_3[7]
VccDMI 1.05 0.042
0.1U_0402_16V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.709
AN26
VCCIO[18]
AN27 3711mA AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+V1.05S_VCCP 10U AP21 +VCCP_VCCDMI R02 +V1.05S_VCCP
C VCCIO[20] R258 C
VccSPI 3.3 0.01
AP23 AT20 +VCCP_VCCDMI 2 @ 1
VCCIO[21] VCCDMI[1]
1
+V1.05S_VCCP
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

DMI
1 1 1 1 1 AP24 0_0603_5% VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221

VCCIO
R02 C220
AP26 AB36 +1.05VS_VCC_DMI_CCI R294 2 @ 1 0_0603_5% 1U_0402_6.3V6K
VCCIO[23] 20mA VCCCLKDMI 2
1 VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.065
+3VS VCCIO[26] VCCDFTERM[1]
R02
R260 2 @ 1 0_0603_5% +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS VccSusHDA 3.3 / 1.5 0.01
VCC3_3[3] 190mAVCCDFTERM[2]

DFT / SPI
1
C227 R02
0.1U_0402_16V7K AJ16 R293 2 @ 1 0_0603_5% VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3]
2 +VCCAFDI_VRM AP16
VCCVRM[2] 1
AJ17 C228 VccCLKDMI 1.05 0.075
VCCDFTERM[4] 0.1U_0402_16V7K
This pin can be left as no connect in BG6
T50 +1.05VS_VCCAPLL_FDI
On-Die VR enabled mode (default). R02 VccAFDIPLL 2 +3VS VccSSC 1.05 0.095
R263 0_0603_5%
2 @ 1 +1.05VS_VCCDPLL_FDI AP17 R02
+V1.05S_VCCP VCCIO[27] V1 +3V_VCCPSPI R399 1 @ 2 0_0402_5% VccDIFFCLKN 1.05 0.055
FDI

20mA VCCSPI
AU20 1
+VCCP_VCCDMI VCCDMI[2]
VccALVDS 3.3 0.001
C230
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2 VccTX_LVDS 1.8 0.04

+VCCAFDI_VRM
+1.5VS

R02
R265 2 @ 1 0_0603_5% +VCCAFDI_VRM

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP

VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 20 of 62
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS +V1.05S_VCCP R268 @
0_0603_5%
2 1 +VCCACLK
10U For Deep S3
R02
R303
2 @ 1+3VS_VCC_CLKF33 +3VALW +V1.05S_VCCP
1 1 R02 U4J POWER

10U_0603_6.3V6M
C231

1U_0402_6.3V6K
C232
0_0603_5% R269 2 @ 1 0_0603_5% +VCCDSW3_3 R20
1 AD49 N26 +1.05VS_VCCUSBCORE R270 2 @ 1 0_0603_5%
VCCACLK VCCIO[29]
2 2 1
C234 P26
0.1U_0402_16V7K T16 VCCIO[30] C233
D 2 VCCDSW3_3 3mA P28 1U_0402_6.3V6K D
VCCIO[31] 2
V12 T27
DCPSUSBYP VCCIO[32]
T29
+3VS_VCC_CLKF33 T38 VCCIO[33] R02 +3V_PCH
On-Die PLL Voltage Regulator VCC3_3[5]
H On-Die PLL voltage regulator enable T101
R272
T23 +3V_VCCPUSB 2 @ 1
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +VCCAPLL_CPY_PCH BH23 119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3V_PCH

0.1U_0402_16V7K
C236
R02 T24 1 0_0603_5% R02
,VCCAPLLSATA R271 2 @ 1 0_0603_5% +VCCDPLL_CPY AL29 VCCSUS3_3[8] R273 +5V_PCH +3V_PCH
+V1.05S_VCCP VCCIO[14] V23 +3V_VCCAUBG 2 @ 1
VCCSUS3_3[9]

USB
1

2
+VCCSUS1 AL24 V24 2 0_0603_5%
DCPSUS[3] VCCSUS3_3[10] C238 R275 D1
1
P24 0.1U_0402_16V7K 10_0402_5% CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 R02 +V1.05S_VCCP
1U_0402_6.3V6K AA19 R276

1
2 VCCASW[1] T26 +1.05VS_VCCAUPLL 2 @ 1 +PCH_V5REF_SUS
+V1.05S_VCCP R20 80mil AA21 VCCIO[34]
VCCASW[2]
1010mA 1
@ J16 0_0603_5%
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
1 2 VCCASW[3] 1mA V5REF_SUS 0.1U_0402_16V7K
1 1 2

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242
AA26

Clock and Miscellaneous

JUMP_43X79 VCCASW[4] AN23 +VCCA_USBSUS C243 @1 2 1U_0402_6.3V6K
AA27 DCPSUS[4]
2 2 VCCASW[5] AN24 +3V_VCCPSUS C316 @1 2 0.1U_0402_16V7K
AA29 VCCSUS3_3[1]
VCCASW[6]
AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN R02 +3V_PCH
VCCASW[8] 1mA V5REF

2
C R278 C
1 1 1

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
AC27 2 @ 1 R279 D2
VCCASW[9] N20 +3V_VCCPSUS CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1 10_0402_5%
+V1.05S_VCCP AC29 0_0603_5%

PCI/GPIO/LPC
2 2 2 VCCASW[10] N22 C247

1
AC31 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
VCCASW[11] P20 2 R02 +3VS
VCCSUS3_3[4] 1
+1.05VS_VCCA_A_DPL AD29 R281
VCCASW[12] P22 2 @ 1 C248
VCCSUS3_3[5]
1

AD31 1 1U_0402_6.3V6K
R300 VCCASW[13] C249 0_0603_5% 2
0_0603_5% W21 AA16 +3VS_VCCPCORE 0.1U_0402_16V7K
VCCASW[14] VCC3_3[1]
@ 2 +3VS
L6 W23 W16 R02
VCCASW[15] VCC3_3[8]
2

1 2 +1.05VS_VCCA_B_DPL R282
10UH_LB2012T100MR_20% W24 T34 +3VS_VCCPPCI 2 @ 1
VCCASW[16] VCC3_3[4]
1 1
220U_B2_2.5VM_R35
C250

1U_0402_6.3V6K
C251

22U_0805_6.3V6M
C187

1U_0402_6.3V6K
C253

1 1 1 W26 0_0603_5%
+ VCCASW[17] C254
W29 R02 +3VS 0.1U_0402_16V7K
VCCASW[18] R283 2
2 2 2 2 W31 AJ2 +VCC3_3_2 2 @ 1
VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +V1.05S_VCCP
1
W33 0_0603_5% R20
VCCASW[20] AF13 R285 2 @ 1 0_0603_5%
VCCIO[5] C255
2 0.1U_0402_16V7K 1
+VCCRTCEXT N16
DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
0.1U_0402_16V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B R02 AF14 B
R274 2 @ 1 0_0603_5% +1.05VS_VCCA_A_DPL BD47 VCCIO[6]
+V1.05S_VCCP VCCADPLLA 80mA

SATA
AK1 +VCCSATAPLL T100
+1.05VS_VCCA_B_DPL BF47 VCCAPLLSATA
1 VCCADPLLB 80mA
+VCCAFDI_VRM On-Die PLL Voltage Regulator
C256 H On-Die PLL voltage regulator enable
1U_0402_6.3V6K AF11 +VCCAFDI_VRM
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK AF17 VCCVRM[1] +1.05VS_VCC_SATA +V1.05S_VCCP
2 VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33 R20
R02 AF34 VCCDIFFCLKN[1]
55mA AC16 +1.05VS_VCC_SATA R288 2 @ 1 0_0603_5% ,VCCAPLLSATA
R280 2 @ 1 0_0603_5% +1.05VS_VCCDIFFCLKN AG34 VCCDIFFCLKN[2] VCCIO[2]
+V1.05S_VCCP VCCDIFFCLKN[3]
1 AC17 1
VCCIO[3] C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +V1.05S_VCCP
R02 DCPSST
1
+V1.05S_VCCP R284 2 @ 1 0_0603_5% C263
1 0.1U_0402_16V7K +1.05VM_VCCSUS T17 T21
V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC

1U_0402_6.3V6K +V1.05S_VCCP R02 V21

2 R286 VCCASW[23]
CPU

@ R290 2 @ 1 +V_CPU_IO BJ8

0_0603_5% V_PROC_IO 1mA T19
2 1 +1.05VM_VCCSUS 0_0603_5% VCCASW[21]
+V1.05S_VCCP 1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265

0.1U_0402_16V7K
C266

R02
1 R287
A22 P32 +VCCSUSHDA 2 @ 1
RTC

2 2 VCCRTC 10mA VCCSUSHDA

HDA

C264 @
1U_0402_6.3V6K
C268

0.1U_0402_16V7K
C269

1U_0402_6.3V6K 1 1 1 0_0603_5%
2 PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V7K A

2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/12/26 2012/07/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 21 of 62
5 4 3 2 1
 5 4 3 2 1

U4I

AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
AF7 VSS[58] VSS[137] AV24 BH35 VSS[224] VSS[324] Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
AH46 VSS[70] VSS[149] AW32 D32 VSS[236] VSS[342] BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 22 of 62
5 4 3 2 1
 5 4 3 2 1

R02 GC6@ +VDD33MISC

1 2
RV54 100K_0402_5%
OVERT#
OVERT# <42> +3VS +3VS_VGA
DGPU_PWR_EN <18,23,25,42>
@
U65A @ 1 2
PCH_THRMTRIP#_R <19>

1
G
PCIE_CTX_GRX_N[0..15] QV11 GC6@ RV53 10K_0402_5%
<5> PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P0 AN12 Part 1 of 7 2N7002KW_SOT323-3 @
PEX_RX0

3
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 AM12 P6 GC6_FB_CLAMP_R 3 1 RV208
<5> PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_P1 AN14 PEX_RX0_N GPIO0 M3 GC6_FB_CLAMP <27,42,46>

D
10K_0402_5% QV7B
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N1 AM14 PEX_RX1 GPIO1 L6 2N7002KDWH_SOT363-6

2
<5> PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_P2 AP14 PEX_RX1_N GPIO2 P5 DGPU_HOLD_RST# <18,23> 5 @
PEX_RX2 GPIO3 GPU_STDBY_EN <54>

2
G
PCIE_CRX_GTX_P[0..15]

0.1U_0402_16V7K
PCIE_CTX_GRX_N2 AP15 P7 QV10 GC6@
<5> PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4

@ CV305
PCIE_CTX_GRX_P3 AN15 L7 GPU_STDBY_EN 2N7002KW_SOT323-3 QV7A 1

4
D PCIE_CTX_GRX_N3 AM15 PEX_RX3 GPIO5 M7 GC6_FB_REQ_R 3 1 GC6_FB_REQ 2N7002KDWH_SOT363-6 D
PCIE_CTX_GRX_P4 AN17 PEX_RX3_N GPIO6 N8 GC6_FB_REQ <42>

D
@
PCIE_CTX_GRX_N4 AM17 PEX_RX4 GPIO7 M1 OVERT# 2
PCIE_CTX_GRX_P5 AP17 PEX_RX4_N GPIO8 M2 GPU_HOT# 2
PCIE_CTX_GRX_N5 AP18 PEX_RX5 GPIO9 L1 GPU_HOT# <54> R02

1
PCIE_CTX_GRX_P6 AN18 PEX_RX5_N GPIO10 M5 NVVDD_PWM_VID

GPIO
PEX_RX6 GPIO11 NVVDD_PWM_VID <54>

1
PCIE_CTX_GRX_N6 AM18 N3 VGA_AC_DET_R OPT@ D
PCIE_CTX_GRX_P7 AN20 PEX_RX6_N GPIO12 M4 GPU_VID5 0_0402_5% 1 2 RV131 NVVDD_PSI +VDD33MISC PLT_RST_VGA# 2 QV9
PCIE_CTX_GRX_N7 AM20 PEX_RX7 GPIO13 N4 NVVDD_PSI <54>
G 2N7002K_SOT23-3
PCIE_CTX_GRX_P8 AP20 PEX_RX7_N GPIO14 P2 VGA_GPIO15 100K_0402_5% 1 @ 2 RV17 GC6@ S @

3
PCIE_CTX_GRX_N8 AP21 PEX_RX8 GPIO15 R8 GC6_FB_REQ_R 1 2
PCIE_CTX_GRX_P9 AN21 PEX_RX8_N GPIO16 M6 RV51 10K_0402_5%
PCIE_CTX_GRX_N9 AM21 PEX_RX9 GPIO17 R1
PCIE_CTX_GRX_P10 AN23 PEX_RX9_N GPIO18 P3 +3VS
PCIE_CTX_GRX_N10 AM23 PEX_RX10 GPIO19 P4 GC6@
PCIE_CTX_GRX_P11 AP23 PEX_RX10_N GPIO20 P1 GC6_FB_REQ 1 2
PCIE_CTX_GRX_N11 AP24 PEX_RX11 GPIO21 RV52 10K_0402_5%
PCIE_CTX_GRX_P12 AN24 PEX_RX11_N if GC6 is supported, stuff the BOM option to
PCIE_CTX_GRX_N12 AM24 PEX_RX12 pull high to 3.3vs system power, if not, stuff
PCIE_CTX_GRX_P13 AN26 PEX_RX12_N the BOM option to pull high to NV3V3;
PCIE_CTX_GRX_N13 AM26 PEX_RX13
PEX_RX13_N For N13P-GS Reserve for GTGE leakage issue
PCIE_CTX_GRX_P14 AP26
PCIE_CTX_GRX_N14 AP27 PEX_RX14
PCIE_CTX_GRX_P15 AN27 PEX_RX14_N AK9 +3VS +VDD33MISC +VDD33MISC
PCIE_CTX_GRX_N15 AM27 PEX_RX15 DACA_RED AL10
PEX_RX15_N DACA_GREEN AL9
DACA_BLUE

2
GPU_HOT# 1 @ 2

DACs
PCIE_CRX_GTX_P0 CV6 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P0 AK14 RV14 RV15 RV49 100K_0402_5%
+VDD33MISC PCIE_CRX_GTX_N0 CV7 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N0 AJ14 PEX_TX0 AM9 VGA_EDID_CLK 1 OPT@ 2
PEX_TX0_N DACA_HSYNC 10K_0402_5% 10K_0402_5%
PCIE_CRX_GTX_P1 CV8 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P1 AH14 AN9 OPT@ RV3 2.2K_0402_5%
+VDD33MISC PEX_TX1 DACA_VSYNC @
PCIE_CRX_GTX_N1 CV9 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N1 AG14 VGA_EDID_DATA 1 OPT@ 2

1
PCIE_CRX_GTX_P2 CV10 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P2 AK15 PEX_TX1_N 10K_0402_5% RV4 2.2K_0402_5%
PEX_TX2
2

C PCIE_CRX_GTX_N2 CV11 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N2 AJ15 AG10 +DACA_VDD 2 RV107 1 VGA_AC_DET_R 2 1VGA_AC_DET VGA_CRT_DATA 1 OPT@ 2 C
PEX_TX2_N DACA_VDD VGA_AC_DET <42>

PCI EXPRESS
RV24 RV25 PCIE_CRX_GTX_P3 CV12 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P3 AL16 AP9 @ DV3 RV10 2.2K_0402_5%
2.2K_0402_5% 2.2K_0402_5% PCIE_CRX_GTX_N3 CV13 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N3 AK16 PEX_TX3 DACA_VREF AP8 SDMK0340L-7-F_SOD323-2 VGA_CRT_CLK 1 OPT@ 2
OPT@ OPT@ PCIE_CRX_GTX_P4 CV15 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P4 AK17 PEX_TX3_N DACA_RSET OPT@ RV11 2.2K_0402_5%
PEX_TX4
5

OPT@ PCIE_CRX_GTX_N4 CV17 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N4 AJ17 I2CB_SCL 1 OPT@ 2

1

QV1B PCIE_CRX_GTX_P5 CV19 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P5 AH17 PEX_TX4_N RV12 2.2K_0402_5%
VGA_SMB_CK2 4 3 PCIE_CRX_GTX_N5 CV14 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N5 AG17 PEX_TX5 I2CB_SDA 1 OPT@ 2
EC_SMB_CK2 <15,39,42> PCIE_CRX_GTX_P6 1 2 PCIE_CRX_C_GTX_P6 AK18 PEX_TX5_N
CV16 0.22U_0402_6.3V K OPT@ RV13 2.2K_0402_5%
2N7002KDWH_SOT363-6 PCIE_CRX_GTX_N6 CV18 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N6 AJ18 PEX_TX6 OVERT# 1 OPT@ 2
PCIE_CRX_GTX_P7 CV20 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P7 AL19 PEX_TX6_N RV1 10K_0402_5%
1 2 PCIE_CRX_GTX_N7 CV22 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N7 AK19 PEX_TX7 R4 VGA_CRT_CLK
RV126 @ 0_0402_5% PCIE_CRX_GTX_P8 CV24 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_P8 AK20 PEX_TX7_N I2CA_SCL R5 VGA_CRT_DATA
PCIE_CRX_GTX_N8 CV26 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_N8 AJ20 PEX_TX8 I2CA_SDA
PEX_TX8_N
2

OPT@ PCIE_CRX_GTX_P9 CV21 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_P9 AH20 R7 I2CB_SCL

QV1A PCIE_CRX_GTX_N9 CV23 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_N9 AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA
VGA_SMB_DA2 1 6 PCIE_CRX_GTX_P10 CV25 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_P10 AK21 PEX_TX9_N I2CB_SDA NVVDD_PSI 1 OPT@ 2

I2C
EC_SMB_DA2 <15,39,42> PCIE_CRX_GTX_N10 1 2 PCIE_CRX_C_GTX_N10 AJ21 PEX_TX10 R2 VGA_EDID_CLK
CV27 0.22U_0402_6.3V K @ RV201 100K_0402_5%
2N7002KDWH_SOT363-6 PCIE_CRX_GTX_P11 CV29 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_P11 AL22 PEX_TX10_N I2CC_SCL R3 VGA_EDID_DATA
PCIE_CRX_GTX_N11 CV31 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_N11 AK22 PEX_TX11 I2CC_SDA
PCIE_CRX_GTX_P12 CV33 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_P12 AK23 PEX_TX11_N T4 VGA_SMB_CK2
PCIE_CRX_GTX_N12 CV28 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_N12 AJ23 PEX_TX12 I2CS_SCL T3 VGA_SMB_DA2
PCIE_CRX_GTX_P13 CV30 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_P13 AH23 PEX_TX12_N I2CS_SDA
PCIE_CRX_GTX_N13 CV32 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_N13 AG23 PEX_TX13 +1.05VS_VGA
PCIE_CRX_GTX_P14 1 2 PCIE_CRX_C_GTX_P14 AK24 PEX_TX13_N
PU AT EC SIDE, +3VS AND 4.7K CV36 0.22U_0402_6.3V K @
PEX_TX14 30 ohms @100MHz (ESR=0.05)
PCIE_CRX_GTX_N14 CV41 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_N14 AJ24
PCIE_CRX_GTX_P15 CV34 1 2 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_P15 AL25 PEX_TX14_N R10
1 2 AK25 PEX_TX15 60mA
PCIE_CRX_GTX_N15 CV35 0.22U_0402_6.3V K @ PCIE_CRX_C_GTX_N15 +PLLVDD LV7 1 OPT@ 2 0_0402_5%
PEX_TX15_N

22U_0805_6.3V6M
+3VS_VGA

0.1U_0402_16V7K

OPT@ CV131

OPT@ CV40
AD8 RV112 1 @ 2 1 1 S SUPPRE_CHILISIN PBY100505T-300Y-N 0402
AJ11 PLLVDD 0_0402_5%
PEX_WAKE_N AE8
45mA SM01000F100
CLK_PCIE_VGA AL13 SP_PLLVDD
B
<15> CLK_PCIE_VGA
CLK_PCIE_VGA# AK13 PEX_REFCLK AD7
45mA +SP_PLLVDD 2 2 Near GPU B
<15> CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD
CLK_REQ_GPU# AK12

CLK
PEX_CLKREQ_N
Differential signal 1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN
PEX_TSTCLK_OUT XTAL_IN
5

RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 H2 XTAL_OUT R02

2 PEX_TSTCLK_OUT_N XTAL_OUT Remove RV232
P

<18,36,37,42> PLT_RST# B 4 PLT_RST_VGA# AJ12 J4 XTALOUT

1 Y PEX_TERMP AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN close to YV1
<18,23> DGPU_HOLD_RST# A PEX_TERMP XTAL_SSIN
G

1
OPT@ 1 2 GCLK_27MHZ
3

GCLK_27MHZ <44>
OPT@ UV2 RV18 RV26 RV27 RV231 0_0402_5%
2

MC74VHC1G08DFT2G_SC70-5 100K_0402_5% 10K_0402_5% 10K_0402_5% OPTGCLK@

RV22 N13P-GL-A1 MP OPT@ OPT@
2.49K_0402_1%
Under GPU
2

2
OPT@ U65 GV2@
1

Under GPU(below 150mils)

OPT@ 150mA
RV29 10K_0402_5% N14P-GV2-B-A2 OPT@
2 1 SA00006B510 1 2 +SP_PLLVDD
<18,23,25,42> DGPU_PWR_EN +1.05VS_VGA

22U_0805_6.3V6M

CV113

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
LV1
+3VS_VGA

OPT@ CV112

CV4

CV5
BLM18PG330SN1D_0603 1 1 1 1
1 180ohms (ESR=0.2) Bead
OPTNOGCLK@

OPT@

OPT@

OPT@
CV42 1 2
2

0.1U_0402_16V7K RV23 10M_0402_5% 2 2 2 2

OPT@ 2 RV30
10K_0402_5%
2
G

OPT@ YV1
4 3 XTAL_OUT
1

A 1 3 CLK_REQ_GPU# NC OSC A
<15> CLK_REQ_VGA#
XTALIN 1 2
D

OSC NC
2

QV2 OPT@ 1 27MHZ_16PF_X3G027000FG1H-HX 1

2N7002K_SOT23-3 @ RV32 OPTNOGCLK@
10K_0402_5% OPTNOGCLK@ CV37 CV38 OPTNOGCLK@
10P_0402_50V8J 10P_0402_50V8J
1 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
1

RV110 @ 0_0402_5%
Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-PCIE/DAC/GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 23 of 62
5 4 3 2 1
 5 4 3 2 1

U65D @

Part 4 of 7
AM6
AN6 IFPA_TXC P8
AP3 IFPA_TXC_N NC AC6
AN3 IFPA_TXD0 NC AJ28
AN5 IFPA_TXD0_N NC AJ4
AM5 IFPA_TXD1 NC AJ5
AL6 IFPA_TXD1_N NC AL11
AK6 IFPA_TXD2 NC C15
IFPA_TXD2_N NC

NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
D IFPA_TXD3_N NC D23 D
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
AM7 IFPB_TXD4_N
AL7 IFPB_TXD5
AN8 IFPB_TXD5_N
AM8 IFPB_TXD6
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <54>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <54>
AJ2
AH3 IFPC_L1_N
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
AG4 IFPC_L3 differential signal routing.
IFPC_L3_N
TEST
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
AM3 IFPD_L0_N AM10
IFPD_L1 JTAG_TCK TV2

1
AM4 AM11
IFPD_L1_N JTAG_TDI TV3
AL3 AP12
IFPD_L2 JTAG_TDO TV4 10K_0402_5%
C AL4 AP11 C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
AK5 IFPD_L3 JTAG_TRST_N RV34 OPT@ 10K_0402_5% OPT@

2
IFPD_L3_N

LVDS/TMDS
AD2
AD3 IFPE_L0
AD1 IFPE_L0_N
AC1 IFPE_L1 SERIAL
AC2 IFPE_L1_N H6 ROM_CS
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK
IFPE_L2_N ROM_SCLK ROM_SCLK <32>
AC4 H5 ROM_SI ROM_SI <32>
AC5 IFPE_L3 ROM_SI H7 ROM_SO
IFPE_L3_N ROM_SO ROM_SO <32>

AE3
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 OPT@ 1
AG1 IFPF_L2_N BUFRST_N
AF1 IFPF_L3 L3 1 2
IFPF_L3_N CEC +3VS_VGA
RV230 @ 10K_0402_5%
J1 1 2
MULTI_STRAP_REF0_GND RV38 OPT@ 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N J2 STRAP0
STRAP0 STRAP0 <32>
J7 STRAP1 STRAP1 <32>
B
AK3 STRAP1 J6 STRAP2 B
IFPD_AUX_I2CX_SCL STRAP2 STRAP2 <32>
AK2 J5 STRAP3 STRAP3 <32>
IFPD_AUX_I2CX_SDA_N STRAP3 J3 STRAP4
STRAP4 STRAP4 <32>
AB3
AB4 IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N K3
THERMDP K4
AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
Reserve 1MB SPI ROM FOR VBIOS ROM
+3VS_VGA
CV295
N13P-GL-A1 MP
2 1 20mils

1
0.1U_0402_16V7K
@ RV229 @ @ RV225
10K_0402_5% 10K_0402_5%

2
@ RV224 0_0402_5% UV15
ROM_CS 1 2 ROM_CS_R 1 8
ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 ROM_HOLD#
@ RV226 0_0402_5% 3 DO HOLD# 6
4 W P# CLK 5 @ RV228 0_0402_5%
GND DIO ROM_SCLK_R 1 2 ROM_SCLK
A MX25L1005AMC-12G_SO8 ROM_SI_R 1 2 ROM_SI A
@ @ RV227 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 24 of 62
5 4 3 2 1
 5 4 3 2 1

+1.5VS_VGA U65E @
Near GPU
Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
D AA27 AG19 D
FBVDDQ_0 PEX_IOVDD_0

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
OPT@ CV273

OPT@ CV269

OPT@ CV270

OPT@ CV271

OPT@ CV272

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
OPT@ CV43

OPT@ CV44

OPT@ CV45

OPT@ CV46

OPT@ CV47

OPT@ CV48

OPT@ CV49

OPT@ CV50

OPT@ CV51

OPT@ CV52
1 2 2 2 2 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 1 1 1 1 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
+1.5VS_VGA AG27 FBVDDQ_7 AG13
0.1uF X7R 0402 * 8 FBVDDQ_8 PEX_IOVDDQ_0
4.7uF X7R 0402 * 2 B13 AG15 Under GPU(below 150mils)
B16 FBVDDQ_9 PEX_IOVDDQ_1 AG16 +1.05VS_VGA
FBVDDQ_10 PEX_IOVDDQ_2 For N13P-GS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Under GPU(below 150mils) B19 AG18
FBVDDQ_11 PEX_IOVDDQ_3

OPT@ CV54

OPT@ CV53

OPT@ CV56

OPT@ CV55
1uF X7R 0402 * 2 E13 AG25 1 1 1 1
E16 FBVDDQ_12 PEX_IOVDDQ_4 AH15
FBVDDQ_13 PEX_IOVDDQ_5
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
E19 AH18 DGPU_PWR_EN#
FBVDDQ_14 PEX_IOVDDQ_6
1U_0402_6.3V6K

1U_0402_6.3V6K
OPT@ CV267

OPT@ CV268

OPT@ CV277

OPT@ CV278

OPT@ CV279

OPT@ CV280

OPT@ CV292

OPT@ CV287

OPT@ CV294

OPT@ CV284

OPT@ CV285

OPT@ CV286
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 H10 AH26
H11 FBVDDQ_15 PEX_IOVDDQ_7 AH27 2 2 2 2 +VDD33MISC +3VS_VGA
FBVDDQ_16 PEX_IOVDDQ_8

2
G
H12 AJ27 DMG2301U-7_SOT23-3 QV8
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27
2 2 2 2 2 2 2 2 2 2 2 2 H14 FBVDDQ_18 PEX_IOVDDQ_10 AL27 +VDD33MISC 3 1

POWER
FBVDDQ_19 PEX_IOVDDQ_11

0.1U_0402_16V7K

0.1U_0402_16V7K
H15 AM28

D
FBVDDQ_20 PEX_IOVDDQ_12

OPT@ CV105
OPT@ CV72
H16 AN28 Under GPU(below 150mils) 1 1 OPT@
H18 FBVDDQ_21 PEX_IOVDDQ_13
H19 FBVDDQ_22 +3VS_VGA
H20 FBVDDQ_23
FBVDDQ_24 2 2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H21 AH12 +PEX_PLLHVDD RV138 1 OPT@ 2 0_0402_5%
FBVDDQ_25 PEX_PLL_HVDD

OPT@ CV70

OPT@ CV74

OPT@ CV73
H22 1 1 1
H23 FBVDDQ_26
H24 FBVDDQ_27
H8 FBVDDQ_28 AG12 +PEX_SVDD3V3
H9 FBVDDQ_29 PEX_SVDD_3V3 2 2 2
rise 1.5v system source voltage to 1.55-1.57V L27 FBVDDQ_30
FBVDDQ_31
M27
N27 FBVDDQ_32 AG26 +PEX_PLLVDD
P27 FBVDDQ_33 PEX_PLLVDD
C
R27 FBVDDQ_34 +VDD33MISC C
T27 FBVDDQ_35
T30 FBVDDQ_36 J8 +3VS_VGA
T33 FBVDDQ_37 VDD33_0 K8
FBVDDQ_38 VDD33_1 Place near balls Place near GPUR20
V27 L8
W27 FBVDDQ_39 VDD33_2 M8 +VDD33 RV5 2 @ 1 0_0603_5%
FBVDDQ_40 VDD33_3

0.1U_0402_16V7K

0.1U_0402_16V7K

4.7U_0603_6.3V6K
W30 LV2
+1.5VS_VGA FBVDDQ_41

1U_0402_6.3V6K
OPT@ CV109

OPT@ CV111

OPT@ CV293

OPT@ CV75
W33 1 1 1 1
Y27 FBVDDQ_42 @
FBVDDQ_43 AH8 +IFPAB_PLLVDD1 RV48 2 10K_0402_5%
IFPAB_PLLVDD AJ8 RV40@1 2 1K_0402_1%
10_0402_5% 2 @ 1 RV141 FB_VDDQ_SENSE IFPAB_RSET @ 2 2 2 2 OPT@
AG8 +IFPAB_IOVDD 1 RV65 2 10K_0402_5% 0_0603_5%
IFPA_IOVDD AG9
10_0402_5% 2 @ 1 RV142 FB_VSS_SENSE F1 IFPB_IOVDD
FB_VDDQ_SENSE @ CV5 Place Under GPU +1.05VS_VGA
AF7 +IFPC_PLLVDD 1 RV42 2 10K_0402_5%
+1.5VS_VGA F2 IFPC_PLLVDD AF8 RV43@2 1 1K_0402_1% Reserve for NV DG LV2 @
FB_GND_SENSE IFPC_RSET @ +PEX_PLLVDD 120mA 2 1

0.1U_0402_16V7K

1U_0402_6.3V6K

CV66
4.7U_0603_6.3V6K
AF6 +IFPC_IOVDD 1 RV44 2 10K_0402_5% +VDD33
IFPC_IOVDD

0.1U_0402_16V7K

0.1U_0402_16V7K

OPT@ CV65

CV3
1 OPT@ 2 J27 1 1 1 BLM18PG121SN1D_0603
FB_CAL_PD_VDDQ

CV303

CV304
RV6 40.2_0402_1% @ 120ohms @100MHz (ESR=0.18)
CALIBRATION PIN DDR3 AG7 +IFPD_PLLVDD 1 RV45 2 10K_0402_5%
1 1
IFPD_PLLVDD

OPT@

OPT@

OPT@
1 OPT@ 2 H27 AN2 RV46@1 2 1K_0402_1%
FB_CAL_PU_GND IFPD_RSET 2 2 2

OPT@
RV8 42.2_0402_1% @
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD 1 RV47 2 10K_0402_5% 2 2
1 OPT@ 2 H25 IFPD_IOVDD
RV9 51.1_0402_1% FB_CAL_TERM_GND @
FB_CAL_x_PU_GND 42.2Ohm AB8 +IFPEF_PLLVDD1 RV72 2 10K_0402_5% CV3 ,CV66 Place near balls
IFPEF_PLVDD AD6 RV50@1 2 1K_0402_1%
IFPEF_RSET
FB_CAL_xTERM_GND 51.1Ohm Place near balls AC7 @ Inc 2pcs 0.1u
IFPE_IOVDD AC8 +IFPE_IOVDD1 RV73 2 10K_0402_5%
IFPF_IOVDD following DG
B B

N13P-GL-A1 MP
+3VS to +3VS_VGA

+3VS +3VS_VGA
J10

@
1 2
1 2

JUMP_43X79
+5VALW
QV5 CV57
LP2301ALT1G_SOT23 10U_0603_6.3V6M

1
DGPU_PWR_EN

D
3 1 2 1
R1103

1
1K_0402_5% OPT@ OPT@
OPT@

G
2

2
RV205 RV206
R02 DGPU_PWR_EN# 1 2 150_0603_5%
1

R1452 10K_0402_5% GV2@

1 2
1
0_0402_5% D OPT@ 1 CV241
R5596 2 @ 1 2 Q128 0.1U_0402_16V7K D RV207 GV2@
<18,23,42> DGPU_PWR_EN
150_0603_5% G 2N7002K_SOT23-3 2 2 1DGPU_PWR_EN#
GV2@ S OPT@ OPT@ G
2

3
2 QV6 S 0_0402_5%

3
1
GV2@
R1105
1

0.1U_0402_16V7K
@ CV242
100K_0402_5% 2N7002K_SOT23-3 1
GV2@ 2 SUSP <10,46,51,54> OPT@

2
G
A A
S Q157
3

2N7002K_SOT23-3 2

for DGPU_PWR_EN discharge 11/13

Security Classification
2012/12/26
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 25 of 62
5 4 3 2 1
 5 4 3 2 1

U65F @

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10 U65G @ +VGA_CORE
AA22 GND_3 GND_103 E22 +VGA_CORE
AB12 GND_4 GND_104 E25
AB14 GND_5 GND_105 E5 Part 7 of 7 V17
AB16 GND_6 GND_106 E7 AA12 VDD_56 V18
AB19 GND_7 GND_107 F28 AA14 VDD_0 VDD_57 V20
AB2 GND_8 GND_108 F7 AA16 VDD_1 VDD_58 V22
AB21 GND_9 GND_109 G10 AA19 VDD_2 VDD_59 W 12
D
A33 GND_10 GND_110 G13 AA21 VDD_3 VDD_60 W 14 D
AB23 GND_11 GND_111 G16 AA23 VDD_4 VDD_61 W 16
AB28 GND_12 GND_112 G19 AB13 VDD_5 VDD_62 W 19
AB30 GND_13 GND_113 G2 AB15 VDD_6 VDD_63 W 21
AB32 GND_14 GND_114 G22 AB17 VDD_7 VDD_64 W 23
AB5 GND_15 GND_115 G25 AB18 VDD_8 VDD_65 Y13
AB7 GND_16 GND_116 G28 AB20 VDD_9 VDD_66 Y15
AC13 GND_17 GND_117 G3 AB22 VDD_10 VDD_67 Y17
AC15 GND_18 GND_118 G30 AC12 VDD_11 VDD_68 Y18
AC17 GND_19 GND_119 G32 AC14 VDD_12 VDD_69 Y20
AC18 GND_20 GND_120 G33 AC16 VDD_13 VDD_70 Y22
AA13 GND_21 GND_121 G5 AC19 VDD_14 VDD_71
AC20 GND_22 GND_122 G7 AC21 VDD_15
AC22 GND_23 GND_123 K2 AC23 VDD_16 U1
AE2 GND_24 GND_124 K28 M12 VDD_17 XVDD_1 U2
AE28 GND_25 GND_125 K30 M14 VDD_18 XVDD_2 U3
GND_26 GND_126 VDD_19 XVDD_3

POWER
AE30 K32 M16 U4
AE32 GND_27 GND_127 K33 M19 VDD_20 XVDD_4 U5
AE33 GND_28 GND_128 K5 M21 VDD_21 XVDD_5 U6
AE5 GND_29 GND_129 K7 M23 VDD_22 XVDD_6 U7
AE7 GND_30 GND_130 M13 N13 VDD_23 XVDD_7 U8
AH10 GND_31 GND_131 M15 N15 VDD_24 XVDD_8
AA15 GND_32 GND_132 M17 N17 VDD_25
AH13 GND_33 GND_133 M18 N18 VDD_26 V1
AH16 GND_34 GND_134 M20 N20 VDD_27 XVDD_9 V2
AH19 GND_35 GND_135 M22 N22 VDD_28 XVDD_10 V3
AH2 GND_36 GND_136 N12 P12 VDD_29 XVDD_11 V4
AH22 GND_37 GND_137 N14 P14 VDD_30 XVDD_12 V5
AH24 GND_38 GND_138 N16 P16 VDD_31 XVDD_13 V6
AH28 GND_39 GND_139 N19 P19 VDD_32 XVDD_14 V7
C C
AH29 GND_40 GND_140 N2 P21 VDD_33 XVDD_15 V8
AH30 GND_41 GND_141 N21 P23 VDD_34 XVDD_16
AH32 GND_42 GND_142 N23 R13 VDD_35
GND
AH33 GND_43 GND_143 N28 R15 VDD_36 W2
AH5 GND_44 GND_144 N30 R17 VDD_37 XVDD_17 W3
AH7 GND_45 GND_145 N32 R18 VDD_38 XVDD_18 W4
AJ7 GND_46 GND_146 N33 R20 VDD_39 XVDD_19 W5
AK10 GND_47 GND_147 N5 R22 VDD_40 XVDD_20 W7
AK7 GND_48 GND_148 N7 T12 VDD_41 XVDD_21 W8
AL12 GND_49 GND_149 P13 T14 VDD_42 XVDD_22
AL14 GND_50 GND_150 P15 T16 VDD_43
AL15 GND_51 GND_151 P17 T19 VDD_44 Y1
AL17 GND_52 GND_152 P18 T21 VDD_45 XVDD_23 Y2
AL18 GND_53 GND_153 P20 T23 VDD_46 XVDD_24 Y3
AL2 GND_54 GND_154 P22 U13 VDD_47 XVDD_25 Y4
AL20 GND_55 GND_155 R12 U15 VDD_48 XVDD_26 Y5
AL21 GND_56 GND_156 R14 U17 VDD_49 XVDD_27 Y6
AL23 GND_57 GND_157 R16 U18 VDD_50 XVDD_28 Y7
AL24 GND_58 GND_158 R19 U20 VDD_51 XVDD_29 Y8
AL26 GND_59 GND_159 R21 U22 VDD_52 XVDD_30
AL28 GND_60 GND_160 R23 V13 VDD_53
AL30 GND_61 GND_161 T13 V15 VDD_54 AA1
AL32 GND_62 GND_162 T15 VDD_55 XVDD_31 AA2
AL33 GND_63 GND_163 T17 XVDD_32 AA3
AL5 GND_64 GND_164 T18 XVDD_33 AA4
AM13 GND_65 GND_165 T2 XVDD_34 AA5
AM16 GND_66 GND_166 T20 XVDD_35 AA6
AM19 GND_67 GND_167 T22 XVDD_36 AA7
AM22 GND_68 GND_168 AG11 XVDD_37 AA8
B
AM25 GND_69 GND_169 T28 XVDD_38 B
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12 N13P-GL-A1 MP
AN19 GND_74 GND_174 U14
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W 13
B25 GND_86 GND_186 W 15
B28 GND_87 GND_187 W 17
B31 GND_88 GND_188 W 18
B34 GND_89 GND_189 W 20
B4 GND_90 GND_190 W 22
B7 GND_91 GND_191 W 28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
A A
GND_99 GND_199 C16
GND_OPT W 32
GND_OPT

N13P-GL-A1 MP Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13-VGA CORE, GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 26 of 62
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] FBA_MA[15..0] <28,29> FBC_D[0..63] FBC_MA[15..0] <30,31>

<28,29> FBA_D[0..63] <30,31> FBC_D[0..63]
FBA_BA[2..0] <28,29> FBC_BA[2..0] <30,31>

U65C @
U65B @
Part 3 of 7
Part 2 of 7 FBC_D0 G9 D13 FBC_CS0#_L
FBB_D0 FBB_CMD0 FBC_CS0#_L <30>
FBA_D0 L28 U30 FBA_CS0#_L FBC_D1 E9 E14
FBA_D0 FBA_CMD0 FBA_CS0#_L <28> FBB_D1 FBB_CMD1
FBA_D1 M29 T31 FBC_D2 G8 F14 FBC_ODT_L
FBA_D1 FBA_CMD1 FBB_D2 FBB_CMD2 FBC_ODT_L <30>
FBA_D2 L29 U29 FBA_ODT_L FBC_D3 F9 A12 FBC_CKE_L
FBA_D2 FBA_CMD2 FBA_ODT_L <28> FBB_D3 FBB_CMD3 FBC_CKE_L <30>
FBA_D3 M28 R34 FBA_CKE_L FBC_D4 F11 B12 FBC_MA14
FBA_D3 FBA_CMD3 FBA_CKE_L <28> FBB_D4 FBB_CMD4
FBA_D4 N31 R33 FBA_MA14 FBC_D5 G11 C14 FBC_RST#
D FBA_D4 FBA_CMD4 FBB_D5 FBB_CMD5 FBC_RST# <30,31> D
FBA_D5 P29 U32 FBA_RST# FBC_D6 F12 B14 FBC_MA9
FBA_D5 FBA_CMD5 FBA_RST# <28,29> FBB_D6 FBB_CMD6
FBA_D6 R29 U33 FBA_MA9 FBC_D7 G12 G15 FBC_MA7
FBA_D7 P28 FBA_D6 FBA_CMD6 U28 FBA_MA7 FBC_D8 G6 FBB_D7 FBB_CMD7 F15 FBC_MA2
FBA_D8 J28 FBA_D7 FBA_CMD7 V28 FBA_MA2 FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA0
FBA_D9 H29 FBA_D8 FBA_CMD8 V29 FBA_MA0 FBC_D10 E6 FBB_D9 FBB_CMD9 D15 FBC_MA4
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA4 FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1
FBA_D11 H28 FBA_D10 FBA_CMD10 U34 FBA_MA1 FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_BA0
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_BA0 FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_WE#
FBA_D12 FBA_CMD12 FBB_D13 FBB_CMD13 FBC_WE# <30,31>
FBA_D13 E31 V34 FBA_WE# FBC_D14 E2 B15 FBC_MA15
FBA_D13 FBA_CMD13 FBA_WE# <28,29> FBB_D14 FBB_CMD14
FBA_D14 E32 V33 FBA_MA15 FBC_D15 F3 C17 FBC_CAS#
FBA_D14 FBA_CMD14 FBB_D15 FBB_CMD15 FBC_CAS# <30,31>
FBA_D15 F30 Y32 FBA_CAS# FBC_D16 C2 D18 FBC_CS0#_H
FBA_D15 FBA_CMD15 FBA_CAS# <28,29> FBB_D16 FBB_CMD16 FBC_CS0#_H <31>
FBA_D16 C34 AA31 FBA_CS0#_H FBC_D17 D4 E18
FBA_D16 FBA_CMD16 FBA_CS0#_H <29> FBB_D17 FBB_CMD17
FBA_D17 D32 AA29 FBC_D18 D3 F18 FBC_ODT_H
FBA_D17 FBA_CMD17 FBB_D18 FBB_CMD18 FBC_ODT_H <31>
FBA_D18 B33 AA28 FBA_ODT_H FBC_D19 C1 A20 FBC_CKE_H
FBA_D18 FBA_CMD18 FBA_ODT_H <29> FBB_D19 FBB_CMD19 FBC_CKE_H <31>
FBA_D19 C33 AC34 FBA_CKE_H FBC_D20 B3 B20 FBC_MA13
FBA_D19 FBA_CMD19 FBA_CKE_H <29> FBB_D20 FBB_CMD20
FBA_D20 F33 AC33 FBA_MA13 FBC_D21 C4 C18 FBC_MA8
FBA_D21 F32 FBA_D20 FBA_CMD20 AA32 FBA_MA8 FBC_D22 B5 FBB_D21 FBB_CMD21 B18 FBC_MA6
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA6 FBC_D23 C5 FBB_D22 FBB_CMD22 G18 FBC_MA11
FBA_D23 H32 FBA_D22
FBA_D23
FBA_CMD22
FBA_CMD23
Y28 FBA_MA11 FBC_D24 A11 FBB_D23
FBB_D24
FBB_CMD23
FBB_CMD24
G17 FBC_MA5 Mode D - Mirror Mode Mapping
MEMORY INTERFACE

FBA_D24 P34 Y29 FBA_MA5 FBC_D25 C11 F17 FBC_MA3

MEMORY INTERFACE B
FBA_D25 P32 FBA_D24 FBA_CMD24 W31 FBA_MA3 FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_BA2
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_BA2 FBC_D27 B11 FBB_D26 FBB_CMD26 A18 FBC_BA1
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_BA1 FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_MA12
FBA_D27 FBA_CMD27 FBB_D28 FBB_CMD28 DATA Bus
FBA_D28 L31 Y31 FBA_MA12 FBC_D29 A8 A17 FBC_MA10
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_MA10 FBC_D30 C8 FBB_D29 FBB_CMD29 B17 FBC_RAS# Address
FBA_D29 FBA_CMD29 FBB_D30 FBB_CMD30 FBC_RAS# <30,31> 0..31 32..63
FBA_D30 L32 Y33 FBA_RAS# FBC_D31 B8 E17
FBA_D30 FBA_CMD30 FBA_RAS# <28,29> FBB_D31 FBB_CMD31
FBA_D31 L33 V31 FBC_D32 F24 FBx_CMD0 CS0#_L
FBA_D32 AG28 FBA_D31 FBA_CMD31 FBC_D33 G23 FBB_D32
FBA_D33 AF29 FBA_D32 FBC_D34 E24 FBB_D33
FBA_D33 FBB_D34 FBx_CMD1
FBA_D34 AG29 FBC_D35 G24 C12
FBA_D35 AF28 FBA_D34 R32 FBC_D36 D21 FBB_D35 FBB_CMD_RFU0 C20
FBA_D35 FBA_CMD_RFU0 FBB_D36 FBB_CMD_RFU1 FBx_CMD2 ODT_L
FBA_D36 AD30 AC32 FBC_D37 E21
C FBA_D37 AD29 FBA_D36 FBA_CMD_RFU1 +1.5VS_VGA FBC_D38 G21 FBB_D37 +1.5VS_VGA C
FBA_D37 FBB_D38 FBx_CMD3 CKE_L
FBA_D38 AC29 FBC_D39 F21
FBA_D39 AD28 FBA_D38 FBC_D40 G27 FBB_D39 G14 RV60 1 @ 2 60.4_0402_1%
FBA_D39 FBB_D40 FBB_DEBUG0 FBx_CMD4 A14 A14
A

FBA_D40 AJ29 R28 RV58 1 @ 2 60.4_0402_1% FBC_D41 D27 G20 RV61 1 @ 2 60.4_0402_1%
FBA_D41 AK29 FBA_D40 FBA_DEBUG0 AC28 RV59 1 @ 2 60.4_0402_1% FBC_D42 G26 FBB_D41 FBB_DEBUG1
FBA_D41 FBA_DEBUG1 FBB_D42 can be unstuff by default FBx_CMD5 RST RST
FBA_D42 AJ30 can be unstuff by default FBC_D43 E27
FBA_D43 AK28 FBA_D42 FBC_D44 E29 FBB_D43
FBA_D43 FBB_D44 FBx_CMD6 A9 A9
FBA_D44 AM29 FBC_D45 F29 D12 FBC_CLK0
FBA_D44 FBB_D45 FBB_CLK0 FBC_CLK0 <30>
FBA_D45 AM31 R30 FBA_CLK0 FBC_D46 E30 E12 FBC_CLK0# FBx_CMD7 A7 A7
FBA_D45 FBA_CLK0 FBA_CLK0 <28> FBB_D46 FBB_CLK0_N FBC_CLK0# <30>
FBA_D46 AN29 R31 FBA_CLK0# FBC_D47 D30 E20 FBC_CLK1
FBA_D46 FBA_CLK0_N FBA_CLK0# <28> FBB_D47 FBB_CLK1 FBC_CLK1 <31>
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D48 A32 F20 FBC_CLK1# FBx_CMD8 A2 A2
FBA_D47 FBA_CLK1 FBA_CLK1 <29> FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D48 AN31 AC31 FBA_CLK1# FBC_D49 C31
FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBB_D49
FBA_D49 AN32 FBC_D50 C32 FBx_CMD9 A0 A0
FBA_D50 AP30 FBA_D49 FBC_D51 B32 FBB_D50
FBA_D51 AP32 FBA_D50 FBC_D52 D29 FBB_D51 F8
FBA_D51 FBB_D52 FBB_WCK01 FBx_CMD10 A4 A4
FBA_D52 AM33 K31 FBC_D53 A29 E8
FBA_D53 AL31 FBA_D52 FBA_WCK01 L30 FBC_D54 C29 FBB_D53 FBB_WCK01_N A5
FBA_D53 FBA_WCK01_N FBB_D54 FBB_WCK23 FBx_CMD11 A1 A1
FBA_D54 AK33 H34 FBC_D55 B29 A6
FBA_D55 AK32 FBA_D54 FBA_WCK23 J34 FBC_D56 B21 FBB_D55 FBB_WCK23_N D24
FBA_D55 FBA_WCK23_N FBB_D56 FBB_WCK45 FBx_CMD12 BA0 BA0
FBA_D56 AD34 AG30 FBC_D57 C23 D25
FBA_D57 AD32 FBA_D56 FBA_WCK45 AG31 FBC_D58 A21 FBB_D57 FBB_WCK45_N B27
FBA_D57 FBA_WCK45_N FBB_D58 FBB_WCK67 FBx_CMD13 WE# WE#
FBA_D58 AC30 AJ34 FBC_D59 C21 C27
FBA_D59 AD33 FBA_D58 FBA_WCK67 AK34 FBC_D60 B24 FBB_D59 FBB_WCK67_N
FBA_D59 FBA_WCK67_N FBB_D60 FBx_CMD14 A15 A15
FBA_D60 AF31 FBC_D61 C24
FBA_D61 AG34 FBA_D60 +1.05VS_VGA +FB_PLLAVDD FBC_D62 B26 FBB_D61
FBA_D61 FBB_D62 FBx_CMD15 CAS# CAS#
FBA_D62 AG32 Place close to BGA FBC_D63 C26 D6
FBA_D63 AG33 FBA_D62 J30 FBB_D63 FBB_WCKB01 D7
FBA_D63 FBA_WCKB01 200mA FBB_WCKB01_N FBx_CMD16 CS0#_H
J31 FBMA-L11-160808300LMA25T_2P FBC_DQM0 E11 C6
FBA_DQM0 P30 FBA_WCKB01_N J32 1 2 +FB_PLLAVDD FBC_DQM1 E3 FBB_DQM0 FBB_WCKB23 B6
FBA_DQM0 FBA_WCKB23 FBB_DQM1 FBB_WCKB23_N FBx_CMD17
FBA_DQM1 F31 J33 LV3 OPT@ FBC_DQM2 A3 F26
FBA_DQM2 F34 FBA_DQM1 FBA_WCKB23_N AH31 FBC_DQM3 C9 FBB_DQM2 FBB_WCKB45 E26
FBA_DQM2 FBA_WCKB45 FBB_DQM3 FBB_WCKB45_N FBx_CMD18 ODT_H
FBA_DQM3 M32 AJ31 FBC_DQM4 F23 A26
B FBA_DQM4 AD31 FBA_DQM3 FBA_WCKB45_N AJ32 from EC FBC_DQM5 F27 FBB_DQM4 FBB_WCKB67 A27 B
FBA_DQM4 FBA_WCKB67 FBB_DQM5 FBB_WCKB67_N FBx_CMD19 CKE_H
FBA_DQM5 AL29 AJ33 GC6_EN 1 GC6@ 2 FBC_DQM6 C30
FBA_DQM5 FBA_WCKB67_N GC6_FB_CLAMP <23,42,46> FBB_DQM6
FBA_DQM6 AM32 RV7 0_0402_5% FBC_DQM7 A24 FBx_CMD20 A13 A13
FBA_DQM7 AF34 FBA_DQM6 FBB_DQM7
FBA_DQM7 RV66 10K_0402_5% FBC_DQS0 D10
FBB_DQS_WP0 FBx_CMD21 A8 A8
FBA_DQS0 M31 E1 2 OPT@ 1 FBC_DQS1 D5
FBA_DQS1 G31 FBA_DQS_WP0 FB_CLAMP FBC_DQS2 C3 FBB_DQS_WP1
FBA_DQS_WP1 +FB_PLLAVDD FBB_DQS_WP2 FBx_CMD22 A6 A6
FBA_DQS2 E33 FBC_DQS3 B9
FBA_DQS3 M33 FBA_DQS_WP2 CV106 OPT@ 0.1U_0402_16V7K FBC_DQS4 E23 FBB_DQS_WP3 H17
FBA_DQS_WP3 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD FBx_CMD23 A11 A11
FBA_DQS4 AE31 K27 1 2 FBC_DQS5 E28

0.1U_0402_16V7K
FBA_DQS_WP4 FB_DLL_AVDD FBB_DQS_WP5

OPT@ CV108
FBA_DQS5 AK30 FBC_DQS6 B30 1 FBx_CMD24 A5 A5
FBA_DQS6 AN33 FBA_DQS_WP5 FBC_DQS7 A23 FBB_DQS_WP6
FBA_DQS_WP6
Place close to ball FBB_DQS_WP7
FBA_DQS7 AF33 FBx_CMD25 A3 A3
FBA_DQS_WP7 U27 FBC_DQS#0 D9
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_RN0 2
FBA_DQS#0 M30 FBC_DQS#1 E4 FBx_CMD26 BA2 BA2
22U_0805_6.3V6M
0.1U_0402_16V7K

FBA_DQS_RN0 FBB_DQS_RN1
OPT@ CV107

OPT@ CV110

OPT@ CV39

FBA_DQS#1 H30 FBC_DQS#2 B2

1U_0402_6.3V6K

FBA_DQS_RN1 1 1 1 FBB_DQS_RN2
FBA_DQS#2 E34 FBC_DQS#3 A9 FBx_CMD27 BA1 BA1
FBA_DQS#3 M34 FBA_DQS_RN2 H26 FBC_DQS#4 D22 FBB_DQS_RN3
FBA_DQS#4 AF30 FBA_DQS_RN3 FB_VREF FBC_DQS#5 D28 FBB_DQS_RN4
FBA_DQS_RN4 2 2 2 FBB_DQS_RN5
Place close to ball FBx_CMD28 A12 A12
FBA_DQS#5 AK31 FBC_DQS#6 A30
FBA_DQS#6 AM34 FBA_DQS_RN5 FBC_DQS#7 B23 FBB_DQS_RN6
FBA_DQS_RN6 FBB_DQS_RN7 FBx_CMD29 A10 A10
FBA_DQS#7 AF32
FBA_DQS_RN7
FBx_CMD30 RAS# RAS#
Place close to ball Place close to BGA
N13P-GL-A1 MP
N13P-GL-A1 MP

<30,31> FBC_DQM[7..0]
<28,29> FBA_DQM[7..0] <30,31> FBC_DQS[7..0]
A <28,29> FBA_DQS[7..0] <30,31> FBC_DQS#[7..0] A
<28,29> FBA_DQS#[7..0] 30ohms (ESR=0.01) Bead
P/N;SM010007W00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 27 of 62
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits FBA_MA[15..0] <27,29>

FBA_D[0..63] <27,29>

FBA_BA[2..0] <27,29>
UV3 @ UV4 @

+1.5VS_VGA FBA_DQM[7..0] <27,29>

+FBA_VREF0 M8 E3 FBA_D4 +FBA_VREF0 M8 E3 FBA_D19
H1 VREFCA DQL0 F7 FBA_D1 H1 VREFCA DQL0 F7 FBA_D20
D VREFDQ DQL1 VREFDQ DQL1 FBA_DQS[7..0] <27,29>D
F2 FBA_D7 F2 FBA_D17
DQL2 DQL2
1

FBA_MA0 N3 F8 FBA_D0 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1)

A0 DQL3 A0 DQL3 FBA_DQS#[7..0] <27,29>
RV79 FBA_MA1 P7 H3 FBA_D6 Group0 (IN3) FBA_MA1 P7 H3 FBA_D16
1.1K_0402_1% FBA_MA2 P3 A1 DQL4 H8 FBA_D3 FBA_MA2 P3 A1 DQL4 H8 FBA_D23
OPT@ FBA_MA3 N2 A2 DQL5 G2 FBA_D5 FBA_MA3 N2 A2 DQL5 G2 FBA_D18
FBA_MA4 P8 A3 DQL6 H7 FBA_D2 FBA_MA4 P8 A3 DQL6 H7 FBA_D22 CMD mapping mod Mode D
2

+FBA_VREF0 FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7

FBA_MA6 R8 A5 FBA_MA6 R8 A5
A6 A6
1

1 FBA_MA7 R2 D7 FBA_D29 FBA_MA7 R2 D7 FBA_D10 DATA Bus

RV68 CV118 FBA_MA8 T8 A7 DQU0 C3 FBA_D25 FBA_MA8 T8 A7 DQU0 C3 FBA_D15
1.1K_0402_1% 0.01U_0402_16V7K FBA_MA9 R3 A8 DQU1 C8 FBA_D28 FBA_MA9 R3 A8 DQU1 C8 FBA_D8 Address
A9 DQU2 A9 DQU2 0..31 32..63
OPT@ OPT@ FBA_MA10 L7 C2 FBA_D26 FBA_MA10 L7 C2 FBA_D13 Group1 (TOP)
2 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D31 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D9
Group3 (BOT) FBx_CMD0 CS0#_L
2

FBA_MA12 N7 A11 DQU4 A2 FBA_D24 FBA_MA12 N7 A11 DQU4 A2 FBA_D12

FBA_MA13 T3 A12 DQU5 B8 FBA_D30 FBA_MA13 T3 A12 DQU5 B8 FBA_D11
A13 DQU6 A13 DQU6 FBx_CMD1
FBA_MA14 T7 A3 FBA_D27 FBA_MA14 T7 A3 FBA_D14
FBA_MA15 M7 A14 DQU7 FBA_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD2 ODT_L
FBx_CMD3 CKE_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD D9 FBA_BA1 N8 BA0 VDD D9
BA1 VDD BA1 VDD FBx_CMD4 A14 A14
FBA_CLK0 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD K2 BA2 VDD K2
VDD VDD FBx_CMD5 RST RST
K8 K8
VDD VDD
2

N1 N1 FBx_CMD6 A9 A9
RV80 FBA_CLK0 J7 VDD N9 FBA_CLK0 J7 VDD N9
<27> FBA_CLK0 CK VDD CK VDD
C 160_0402_1% FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 FBx_CMD7 A7 A7 C
<27> FBA_CLK0# CK VDD CK VDD
OPT@ FBA_CKE_L K9 R9 FBA_CKE_L K9 R9
<27> FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD8 A2 A2
1

FBA_CLK0# FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD9 A0 A0

<27> FBA_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8
<27> FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD10 A4 A4
<27,29> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBA_ODT_L
<27,29> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD11 A1 A1
<27,29> FBA_WE# WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1 FBA_CKE_L
VDDQ VDDQ FBx_CMD12 BA0 BA0
FBA_DQS0 F3 H2 FBA_DQS2 F3 H2
FBA_DQS3 C7 DQSL VDDQ H9 FBA_DQS1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ FBx_CMD13 WE# WE#

2
RV67 RV76 FBx_CMD14 A15 A15
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5%
FBA_DQM3 D3 DML VSS B3 FBA_DQM1 D3 DML VSS B3 OPT@ OPT@
DMU VSS DMU VSS FBx_CMD15 CAS# CAS#
E1 E1

1
VSS G8 VSS G8
VSS VSS FBx_CMD16 CS0#_H
FBA_DQS#0 G3 J2 FBA_DQS#2 G3 J2
FBA_DQS#3 B7 DQSL VSS J8 FBA_DQS#1 B7 DQSL VSS J8
DQSU VSS DQSU VSS FBx_CMD17
M1 M1
VSS M9 VSS M9
VSS VSS FBx_CMD18 ODT_H
P1 P1
FBA_RST# T2 VSS P9 FBA_RST# T2 VSS P9
<27,29> FBA_RST# RESET VSS RESET VSS FBx_CMD19 CKE_H
T1 T1 UV3 UV3 UV3 UV3 UV3
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD20 A13 A13
B B
FBx_CMD21 A8 A8
1

1
J1 B1 J1 B1
NC/ODT1 VSSQ NC/ODT1 VSSQ
1

RV78 RV77 L1 B9 RV69 L1 B9 FBx_CMD22 A6 A6

10K_0402_5% J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ Samsung Micron Samsung Micron Hynix
OPT@ OPT@ L9 D8 OPT@ L9 D8 S2@ M2@ S1@ M1@ H1@ FBx_CMD23 A11 A11
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 SA000068R00 SA000065D00 SA000068U00 SA000067500 SA00003YOI0
2

2
VSSQ E8 VSSQ E8 FBx_CMD24 A5 A5
2

VSSQ F9 VSSQ F9 UV4 UV4 UV4 UV4 UV4

VSSQ G1 VSSQ G1
VSSQ VSSQ FBx_CMD25 A3 A3
G9 G9
VSSQ VSSQ
FBx_CMD26 BA2 BA2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD27 BA1 BA1
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 Samsung Micron Samsung Micron Hynix
S2@ M2@ S1@ M1@ H1@ FBx_CMD28 A12 A12
SA000068R00 SA000065D00 SA000068U00 SA000067500 SA00003YOI0
FBx_CMD29 A10 A10
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE
FBx_CMD30 RAS# RAS#
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
OPT@ CV119

OPT@ CV120

OPT@ CV121

OPT@ CV123

OPT@ CV162

OPT@ CV159

OPT@ CV134

OPT@ CV129

OPT@ CV160

OPT@ CV133

OPT@ CV132

OPT@ CV164

@ CV136

OPT@ CV163

OPT@ CV137

OPT@ CV135

@ CV155

@ CV138

OPT@ CV142

OPT@ CV158
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 28 of 62
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 FBA_D[0..63] <27,28>

bits FBA_MA[15..0] <27,28>
UV5 @ UV6 @
+1.5VS_VGA
FBA_BA[2..0] <27,28>
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63
H1 VREFCA DQL0 F7 FBA_D34 H1 VREFCA DQL0 F7 FBA_D58
VREFDQ DQL1 VREFDQ DQL1 FBA_DQM[7..0] <27,28>
1 F2 FBA_D37 F2 FBA_D60
RV70 FBA_MA0 N3 DQL2 F8 FBA_D35 FBA_MA0 N3 DQL2 F8 FBA_D59
A0 DQL3 A0 DQL3 FBA_DQS[7..0] <27,28>
D 1.1K_0402_1% FBA_MA1 P7 H3 FBA_D39 Group4 (IN1) FBA_MA1 P7 H3 FBA_D61 Group7 (IN3) D
OPT@ FBA_MA2 P3 A1 DQL4 H8 FBA_D32 FBA_MA2 P3 A1 DQL4 H8 FBA_D56
A2 DQL5 A2 DQL5 FBA_DQS#[7..0] <27,28>
FBA_MA3 N2 G2 FBA_D38 FBA_MA3 N2 G2 FBA_D62
2

+FBA_VREF1 FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA4 P8 A3 DQL6 H7 FBA_D57

FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7
A5 A5
1

FBA_MA6 R8 FBA_MA6 R8
RV82
1
CV178 FBA_MA7 R2 A6
A7 DQU0
D7 FBA_D45 FBA_MA7 R2 A6
A7 DQU0
D7 FBA_D55 CMD mapping mod Mode D
1.1K_0402_1% 0.01U_0402_16V7K FBA_MA8 T8 C3 FBA_D42 FBA_MA8 T8 C3 FBA_D51
OPT@ OPT@ FBA_MA9 R3 A8 DQU1 C8 FBA_D46 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
2 A9 DQU2 A9 DQU2 DATA Bus
FBA_MA10 L7 C2 FBA_D41 Group5 (TOP) FBA_MA10 L7 C2 FBA_D49
2

FBA_MA11 R7 A10/AP DQU3 A7 FBA_D47 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D52 Address

A11 DQU4 A11 DQU4 Group6 (BOT) 0..31 32..63
FBA_MA12 N7 A2 FBA_D43 FBA_MA12 N7 A2 FBA_D50
FBA_MA13 T3 A12 DQU5 B8 FBA_D44 FBA_MA13 T3 A12 DQU5 B8 FBA_D53
A13 DQU6 A13 DQU6 FBx_CMD0 CS0#_L
FBA_MA14 T7 A3 FBA_D40 FBA_MA14 T7 A3 FBA_D48
FBA_MA15 M7 A14 DQU7 FBA_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD1
FBx_CMD2 ODT_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD D9 FBA_BA1 N8 BA0 VDD D9
BA1 VDD BA1 VDD FBx_CMD3 CKE_L
FBA_CLK1 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD K2 BA2 VDD K2
VDD VDD FBx_CMD4 A14 A14
K8 K8
VDD VDD
2

N1 N1 FBx_CMD5 RST RST

RV83 FBA_CLK1 J7 VDD N9 FBA_CLK1 J7 VDD N9
<27> FBA_CLK1 CK VDD CK VDD
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1 FBx_CMD6 A9 A9
<27> FBA_CLK1# CK VDD CK VDD
OPT@ FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
<27> FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD7 A7 A7
1

C C
FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD8 A2 A2
<27> FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
<27> FBA_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD9 A0 A0
<27,28> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9
<27,28> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD10 A4 A4
<27,28> FBA_WE# WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD11 A1 A1
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 C7 DQSL VDDQ H9 FBA_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ FBx_CMD12 BA0 BA0
FBx_CMD13 WE# WE#
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 D3 DML VSS B3 FBA_DQM6 D3 DML VSS B3
DMU VSS DMU VSS FBx_CMD14 A15 A15
E1 E1
VSS G8 VSS G8
VSS VSS FBx_CMD15 CAS# CAS#
FBA_DQS#4 G3 J2 UV5 UV5 UV5 UV5 UV5 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS J8 FBA_DQS#6 B7 DQSL VSS J8
DQSU VSS DQSU VSS FBx_CMD16 CS0#_H
M1 M1
FBA_CKE_H VSS M9 VSS M9
VSS VSS FBx_CMD17
P1 P1
FBA_RST# T2 VSS P9 FBA_RST# T2 VSS P9
<27,28> FBA_RST# RESET VSS RESET VSS FBx_CMD18 ODT_H
FBA_ODT_H T1 Samsung Micron Samsung Micron Hynix T1
L8 VSS T9 S2@ M2@ S1@ M1@ H1@ L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD19 CKE_H
SA000068R00 SA000065D00 SA000068U00 SA000067500 SA00003YOI0
FBx_CMD20 A13 A13
1

1
RV84 RV87 J1 B1 UV6 UV6 UV6 UV6 UV6 J1 B1
10K_0402_5% 10K_0402_5% RV86 L1 NC/ODT1 VSSQ B9 RV85 L1 NC/ODT1 VSSQ B9
B NC/CS1 VSSQ NC/CS1 VSSQ FBx_CMD21 A8 A8 B
OPT@ OPT@ 243_0402_1% J9 D1 243_0402_1% J9 D1
OPT@ L9 NC/CE1 VSSQ D8 OPT@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ NCZQ1 VSSQ FBx_CMD22 A6 A6
E2 E2
2

2
VSSQ E8 VSSQ E8
VSSQ VSSQ FBx_CMD23 A11 A11
F9 Samsung Micron Samsung Micron Hynix F9
VSSQ G1 S2@ M2@ S1@ M1@ H1@ VSSQ G1
VSSQ VSSQ FBx_CMD24 A5 A5
G9 SA000068R00 SA000065D00 SA000068U00 SA000067500 SA00003YOI0 G9
VSSQ VSSQ
FBx_CMD25 A3 A3
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD26 BA2 BA2
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
+1.5VS_VGA UV5 SIDE +1.5VS_VGA UV6 SIDE
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
OPT@ CV145

OPT@ CV174

OPT@ CV296

OPT@ CV301

OPT@ CV291

OPT@ CV302

OPT@ CV299

OPT@ CV290

OPT@ CV300

OPT@ CV297

OPT@ CV298

OPT@ CV165

OPT@ CV177

@ CV170

OPT@ CV166

OPT@ CV172

@ CV169

@ CV180

OPT@ CV167

OPT@ CV171
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 29 of 62
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits FBC_D[0..63]

FBC_MA[15..0]
<27,31>

<27,31>

FBC_BA[2..0] <27,31>

FBC_DQM[7..0] <27,31>
+1.5VS_VGA UV7 @ UV8 @
FBC_DQS[7..0] <27,31>
+FBB_VREF0 M8 E3 FBC_D4 +FBB_VREF0 M8 E3 FBC_D16
VREFCA DQL0 VREFCA DQL0 FBC_DQS#[7..0] <27,31>
1
D
H1 F7 FBC_D3 H1 F7 FBC_D21 D
RV111 VREFDQ DQL1 F2 FBC_D7 VREFDQ DQL1 F2 FBC_D18
1.1K_0402_1% FBC_MA0 N3 DQL2 F8 FBC_D0 N3 DQL2 F8
A0 DQL3 Group0 (IN3)FBC_MA0 A0 DQL3
FBC_D17
@ FBC_MA1 P7 H3 FBC_D5 FBC_MA1 P7 H3 FBC_D20 Group2 (IN1)
FBC_MA2 P3 A1 DQL4 H8 FBC_D1 FBC_MA2 P3 A1 DQL4 H8 FBC_D23 CMD mapping mod Mode D
2

+FBB_VREF0 FBC_MA3 N2 A2 DQL5 G2 FBC_D6 FBC_MA3 N2 A2 DQL5 G2 FBC_D19

FBC_MA4 P8 A3 DQL6 H7 FBC_D2 FBC_MA4 P8 A3 DQL6 H7 FBC_D22
A4 DQL7 A4 DQL7
1

1 FBC_MA5 P2 FBC_MA5 P2 DATA Bus

RV115 CV202 FBC_MA6 R8 A5 FBC_MA6 R8 A5
1.1K_0402_1% 0.01U_0402_16V7K FBC_MA7 R2 A6 D7 FBC_D28 FBC_MA7 R2 A6 D7 FBC_D8 Address
A7 DQU0 A7 DQU0 0..31 32..63
@ @ FBC_MA8 T8 C3 FBC_D27 FBC_MA8 T8 C3 FBC_D15
2 FBC_MA9 R3 A8 DQU1 C8 FBC_D31 FBC_MA9 R3 A8 DQU1 C8 FBC_D11 FBx_CMD0 CS0#_L
2

FBC_MA10 L7 A9 DQU2 C2 FBC_D25 FBC_MA10 L7 A9 DQU2 C2 FBC_D12

FBC_MA11 R7 A10/AP DQU3 A7 FBC_D29 R7 A10/AP DQU3 A7
A11 DQU4 Group3 (BOT)FBC_MA11 A11 DQU4
FBC_D9 Group1 (TOP) FBx_CMD1
FBC_MA12 N7 A2 FBC_D24 FBC_MA12 N7 A2 FBC_D13
FBC_MA13 T3 A12 DQU5 B8 FBC_D30 FBC_MA13 T3 A12 DQU5 B8 FBC_D10
A13 DQU6 A13 DQU6 FBx_CMD2 ODT_L
FBC_MA14 T7 A3 FBC_D26 FBC_MA14 T7 A3 FBC_D14
FBC_MA15 M7 A14 DQU7 FBC_MA15 M7 A14 DQU7
A15/BA3 A15/BA3 FBx_CMD3 CKE_L
+1.5VS_VGA +1.5VS_VGA
FBx_CMD4 A14 A14
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 N8 BA0 VDD D9 FBC_BA1 N8 BA0 VDD D9
BA1 VDD BA1 VDD FBx_CMD5 RST RST
FBC_CLK0 FBC_BA2 M3 G7 FBC_BA2 M3 G7
BA2 VDD K2 BA2 VDD K2
VDD VDD FBx_CMD6 A9 A9
K8 K8
VDD VDD
2

310mA N1 N1 FBx_CMD7 A7 A7
RV89 FBC_CLK0 J7 VDD N9 FBC_CLK0 J7 VDD N9
<27> FBC_CLK0 CK VDD CK VDD
C 160_0402_1% FBC_CLK0# K7 R1 FBC_CLK0# K7 R1 FBx_CMD8 A2 A2 C
<27> FBC_CLK0# CK VDD CK VDD
@ FBC_CKE_L K9 R9 FBC_CKE_L K9 R9
<27> FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD9 A0 A0
1

FBC_CLK0# FBC_ODT_L K1 A1 FBC_ODT_L K1 A1 FBx_CMD10 A4 A4

<27> FBC_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CS0#_L L2 A8 FBC_CS0#_L L2 A8
<27> FBC_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD11 A1 A1
<27,31> FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
<27,31> FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD12 BA0 BA0
<27,31> FBC_WE# WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD13 WE# WE#
FBC_DQS0 F3 H2 FBC_DQS2 F3 H2
FBC_DQS3 C7 DQSL VDDQ H9 FBC_DQS1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ FBx_CMD14 A15 A15
FBx_CMD15 CAS# CAS#
FBC_DQM0 E7 A9 FBC_DQM2 E7 A9
FBC_DQM3 D3 DML VSS B3 FBC_DQM1 D3 DML VSS B3 FBC_ODT_L
DMU VSS DMU VSS FBx_CMD16 CS0#_H
E1 E1
VSS G8 VSS G8
VSS VSS FBx_CMD17
FBC_DQS#0 G3 J2 FBC_DQS#2 G3 J2 FBC_CKE_L
FBC_DQS#3 B7 DQSL VSS J8 FBC_DQS#1 B7 DQSL VSS J8
DQSU VSS DQSU VSS FBx_CMD18 ODT_H
M1 M1
VSS M9 VSS M9
VSS VSS FBx_CMD19 CKE_H

1
P1 P1 RV117 RV116
FBC_RST# T2 VSS P9 FBC_RST# T2 VSS P9 10K_0402_5% 10K_0402_5%
<27,31> FBC_RST# RESET VSS RESET VSS FBx_CMD20 A13 A13
T1 T1 @ @
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD21 A8 A8
B B

2
FBx_CMD22 A6 A6
1

1
J1 B1 J1 B1
NC/ODT1 VSSQ NC/ODT1 VSSQ
1

RV91 RV90 L1 B9 RV88 L1 B9 FBx_CMD23 A11 A11

10K_0402_5% J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
@ @ L9 D8 @ L9 D8 FBx_CMD24 A5 A5
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 FBx_CMD25 A3 A3
2

VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ VSSQ FBx_CMD26 BA2 BA2
G9 G9
VSSQ VSSQ
FBx_CMD27 BA1 BA1
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD28 A12 A12
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VS_VGA UV7 SIDE +1.5VS_VGA UV8 SIDE
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
@ CV191

@ CV183

@ CV199

@ CV189

@ CV205

@ CV188

@ CV190

@ CV206

@ CV181

@ CV182

@ CV185

@ CV194

@ CV192

@ CV203

@ CV195

@ CV184

@ CV187

@ CV198

@ CV200

@ CV201

@ CV204

@ CV193
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM C Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 30 of 62
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

FBC_D[0..63] <27,30>

FBC_MA[15..0] <27,30>

FBC_BA[2..0] <27,30>
UV9 @

+1.5VS_VGA FBC_DQM[7..0] <27,30>

+FBB_VREF1 M8 E3 FBC_D39
H1 VREFCA DQL0 F7 FBC_D33 UV10 @
D VREFDQ DQL1 FBC_DQS[7..0] <27,30>D
F2 FBC_D38
DQL2
1

FBC_MA0 N3 F8 FBC_D32 +FBB_VREF1 M8 E3 FBC_D60

A0 DQL3 VREFCA DQL0 FBC_DQS#[7..0] <27,30>
RV120 FBC_MA1 P7 H3 FBC_D36 Group4 (IN1) H1 F7 FBC_D57
FBC_MA2 P3 A1 DQL4 H8 FBC_D35 VREFDQ DQL1 F2 FBC_D63
1.1K_0402_1% FBC_MA3 N2 A2 DQL5 G2 FBC_D37 FBC_MA0 N3 DQL2 F8 FBC_D58
@ FBC_MA4 P8 A3 DQL6 H7 FBC_D34 FBC_MA1 P7 A0 DQL3 H3 FBC_D61 Group7 (IN3) CMD mapping mod Mode D
2

+FBB_VREF1 FBC_MA5 P2 A4 DQL7 FBC_MA2 P3 A1 DQL4 H8 FBC_D56

FBC_MA6 R8 A5 FBC_MA3 N2 A2 DQL5 G2 FBC_D62
A6 A3 DQL6
1

1 FBC_MA7 R2 D7 FBC_D47 FBC_MA4 P8 H7 FBC_D59 DATA Bus

RV127 CV229 FBC_MA8 T8 A7 DQU0 C3 FBC_D43 FBC_MA5 P2 A4 DQL7
1.1K_0402_1% 0.01U_0402_16V7K FBC_MA9 R3 A8 DQU1 C8 FBC_D46 FBC_MA6 R8 A5 Address
A9 DQU2 A6 0..31 32..63
@ @ FBC_MA10 L7 C2 FBC_D42 FBC_MA7 R2 D7 FBC_D54
2 FBC_MA11 R7 A10/AP DQU3 A7 FBC_D40 FBC_MA8 T8 A7 DQU0 C3 FBC_D51
Group5 (TOP) FBx_CMD0 CS0#_L
2

FBC_MA12 N7 A11 DQU4 A2 FBC_D45 FBC_MA9 R3 A8 DQU1 C8 FBC_D55

FBC_MA13 T3 A12 DQU5 B8 FBC_D44 FBC_MA10 L7 A9 DQU2 C2 FBC_D49
A13 DQU6 A10/AP DQU3 FBx_CMD1
FBC_MA14 T7 A3 FBC_D41 FBC_MA11 R7 A7 FBC_D52 Group6 (BOT)
FBC_MA15 M7 A14 DQU7 FBC_MA12 N7 A11 DQU4 A2 FBC_D50
A15/BA3 A12 DQU5 FBx_CMD2 ODT_L
+1.5VS_VGA FBC_MA13 T3 B8 FBC_D53
FBC_MA14 T7 A13 DQU6 A3 FBC_D48
A14 DQU7 FBx_CMD3 CKE_L
FBC_BA0 M2 B2 FBC_MA15 M7
FBC_BA1 N8 BA0 VDD D9 A15/BA3 +1.5VS_VGA
BA1 VDD FBx_CMD4 A14 A14
FBC_BA2 M3 G7
FBC_CLK1 BA2 VDD K2 FBC_BA0 M2 B2
VDD BA0 VDD FBx_CMD5 RST RST
K8 FBC_BA1 N8 D9
VDD N1 FBC_BA2 M3 BA1 VDD G7
VDD BA2 VDD FBx_CMD6 A9 A9
2

FBC_CLK1 J7 N9 K2
<27> FBC_CLK1 CK VDD VDD
C RV129 FBC_CLK1# K7 R1 K8 FBx_CMD7 A7 A7 C
<27> FBC_CLK1# CK VDD VDD
160_0402_1% FBC_CKE_H K9 R9 N1
<27> FBC_CKE_H CKE/CKE0 VDD VDD
@ FBC_CLK1 J7 N9 FBx_CMD8 A2 A2
FBC_CLK1# K7 CK VDD R1
1

FBC_ODT_H K1 A1 FBC_CKE_H K9 CK VDD R9

<27> FBC_ODT_H ODT/ODT0 VDDQ CKE/CKE0 VDD FBx_CMD9 A0 A0
FBC_CLK1# FBC_CS0#_H L2 A8
<27> FBC_CS0#_H CS/CS0 VDDQ
FBC_RAS# J3 C1 FBx_CMD10 A4 A4
<27,30> FBC_RAS# RAS VDDQ
FBC_CAS# K3 C9 FBC_ODT_H K1 A1
<27,30> FBC_CAS# CAS VDDQ ODT/ODT0 VDDQ
FBC_WE# L3 D2 FBC_CS0#_H L2 A8 FBx_CMD11 A1 A1
<27,30> FBC_WE# WE VDDQ CS/CS0 VDDQ
E9 FBC_RAS# J3 C1
VDDQ F1 FBC_CAS# K3 RAS VDDQ C9
VDDQ CAS VDDQ FBx_CMD12 BA0 BA0
FBC_DQS4 F3 H2 FBC_WE# L3 D2
FBC_DQS5 C7 DQSL VDDQ H9 WE VDDQ E9
DQSU VDDQ VDDQ FBx_CMD13 WE# WE#
F1
FBC_DQS7 F3 VDDQ H2
DQSL VDDQ FBx_CMD14 A15 A15
FBC_DQM4 E7 A9 FBC_DQS6 C7 H9
FBC_DQM5 D3 DML VSS B3 DQSU VDDQ
DMU VSS FBx_CMD15 CAS# CAS#
E1
VSS G8 FBC_DQM7 E7 A9
VSS DML VSS FBx_CMD16 CS0#_H
FBC_DQS#4 G3 J2 FBC_DQM6 D3 B3
FBC_DQS#5 B7 DQSL VSS J8 DMU VSS E1
DQSU VSS VSS FBx_CMD17
FBC_ODT_H M1 G8
VSS M9 FBC_DQS#7 G3 VSS J2
VSS DQSL VSS FBx_CMD18 ODT_H
P1 FBC_DQS#6 B7 J8
FBC_CKE_H FBC_RST# T2 VSS P9 DQSU VSS M1
<27,30> FBC_RST# RESET VSS VSS FBx_CMD19 CKE_H
T1 M9
L8 VSS T9 VSS P1
ZQ/ZQ0 VSS VSS FBx_CMD20 A13 A13
1

B RV118 RV119 FBC_RST# T2 P9 B

10K_0402_5% 10K_0402_5% RESET VSS T1
VSS FBx_CMD21 A8 A8
1

@ @ J1 B1 L8 T9
RV123 L1 NC/ODT1 VSSQ B9 ZQ/ZQ0 VSS
NC/CS1 VSSQ FBx_CMD22 A6 A6
243_0402_1% J9 D1
2

NC/CE1 VSSQ

1
@ L9 D8 J1 B1 FBx_CMD23 A11 A11
NCZQ1 VSSQ E2 RV128 L1 NC/ODT1 VSSQ B9
2

VSSQ E8 J9 NC/CS1 VSSQ D1

VSSQ 243_0402_1% NC/CE1 VSSQ FBx_CMD24 A5 A5
F9 @ L9 D8
VSSQ G1 NCZQ1 VSSQ E2 FBx_CMD25 A3 A3

2
VSSQ G9 VSSQ E8
VSSQ VSSQ F9
VSSQ FBx_CMD26 BA2 BA2
96-BALL G1
SDRAM DDR3 VSSQ G9
VSSQ FBx_CMD27 BA1 BA1
K4W1G1646E-HC12_FBGA96
96-BALL FBx_CMD28 A12 A12
SDRAM DDR3
K4W1G1646E-HC12_FBGA96 FBx_CMD29 A10 A10
+1.5VS_VGA UV9 SIDE +1.5VS_VGA UV10 SIDE
FBx_CMD30 RAS# RAS#
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
@ CV209

@ CV227

@ CV213

@ CV233

@ CV226

@ CV207

@ CV230

@ CV220

@ CV228

@ CV225

@ CV210

@ CV208

@ CV223

@ CV211

@ CV222

@ CV224

@ CV214

@ CV215

@ CV217
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM C Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 31 of 62
5 4 3 2 1
 5 4 3 2 1

+3VS_VGA Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG/PCI_DEVID[5] PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]

2
RV92 GV2@ RV93 @ RV94 @ RV121 @ RV122 @ ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
45.3K_0402_1% 45.3K_0402_1% 30.1K_0402_1% 20K_0402_1% 20K_0402_1%
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]

1
STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
D <24> STRAP0 STRAP0 D
<24> STRAP1 STRAP1 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP4 STRAP4
STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
2 CHANGE_GEN3

2
RV95 @ RV96 GV2@ RV97 GV2@ RV124 GV2@ RV125 GV2@
45.3K_0402_1% 45.3K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1% Pull-up to
Resistor Values +3VS_VGA Pull-down to Gnd Vendor VRAM Sturcture
1

1
5K 1000 0000 Samsung 2G S2@
10K 1001 0001 Micron 2G M2@
15K 1010 0010 Samsung 1G S1@
+3VS_VGA 20K Micron 1G
1011 0011 M1@
25K 1100 0100
30K 1101 0101
35K 1110 0110
2

2
C C
RV98 45K 1111 0111
4.99K_0402_1% RV99 GV2@ RV100 GV2@
@ 4.99K_0402_1% 4.99K_0402_1%
1

SUB_VENDOR 3GIO_PADCFG
1

<24> ROM_SI ROM_SI RV101 S1@ ZZZ1

<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM_SCLK 0 No VBIOS ROM 3GIO_PADCFG[3:0]
2

1 BIOS ROM is present (Default) 0110 Notebook Default

RV101 RV102 @ RV103 @ 45.3K_0402_1% Samsung
X76 20K_0402_1% 10K_0402_1% 15K_0402_1% SD034453280 S1_GV2@
S2@ X7643238L09
FB_0_BAR_SIZE SLOT_CLK_CFG
1

RV101 M1@ ZZZ2

0 Reserved 0 GPU and MCH don't share a common reference clock

1 Reserved 1 GPU and MCH share a common reference clock (Default)

30.1K_0402_1% Micron
SD034301280 M1_GV2@ 2 256MB (Default)
X7643238L10 SMBUS_ALT_ADDR
RV101 H1@ ZZZ5 3 Reserved 0 0x9E (Default)
B B

USER Straps 1 0x9C (Multi-GPU usage)

34.8K_0402_1% Hynix User[3:0]

SD034348280 H1_GV2@
X7643238L08
1000-1100 Customer defined
ZZZ3

PEX_PLL_EN_TERM XCLK_417
0 Disable (Default) 0 277MHz (Default)
Samsung
S2_GV2@
X7643238L11 1 Enable 1 Reserved
RV101 M2@ ZZZ4
PCIE_MAX_SPEED VGA_DEVICE
0 Limit to PCIE Gen1 0 3D Device (Class Code 302h)
10K_0402_1% Micron
SD034100280 M2_GV2@ 1 PCIE Gen 2/3 Capable 1 VGA Device (Default)
A A
X7643238L12

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X_MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 32 of 62
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+LCDVDD +5VALW +3VS
+3VS
W=60mils
(20 MIL)
1 CMOS@ +3VS_CMOS
Q83

1
R400 R401 C513
150_0603_1% 100K_0402_5% 4.7U_0603_6.3V6K PMV65XP_SOT23-3~D R02 (20 MIL)
D R296 D
2

D
3 1 2 @ 1 10U
R403 1

2
1

3
D 220K_0402_5%
S
CMOS@ 0_0603_5%
G
2 1 2 2 Q80 C518

G
2
Q79 G PMV65XP_SOT23-3~D 0.1U_0402_16V7K
2N7002K_SOT23-3 R435 CMOS@ 2
S 1
D
W=60mils

1
1
C515 150K_0402_5%
0.1U_0402_16V7K 4.7V

OUT
<42> CMOS_ON#
2 +LCDVDD +LCDVDD_CONN
L29 1
<17> PCH_ENVDD 2 R296 for CMOS shake issue reserve
IN 1 2 C520 CMOS@

GND
0.1U_0402_16V7K
Q81 DTC124EK FBMA-L11-201209-221LMA30T_0805 2
1

DTC124EKAT146_SC59-3 1 1

3
C516 C517
@ R408 4.7U_0603_6.3V6K 0.1U_0402_16V7K
100K_0402_5%
2 2
2

+3VS VGA LCD/PANEL BD. Conn.

R02
+LEDVDD B+
1 R02
C R433 @ R813 0_0805_5% C
1 2
R717 4.7K_0402_5% 1
0_0402_5%
2

BKOFF# 1 @ 2 DISPOFF# C541

<42> BKOFF# 4.7U_0805_25V6-K
2
1

R02
R716 JLVDS1 ME@
10K_0402_5% 1
2 1 41
3 2 G1 42
2

R03 4 3 G2 43
5 4 G3 44
R02 R447 1 @ 2 0_0402_5% 6 5 G4 45
R538 1 @ 2 0_0402_5% @ DISPOFF# 7 6 G5 46
<17> PCH_ENBKL ENBKL <42> 7 G6
R430 1 2 0_0402_5% INVT_PWM 8
<17> PCH_PWM 8
9
R30 10 9
<17> LVDS_BCLK 10
<42> EC_INVT_PWM R431 1 2 0_0402_5% <17> LVDS_BCLK# 11
11
2

<17> LVDS_B2 12
R438 13 12
<17> LVDS_B2# 13
100K_0402_1% <17> LVDS_B1 14
15 14
<17> LVDS_B1# 15
<17> LVDS_B0 16
1

17 16
<17> LVDS_B0# 17
18
19 18
B <17> LVDS_ACLK 19 B
20
<17> LVDS_ACLK# 20
21
<17> LVDS_A2 21
22
<17> LVDS_A2# 22
23
<17> LVDS_A1 23
24
<17> LVDS_A1# 24
25
<17> LVDS_A0 25
26
<17> LVDS_A0# 26
<17> EDID_DATA 27
28 27
<17> EDID_CLK 28
+3VS 29
30 29
+LCDVDD_CONN 30
(60 MIL) 31
32 31
33 32
+3VS 33
DMIC_DATA 34
<41> DMIC_DATA 34
DMIC_CLK 35
<41> DMIC_CLK 35
36
37 36
USB20_P3 38 37
<18> USB20_P3 38
<18> USB20_N3 USB20_N3 39
40 39
CMOS +3VS_CMOS 40
ACES_50203-04001-001

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 33 of 62
5 4 3 2 1
 A B C D E

1 1

+5VS
D10
+CRT_VCC
CRT Connector
F1
2 1 1 2 +CRT_VCC_F
1
RB491D_SC59-3
FCM1608CF-121T03 0603 1.1A_6V_SMD1812P110TF C521
1 2 RED
<17> DAC_RED
L30 W=40mils 2
0.1U_0402_16V7K

FCM1608CF-121T03 0603
1 2 GREEN
<17> DAC_GRN
L31
FCM1608CF-121T03 0603
1 2 BLUE
<17> DAC_BLU

C522

C523

C524

C525

C526

C527
L32 JCRT1

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1

1
1 1 1 1 1 1 6
PAD T66 NC11 11
R445 R443 R446 RED 1
150_0402_1% 150_0402_1% 150_0402_1% 7
2 2 2 2 2 2 CRT_DDC_DAT_CONN 12
2

2
GREEN 2
8
CLOSE TO CONN JVGA_HS 13
BLUE 3
9
JVGA_VS 14
4
2 10 G 16 2
+CRT_VCC CRT_DDC_CLK_CONN 15 G 17
R448
5
1 2 1
1 C528 ME@

2
C-H_13-12201557CP

0_0402_5%

0_0402_5%

0_0402_5%
1K_0402_5%

R437
C529 100P_0402_50V8J

0_0402_5%
2

R436

R434

R432
0.1U_0402_16V7K @ @ @ @
2
5

1
FCM1608CF-121T03 0603
OE#
P

2 4 CRT_HSYNC_1 1 2 JVGA_HS
<17> CRT_HSYNC A Y L33
G

U23
SN74AHCT1G125DCKR_SC70-5
EMI Request
3

+CRT_VCC
R451
1 2
1
C531 1K_0402_5%
0.1U_0402_16V7K
2
5

FCM1608CF-121T03 0603
OE#
P

2 4 CRT_VSYNC_1 1 2 JVGA_VS
3 <17> CRT_VSYNC A Y 3
L34
G

U24
SN74AHCT1G125DCKR_SC70-5
3

+CRT_VCC
+3VS
1

Pull high at chipset/VGA side R456 R457

5

2.2K_0402_5% 2.2K_0402_5%
2

<17> CRT_DDC_DATA 4 3 CRT_DDC_DAT_CONN

2N7002DW -T/R7_SOT363-6
2

Q62B

<17> CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN

4
2N7002DW -T/R7_SOT363-6 4
Q62A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: W ednesday, January 09, 2013 Sheet 34 of 62
A B C D E
 5 4 3 2 1

+5VS
W=40mils +5VS_HDMI
+5VS PMEG2010ET_SOT23-3 F2 HDMI@
+3VS D13 HDMI@ 1.1A_8V_SMD1812P110TF
2 1+HDMI_5V 1 2 +5VS_HDMI

2
1

2
C543
D R485 HDMI@ D
1M_0402_5% Q93 D14 @ 0.1U_0402_16V7K 2
HDMI@ HDMI@ BAT54S-7-F_SOT23-3

1
2
G
2N7002K_SOT23-3

1
TMDS_B_HPD# 3 1
<17> TMDS_B_HPD#

2
2
HDMI@ R483 R484 HDMI@
R488 2.2K_0402_5% 2.2K_0402_5%
20K_0402_5%

1
HDMI@
JHDMI1

1
HDMI_DET 19
18 HP_DET
+5VS_HDMI +5V
17
HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK-_CK R464 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 CEC 20
<17> HDMI_CLK-_CK CK- GND
11 21
<17> HDMI_CLK+_CK CK_shield GND
C
HDMI_CLK+_CKR465 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10
C
HDMI_TX0-_CK R466 1 @ 2 0_0402_5% HDMI_TX0-_CONN 9 CK+
<17> HDMI_TX0-_CK D0-
<17> HDMI_TX0+_CK 8
HDMI_TX0+_CK R467 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7 D0_shield
+3VS HDMI_TX1-_CK R468 1 @ 2 0_0402_5% HDMI_TX1-_CONN 6 D0+
<17> HDMI_TX1-_CK D1-
<17> HDMI_TX1+_CK 5
HDMI_TX1+_CK R469 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CK R470 1 @ 2 0_0402_5% HDMI_TX2-_CONN 3 D1+
<17> HDMI_TX2-_CK D2-
2

R02 2
<17> HDMI_TX2+_CK D2_shield
R783 HDMI_TX2+_CK R471 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1
D2+
0_0402_5%
@ ACON_HMR2H-AK120C
Pull up R for PCH OR VGA SIDE ME@
1

Q63A
HDMI@
2

2N7002KDWH_SOT363-6
L35 HDMI@
1 6 HDMICLK_R HDMI_CLK-_CK 1 2 HDMI_CLK-_CONN 680 +-5% 8P4R
<17> HDMICLK_NB 1 2 C982 1 2 0.1U_0402_16V7K @ HDMI_CLK-_CONN 5 4
5

HDMI_CLK+_CONN 6 3
HDMI_CLK+_CK 4 3 HDMI_CLK+_CONN HDMI_TX1-_CONN 7 2
4 3 HDMIDAT_R 4 3 C983 1 2 0.1U_0402_16V7K @ HDMI_TX1+_CONN 8 1
B <17> HDMIDAT_NB SD309680080 B
WCM-2012HS-900T_4P
Q63B RP5 HDMI@ S ROW RES 1/16W 680 +-5% 8P4R
HDMI@ L36 HDMI@
2N7002KDWH_SOT363-6 HDMI_TX0-_CK 1 2 HDMI_TX0-_CONN 680 +-5% 8P4R
1 2 C984 1 2 0.1U_0402_16V7K @ HDMI_TX0-_CONN 5 4
HDMI_TX0+_CONN 6 3
HDMI_TX0+_CK 4 3 HDMI_TX0+_CONN HDMI_TX2-_CONN 7 2
HDMIDAT_R 4 3 C985 1 2 0.1U_0402_16V7K @ HDMI_TX2+_CONN 8 1
WCM-2012HS-900T_4P +3VS
RP6 HDMI@

1
HDMICLK_R L37 HDMI@ D
HDMI_TX1-_CK 1 2 HDMI_TX1-_CONN 2
1 2 C986 1 2 0.1U_0402_16V7K @ G
S Q95

3
3

HDMI_TX1+_CK 4 3 HDMI_TX1+_CONN HDMI@

D11 @ 4 3 C987 1 2 0.1U_0402_16V7K @ 2N7002K_SOT23-3
YSLC05CH_SOT23-3 WCM-2012HS-900T_4P

L38 HDMI@
HDMI_TX2-_CK 1 2 HDMI_TX2-_CONN
1 2 C988 1 2 0.1U_0402_16V7K @

HDMI_TX2+_CK 4 3 HDMI_TX2+_CONN
1

A 4 3 C989 1 2 0.1U_0402_16V7K @ A
WCM-2012HS-900T_4P

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 35 of 62
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half)

R5550
+3VS_WLAN 0_0402_5%
USB20_N10_WLAN 1 @ 2 USB20_N10
USB20_N10 <18>

1 1
+3VS_WLAN C548 @ C547 USB20_P10_WLAN 1 @ 2 USB20_P10
1
Mini-Express
@
Card(WLAN/WiMAX) +1.5VS
4.7U_0603_6.3V6K 0.1U_0402_16V7K
0_0402_5%
USB20_P10 <18> 1

R1505 1 2 0_0402_5% EC_WL_WAKE#_R 2 2 R5551

<42,44> EC_WL_WAKE#
JWLN1
<16,37> PCIE_WAKE# PCIE_WAKE# R514 1 @ 2 0_0402_5% 1 2 for Intel AOAC function Reserved
BT_ACTIVE 1 R497 2 @ 0_0402_5% 3 1 2 4
<40> BT_ACTIVE 3 4
1 @ 2 BT_DISABLE_F_R R5580 1 @ 2 0_0402_5% BT_DISABLE_R 5 6
<19,40> PCH_BT_ON# 7 5 6 8
R892 0_0402_5% <15> CLKREQ_WLAN# LPC_FRAME#_R
1 @ 2 9 7 8 10 LPC_AD3_R
<19> BT_DISABLE 9 10
11 12 LPC_AD2_R
<15> CLK_PCIE_WLAN1# 13 11 12 14
Low - Disable R897 0_0402_5% LPC_AD1_R
<15> CLK_PCIE_WLAN1 13 14
R02 15 16 LPC_AD0_R
PCI_RST#_R 17 15 16 18 R02
1 @ 2 INTEL_BT_OFF#_R CLK_PCI_DB 19 17 18 20 R498 1 @ 2 0_0402_5%
19 20 PCH_WL_OFF# <18>
R893 1K_0402_1% 21 22
23 21 22 24 PLT_RST# <18,23,37,42>
R499 1 2 @ 0_0402_5%
+3VALW
<15> PCIE_PRX_DTX_N2 23 24
25 26 R500 1 @ 2 0_0402_5% +3VS_WLAN
1 2 <15> PCIE_PRX_DTX_P2 27 25 26 28 R02
<19> INTEL_BT_OFF# 27 28
R894 1K_0402_1% 29 30 1 R501 2 @ 0_0402_5% SMB_CLK_S3 <12,13,15,43>
R03 31 29 30 32 1 R502 2 @ 0_0402_5%
<15> PCIE_PTX_C_DRX_N2 31 32 SMB_DATA_S3 <12,13,15,43>
33 34
<15> PCIE_PTX_C_DRX_P2 33 34
35 36 USB20_N10_WLAN
+3VS_WLAN 37 35 36 38 USB20_P10_WLAN
39 37 38 40
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<42> EC_TX 49 50
1 2 51 52
<42> EC_RX 51 52
R506
R03 100_0402_1% 53 54
INTEL_BT_OFF#_R GND1 GND2 +3VS 80mil +3VS_WLAN
for Intel AOAC function
BELLW_80003-3041
ME@
R308 2 1 0_0805_5%
2 R02 NOAOAC@ 2

2
For EC to detect
R507
debug card insert. 100K_0402_5%
+3VALW
1

Q105 AO3413_SOT23-3

D
3 1 1
AOAC@
AOAC@ C536
0.1U_0402_16V7K

G
2
2
Reserve for SW mini-pcie debug card. <42> AOAC_ON#
1
Series resistors closed to KBC side. R439
150K_0402_5%
AOAC@
C537
AOAC@ 0.1U_0402_16V7K
LPC_FRAME#_R R508 1 @ 2 0_0402_5% LPC_FRAME# 2
LPC_FRAME# <14,42>
LPC_AD3_R R509 1 @ 2 0_0402_5% LPC_AD3
1 2 LPC_AD3 <14,42>
LPC_AD2_R R510 @ 0_0402_5% LPC_AD2
LPC_AD2 <14,42>
LPC_AD1_R R511 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 <14,42>
LPC_AD0_R R512 1 @ 2 0_0402_5% LPC_AD0
1 2 LPC_AD0 <14,42>
PCI_RST#_R R513 @ 0_0402_5% PLT_RST#
CLK_PCI_DB CLK_PCI_DB <18>

Mini-Express Card(SSD) SSD Active:4.5W(1.5A)

3 3
+3VS_SSD +3VS +3VS_SSD
J5
0.1U_0402_16V7K
1 2
1 2
1 1 1
C566@ C567@ C568 @ JUMP_43X79
@
2 2 2 JSSD1
1 2
0.01U_0402_16V7K 10U_0603_6.3V6M 3 1 2 4
5 3 4 6
11/07 Change type to 0603 5 6
7 8
9 7 8 10
11 9 10 12
13 11 12 14
15 13 14 16
17 15 16 18
19 17 18 20
0.01U_0402_16V7K @ 21 19 20 22
SATA_DTX_C_IRX_P0 2 1 C572 SATA_DTX_IRX_P0 23 21 22 24
<14> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 2 1 C573 SATA_DTX_IRX_N0 25 23 24 26
<14> SATA_DTX_C_IRX_N0 27 25 26 28
0.01U_0402_16V7K @ 29 27 28 30
SATA_ITX_DRX_N0 31 29 30 32
<14> SATA_ITX_DRX_N0 31 32
SATA_ITX_DRX_P0 33 34
<14> SATA_ITX_DRX_P0 33 34
35 36
37 35 36 38
+3VS_SSD 39 37 38 40
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50
R558 1 @ 2 0_0402_5% mSATA_DET#_R 51 49 50 52
<19> mSATA_DET# 51 52
4 For SSD use: 53 54 4
GND1 GND2
1

BELLW_80003-3041
R5554 ME@
220_0402_5% @
2

Security Classification
2012/12/26
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/NEW Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 36 of 62
A B C D E
 5 4 3 2 1

+3VALW +3V_LAN

J15
1 2
1 2

JUMP_43X79

@
D +3V_LAN D

W=60mils +LAN_VDD10
L74 W=60mils 1.5A
U47 8105@ +LAN_REGOUT 1 2 1 2
2.2UH_NLC252018T-2R2J-N_5% 0.1U_0402_16V7K C1189
1 2

2
0.1U_0402_16V7K C1190
C1184 C1182 1 2
4.7U_0603_6.3V6K 0.1U_0402_16V7K 0.1U_0402_16V7K C1191

1
RTL8105E-VL-CGT 1 2
SA00003PO40 GIGA@ 0.1U_0402_16V7K C1192
1 2
The C1183, C1186 close to U47 Pin 22, 23 GIGA@ 0.1U_0402_16V7K C1193
U47 These components close to U47 : Pin 36 1 2
( Should be place within 200 mils ) GIGA@ 0.1U_0402_16V7K C1194
<15> PCIE_PRX_DTX_P1 C1183 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 22 31
HSOP LED3/EEDO 37
LED1/EESK These caps close to U47 : Pin 12,27,39,42,47,48
<15> PCIE_PRX_DTX_N1 C1186 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 23 40
HSON LED0 @
17 30 R1506 2 1 10K_0402_5% +LAN_VDD10 R02 +LAN_EVDD10
<15> PCIE_PTX_C_DRX_P1 18 HSIP EECS 32 R1507 2 1 10K_0402_5% L75
<15> PCIE_PTX_C_DRX_N1 HSIN EEDI 2 1
@ @

2
16 1 MDI0+ 0_0603_5%
<15> CLKREQ_LAN# CLKREQB MDIP0 MDI0+ <38>
2 MDI0- C1187 C1188
25 MDIN0 4 MDI0- <38> +LAN_VDD10
MDI1+ 1U_0402_6.3V4Z 0.1U_0402_16V7K
<18,23,36,42> PLT_RST# MDI1+ <38>

1
PERSTB MDIP1 5 MDI1-
19 MDIN1 7 MDI2+ MDI1- <38> 1 2
<15> CLK_PCIE_LAN REFCLK_P NC/MDIP2 MDI2+ <38>
20 8 MDI2- 0.1U_0402_16V7K C1197
<15> CLK_PCIE_LAN# REFCLK_N NC/MDIN2 10 MDI2- <38> 1 2
C MDI3+ C
NC/MDIP3 11 MDI3- MDI3+ <38>
NOGCLK@ 0.1U_0402_16V7K C1198
NC/MDIN3 MDI3- <38>
LAN_XTALI R1373 1 2 0_0402_5% LAN_XTALI_R 43 1 2
R03 GCLK@ CKXTAL1 0.1U_0402_16V7K C1199
GCLK_LAN_25MHZ R5585 1 2 0_0402_5% LAN_XTALO 44 13 +3V_LAN Rising time (10%~90%) >1mS and <100mS 1 2
44> GCLK_LAN_25MHZ CKXTAL2 DVDD10 +LAN_VDD10
29 GIGA@ 0.1U_0402_16V7K C1200
R02 DVDD10 41 1 2
R1508 1 @ 2 0_0402_5% PCIE_WAKE#_R 28 DVDD10 +3V_LAN R02 +LAN_VDDREG GIGA@ 0.1U_0402_16V7K C1201
<42> LAN_WAKE# LANW AKEB L76 1 2
ISOLATEB 26 27
+3V_LAN
2 @ 1 GIGA@ 0.1U_0402_16V7K C1202
ISOLATEB DVDD33 39 1 2
DVDD33

2
0_0603_5% GIGA@ 0.1U_0402_16V7K C1203
14 12 C1195 C1196
NC/SMBCLK AVDD33 +3V_LAN
@ 2 R1510 1 10K_0402_5% 15 42 4.7U_0603_6.3V6K 0.1U_0402_16V7K

1
@ 1 R1511 2 1K_0402_5% 38 NC/SMBDATA AVDD33 47
+3V_LAN GPO/SMBALERT AVDD33 48 These caps close to U47 : Pin 3,6,9,13,29,41,45
AVDD33
ENSWREG 33
ENSW REG 21
EVDD10 +LAN_EVDD10
34
+LAN_VDDREG VDDREG
35 3
VDDREG AVDD10 +LAN_VDD10
6
AVDD10 9
1 2 46 AVDD10 45 +3VS +3V_LAN
R1513 2.49K_0402_1% RSET AVDD10

2
24 36 +LAN_REGOUT
GND REGOUT

1
49 R1515
PGND R1514 0_0402_5%
1K_0402_5% @
R1512 1 @ 2 10K_0402_5% CLKREQ_LAN# RTL8111F-CGT_QFN48_6x6
+3V_LAN

1
B B
GIGA@

2
ISOLATEB ENSWREG
R1518 1 @ 2 10K_0402_5% PCIE_WAKE#_R

R1516
15K_0402_5%

LAN_XTALI

Y4 LAN_XTALO
4 3
NC OSC
1 2
OSC NC
R03 1 25MHZ_10PF_7V25000014 1 R03
C1204 NOGCLK@ C1205
12P_0402_50V8J 12P_0402_50V8J
NOGCLK@ NOGCLK@
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-RTL8111F/8105E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 37 of 62
5 4 3 2 1
 5 4 3 2 1

Reserve gas tube for EMI go rural solution

T71

MDI3+ 1 16 MDO3+ @
<37> MDI3+ TD+ TX+
MDI3- 2 15 MDO3- DL3
<37> MDI3- 3 TD- TX- 14 2 1
@ MCT3 GT1812-420CSMD_1812-2
D D34 4 CT CT 13 CHASSIS1_GND D
AZC099-04S.R7G_SOT23-6 5 NC NC 12 DL2
MDI2+ 1 4 MDI3+ 6 NC NC 11 MCT2 2 1 GT1812-420CSMD_1812-2
I/O1 I/O3 MDI2+ 7 CT CT 10 MDO2+ CHASSIS1_GND
<37> MDI2+ 8 RD+ RX+ 9
MDI2- MDO2- @
<37> MDI2- RD- RX-
2 5
GND VDD +3V_LAN
MHPC_NS681610H
GIGA@
Place Close to T1,T2
MDI3- 3 6 MDI2-
I/O2 I/O4
T72

Place Close to T71 MDI0+ 1 16 MDO0+ @

<37> MDI0+ TD+ TX+
MDI0- 2 15 MDO0- DL5
<37> MDI0- 3 TD- TX- 14 2 1
MCT0 GT1812-420CSMD_1812-2
4 CT CT 13 CHASSIS1_GND
5 NC NC 12 DL4
6 NC NC 11 MCT1 2 1 GT1812-420CSMD_1812-2
1 CT CT
MDI1+ 7 10 MDO1+ CHASSIS1_GND
<37> MDI1+ 8 RD+ RX+ 9
@ MDI1- MDO1- @
<37> MDI1- RD- RX-
D35 C1207
AZC099-04S.R7G_SOT23-6 2 0.01U_0402_16V7K
C C
MDI1+ 1 4 MDI0+ MHPC_NS681610H
I/O1 I/O3

MCT3 R60 1 GIGA@ 2 75_0603_5%

2 5 +3V_LAN
GND VDD MCT2 R289 1 GIGA@ 2 75_0603_5%

MDI0- 3 6 MDI1-
I/O2 I/O4 MCT0 R305 1 2 75_0603_5%

MCT1 R306 1 2 75_0603_5%

Place Close to T72
R03
JRJ45 ME@

1
12 R03
GND R307
11
D34/D35 GND 0_0603_5%

1
10
1'S PN:SC300001G00

2
MDO0+ 1 GND Gastube@ DL6
PR1+ 9 1
B 2'S PN:SC300002E00 MDO0- 2
PR1-
GND BS4200N-C-LV_SMB-F2 C906
10P_0603_50V8-J
B

2
MDO1+ 3
PR2+ CHASSIS1_GND 2
MDO2+ 4
PR3+
MDO2- 5
PR3-
MDO1- 6 CHASSIS1_GND
PR2-
MDO3+ 7
PR4+ R03
MDO3- 8
PR4-
CHASSIS1_GNDC1325 1 2 .1U_0603_25V7K
SANTA_130460-3
DC231112261 C1326 1 2 .1U_0603_25V7K

C1327 1 2 .1U_0603_25V7K

CHASSIS1_GND
Reserve for EMI go rural solution
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_Transformer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 38 of 62
5 4 3 2 1
 5 4 3 2 1

SMSC thermal sensor

placed near by VRAM
+3VS REMOTE1+
Close to DDR
D D
Close U27 1

1
C

1
REMOTE1+ @ C586 2 Q97
+3VS R540 100P_0402_50V8J B MMST3904-7-F_SOT323-3
1 2
10K_0402_5% E

3
C587 @ REMOTE1-
2200P_0402_50V7K U27

2
2 REMOTE1-

1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <15,23,42>
REMOTE1+ 2 9 EC_SMB_DA2
REMOTE2+ 2
DP1 SMDATA EC_SMB_DA2 <15,23,42>
REMOTE2+
Under WWAN
1 REMOTE1- 3 8 1
DN1 ALERT#

1
C590 C
C588 @ 0.1U_0402_16V7K REMOTE2+ 4 7 @ C589 2 Q98
2200P_0402_50V7K 1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 5 6 2 E

3
DN2 GND REMOTE2-

EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
C Address 1001_101xb Trace width/space:10/10 mil C

Trace length:<8"

R02 R02
CPU VGA_L VGA_R new new new
H1 H2 H3 H18 new
HOLEA HOLEA HOLEA H4 H5 HOLEA H20 H21
HOLEA HOLEA HOLEA HOLEA H22
HOLEA FD1 FD2 FD3 FD4

1
1

1
H_3P8 H_3P8 H_3P8 H_3P9N CHASSIS1_GND CHASSIS1_GND
H_3P3 H_3P3
H_3P3 H_4P6 H_3P3
A B

B FAN1 Conn M/B B

new M/B
R02 new
H6 H7 H8 H9 H10 H11 H12 H13 H14 H19 L
+5VS HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H15 H23 H17
R02 HOLEA HOLEA HOLEA
R581 JFAN1
2 @ 1 1
1

1
2 1
<42> EC_TACH

1
0_0603_5% 3 2
<42> EC_FAN_PWM 3
4
5 4 H_2P8 H_3P0 H_2P3 H_2P8 H_2P8 H_2P8 H_2P8 H_2P3 H_2P8 H_2P8 H_3P0X4P0N H_3P0X4P0N
2 G5 H_3P0N
6
C591 G6
10U_0603_6.3V6M ACES_85205-04001 D
1 ME@
2P8 * 7 pcd E
10U

A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title
Fintek-Thermal IC/FAN/screw
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 39 of 62
5 4 3 2 1
 A B C D E F G H

BT MODULE CONN SATA HDD Conn.

JHDD1

1
SATA_ITX_DRX_P1 2 GND
<14> SATA_ITX_DRX_P1 A+
<14> SATA_ITX_DRX_N1 SATA_ITX_DRX_N1 3
4 A-
SATA_DTX_C_IRX_N1 C596 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5 GND
<14> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C597 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P1 6 B-
<14> SATA_DTX_C_IRX_P1 7 B+
GND

R632 BT@ C709 BT@ 8

100K_0402_5% 0.1U_0402_16V7K 9 V33
1 2 1 2 +3VS 10 V33
<19,36> PCH_BT_ON# 11 V33
1 GND 1
+3VS_BT 12
13 GND
+3VS R550 0_0805_5% 14 GND
R02 +5V_HDD 15 V5
+5VS 16 V5
R583 30mils V5

D
3 1 2 @ 1 17
18 GND
0_0603_5% 19 DAS/DSS
Q104 20 GND

G
2
PMV65XP_SOT23-3~D 21 V12 24
BT@ +5V_HDD 22 V12 GND 23
JBT1 V12 GND
1
2 1 SUYIN_127043HR022M25KZR
2 1 1 1
<18> USB20_P2 USB20_P2 3 ME@
USB20_N2 4 3 C598 C599 C602 DC010007P00
<18> USB20_N2 4
BTON_LED:NC 5 7 1000P_0402_50V7K 0.1U_0402_16V7K 10U_0603_6.3V6M
BT_ACTIVE 6 5 G1 8 2 2 2
<36> BT_ACTIVE 6 G2
ACES_87213-0600G
ME@

ODD Power Control

@ J9
1 2
1 2 +5V_ODD FOR 15"
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
S

3 1 JODD2
1 <14> SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 15@ C605 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_15 1
1
1

2 Q99 @ <14> SATA_ITX_C_DRX_N2 SATA_ITX_C_DRX_N2 15@ C606 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N2_15 2 2

R552 @ PMV65XP_SOT23-3~D C604 3 2
G
2

R568 @ 10K_0402_5% 0.1U_0402_16V7K SATA_DTX_C_IRX_N2 15@ C618 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2_15 4 3

10K_0402_5% R675 @ 2 <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 15@ C617 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2_15 5 4
100K_0402_5% <14> SATA_DTX_C_IRX_P2 6 5
1
2

1 2 R710 1 @ 2 0_0402_5% ODD_DETECT# 7 6

C608 +5V_ODD 8 7
8
1

1 10U_0603_6.3V6M R02 R554 0_0402_5% 9

2 ODD_DA# 1 @ 2 R_ODD_DA# 10 9
OUT

C607 @ <18> ODD_DA# 10

0.01U_0402_16V7K 11
2 2 1 R555 2 12 GND
<19> ODD_EN IN +3VS GND
10K_0402_5%
GND

ACES_51524-01001-003
Q100 @ ME@
DTC124EKAT146_SC59-3
3

JODD3
SATA_ITX_DRX_P2_15 1
SATA_ITX_DRX_N2_15 2 1
3 2
SATA_DTX_IRX_N2_15 4 3
SATA_DTX_IRX_P2_15 5 4
6 5
ODD_DETECT# 7 6
+5V_ODD 8 7
9 8
R_ODD_DA# 10 9
11 10
+5VS 11
12
13 12
+5VALW 13
<42,43> LED_KB_PWM_R
14
15 14
16 15
16
3
17 3
18 GND
GND
ACES_51524-0160N-001
ME@

Co-lay
FOR 14"
SATA ODD Conn.
JODD1 ME@
1
SATA_ITX_C_DRX_P2 14@ C616 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_14 2 GND
SATA_ITX_C_DRX_N2 14@ C615 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N2_14 3 RX+
4 RX-
SATA_DTX_C_IRX_N2 14@ C614 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2_14 5 GND
SATA_DTX_C_IRX_P2 14@ C613 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2_14 6 TX-
7 TX+
GND
ODD_DETECT# 8
+5V_ODD 9 DP
10 +5V
R_ODD_DA# 11 +5V
12 MD 14
13 GND GND1 15
GND GND2
SUYIN_127382FB013M266ZR
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 40 of 62
A B C D E F G H
 5 4 3 2 1

600ohms @100MHz 1A +3VS +3VDD_CODEC +IOVDD_CODEC +3VDD_CODEC

P/N: SM01000BU00
R20
+5VS +5VDDA_CODEC +5VDDA_CODEC R1529 0_0805_5% R1530
L77 1 @ 2 1 2

0.1U_0402_16V7K

1U_0402_6.3V6K
1 2 1 SUPPRE_ KC FBMA-10-100505-101T 0402

1
C1226

C1227
FBMA-L11160808601LMA10T_2P

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 2

2
2

C1231

C1232
C1230

C1233
2 2 2 1
Place near Pin1
600ohms @100MHz 2A
P/N: SM01000EE00 +5VS_PVDD
D R02 D
Place near Pin25 Place near Pin38
R1531 0_0805_5%
+5VS 1 2 +5VS_PVDD

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
2 1 1 +3VDD_CODEC

C1235

C1236
C1234
1 2 2 +IOVDD_CODEC Vendor recommend. 2.2K
+MIC1_VREFO_L

39

46

25

38

9
Power down (PD#) power stage for save power U50

2
DVDD-IO
PVDD1

PVDD2

AVDD1

AVDD2

DVDD1
0V: Power down power stage R1537
3.3V: Power up power stage 2.2K_0402_5%

MIC_JD 1 @ 2 MIC_JD_R 47 24 Vendor recommend. 2.2u

1
R1533 0_0402_5% DAPD/COMB_JACK LINE1-R(PORT-C-R)
EC_MUTE# 1 @ 2 EC_MUTE#_R 4 23
<42> EC_MUTE# PD# LINE1-L(PORT-C-L)
R1538 0_0402_5%
HDA_SDOUT_AUDIO 5 22 MIC_EXTR_C 1 2 2 1 EXT_MIC external MIC
+3VS <14> HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) EXT_MIC <43>
C1237 2.2U_0402_6.3V6M R1534 1K_0402_5%
HDA_BITCLK_AUDIO 6 21 MIC_EXTL_C 1 2
<14> HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L) C1238 2.2U_0402_6.3V6M
2

HDA_SDIN0 2 1 SDATA_IN 8 17 Placement near Audio Codec

R1535
<14> HDA_SDIN0
R1536 22_0402_5% SDATA-IN MIC2-R(PORT-F-R)
Head Phone Woofer

1
4.7K_0402_5% 16 R5567
MIC2-L(PORT-F-L) R5571 SENSEB 2 1
@
10 15 22K_0402_5% woofer@
<14> HDA_SYNC_AUDIO
1

SYNC LINE2-R(PORT-E-R) Reference Schematic 22Kohm 39.2K_0402_1%

HDA_RST_AUDIO# 11 14
<14> HDA_RST_AUDIO#

2
RESET# LINE2-L(PORT-E-L)

1
PC_BEEP 12 R02 D +5VS_PVDD
PCBEEP woofer@ Q11 2 Woofer_JD
40 SPK_L2+ 2N7002K_SOT23-3 G
2 1 JDREF 19 SPK-OUT-L+
S

3
JDREF

1
C 20K_0402_1% R1541 41 SPK_L1- Internal Speaker R4946 C
SPK-OUT-L-

2
20 SENSEA 2 1SENSEA_R R4948
MONO-OUT(PORT-H) 44 SPK_R1- R4947 U73 woofer@ 100K_0402_5%
SENSEA 13 SPK-OUT-R- 39.2K_0402_1% 200K_0402_5% EXT_MIC_RC 1 woofer@
Sense A 45 SPK_R2+ woofer@ IN+ 5

2
SENSEB 18 SPK-OUT-R+ 2 VCC+

1
Sense-B GND

1
R02 D 4 Woofer_JD
CBN 35 33 HPOUT_R 2 1 Q12 2 3 OUT
MIC Sense CBN HPOUT-R(PORT-A-R) 75_0402_5% R1544
HP_OUTR <43>
2N7002K_SOT23-3
PLUG_IN <43> IN-
R939 place near pin13 Headphone G

1
2 1 CBP 36 32 HPOUT_L 2 1 S LMV331IDCKRG4_SC70-5
HP_OUTL <43>

3
C1239 2.2U_0402_6.3V6M CBP HPOUT-L(PORT-A-L) 75_0402_5% R1545 R4950
Capless HP Sense 2 1 34 48 300K_0402_5%
C1240 2.2U_0402_6.3V6M CPVEE SPDIF-OUT woofer@
R940 place near pin34 2 1 28 R20

2
C1241 4.7U_0603_6.3V6K LDO-CAP 3 DMIC_CLK_R R937 2 @ 1 0_0402_5%
GPIO1/DMIC-CLK DMIC_CLK <33>
29 2 DMIC_DATA_R R1548 2 @ 1 0_0402_5% DMIC_DATA <33>
MIC2-VREFO GPIO0/DMIC-DATA
30
MIC1-VREFO-R
+MIC1_VREFO_L 31
MIC1-VREFO-L

42 27 Place close to pin 27

PVSS1 VREF

1U_0402_6.3V6K

0.1U_0402_16V7K
43 26 1
PVSS2 AVSS1

1
C1242

C1243
7 37
DVSS AVSS2

2
49 2
Thermal PAD

ALC259Q-VC2-GR_QFN48_6X6

R1549
1 2
B B
0_0402_5%
R1550
Pin Assignment Location Function 1 2
0_0402_5%
EMI
R1551
SPK-OUT (Pin40/41/44/45) Internal Int Speaker 1 2
@ 0_0402_5%
wide 25MIL Capless HP-OUT (Pin32/33) External Headphone out
1 2 HDA_BITCLK_AUDIO

R1552 27_0402_5%
SPK L+L-R+R- trace width MIC1(Pin21/22) External Mic in
1
Speaker 4 ohm ==>40 mils C1247
@ 33P_0402_50V8J
Speaker 8 ohm ==>20 mils 2
R02
JSPK1
SPK_L2+ R1556 1 @ 2 0_0603_5% SPK_L2+_CONN 1
SPK_L1- R1554 1 @ 2 0_0603_5% SPK_L1-_CONN 2 1
SPK_R1- R1555 1 @ 2 0_0603_5% SPK_R1-_CONN 3 2 GND GNDA
SPK_R2+ R1553 1 @ 2 0_0603_5% SPK_R2+_CONN 4 3
4
Combo Jack detect (normal open)
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

1 1 1 1 5
GND1
C1248

C1249

C1250

C1251

6
GND2
R1559 and C1135
2 2 2 2
ACES_88231-04001
ME@ R5582 PC Beep
R1123,C1134 Close to U73.1
Close to U50.47 R02 R02

R1123 47K_0402_5% R1559 EC Beep <42> BEEP# 1 2

MIC_JD 1 2 EXT_MIC 1 2 EXT_MIC_RC C1252 0.1U_0402_16V7K
0_0402_5%
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

woofer@ R1557 C1254

SPK_R2+_CONN SPK_L1-_CONN 2 woofer@ 2 PCH Beep <14> HDA_SPKR
1 2PC_BEEP1 1 2 1 2 PC_BEEP
C1253 0.1U_0402_16V7K 33_0402_5%
C1134

C1135

SPK_R1-_CONN SPK_L2+_CONN 0.1U_0402_16V7K

A A
1 1
3

@ @
D38 D39
PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2012/12/26 Deciphered Date 2012/12/31 Title
Reserve for ESD request. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC259Q-VC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 41 of 62
5 4 3 2 1
 +3VLP
Vcc 3.3V +/- 5%
1 R694 100K +/- 5%
C535
+3VALW 100P_0402_50V8J Board ID R695 VAD_BID min V AD_BID typ VAD_BID max PCB
GC6@
2 0_0402_5%
L44 EC_WAKE# R613 2 1
0 0 0 V 0 V 0 V MP LA-9061P
+3VALW GC6_1.5V_EN# <46>
FBMA-L11-160808-601LMT_2P 8.2K +/- 5% 0.216
1 1 1 1 1 1
+EC_VCCA 1 V 0.250 V 0.289 V PVT LA-9061P

0.1U_0402_16V7K
C653

0.1U_0402_16V7K
C654

0.1U_0402_16V7K
C662

0.1U_0402_16V7K
C655

1000P_0402_50V7K
C657

1000P_0402_50V7K
C658
1 2 0_0402_5%
+3VALW +EC_VCCA
AOAC_ON# R614 2 1 18K +/- 5%
1 1
C659
GC6_FB_CLAMP <23,27,46> 2 0.436 V 0.503 V 0.538 V DVT LA-9061P
C656 2 2 2 2 2 2 GC6@
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT LA-9061P

111
125
0.1U_0402_16V7K 1000P_0402_50V7K U31

22
33
96

67
9
1 2 2 ECAGND 2
4 56K +/- 5% 1.036 V 1.185 V 1.264 V PVT LA-9063P
L45

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
FBMA-L11-160808-601LMT_2P 100K +/- 5% 1.453
5 V 1.650V 1.759 V PVT LA-9063P TS_15
R1443 0_0402_5%
1 21 LED_KB_PWM 2 @ 1
<19> GATEA20 GATEA20/GPIO00 GPIO0F LED_KB_PWM_R <40,43>
2 23 BEEP#
<19> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <41>
3 26 NOVO#
<14> SERIRQ SERIRQ GPIO12 NOVO# <43>
4 27 ACOFF R695 15@ +3VALW
<14,36> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <49>
LPC_AD3 5
<14,36> LPC_AD3

2
LPC_AD2 7 LPC_AD3
<14,36> LPC_AD2 LPC_AD2 PWM Output
LPC_AD1 8 63 BATT_TEMP
<14,36> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <48>
LPC_AD0 10 LPC & MISC 64 VGA_IMVP_IMON R758 2 @ 1 0_0402_5% R694
<14,36> LPC_AD0 LPC_AD0 GPIO39 GPU_IMON
2 1 2 1 65 R02 100K_0402_1%
ADP_I/GPIO3A ADP_I <48,49>
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 EC_TS_ON# 100K_0402_5%
<18> CLK_PCI_EC EC_TS_ON# <43>

1
R03 2 @ 1 13 CLK_PCI_EC GPIO3B 75 BRDID SD028100380 BRDID
3,50> KBC_HANGUP_RESET# <18,23,36,37> PLT_RST# PCIRST#/GPIO05 GPIO42
1 2 R612 0_0402_5% EC_RST# 37 76 R03
+3VALW IMVP_IMON <55>

2
R590 47K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43 R5586 0_0402_5%
<19> EC_SCI# EC_SCII#/GPIO0E
2 38 WLAN_USB_ON#_R 2 @ 1 PCH_PWR_EN2 R01 R695
<45> PWRSHARE_EN_R GPIO1D PCH_PWR_EN2 <46>
68 EC_WL_WAKE# 56K_0402_1%
DAC_BRIG/GPIO3C EC_WL_WAKE# <36,44>
C661 R02 70 WLAN_USB_ON#_R
0.1U_0402_16V7K EN_DFAN1/GPIO3D 71 14@
DA Output DPWROK_EC <16>

1
1 KSI0 55 IREF/GPIO3E 72 +3VALW +5VALW
KSI0/GPIO30 CHGVADJ/GPIO3F SUSWARN# <16>
KSI1 56
KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R593 2 10K_0402_5%
KSO[0..17] KSI3 58 KSI2/GPIO32 83 R594 +3VS
<43> KSO[0..17] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <41>
KSI4 59 84 USB_ON# USB_ON# 1 2
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <43,45>
KSI5 60 85 EC_WAKE#
<43> KSI[0..7] KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 10K_0402_5%
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D CHG_ON# <45>
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <43>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <43>
KSO1 40 TP_CLK R603 1 2 4.7K_0402_5%
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 CPU1.5V_S3_GATE TP_DATA R598 1 2 4.7K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 CPU1.5V_S3_GATE <46>
KSO4 43 98 VGA_AC_DET
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET <23>
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 NTC_V_R R750 2 @ 1 0_0402_5%
ME_FLASH <14>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <48>
+3VALW KSO7/GPIO27 SPI Device Interface
+3VS KSO8 47
R600 KSO9 48 KSO8/GPIO28 119 PCH_PWR_EN PCH_PWR_EN BATT_TEMP 1 2
KSO9/GPIO29 SPIDI/GPIO5B PCH_PWR_EN <46,48>
1 2 EC_SMB_CK1 KSO10 49 120 GPU_PWR_EN C663 100P_0402_50V8J
KSO10/GPIO2A SPIDO/GPIO5C GPU_PWR_EN <46,54>
2.2K_0402_5% KSO11 50 SPI Flash ROM 126 AOAC_ON# ACIN 1 2
AOAC_ON# <36>

1
R604 KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 C664 100P_0402_50V8J
R601 R602 1 2 EC_SMB_DA1 KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A SUSACK# <16> For DS3 R5537
2.2K_0402_5% KSO14 53 KSO13/GPIO2D 100K_0402_5%
2.2K_0402_5% 2.2K_0402_5%
KSO15 54 KSO14/GPIO2E 73 R02
KSO15/GPIO2F ENBKL/GPIO40 ENBKL <33>
KSO16 81 74
EC_PWRSHARE_EN# <45>

2
EC_SMB_CK2 KSO17 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 DGPU_PWR_EN
KSO17/GPIO49 FSTCHG/GPIO50 DGPU_PWR_EN <18,23,25>
EC_SMB_DA2 90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <43>
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <43>
EC_SMB_CK1 77 GPIO 92
<48,49> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <43> +3VLP
EC_SMB_DA1 78 93 BATT_LOW_LED#
<48,49> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <43>
EC_SMB_CK2 79 SM Bus 95 SYSON
<15,23,39> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <46,51>
EC_SMB_DA2 80 121 @
<15,23,39> EC_SMB_DA2 VR_ON <55>

1
EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 KB9012A2 work around
PM_SLP_S4#/GPIO59 PM_SLP_S4# <16>
R4945 R737
47K_0402_5% VR_HOT# 1 @ 2 H_PROCHOT# <6,48>
<55> VR_HOT#
6 100
<16> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <16>
14 101 EC_LID_OUT# 0_0402_5%
<16> PM_SLP_S5# EC_LID_OUT# <19>

1
EC_SMI# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 Turbo_V D
<19> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <48>
16 103 H_PROCHOT#_EC R02 R757 1 @ 2 0_0402_5% H_PROCHOT#_EC 2
+3VS
For DS3 <33> CMOS_ON#
17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 MAINPWON_R R02 R738 1 @ 2 0_0402_5%
PROCHOT <48>
G
1
<16,46> SLP_SUS# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <48,50>
18 GPO 105 BKOFF# Q37 S C493
<7> DRAMRST_CNTRL_EC BKOFF# <33>

3
19 GPIO0C BKOFF#/GPXIOA08 106 PBTN_OUT# 2N7002K_SOT23-3 47P_0402_50V8J
<23> GC6_FB_REQ GPIO0D GPIO PBTN_OUT#/GPXIOA09 PBTN_OUT# <16> 2
EC_INVT_PWM 25 107 PCH_APWROK <16>
<33> EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
1 2 EC_TACH EC_TACH 28 108 SA_PGOOD <52>
<39> EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
R605 10K_0402_5% EC_PME# 29
EC_TX 30 EC_PME#/GPIO15
<36> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<36> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <16,49>
PCH_PWROK 32 112 EC_ON +3VALW
<16> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <50>
EC_FAN_PWM 34 114 ON/OFF <43>
<39> EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
2 1 36 GPI 115 LID_SW#
<43> NUM_LED# LID_SW# <43>

2
@ R608 10K_0402_5% NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP#
SUSP#/GPXIOD05 SUSP# <46,51,53>
117 PCH_HOT#_R
GPXIOD06 118 PECI_KB9012 R793 2 @ 1 0_0402_5% R606
PECI_KB9012/GPXIOD07 OVERT# <23>
AGND/AGND

R611 0_0402_5% EC_RTCX1 122 R20 10K_0402_5%

XCLKI/GPIO5D
GND/GND
GND/GND
GND/GND
GND/GND

2 @ 1 SUSCLK_R SUSCLK_R 123 124 +V18R R669 1 2 43_0402_1%

<16> SUSCLK H_PECI <6>

1
XCLKO/GPIO5E V18R
1
GND0
1

C694 R02
1

4.7U_0603_6.3V6K R609 1 @ 2 0_0402_5%

R740 C93 2 LAN_WAKE# <37>
11
24
35
94
113

69

100K_0402_5% 20P_0402_50V8
2
2

KB9012QF-A3_LQFP128_14X14
ECAGND

EMC Request

EC_RTCX1 SYSON EC_PME# 1 3

S
PCI_PME# <18>

C492
1 2 SUSCLK_R ECAGND Q102 @

0.1U_0402_16V7K
R120 @ 2N7002K_SOT23-3

G
2
10M_0402_5% 1 +3VALW

PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER 2

32.768KHZ_12.5PF_9H03200413
1

Y5
OSC

OSC

@
NC

NC
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title
check
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 42 of 62
 ON/OFF switch K/B Connector
+3VALW
15" 14"

2
R642 KSI[0..7] JKB1 ME@ JKB2 ME@
KSI[0..7] <42>
100K_0402_5% KSI1 30 32
KSO[0..17] KSI7 29 30 GND 31 28
KSO[0..17] <42> 29 GND GND1
KSI6 28 27

1
D26 KSO9 27 28 KSI1 26 GND2
NOVO# 2 KSI4 26 27 KSI7 25 26
<42> NOVO# 26 25
1 NOVO_BTN# KSI5 25 KSI6 24
ON/OFF R02 R725 1 @ 2 0_0402_5% 3 KSO0 24 25 KSO9 23 24
<42> ON/OFF 24 23
KSI2 23 KSI4 22
KSI3 22 23 KSI5 21 22
DAN202UT106_SC70-3 KSO5 21 22 KSO0 20 21
KSO1 20 21 KSI2 19 20
KSI0 19 20 KSI3 18 19
KSO2 18 19 KSO5 17 18
KSO4 17 18 KSO1 16 17
+3VLP KSO7 16 17 KSI0 15 16
KSO8 15 16 KSO2 14 15
KSO6 14 15 KSO4 13 14
14 13

2
+3VS KSO3 13 KSO7 12
KSO12 12 13 KSO8 11 12
R701 KSO13 11 12 KSO6 10 11
100K_0402_5% KSO14 10 11 KSO3 9 10
10 9

2
ON/OFFBTN# KSO11 9 KSO12 8

1
R207 R96 KSO10 8 9 KSO13 7 8
300_0402_5% 300_0402_5% KSO15 7 8 KSO14 6 7
J11 7 6
KB1 6 KSO11 5
1 2 R02 R720 1 @ 2 0_0402_5% ON/OFF KB2 5 6 KSO10 4 5

1
KB_LED_PWR 4 5 KSO16 R5563 1 15@ 2 0_0402_5% KSO15 3 4
SHORT PADS CAPS_LED# 3 4 KB_LED_PWR R5564 1 14@ 2 0_0402_5% KB1 2 3
<42> CAPS_LED# 3 2
2 KSO17 R5565 1 15@ 2 0_0402_5% KB2 1
J13 2 1
1 CAPS_LED# R5566 1 14@ 2 0_0402_5%
<42> NUM_LED# 1
1 2
TYCO_3-2041084-0 ACES_88514-02601-071
SHORT PADS

TP/B Connector PWR/B Connector USB I/O Connector

+5VALW
R03 R03 +USB_VCCB
JTP1 ME@ +3VALW JUSB3
+3VS 1 USB20_N8 3 L78 4 USB20_N8_R 1
TP_CLK 2 1 3 4 2 1
<42> TP_CLK 2 2
TP_DATA 3 JPWRB1 ME@ 3
<42> TP_DATA 3 3
C760 4 1 USB20_P8 2 1 USB20_P8_R 4
SMB_CLK_S3_R 5 4 2 1 2 1 USB20_P8 R5587 1 @ 2 0_0402_5% USB20_P8_R 5 4
5 2 <18> USB20_P8 5
0.1U_0402_16V7K SMB_DATA_S3_R 6 NOVO_BTN# 3 WCM-2012-900T_4P USB20_N8 R5588 1 @ 2 0_0402_5% USB20_N8_R 6
6 3 <18> USB20_N8 6
ON/OFFBTN# 4 7
7 PWR_LED# 5 4 USB20_N9 3 L79 4 USB20_N9_R USB20_P9 R5589 1 @ 2 0_0402_5% USB20_P9_R 8 7
GND 5 3 4 <18> USB20_P9 8
8 LID_SW# 6 USB20_N9 R5590 1 @ 2 0_0402_5% USB20_N9_R 9
GND 6 <18> USB20_N9 9
7 R02 10
ACES_88514-00601-071 8 7 USB20_P9 2 1 USB20_P9_R 11 10
9 8 2 1 12 11
GND +3VS 12
10 WCM-2012-900T_4P 13
GND EXT_MIC R20 R5568 1 @ 2 0_0603_5% EXT_MIC_R 14 13
<41> EXT_MIC 14
ACES_51524-00801-001 HP_OUTR R5569 1 @ 2 0_0603_5% HP_OUTR_R 15
<41> HP_OUTR 15
HP_OUTL R5570 1 @ 2 0_0603_5% HP_OUTL_R 16
<41> HP_OUTL 16
<41> PLUG_IN PLUG_IN 17 19
18 17 G1 20
18 G2
ACES_50505-0184N-001
LID_SW# <42>
0_0402_5% ME@
R723 1 @ 2 SMB_CLK_S3_R
<12,13,15,36> SMB_CLK_S3
R724 1 @ 2 SMB_DATA_S3_R
<12,13,15,36> SMB_DATA_S3
0_0402_5%

LED (For 14")

LED1 14@ R10

PWR_LED# 1 2
R623
2 1
LED (For 15")
<42> PWR_LED# +5VALW
560_0402_5%
14@
19-213A-T1D-CP2Q2HY-3T_WHITE
JLED1 ME@
LED2 14@ +5VALW 1
2 1
Right Side USB2.0 Port X 2 (USB/B)
+3VALW 2
<42> BATT_LOW_LED# BATT_LOW_LED# 1 2 2 R764 1 +3VALW PWR_LED# 3
470_0402_5% BATT_LOW_LED# 4 3
BATT_CHG_LED# 5 4 +5VALW +USB_VCCB
14@ 5
HT-191UD5_AMBER 6 U42
6 1 8
LED5 14@
R10 7 C768 0.1U_0402_16V7K 2 GND VOUT 7
R765 8 GND 2 1 3 VIN VOUT 6
BATT_CHG_LED# 1 2 2 1 GND USB_ON# 4 VIN VOUT 5 USB_OC4#
<42> BATT_CHG_LED# +5VALW <42,45> USB_ON# EN FLG USB_OC4# <18>
130_0402_5% ACES_88514-00601-071
14@ SY6288DCAC_MSOP8
19-213A-T1D-CP2Q2HY-3T_WHITE

Low Active 2A

EC RESEST function KB Lighting CONN.4pin

R20 R03 ACES_88514-0401
R4961 1 @ 2 0_0402_5% ME@
+3VALW
6
R4960 1 @ 2 0_0402_5% +VCC_KB_LED 5 GND
+3VLP GND
U74 RESET@
C554 1 2 0.1U_0402_16V7K 1 6 R4958 1 @ 2 0_0402_5% +3VS 4
2 MRDLY VCC 5 3 4
GND RESET KBC_HANGUP_RESET# <42,50> 3
RESET@ 3 4 2
CD MR R03 1 2
1 1
R20 S IC G601A31U ADFN 6P RESET
R5579 1 @ 2 0_0402_5% C1311 RESET@ JKBL1
0.1U_0402_16V7K
ON/OFFBTN# 2

+5VS
SA00005VZ00 S IC G601A31U ADFN 6P RESET
+5VALW
+VCC_KB_LED
Q153

D
11/07 change to +5VALW 3 1
Touch Screen R5548
10K_0402_5% AO3413_SOT23-3
KBL@ KBL@ KBL@

C1315
G
1 2

10U_0603_6.3V6M
2

2
R02
R5581 TS_14@ C1331 TS_14@ 1 R5549 2 C1316
10K_0402_5% 0.1U_0402_16V7K JTS1 100K_0402_5% 0.1U_0402_16V7K
1 2 1 2 1 KBL@ KBL@ 2 1

KBL@
<42> EC_TS_ON# +3VS_TS 1 1
R20 2
R718 1 @ 2 0_0402_5% USB20_N1_R 3 2 C1317
+3VS_TS_R +3VS_TS <18> USB20_N1 3
R719 1 @ 2 0_0402_5% USB20_P1_R 4 0.01U_0402_16V7K
<18> USB20_P1 4 2
R10 5 7
5 G1
1
EC_TS_ON# R721 1 TS_15@ 2 0_0402_5% TS_RST# 6 8
6 G2
OUT
S

3 1 ACES_87213-0600G
ME@ 11/07 Change type to 0603
<40,42> LED_KB_PWM_R 2
Q156 IN
Touch Screen
G

GND
0.1U_0402_16V7K
2

PMV65XP_SOT23-3~D 2 +5VS +3VS_TS_R

C1322

TS_14@ Q154
R10 DTC124EKAT146_SC59-3
3

TS@ 1 TS_15@ 2 KBL@

1 R03 R5592 0_0402_5%
+3VS +3VS_TS
R02
1 TS_14@ 2 1 TS_15@ 2
R5572 0_0402_5% R5583 0_0402_5%
+3VALW Security Classification Compal Secret Data Compal Electronics, Inc.
2012/12/26 2012/07/11 Title
1 2
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
R5584 @ 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 43 of 62
 A B C D E

RTS5178 CardReader U9 RTS5170@

R20
R76 2 @ 1 0_0603_5%
+3VS +3VS_CARD

SA00005T300 S IC RTS5170-GR QFN 24P CARD READER

U9
JCR1
+3VS_CARD +VCC_3IN1 R31 2 CR@ 1 6.19K_0402_1% RREF 1 4
RREF +VCC_3IN1 VDD
22
R20 MS_BS/SP14 21 SD_D2_R R3 1 @ 2 0_0402_5% SD_D2 SD_D0 7
SD_D2/SP13 1 DAT0

C50
R688 2 @ 1 0_0402_5% USB20_N11_C 2 20 SD_D3_R R4 1 @ 2 0_0402_5% SD_D3 SD_D1 8
<18> USB20_N11 DM MS_D1/SD_D3/SP12 DAT1
R684 2 @ 1 0_0402_5% USB20_P11_C 3 19 SD_D2 9
1 <18> USB20_P11 DP SP11 DAT2 1
C40 C36 C37 18 SD_CMD_R R5 1 @ 2 0_0402_5% SD_CMD CR@ SD_D3 1
SD_CMD/SP10 2 DAT3

4.7U_0603_6.3V6K
16
1 1 1 Trace width:40mil 4 MS_D0/SP9 15 SD_CLK_R R8 1 CR@ 2 0_0402_5% SD_CLK SD_CD# 11
+3VS_CARD 3V3_IN MS_D2/SD_CLK/SP8 CD
CR@ CR@ CR@ 5 14 SD_WP/XD_D7 10
+VCC_3IN1 CARD_3V3 SP7 WP
0.1U_0402_16V7K

4.7U_0603_6.3V6K

0.1U_0402_16V7K
13 SD_CD#
2 2 2 SD_CD#/SP6 12 SD_CMD 2
7 MS_D3/SP5 11 SD_D0_R R14 1 @ 2 0_0402_5% SD_D0 SD_CLK 5 CMD
23 XD_CD# SD_D0/SP4 10 SD_D1_R R19 1 @ 2 0_0402_5% SD_D1 CLK

2
17 XD_D7 SD_D1/SP3 9 3 12
GPIO0 MS_INS#/SP2 8 SD_WP/XD_D7 R80 @ 6 VSS1 GND 13
6 MS_CLK/SD_WP/SP1 0_0402_5% VSS2 GND
V18 24 SDREG TAITW_PSDBTC-09GLBS1N14N0
V18 ME@

1
C42 C43 25
2 2
Thermal pad
1 SD/MMC
CR@ CR@ RTS5178-GR_QFN24_4X4
RTS5178@ C45 @
C37 R6 close to JCR1 Pin4 68P_0402_50V8K

De-coupling and Bulk

1 1 update PN to RTS5178 (SA000050K00) 2

1U_0402_6.3V6K

1U_0402_6.3V6K
0907 Vendor not agree mount C45
capacitor should place
near to RTS5179 chip and
Combo Socket

2 2

Every power trace need:

Green Clock W=20mils
U69 GCLK244@ U69 GCLK304@

For GreenCLK generate CLK:

SLG3NB244VTR_TQFN16_2X3 SLG3NB300VTR_TQFN16_2X3
Mount: All parts in this page except
+CHGRTC_R
+RTCBATT Swing Level RES (Marked "*")
R10
NA: PD108,
2
+3VLP RG10 @ Y1,R98,C180,C181,
+3VLP +V1.05S_VCCP +3V_GCLK +3VS_VGA +3V_GCLK
0_0402_5% Y2,R169,C196,C197,
1 Y6,C968,C969
1

3 3
CG3 GCLK@
0_0402_5%
1

GCLK@ 1 22U_0805_6.3V6M
CG2
0_0402_5%

1
1

2
GCLK304@
0.1U_0402_16V7K

RG9

CG4
2 R02 @ 2.2U_0402_6.3V6M
2
1

R02 U69 2 GCLK@

RG11
2

10 14
RG8

@ 0_0402_5% 1
CG6 VBAT VDD_RTC_OUT
GCLK@ 1 15
0.1U_0402_16V7K

+V3.3A
2

CG5
GCLK304@

2 2 1 +3VS_GCLK 2
0.1U_0402_16V7K

GCLK@ CG1 VDD 9 GCLK_32K_R RG1 1 2 0_0402_5% GCLK_32K

CG7
1 2
0.1U_0402_16V7K
32kHz GCLK@
GCLK_32K <14> PCH_32.768K
NV_GPU
0.1U_0402_16V7K

GCLK@ VGA_GCLK 11 12 GCLK_27MHZ_R RG2 1 2 22_0402_5% GCLK_27MHZ

2 VDDIO_27M 27MHz GCLK_27MHZ <23>
GCLK304@
8
VDDIO_25M_A 25MHz_A
6 GCLK_LAN_25MHZ_R RG3 1 2 33_0402_5% GCLK_LAN_25MHZ
GCLK_LAN_25MHZ <37>
LAN
GCLK@
PCH_GCLK 3
VDDIO_25M_B 25MHz_B
5 GCLK_PCH_25MHZ_R RG4 1 2 0_0402_5% GCLK_PCH_25MHZ
GCLK_PCH_25MHZ <15>
PCH_25M
GCLK@
GreenCLK_XTALI 1
Y8 GreenCLK_XTALO 16 XTAL_IN
XTAL_OUT
Close to GCLK
GND1
GND2
GND3

GND4

4 3
NC OSC
1 2
OSC NC
SLG3NB274VTR_TQFN16_2X3
Reserved for Swing Level adjustment
4
7
13

17

1 GCLK@ 1
GCLK@ CG8 25MHZ_10PF_7V25000014 GCLK@ CG9 GCLK274@
15P_0402_50V8J 15P_0402_50V8J ( Close GCLK side )
2 2
@
GCLK_27MHZ RG5 *1 2 0_0402_5%

RG13 GCLK@ CG10 GCLK@ @

4 10K_0402_5% 0.1U_0402_16V7K GCLK_LAN_25MHZ RG6 * 1 2 0_0402_5% 4
1 2 1 2
<36,42> EC_WL_WAKE#
@
GCLK_PCH_25MHZ RG7 *1 2 0_0402_5%

+3VALW +3V_GCLK
S

3 1

QG1
Security Classification Compal Secret Data Compal Electronics, Inc.
G
2

PMV65XP_SOT23-3~D 2012/12/26 2012/07/11 Title

Issued Date Deciphered Date
GCLK@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTS5178/Green Clock
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 44 of 62
A B C D E
 5 4 3 2 1

LEFT SIDE USB3.0 PORT X1

+5VALW +5V_CHGUSB
U41
C767 0.1U_0402_16V7K 1 8
2 1 2 GND VOUT 7
3 VIN VOUT 6
R1169 1 NOCHG@
2 0_0402_5% 4 VIN VOUT 5 USB_OC0#
<42,43> USB_ON# EN FLG USB_OC0# <18> +5V_CHGUSB
D D
For EMI request SY6288DCAC_MSOP8 C814 220U_6.3V_M
1 2

+
USB2.0 choke --> SM070000K00 <42> EC_PWRSHARE_EN# R5577 1 CHG@ 2 0_0402_5%

R02
Low Active 2A 1 2
USB3.0 Choke --> SM070001S00
C816 470P_0402_50V7K

R20
L68
USB30_RX_N1 2 1 USB30_RX_R_N1 R20 JUSB1 ME@
2 1 USB30_TX_P1 C299 1 2 0.1U_0402_16V7K USB30_TX_C_P1 R1156 1 @ 2 0_0402_5% USB30_TX_R_P1 9
<18> USB30_TX_P1 SSTX+
R20 1
USB30_RX_P1 3 4 USB30_RX_R_P1 USB30_TX_N1 C300 1 2 0.1U_0402_16V7K USB30_TX_C_N1 R1157 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
3 4 <18> USB30_TX_N1 SSTX-
USB20_P0_C R1162 1 @ 2 0_0402_5% USB20_P0_R 3
WCM-2012HS-900T_4P 7 D+
R20 USB20_N0_C R1163 1 @ 2 0_0402_5% USB20_N0_R 2 GND 10
L70 USB30_RX_P1 R1154 1 @ 2 0_0402_5% USB30_RX_R_P1 6 D- GND 11
<18> USB30_RX_P1 SSRX+ GND
USB30_TX_C_N1 2 1 USB30_TX_R_N1 R20 4 12
2 1 USB30_RX_N1 R1155 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND GND 13
<18> USB30_RX_N1 SSRX- GND
USB30_TX_C_P1 3 4 USB30_TX_R_P1 TAITW_PUBAU1-09FNLSCNN4H0
3 4
For ESD request
WCM-2012HS-900T_4P

D27 D28
@ @
C USB20_N0_C 3 L72 4 USB20_N0_R USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_P0_R 3 6 C
3 4 I/O2 I/O4
USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1
USB20_P0_C 2 1 USB20_P0_R
2 1 USB30_TX_R_N1 7 4 USB30_TX_R_N1 2 5
7 4 +5VALW
WCM-2012-900T_4P GND VDD
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

3 3 1 4 USB20_N0_R
I/O1 I/O3
8 AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9

Left Side Charger USB3.0 Port

R20

R20 U76
R5578 1 @ 2 0_0402_5% PWRSHARE_EN 1 8 R5555 1 @ 2 0_0402_5%
<42> PWRSHARE_EN_R CEN CB CHG_ON# <42>
USB20_N0_C 2 7 USB20_N0 <18>
DM TDM

1
USB20_P0_C 3 6 USB20_P0 <18>
SELCDP 4 DP TDP 5 R5556
SELCDP VDD +5VALW
B 9 100K_0402_5% B
Thermal Pad CHG@
2

SLG55584AVTR_TDFN8_2X2

2
CHG@ C991
0.1U_0402_16V7K
1

CHG@

R03
+5VALW +5VALW
NOCHG@ NOCHG@
USB20_P0 R1167 1 2 0_0402_5% USB20_P0_C_R R1171 1 2 0_0402_5% USB20_P0_C
1

USB20_N0 R1166 1 2 0_0402_5% USB20_N0_C_R R1170 1 2 0_0402_5% USB20_N0_C

R5560 R5557 NOCHG@ NOCHG@
10K_0402_5% 10K_0402_5%
CHG@ CHG@
2

SELCDP PWRSHARE_EN CB SELCDP Function

0 X DCP autodetect with mouse /keyboard wakeup
1

R5559 1 0 S0 charging with SDP only

R5561 10K_0402_5%
10K_0402_5% @ 1 1 S0 charging with CDP or SDP only (depending on external device )
A @ A
2

USB2.0/3.0 choke and ESD diode at sub-B.

Security Classification Compal Secret Data
Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/Left USB Ports
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 09, 2013 Sheet 45 of 62
5 4 3 2 1
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS for Deep Sleep S3 +5VALW

2
+5VALW +5VS +3VALW +3VS
U38 R5531
U39 100K_0402_5%
AP4800BGM-HF_SO-8 AP4800BGM-HF_SO-8 R03 DS3@
8 1 8 1 DS3@

1
1 7 2 1 1 10U 1 7 2 1 1 R5591 PCH_PWR_EN#

1
6 3 6 3 <42> PCH_PWR_EN2
1 2
C720 5 C721 C722 C723 5 C724 C725 0_0402_5%
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K @ R644 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R645

1
2 2 2 470_0603_5% 2 2 2 470_0603_5% @ D

4
10U 10U @ 1 R5532 2 2 Q151
<42,48> PCH_PWR_EN

1 2

1 2
+VSB 0_0402_5% G DS3@
D +VSB D
S

3
2 SUSP 2 SUSP 1 @ 2 S 2N7002-7-F 1N SOT23
<16,42> SLP_SUS#
1

1
1 1
G G 0_0402_5%
R646 S @ Q107 S Q108 R5533

3
150K_0402_5% 2N7002K_SOT23-3 R647 2N7002K_SOT23-3
470K_0402_1% @
2

2
5VS_GATE 2 R649 15VS_GATE_R
1 1
1

1
D D
SUSP 2 Q110 82K_0402_5% C726 SUSP 2 Q111 C727
G 2N7002K_SOT23-3 0.01U_0402_25V7K G 2N7002K_SOT23-3 0.01U_0402_25V7K
S 2 S 2 for Deep Sleep S3 +3VALW +3VALW TO +3V_PCH +3V_PCH
3

3
@

2 1

2MM J20

DS3@ Q152 AO3413_SOT23

3 1

D
+1.8VS +1.5V +V1.05S_VCCP +0.75VS +1.5V to +1.5VS

0.1U_0402_16V7K
G
2
+1.5V Q8 +1.5VS
1
1

PMV65XP_SOT23-3~D

C1312
PCH_PWR_EN# R5534 2 DS3@ 1 47K_0402_5% DS3@
3 1

D
R655 R656 R659 R658
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 2
1 1 1

1
@ @ @ 2 1 1
1 2

1 2

1 2

1 2

CPU1.5V_S3_GATE <42>

0.1U_0402_16V7K
@ R91 0_0402_5% C717 C718 C719

G
2
D D D D

C1313
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R643 DS3@
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 2 2 470_0603_5%
G G G G @ 2

2
S Q113 S Q114 S Q116 S Q115
3

2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3

1
@ @ @ +3VALW D
2 SUSP
2 For Intel S3 Power Reduction. G 2

1
S Q109

3
2N7002K_SOT23-3
100K_0402_5% @ for Deep Sleep S3
R648 +5VALW +5VALW TO +5V_PCH +5V_PCH
@

2
2 R651 1 1.5VS_GATE
Q112 1 2 1

1
D
SUSP# 2 0_0402_5% C729 2MM J21
G 0.1U_0402_16V7K
2N7002K_SOT23-3 S 2

3
DS3@ QH1 AO3413_SOT23

3 1

0.1U_0402_16V7K
add D60 for GPU sequence issue 11/13

G
1

2
1 2

CH1
DS3@
D60 +5VALW PCH_PWR_EN# 1 2
GV2@ 0_0402_5% 2
CH751H-40PT_SOD323-2 DS3@ R5573 1

1
@

0.1U_0402_16V7K
C1323
R1111 OPT@ R1107
2 1 100K_0402_5% 2
<42,46,54> GPU_PWR_EN
OPT@

2
40.2K_0402_1%
+RTCVCC +5VALW DGPU_PWROK#
DGPU_PWROK# <54>

1
R1106 @ D
2

2 1 2 Q129
<19,46,54> DGPU_PWROK
R652 0_0402_5% G 2N7002K_SOT23-3
220K_0402_5% R654 @ 1 S OPT@

3
100K_0402_5% C1108
0.1U_0402_16V7K
1

SUSP SYSON# OPT@

<10,25,51,54> SUSP 2
1

Q117
+1.5V to +1.5VS_VGA Transfer
1

3 3
DTC124EKAT146_SC59-3 Q119@ R5597
OUT

DTC124EKAT146_SC59-3 0_0402_5%
OUT

SYSON 2 add D61 for GPU sequence issue 11/13 +1.5V +1.5VS_VGA
1

2 <42,51> SYSON IN
GND

<10,42,51,53> SUSP# IN 1 2
GND

D61 +5VALW Del J12

@ 300mil(7.2A)
3
1

CH751H-40PT_SOD323-2
3

1
R1110 @ 2 @ 1 OPT@
<42,46,54> GPU_PWR_EN
100K_0402_5% R1113 C856
R1116 40.2K_0402_1% 100K_0402_5% 10U_0603_6.3V6M AO4430: Rdson: 5.5mohm @ VGS=10V
2

OPT@ 2
2

DV2 OPT@
@ GC6_1.5V_EN# U49 AO4304L_SO8
8 1
300mil(7.2A)
DAN202UT106_SC70-3
1

2 D 7 2
<23,27,42> GC6_FB_CLAMP 1 2 6 3
Q130

2
3 G 2N7002K_SOT23-3 5 1 1
<19,46,54> DGPU_PWROK
S OPT@ 1 C853 C854 R1101
3

C852 10U_0603_6.3V6M 0.1U_0402_16V7K 75_0603_5%

4
1 10U_0603_6.3V6M OPT@ OPT@ GV2@
C1112 OPT@ 2 2

1
0.1U_0402_16V7K 2
@
2 +VSB

R1102 10K_0402_5%
2 1

1
OPT@ GV2@ D GV2@
1 Q127 2 2 R790 1 GC6_1.5V_EN#
<42> GC6_1.5V_EN#
C855 2N7002K_SOT23-3 G 0_0402_5%
Q126 OPT@ 0.1U_0402_25V7K S

3
2N7002K_SOT23-3 OPT@
EC L - 1.5_VGA ON
1

R20 @ D 2 2 R791 @1 SUSP

R782 2 1 0_0402_5% 2 0_0402_5%
G
S
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 46 of 62
A B C D E
 5 4 3 2 1

D D

VIN

PF101 PL101
JDCIN 7A_24VDC_429007.WRML SMB3025500YA_2P
1 APDIN 1 2 APDIN1 1 2
1 2
2 3
3 4
4

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
5
GND 6
GND

1
@
ACES_50305-00441-001

2
PC101

PC102

PC103

PC104
C
20120723 C
For all sku
1. Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080
Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080

+CHGRTC_R +3VLP
20120731
1. Change PR106 footprint to R0402_0ohm-NEW
+CHGRTC

1
- JRTC1 + PR108
150_0603_5%
PR109
1K_0603_5%
PD103
RB751V-40_SOD323-2
PR106
0_0402_5%
2 1 1 2 1 2 2 1 +RTCBATT @

2
@ MAXEL_ML1220T10 1 2
RTCVREF
PD104
RB751V-40_SOD323-2

RTC Battery

20120731
1. Add PR110 SD013000080 0_0603_5%
B Add PR111 SD013150080 150_0603_5% B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / RTC Battery
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Xz90
Date: Wednesday, January 09, 2013 Sheet 47 of 62
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
JBATT1 PF201 PL201
1 12A_65V_451012MRL SMB3025500YA_2P
1 2 1 2 1 2
2 3 BATT+
3 4
4 5 EC_SMCA
5 6 EC_SMDA
6 7

1
D D
7 8

1
PC201 PC202
8 9

100_0402_1%

100_0402_1%
1000P_0402_50V7K 0.01U_0402_25V7K
ADP_I need to write Charge Options Register (0x12H)=> bit6=1

2
9 10
10 PR201

PR202
ACES_50299-01001-001
0: IOUT is the 20x current amplifier output <default @ POR>
2

2
ME@ 1: IOUT is the 40x current amplifier output

90W(DIS) : 6.65K 100W active 90W recovery

PH201 under CPU botten side : 65W(UMA): 1.65K 70W active 65W recovery
EC_SMB_CK1 [42,49] CPU thermal protection at 93 +-3 degree C 20120314
Recovery at 56 +-3 degree C Change to +EC_VCCA from +3VLP
EC_SMB_DA1 [42,49]

1 2
+3VALW
VL
PR203
6.49K_0402_1%
+EC_VCCA
[42,49] ADP_I

21.5K_0402_1%
<BOM Structure>

1
6.65K_0402_1%

12.7K_0402_1%
1

PR207
1 2
BATT_TEMP [42] A/D

PR205

PR206
PR204

1
10K_0402_5%
<BOM Structure> PC203 +3VS

2
@ 0.1U_0603_16V7K PU201

2
1 8 NTC_V_1 @
VCC TMSNS1

100K_0402_1%
C 2 7 OTP_N_002 2 1 C
GND RHYST1

PR208
PR209
3 6 Turbo_V_1 @ 10K_0402_1%
[42,6] H_PROCHOT# OT1 TMSNS2

100K_0402_1%_TSM0B104F4251RZ
PR210
4 5 ADP_OCP_2 1 2

1
OT2 RHYST2

1
PQ201

2
D

10K_0402_1%

PH201
<BOM Structure>
@ G718TM1U_SOT23-8 @ 27.4K_0402_1% PR213
PR211

PR212
2 ADP_OCP_1 0_0402_5% PR235

OTP_N_003
G @ 0_0402_5% @ 0_0402_5%
S 2N7002KW_SOT323-3
90W(DIS) : 27.4K @

2
2
65W(UMA) : 5.11K 1 2

1
2
PR216
@ 47K_0402_1%

0_0402_5%
[42] PROCHOT 1 2 2 1 1 2 ECAGND
MAINPWON [42,50]

PR218
PR217
PR214 @ PR215 0_0402_5% 1 2
@ 0_0402_5% +3VALW
@ 0_0402_5%

2
@

Turbo_V

NTC_V
[42]

[42]
20120731
1. Change PR214,PR211,PR213 and PR235 footprint to R0402_0ohm-NEW

B B

PQ202
TP0610K-T1-GE3_SOT23-3

3 1
B+ +VSBP

100K_0402_1%

0.22U_0603_25V7K
1

1
PR219

PC204
PC205
0.1U_0603_25V7K

2
2

2
PR220
VL 22K_0402_1%
1 2
2

PR221
@ 100K_0402_1%

PR222
1

@ 1K_0402_5% D PJ201
1 2 2 PQ203 @ JUMP_43X39
[50] SPOK 1 2
G 2N7002KW_SOT323-3 +VSBP 1 2 +VSB
1U_0402_6.3V6K

S
3
1

PC206

PR223
1K_0402_5%
1 2
2

[42,46] PCH_PWR_EN
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: Wednesday, January 09, 2013 Sheet 48 of 62
5 4 3 2 1
 5 4 3 2 1

P3
B+ Need EC write ChargeOption() bit[8]=1
P2 Setting (ACP to PHASE Rising Threshold)=1350mV(min)
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
SH00000AA00
5 5 1 4 1 2 PQ303
PL301 AO4407AL_SO8
2 3 1UH_PCMB061H-1R0MS_7A_20% 1 8

4
2 7
3 6

@ 10U_0805_25V6K

@ 10U_0805_25V6K

2200P_0402_50V7K
PQ304 5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
1 2
47K_0402_5%
1

2
200K_0402_1%
0.1U_0603_25V7K

PC308

4
1
PR301

PC303

PC304

PC305

PC306

PC307
DTA144EUA_SC70-3 PC302 DISCHG_G

PC301

PR303
5600P_0402_25V7K

1
PR304
200K_0402_1%
2

2
2 1 2

2
ACN VIN

1SS355_SOD323-2
2

2ACOFF
1

ACP PR305

1DISCHG_G-1
47K_0402_1%
1

2
+3VALW

PD301
P2-1 PR306

0.1U_0603_25V7K

1
2 200K_0402_1%
PQ305 PQ306
PC309 PC310 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3
[49] ACPRN 1 2 2 1
3

0.1U_0603_25V7K 2 1 2
6

150K_0402_1%

PC311 PD302 PQ308

PR307

PQ307A 1SS355_SOD323-2
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K P2 2N7002KW _SOT323-3

1
D

0.1U_0603_25V7K
2 1 2 PACIN
1

1
PC312
VIN @ @ G

10K_0402_5%

10K_0402_5%
S

3
2

2
390K_0603_1%

2
1
P2-2

PR309

PR310

10_1206_5%
2

5
6
7
8
C C
PR308
2N7002KDW-2N_SOT363-6

PQ309
PR311

AO4466L_SO8
3
PQ307B

<BOM Structure>

ACOK

CMPIN

CMPOUT

ACP

ACN
1

1
PR312 [42,48] ADP_I
2

47K_0402_1% PR313 21

1
PACIN 1 2 5 1 2 6 TP 4
PACIN ACDET PC315
59K_0603_1% PC314 20 BQ24727VCC1 2
4

PC313 1 2 7 VCC
ACON 1 2 IOUT PL302 PR314

3
2
1
1U_0603_25V6K
1

PQ310 100P_0603_50V8 19 10UH_PCMB063T-100MS_4A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 0.1U_0603_25V7K
[42,48] EC_SMB_DA1
8
SDA
PU301
1 2CHG 1 4
BATT+
BQ24727RGRR_QFN20_3P5X3P5 LX_CHG
18 DH_CHG
HIDRV

5
6
7
8
ACOFF 2 9 2 3
[42] ACOFF SCL SA000051W00

1
[42,48] EC_SMB_CK1

PQ311
PR316 PR317 PC316

AO4466L_SO8

4.7_1206_5%
PR318
316K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
ILIM BTST
1

16251_SN
+3VALW
3

PD303 4
PR319 @

LODRV

1
PC317

PC318
100K_0402_1% 16 2 1

GND
SRN

SRP
REGN

BM
20120615
Change PR313 to 60.4K_0603_1% SD014604280
2

2
RB751V-40_SOD323-2

680P_0603_50V7K
11

1 12

13

14

15

3
2
1
from 64.9K_0603_1% SD014649280

PC319
10_0603_5%
6.8_0603_5%

2
BQ24727VDD

PR321
PC320

PR320
20120723 1U_0603_25V6K

2
@
Change PR313 to 59K_0603_1% SD014590280
from 60.4K_0603_1% SD014604280 2
2

PC321 DL_CHG
B 0.1U_0603_25V7K B
2 1
1

1
PC322 @
0.1U_0603_25V7K PC323
2

2 0.1U_0603_25V7K

BQ24727VDD

PR322
10K_0402_1%
1

1 2
ACIN [16,42]
PR324
PR323 10K_0402_1%
47K_0402_1%
PACIN
2

1 2

ACPRN [49] PR325

2
12K_0402_1%
2

PQ312

A DTC115EUA_SC70-3 A
3

For disable pre-charge circuit.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: W ednesday, January 09, 2013 Sheet 49 of 62

5 4 3 2 1
 5 4 3 2 1

2VREF_8205 PJ402
+3VALW P 2 1 +3VALW
2 1
@ JUMP_43X118

1U_0603_10V6K
D D

1
PJ403

PC402
+5VALW P 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR401 PR402
20120321 13K_0402_1% 30K_0402_1%
1 2 1 2
Change netname to CPU_B+ from B+
PR403 PR404
RT8205_B+ 20K_0402_1% 19.6K_0402_1% RT8205_B+
1 2 1 2
CPU_B+ PJ401 Typ: 175mA
2 1 +3VLP
0.1U_0603_25V7K

2 1

ENTRIP2

ENTRIP1
@ JUMP_43X118 PR405 PR406
PC401

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

130K_0402_1% 66.5K_0402_1%
1 2 1 2
PC403

PC409
4.7U_0805_10V6K
1

1
PC404

PC405

PC406

PC407

PC408

PC411
2

8
7
6
5

5
6
7
8
2

2
PC410

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
C PQ401 C

MDS1525URH_SO8
25

PQ402
AO4466L_SO8 P PAD

2
4 4
7 24
VO2 VO1 SPOK [48]
8 23 PR408 PC413
PR407 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
2.2_0603_5% BOOT2 BOOT1
PL401 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH_PCMB063T-4R7MS_5.5A_20% 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_PCMB063T-4R7MS_5.5A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V 12 19 LG_5V
4.7_1206_5%

4.7_1206_5%
LGATE2 LGATE1

5
6
7
8
PQ403
PR409

PR410
SKIPSEL
AO4712L_SO8 KBC_HANGUP_RESET#

VREG5

150U_B2_6.3VM_R35M
PU401

GND
[43]

VIN
2 1

NC
@ RT8205LZQW (2)_W QFN24_4X4 @

EN
1 1
2

2
4 0_0402_5%
+ @ PR420 4 +

PC416
13

14

15

16

17

18
1

1
PC414 PR411
680P_0603_50V7K

PQ404
150U_B2_6.3VM_R35M 499K_0402_1%

680P_0603_50V7K
MDS1521URH 1N SO8
2 1 2 2
PC417

PC418
2

1
2
3

2
CPU_B+

3
2
1
1
@ 20120402 @
100K_0402_1%
+3VALWP

1U_0603_10V6K
VL

1
PC419
Change netname to CPU_B+ from B+

1
OCP min 6.8A
PR412

PC420
Typ: 175mA

4.7U_0805_10V6K
B B
OVP min 3.56V

2
ENTRIP1 ENTRIP2
2

2
RT8205_B+
6

1
PQ405B
PQ405A 2N7002KDW -2N_SOT363-6

0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205

2
PC421
[43] KBC_HANGUP_RESET#
1

20120606
+5VALWP
PR419 and PR420 unmount OCP min 8.5A
2

@ PR419 PR415 OVP min 5.4V

0_0402_5% 100K_0402_1%
2 1
VL
[42] EC_ON
1

PR413
2.2K_0402_5%
2 1

PQ407
PR414
[42,48] MAINPWON @ 0_0402_5% 2N7002KW _SOT323-3
1

D
1 2 2
G
S
4.7U_0603_6.3V6M

A A
1

PC422

20120731
1. Change PR414 footprint to R0402_0ohm-NEW
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: W ednesday, January 09, 2013 Sheet 50 of 62
5 4 3 2 1
 A B C D

@PJ501
1.5V_B+ 1
1 2
2 CPU_B+
STATE S3 S5 1.5VP VTT_REFP 0.75VSP

4.7U_0805_25V6-K

4.7U_0805_25V6-K
JUMP_43X118

1
PC501

PC502
S0 Hi Hi On On On 20120321

5
Change netname to CPU_B+ from B+
Off

2
S3 Lo Hi On On (Hi-Z) +1.5VP PQ501
TPCA8065-H_PPAK56-8-5
UG_1.5V 4
S4/S5 Lo Lo Off Off Off PJ502 @

1
1
JUMP_43X39 20120405 1
LX_1.5V
Change PL501 to H = 3 SH00000AB00

3
2
1
Note: S3 - sleep ; S5 - power off

2
PR501 PC503 PL501

2
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB103T-1R0MS_13A_20%
BST_1.5V 1 2 BST_1.5V-1 1 2 2 1
+0.75VSP +1.5VP
201201002

10U_0805_25V6K

10U_0805_25V6K

1
Change PC506 to 15mohm SGA00002280

5
20

19

18

17

16

TPCA8057-H_PPAK56-8-5
<BOM Structure> <BOM Structure>

PQ502
PC504

PC505
PU501 PR502 @
4.7_1206_5% 1

VTT

VLDOIN

BOOT

UGATE

PHASE
21

2
PAD + PC506
1 15 LG_1.5V 4 330U_D2_2.5VY_R9M
VTTGND LGATE

1
2

680P_0603_50V7K
2 14
VTTSNS PGND

PC507
PR503

3
2
1

2
6.65K_0402_1%
3 13 2 1
GND RT8207MZQW _W QFN20_3X3 CS

4 12
+1.5VP
+VTT_REFP VTTREF VDDP @ OCP min 20A
5 11 2 1 OVP min 1.65V
+1.5VP VDDQ VDD
+5VALW

PGOOD
PR504
+3VALW
1

5.1_0603_5%

1U_0603_10V6K
TON
PC508

FB

S3

S5
2 0.033U_0402_16V7K 2
2

1
PC509
10K_0402_5%
6

10

PR505
PC510
1U_0603_10V6K

S3_1.5V

2
PR506

S5_1.5V
49.9K_0402_5% @

2
42,46,51,53,54] SUSP# 1 2 PGOOD_1.5V
20120321
PR507 PR508
0_0402_5% 887K_0402_1%
Add PJ507
[42,46] SYSON 1 2 2 1 1.5V_B+

PR509 PJ507
1

PC511 @ PC512 6.2K_0402_1% 2 1

0.1U_0402_16V6K 0.1U_0402_16V7K 2 1 2 1
@ JUMP_43X118
2

PQ503@ FB=0.75V 20120626

1

D
1

2N7002KW _SOT323-3 PJ503

2 To GND = 1.5V Change PR509 to 6.34K_0402_1% SD034634180 from 5.9K_0402_1% SD034590180 +1.5VP 2 1 +1.5V
G PR510 To VDD = 1.8V 20121204 2 1
[10,46,54] SUSP S
5.6K_0402_1% Change PR509 to 6.2K_0402_1% SD00000GM80 from 6.34K @ JUMP_43X118
3

PJ504
2 1
+0.75VSP 2 1 +0.75VS

JUMP_43X79
@
3 3

20120723
Change PU502 to SA00004CY10 S IC RT8061AZQW WDFN 10P PWM from SA00003RU00 S IC SY8033BDBC DFN 10P SINGLE BUCK

PU502 PL502
+1.8VP
4

PJ505 1UH_PH041H-1R0MS_3.8A_20% current limit min 4A

2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+3VALW
PG

2 1 PVIN LX +1.8VSP
@ JUMP_43X79 9 3
68P_0402_50V8J

PVIN LX
1

1
680P_0603_50V7K 4.7_1206_5%
1

1
PC514

PC513 8
SVIN
PR511

22U_0805_6.3VAM PR512
6 20K_0402_1%

2200P_0402_50V7K

68P_0402_50V8J

0.1U_0402_25V6
2

5 FB
22U_0805_6.3VAM

22U_0805_6.3VAM
1 2

EN
1

1
PC520

PC517

PC518
NC

NC

@ PJ506
TP

PC515

PC516
FB=0.6Volt +1.8VSP 2 1 +1.8VS
2 1
[10,25,42,46,51,53,54] SUSP#
PC519

PR513
11

2
1 2 EN_1.8VSP @ JUMP_43X79
2

0_0402_5% @
0.1U_0402_10V7K
2

PC521 @

SY8033BDBC_DFN10_3X3 @ @
1

PR514 @ 1.8VSP max current=4A

1M_0402_5%
1.8VSP_FB
2
1

PR515
4
10K_0402_1% 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: Thursday, January 10, 2013 Sheet 51 of 62
A B C D
 5 4 3 2 1

D D
+3VS PR602
1K_0402_5%
2 1
VID [0] VID[1] VCCSA Vout
PJ602
+VCC_SAP

100K_0402_5%
0 0 0.9V H_VCCSA_VID1 [10] +VCCSAP 2
2 1
1 +VCCSA

1
TDC 4.2A
0 1 0.8V @ JUMP_43X118

PR601
Peak Current 6A
1 0 0.725V OCP current 7.2A
OVP 1.06V

2
1 1 0.675V

+VCCSA_PWRGD
H_VCCSA_VID0 [10]

PR603
[42] SA_PGOOD
1K_0402_5%
output voltage adjustable network 2 1
The 1k PD on the VCCSA VIDs are empty.
20120731 These should be stuffed to ensure that

+VCCSA_VID0
VCCSA VID is 00 prior to VCCIO stability.

+VCCSA_VID1
+5VALW

+VCCSA_PWRGD
1U_0603_10V6K
1. Change PR605 footprint to R0402_0ohm-NEW

2
PR605

PC602
PR604 @ 0_0402_5%
10_0402_1%

1
2 1 +VCCSA_EN 1 2
+V1.05S_VCCP_PWRGOOD [53]
PC601
2.2U_0603_10V7K
1 2
20120731
1. Change PR606 footprint to R0603_0ohm-NEW

18

17

16

15

14

13
PU601 20120411
PR606 PC603

VID1

VID0
Change PL601 footprint to PL302 footprint

PGOOD

EN
V5FILT
V5DRV
@ 0_0603_5% 0.22U_0603_16V7K
C 12 +VCCSA_BT 2 1+VCCSA_BT_1 1 2 C
19 BST PL601
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_10V7K
1
10

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2200P_0402_50V7K
SW
2200P_0402_50V7K

21 @ PR607
0.1U_0603_25V7K

2
PGND
10U_0805_6.3V6M

10U_0805_6.3V6M

4.7_1206_5%

PC604

PC605

PC607

PC608

PC610

PC611
TPS51461RGER_QFN24_4X4 9

PC606

PC609
22 SW
PC613

1 2 2

1
2

VIN
PC612

PC614

PC615

1
23 SW @ PC616
1

2 1 1 VIN 1000P_0603_50V7K
PJ601 7

2
+3VALW 2
2 1
1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
VIN
SW

@ JUMP_43X118 25

COMP

MODE
TP

SLEW

VOUT
VREF
GND
1

6
@ PR608
2 1

33K_0402_5%
PC617 PR609
2 1 100_0402_5%
2 1
0.22U_0402_10V6K

0.01U_0402_25V7K
2
2 1 2 1 PR611
@ 0_0402_5%
PC619

PC618 PR610 1
3300P_0402_50V7K 5.1K_0402_1% 1 2
+VCCSA_SENSE [10]

B B

20120731
1. Change PR611 footprint to R0402_0ohm-NEW

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCCSAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: Wednesday, January 09, 2013 Sheet 52 of 62
5 4 3 2 1
 5 4 3 2 1

D D

20120330
Change net name to +V1.05S_VCCP from +1.05S_VCCP
PJ703
PR705 2 1
[10,25,42,46,51,54] SUSP# 60.4K_0402_1% 2 1
1 2 @ JUMP_43X118
+1.05VS_VCCPP PJ704 +V1.05S_VCCP

@ 10K_0402_1%
2
2 1

.1U_0402_16V7K
<bom structure>
+3VS 2 1

1
PR706
@ JUMP_43X118

PC707

100K_0402_1%
2
1

2
PR707
PR709

1
C 0_0402_5% PJ707 C

100K_0402_1%
[52] +V1.05S_VCCP_PW RGOOD 1 2 1.05VS_B+ 2 1

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1 B+

0.1U_0402_25V6
2
PQ701 @ JUMP_43X118

PR708

1
TPCA8065-H_PPAK56-8-5

PC708

PC712
<BOM Structure>
5
PR710 PC710

PC709

PC711
2.2_0603_5% 0.1U_0603_25V7K

2
1
BST_1.05VS_VCCP 2 1 2

1
10.7K_0402_1%~N

17

16

15

14

13
PU702 4

PAD

PGOOD

EN
MODE

BST
2
PR712

1 12 LX_1.05VS_VCCP PL701
0.1U_0402_25V6

3
2
1
VREF SW 1UH_PCMB104T-1R0MH_18A_20%
+1.05VS_VCCPP
1

2 1
12K_0402_1%
1
PC713

2 11 DH_1.05VS_VCCP
2

REFIN DH
2

1
PR713

1000P_0603_50V7K 4.7_1206_5%
5
PR715 PC714
@ 0_0402_5% TPS51219RTER_QFN16_3X3

PR714
0.01UF_0402_25V7K 1
1

3 <BOM Structure> 10 DL_1.05VS_VCCP

330U_D2_2.5VY_R9M
1 2 GSNS DL +
1

2
@

PC715
TPCA8057-H_PPAK56-8-5
4
4 9 2
VSNS V5 +5VALW +1.05VP
COMP

1
PGND
OCP min 20A

PQ703
TRIP

GND

B B
OVP min 1.24V

3
2
1
[9] VSSIO_SENSE_L

PC716
2
PC717
PR716
5

[9] VCCIO_SENSE

1
1 2 1 2 @
75K_0402_1%

PR717
1

PC718
1 2 @ 10_0402_5% 0.01UF_0402_25V7K 1U_0603_10V6K

2
10_0402_1%
PR718

2
2

20120731
PC719
1. Change PR715 footprint to R0402_0ohm-NEW
1000P_0402_50V7K
1

<BOM Structure> PR719

1 2

10_0402_1%
2

PC720
1000P_0402_50V7K
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS_VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: W ednesday, January 09, 2013 Sheet 53 of 62
5 4 3 2 1
 A B C D

20120405
20121015 +V1.05S_VCCP +1.05VS_VGA Change PQ802 and PJ802 netname to +V1.05S_VCCP from +1.05VS
PJ802
1.Change PR816 from SD028100380 S RES 1/16W 100K +-5% 0402 to +V1.05S_VCCP
2 1
SD028100180 S RES 1/16W 1K +-5% 0402 +5VALW 2 1 +1.05VS_VGA
8 1
7 2 @ JUMP_43X118

2
2.Change PQ803 from NA to SB000009Q80 S TR 2N7002KW 1N SOT323-3 6 3

1
PC801 5 PC802 PC803 PR813
10U_0805_10V6K 22_0603_5%

2
2
3.Change PR813 from NA to SD000001R80 S RES 1/10W 22 +-5% 0603 MDS1521URH 1N SO8 10U_0805_10V6K 1U_0603_10V6K PR815

2
PR814 PQ802 <BOM Structure> 0_0402_5%

1
20K_0402_1% PQ803
4.Change PR815 from NA to SD028000080 S RES 1/16W 0 +-5% 0402 PR816 2N7002KW_SOT323-3 1 2
DGPU_PWROK# [46,54]

1
1K_0402_5% D

1
1 2 2 1 2 SUSP GPU_B+ PJ801 B+
SUSP [10,46,51,54]

1
PR818 PC804 G 2 1
0_0402_5% PR817 @ 2 1
S

3
0.1U_0603_25V7K 0_0402_5% @ JUMP_43X118

2
1 1
1 2
[46,54] DGPU_PWROK# PQ804

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

2200P_0402_50V7K
1
D 2N7002KW_SOT323-3 PR821
1 2 2
[10,46,51,54] SUSP SUSP 2.2_0603_5%
+VGA_COREP

1
1
U2_BOOT1 2

PC805

PC806

PC807

PC808
G
PR819 @ S OCP min 60A

3
0_0402_5%
OVP min 1.525V

2
2

5
+3VS_VGA PC809
0.22U_0603_10V7K

1
1
PR801 U2_UGATE1 4
20120926 0_0402_5% PR823
0_0402_5%
1. Add PC871 for reserve @
PQ801

2
1 2 NVVDD_PWM_VID <23>
TPCA8065-H_PPAK56-8-5

3
2
1
+VGA_CORE
<BOM Structure>

1
PL801
2phase --> PSI > 2.4V

1
@ PC871 PR826 0.36UH_PDME064T-R36MS1R405_24A_20%
20120919 2700P_0402_50V7K 0_0402_5% 1phase --> PSI < 0.8V U2_PHASE1 1 2
1. Change PQ810 gnd net name to gnd from GPU_FBRTN @ HW pull high

2
PQ806

5
1 1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
1
PR832
Change PR842 to 12K from 8.6K

TPCA8057-H_PPAK56-8-5
0_0402_5% PR828 @ + + + +

PC811

PC812

PC866

PC865
4.7_1206_5%
1

1 2 NVVDD_PSI <23>

1
PC846 U2_LGATE1 4 2 2 2 2

2
1U_0402_6.3V6K PR834 +3VS

47P_0402_50V8J
2

2
20K_0402_1% PR842 @

PC854
1

1
PR836 @ PR850 PC813 @

12K_0402_1%
0_0402_5% 10K_0402_1% 680P_0603_50V7K

3
2
1
@

2
<23> GPU_STDBY_EN GPU_FBRTN PR827 PR839 @ PR838

1
2K_0402_1% 20K_0402_1% 0_0402_5%

1
1 2 1 2 GPU_PWR_EN <18,27,46>
1 2
2 GPU_REFIN 2
1

PR805 PR811
2

@ 3K_0402_1% PC827 1 2 NVDD_PWR_EN <18,27,46> GPU_B+

1

PR802 18K_0402_1%
1

1
DMN65D8LW-7_SOT323-3

@ 0_0402_5% PC856 .01U_0402_16V7K @ PR837

@ PQ810 0_0402_5% PR860
12

D 2700P_0402_50V7K @ 2.2_0603_5%

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
2200P_0402_50V7K
2 1

2 2 1 U2_BOOT2 1 2 PQ807

GPU_REFADJ

U2_BOOT1
1 2

5
U2_UGATE1
G

1
GPU_VID
@ PD801

GPU_PSI

PC857

PC858

PC859

PC860
S

GPU_EN
.01U_0402_16V7K

3
1

TPCA8065-H_PPAK56-8-5
PR803 PR829 @ PC810 RB751V-40_SOD323-2 PC861
@ 10K_0402_1% 0_0402_5% 0.1U_0402_25V6
PC864

0.22U_0603_10V7K

2
@
2

2
U2_UGATE2 4
2

GPU_FBRTN
6

1
PU801
PR804 PR822
UGATE1

BOOT1
VID

PSI

EN
REFADJ

3
2
1
0_0402_5% 499K_0402_1% PL802 +VGA_CORE
<24>

VSSSENSE_VGA

GPU_B+ 1 2 2 1 0.36UH_PDME064T-R36MS1R405_24A_20%
PR806 GPU_REFIN 7 24 U2_PHASE1 U2_PHASE2 1 2
.01U_0402_16V7K
1

0_0402_5% PC840 REFIN PHASE1

GPU_VREF 8 23 U2_LGATE1
1 2 @ VREF LGATE1
2

5
GPU_TON 9 22 U2_PWM3 U2_PWM3
TON GND/PWM3

1
PR862 @
1 2 GPU_FBRTN 10 21 PQ809 4.7_1206_5%
PR807 RGND PVCC TPCA8057-H_PPAK56-8-5
<24>

1
VCCSENSE_VGA

TALERT/ISEN2

0_0402_5% @ GPU_FB 11 20 U2_LGATE2

VSNS LAGTE2 U2_LGATE2 4
TSNS/ISEN3

PR808 PC867
VCC/ISNE1

1 2
0_0402_5% 0.1U_0402_25V6 PC853 @ GPU_COMP 12 19 U2_PHASE2
2

SS PHASE2
UGATE2
PGOOD

@ 33P_0402_50V8J
BOOT2

1 2 1 2 1 2 PC870 @
GND

PR812 680P_0603_50V7K

3
2
1

2
0_0402_5%
0_0402_5% RT8813AGQW_WQFN24_4X4
25

13

14

15

16

17

18

1 2 1 2
+VGA_CORE
PR824
3
PR809 20120919 3
GPU_DSBL/ISEN1

PC842
GPU_TSNS/ISEN3

GPU_TALERT/ISEN2

100_0402_1% @ PR810 @
1 2 1 2
1. Del PC847,PC844,PC850,PC851 0.1u_0402_10V7K
GPU_PGOOD1

20121023 2.Add PC828,PC855,PC862,PC863,PC868,PC869 22u_0805_6.3V6M

15.8K_0402_1%
1.Change PR807 to 0ohm SD028000080 from 100ohm SD034100080 .01U_0402_16V7K 20121026
Del PC823,PC825,PC828,PC855,PC862,PC869 SE000000I10 S CER CAP 22UF 6.3V M X5R
U2_UGATE2

1 2
U2_BOOT2

@ PC841
+VGA_CORE Under VGA Core
47P_0402_50V8J +VGA_CORE Near VGA Core
GPU_VREF

+3VS_VGA

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
1

10K_0402_1%

1
PR833

PC815

PC816

PC817

PC818

PC819

PC820

PC821

PC822

47U_0805_4V

4.7U_0805_6.3V6K
1
PR840

9.09K_0402_1%

1
PC824

PC826
2

2
2

2
470K_0402_5%_TSM0B474J4702RE

470K_0402_1%

DGPU_PWROK
2

<19,27,46>
1
PH801

PR820

1U_0402_6.3V6K
1

+5VS
PC814

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
1

1
PC829

PC830

PC831

PC832

PC833

PC834

PC835
1

1
PC836

PC837

PC838

PC839
2

PR831
2

2
0_0402_5% PR830

2
2.2_0603_5%
1 2 1 2
.1U_0603_25V7K

PR825
1

2 1
PC852

+3VS_VGA
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
100K_0402_1%
2

1
4 4
PC848

PC843

PC845

PC849

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1
<23> GPU_HOT# 1 2

PC828

PC855

PC863

PC868
2

PR835
0_0402_5% 2 2 2 2

@ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9601P
Date: Wednesday, January 09, 2013 Sheet 54 of 62
A B C D
 5 4 3 2 1

20120514 PR915,PR946=200K(setting 113 degreeC)

Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE PR915,PR946=8.25K(setting 93 degreeC)
from SL200000500 220K_0402_5%_ERTJ0EV224J
PC902

1200P_0402_50V7K
1 PR901 2 FBA3 1 2 PC901 1 2

1000P_0402_50V7K
<BOM Structure>
D PUT COLSE D

75K_0402_1%
10_0402_1% 680P_0402_50V7K .1U_0402_16V7K
TO GT

1
PR903 1 PR904 2
Inductor

PC903

PC904

PR905
TRBSTA# 1 PR902 2 FBA1 1 2 PH901
2P: 24K 24.9K_0402_1% PR906 PC906

1
1
1.21K_0402_1% 10.7K_0402_1%~N 220K_0402_5%_TSM0B224J4702RE CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC905 1P: 24.9K

2
PR908 PC907 PC908 2 PR907 1 NTC_PH203 1K_0402_1% 1000P_0402_50V7K

2
4700P_0402_25V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 20120514 2P: 1.65K
680P_0402_50V7K PR910 10P_0402_50V8J PC909
1 PR909 2 1 2 COMPA1 1 2
Change PR921 to 71.5K_0603_1% SD014715280 1P: 1K
from 63.4K_0603_1% SD014634280
1K_0402_1% 6.04K_0402_1% 2200P_0402_50V7K CSREFA
20120731 <BOM Structure> PC910 TSENSEA

2
1 PR912 2 SWN1A 0.047U_0402_16V7K
1. Change PR937,PR954,PR926,PR936,PR938
footprint to R0402_0ohm-NEW 2P: 21.5K 71.5K_0603_1% PR913 6.98K_0402_1%

1
PR937 CSP1A 1 2
1P: 15.8K SWN1A [56]

2
15.8K_0402_1%
@ 0_0402_5%

CSCOMPA
1 2 PC911
[10] VCC_AXG_SENSE

2
200K_0402_1%
1PR914
1000P_0402_50V7K

1
PR954 PC912 PH904

PR915
@ 0_0402_5% 1000P_0402_50V7K
CSREFA [56]

1
1 2 100K_0402_1%_TSM0B104F4251RZ
[10] VSS_AXG_SENSE
PC914

1
CSP2A
CSP1A
1 2

TRBSTA#

DROOPA

CSSUMA

TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K

DIFFA

ILIMA
+V1.05S_VCCP @

PR918 2P: 36K

1 2 PUT COLSE
26.1K_0402_1% 1P: 26.1K

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+5VS 1 PR919 2 PU901 TO V_GT
C HOT SPOT C
2_0603_5%

VSNA
VSPA
DIFFA

FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD

TRBSTA#
6132_PWMA
PC915
1 2 6132_VCC
.1U_0402_16V7K

.1U_0402_16V7K

1 45 PR921 PC918
2.2U_0603_10V7K 2 VCC PWMA 44 BSTA1 1 2 BSTA1_11 2
VDDBP BSTA +5VS
130_0402_1%

54.9_0402_1%

PR920 3 43 2.2_0603_5% 0.22U_0603_25V7K

VRDYA HGA HG1A [56]
1

PR922 2

1 2VR_ON_CPU 4 42
[42] VR_ON EN SWA SW1A [56]
PR923

PC916 PC917 0_0402_5% VR_SVID_DAT1 5 41 PC919

SDIO LGA LG1A [56]
VR_SVID_ALRT# 6 40 BST2 1 PR924 2 BST2_1 1 2 2Phase: @
2

PR927 PR925 VR_SVID_CLK 7 ALERT# BST2 39 2.2_0603_5% 0.22U_0603_25V7K

SCLK HG2 HG2 [56] 1Phase: install

1
@ PR926 0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 [56]
1

1 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37 PC920 PR928

[9] VR_SVID_DAT ROSC LG2 LG2 [56] 1 phase GFX
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR930 2 1 2 0_0402_5%
[9] VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 0_0402_5% 2.2U_0603_10V7K
[9] VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K

PR929 1K_0402_1% VGATE 12 34

LG1 [56] +5VS

2
VRDY LG1
1

13 33 CSP2A
+V1.05S_VCCP VSN SW1 SW1 [56]
PC921 14 32 PC922
+3VS VSP HG1 HG1 [56]
DIFF_CPU 15 31 BST1 1 PR931 2 BST1_1 1 2

CSCOMP
2

DIFF BST1

TRBST#
2.2_0603_5% 0.22U_0603_25V7K

DROOP

CSSUM

DRVEN
CSREF
1

COMP

TSNS
CSP3
CSP2
CSP1

PWM
IOUT
ILIM
1

PR932 @

FB
75_0402_1% PR933 +5VS
10K_0402_5%

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3P: 73.2K
2

1 PR934 2
[42] VR_HOT# 2P: 41.2K
2

COMP_CPU

1
PR936 FB_CPU 41.2K_0402_1% Option for 3Phase: @
TRBST#
[16] VGATE
@ 0_0402_5% 2 phase CPU PR935

DROOP
2Phase: install

TSENSE
ILIM_CPU
1 2 VSN 3P: 22p 0_0402_5%
[9] VSSSENSE 6132_PWM
1

2P: 10p
IMON

PR938 PC923

2
@ 0_0402_5% 1000P_0402_50V7K CSP3
2

1 2 VSP PC924
[9] VCCSENSE
2
PR939 12.4K_0402_1%

1 2
.1U_0402_16V7K
IMVP_IMON

B PR941 B
20120514 PC926 CSP1 CSP2 1 6.98K_0402_1%
2 TSENSE
SWN2 [56]
3P: 330p 1 PR940 2 2 1 CSP2 20120723
Change PC928 to 560P_0402_50V7K SE074561K80
1

2
1K_0402_1% CSP3
2P: 1000p unmount PR915 and PR946

1
from 680P_0402_50V7K SE074681K80 22P_0402_50V8J PC927 PR960 @
0.047U_0402_16V7K 6.98K_0402_1%
PR942 PC928 PR943 PC929 3P: 21K

2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1
2P: 12.4K

1
PR944 PC930 49.9_0402_1% 6.04K_0402_1% CSREF

200K_0402_1%
1 2FB_CPU3 1 2 560P_0402_50V7K 1500P_0402_50V7K

PR946 1

2
10_0402_1% 3P: 6.04K CSP1 1 PR9452
CSREF [56] SWN1 [56]
CSCOMP

0.033U_0402_16V7K 6.98K_0402_1% PH902

2P: 4.32K

2
PR947 PR948 PC932 PC931
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p0.047U_0402_16V7K PR961 @ 100K_0402_1%_TSM0B104F4251RZ
1
0.033U_0402_16V7K

2P: 1200p 6.98K_0402_1%

1
1

8.06K_0402_1% 806_0402_1% 3P: 2200p

PC933
2P: 3300p

1
CSSUM CSREF
2

PC934 @
3P: 348 3P: 3.65K
1 2
2P: 1.21K 2P: 9.53K 1000P_0402_50V7K 1 PR949 2 SWN1
24.9K_0402_1%

143K_0603_1% PUT COLSE

2

.1U_0402_16V7K

TO VCORE
PC935

3P: 23.7K 1 2 PC936 1 PR951 2 SWN2

HOT SPOT
PR950

1000P_0402_50V7K 143K_0603_1%
2P: 24.9K
1

1 PR952 2NTC_PH201 1 PR953 2 20120514

1

75K_0402_1%
PR955 PC937 165K_0402_1%
Change PR949,PR951 to 143K_0603_1% SD014143380 from 130K_0603_1% SD014130380
CSCOMP 1 2 DROOP 1 2 CSREF PH903 20120514
PUT COLSE Change PC936 to 1000P_0402_50V7K SE074102K80 from 680P_0402_50V7K SE074681K80
1K_0402_1% 1000P_0402_50V7K 2 1
TO VCORE
3P: 806 Phase 1 220K_0402_5%_TSM0B224J4702RE
2P: 1K Inductor
A A

[42] IMVP_IMON

Security Classification
2009/12/01
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C38-G series Chief River Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 09, 2013 Sheet 55 of 62
5 4 3 2 1
 5 4 3 2 1

CPU_B+ CPU_B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
5

5
PL901
FBMA-L11-453215800LMA90T_2P PQ902

1
PQ901 1 2

PC938

PC939

PC940

PC941

PC942

PC943

PC944

PC946
1 CPU_B+

100U_25V_M
+

PC953
2

2
4 1 4
[55] HG1 [55] HG2

100U_25V_M
+VCC_CORE 2 + +VCC_CORE

PC954
TPCA8065-H_PPAK56-8-5 PL902 TPCA8065-H_PPAK56-8-5

3
2
1

3
2
1
D 2 D
0.36UH_PCMB104T-R36MH1R105_30A_20% PL903
<BOM Structure>
0.36UH_PCMB104T-R36MH1R105_30A_20%
1 4 1 4
[55] SW1 [55] SW2

1
2 3 2 3

5
@ PR956 PQ904 @ PR957
PQ903 4.7_1206_5% 4.7_1206_5%

2
PR958
4 V1N_CPU2 1 4 V2N_CPU 2 PR959 1 CSREF
[55] LG1 CSREF [55] [55] LG2

1SNUB_CPU1

SNUB_CPU2
10_0402_1%
10_0402_1%

TPCA8057-H_PPAK56-8-5
SWN1 [55] SWN2 [55]

3
2
1

3
2
1
TPCA8057-H_PPAK56-8-5
@ PC948

1
680P_0603_50V7K @ PC949

2
680P_0603_50V7K

2
C C

DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A

CPU_B+
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_25V7K

B B
1

1
PC957

PC958

PC959

PC960
2

2
5

PQ907

4
[55] HG1A
PL905

TPCA8065-H_PPAK56-8-5
+VCC_GFXCORE_AXG
3
2
1

0.36UH_PCMB104T-R36MH1R105_30A_20%

1 4
[55] SW1A
1

2 3
5

PQ909 @ PR967
V1N_GFX

4.7_1206_5%
2

4
[55] LG1A
SNUB_GFX1

TPCA8057-H_PPAK56-8-5 2 PR971 1
CSREFA [55]
3
2
1

<BOM Structure>
10_0402_1%
1

@ PC968
680P_0603_50V7K SWN1A [55]
2

A A

DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2012/07/11 Title
R_LL=3.9m ohm
OCP~40A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C C38-G series Chief River Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 09, 2013 Sheet 56 of 62
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC1
Socket Bottom 5 x (0805) no-stuff
PC2 PC3 PC4 PC5
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM +VCC_GFXCORE_AXG sites
2 2 2 2 2

D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
@ @ @
sites

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1

PC12

PC13

PC14

PC15

PC16

PC17

PC18

PC19
PC6 PC7 PC8 PC9 PC10 PC11
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+V1.05S_VCCP
+VCC_CORE @
+V1.05S_VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @ @

PC25

PC26

PC27

PC28

PC29

PC30

PC31

PC32

PC33

PC34

PC35
PC20 PC21 PC22 PC23 PC24
2 2 2 2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 @ 1 1 1 1 1 1
2 2 2 2 2

PC36

PC37

PC38

PC39

PC40

PC41

PC42

PC43
2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @

PC49

PC50

PC51

PC52

PC53

PC54

PC55

PC56
PC44 PC45 PC46 PC47 PC48
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2
1 1 1
+ PC57 + PC58 + PC59
C 330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M C

2 2 2
1 1 1
1 1 1 1 1
@ @ PC65 + + PC66 +
PC60 PC61 PC62 PC63 PC64 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 20120514
2 2 2 2 2 2 2 2
Unpop PC58 PC67
@ 330U_D2_2.5VY_R9M

1 1 1 1 20120514
@ @
PC68 PC69 PC70 PC71
Unpop PC66
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2

+VCC_CORE

1 PC72 1 1
330U_D2_2.5VY_R9M
+ + PC73 + PC76
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
B 2 2 2 B

1 1
+ PC74 + PC75
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
2 2

@
20120514
Unpop PC75
Change PC72,PC73,PC74,PC76 to SGA00006100 from 330U_D2_2.5VY_R9M SGA00002680
20120318
Change PC72,PC73,PC74,PC75 to 2 pin footprint

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - PROCESSOR DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9601P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, January 09, 2013 Sheet 57 of 62
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

1 For EC net name P48 PR206 change pull high voltage to +EC_VCCA from +3VLP 20120316 EVT
1.Change PR848 to 1.47K SD000009480 from 1.15K
D
2 Intersil advise P54 2.Unmount PC864 20120316 EVT D

3 VGA IMON setting P54 Change PR853 to 11K SD034110280 from 11.3K 20120316 EVT

4 set OCP is 56A P54 Change PR869 to 1.58K (SD00000SJ80) from 1K 20120316 EVT

5 For 1.5V current P51 Add PJ507 for 1.5V 20120321 EVT

P55 1.Change PC954 pull high to CPU_B+ from B+

6 For B+ layout P50 2.Change 3/5VALWP B+ input netname to CPU_B+
P51 3.Change 1.5VALWP B+ input netname to CPU_B+ 20120321 EVT
P50 4.Change PR411 netname to CPU_B+ from B+

P53 1.Change +1.05S_VCCP netname to +V1.05S_VCCP

7 For HW net name P54 2.Change PQ802.5 netname to +V1.05S_VCCP from +1.05VS 20120330 EVT
C C

1.Add control PU801 pin GPU_PWR_EN and reserve PR956 0_0402_5%

8 For HW power sequence P54 2.Change PR820 to SD034150380 150K_0402_1% from 100K 20120330 EVT
3.Change PC810 to SE071101J80 100P_0402_50V8J from 0.1u

9 For Intersil advise P54 Change PR853 pull down netname to gnd 20120409 EVT

10 For IMON design P55 Change PU901 to NCP6132A from ISL95836 20120412 EVT

11 For layout design P54 1.Del PJ803 PJ804 20120511 DVT

2.Change net name to VGACORE from VGACOREP

12 For 1.05V, GFX_CORE,CPU_CORE design fine tune P57 Unpop PC58, PC66,PC75 330U_D2_2.5VY_R9M SGA00002680 20120514 DVT
B B

13 For CPU_CORE design fine tune and ON advise P57 Change PC72,PC73,PC74,PC76 to S POLY C 330U 2V M D2 ESR9M SGA00006100 20120514 DVT
from 330U_D2_2.5VY_R9M SGA00002680

14 For CPU_CORE design fine tune and ON advise P55 1.Change PC928 to 560P_0402_50V7K SE074561K80 20120514 DVT
from 680P_0402_50V7K SE074681K80
2.Change PR949,PR951 to 140K from 130K
3.Change PR912 to 71.5K_0603_1% SD014715280 from 63.4K_0603_1% SD014634280
4.Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE
from SL200000500 220K_0402_5%_ERTJ0EV224J

15 For material EOL P55 Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE 20120514 DVT
from SL200000500 220K_0402_5%_ERTJ0EV224J

A 16 For HW VGA power sequence P54 Add PR972 SD028000080 0_0402_5% 20120516 DVT A

Unmount PD801
Change PR820 to 0_0402_5% SD028000080 from 150K_0402_1% SD034150380
Unmount PC810
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/06 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: W ednesday, January 09, 2013 Sheet 58 of 62
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

17 For HW reset function P50 1.Add PR420 SD028000080 0_0402_5% for reserve 20120606 PVT
2 reserve.PR419 and PR420
D D

18 For ACDET function P49 1.Change PR313 to 60.4K_0603_1% SD014604280 from 64.9K_0603_1% SD014649280 20120615 PVT

19 For HW Grenn clock UMA sku trial tun P47 1. unmount PD103 20120625 PVT
2. Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080
Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080

20 For ACDET function P49 1.Change PR313 to 59K_0603_1% SD014590280 from 60.4K_0603_1% SD014604280 20120705 PVT

21 For VR_HOT P55 1.unmount PR915 and PR946 20120705 PVT

22 For HW Grenn clock P47 1. mount PD103 20120723 SVT

2. Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080
Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080

C C
23 For material issue P51 1.Change PU502 to SA00004CY10 S IC RT8061AZQW WDFN 10P PWM 20120723 SVT
from SA00003RU00 S IC SY8033BDBC DFN 10P SINGLE BUCK

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Zx90
Date: W ednesday, January 09, 2013 Sheet 58 of 62
5 4 3 2 1
 5 4 3 2 1

COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-7981P
D REVISION: D

DATE: 2011/07/13 10

PCH_PWROK
AC A1
MODE VIN +3V_PCH

V V
A2 A3 B5 +5V_PCH

VV
A5 3

V
PU301 PU401

V
B+
+3VALW B7 3 3
BATT BATT V 10
+5VALW
MODE
B1
B2
B+ B4 V PCH_PWROK
V SYS_PWROK 15 14 VGATE

V
EC 4
PQ2 11
PCH_RSMRST#_R PM_DRAM_PWRGD

V
V V PCH
B3 A5 B7 5 12
PBTN_OUT# H_CPUPWRGD
CPU

V V
13 SVID

V
C C
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 16
PM_SLP_S5#
PM_SLP_SUS#
A4 B6 6
DGPU_PWROK

V
V
ON/OFF

SYSON 7 SYSON#

V
+1.5V
PU501

DGPU_PWR_EN
SUSP#,SUSP 8

(DIS)

V
PU601 U38
B +VCC_SA +5VS 8b B

(DIS)
V

V
PU702 U39
8a
+V1.05S +3VS DGPU

V
V
V

PU602 Q8
+V1.05S_VCCP +1.5VS

PU701

V
SA_PGOOD 8a +0.75VS

13 SVID
VR_ON 9 PU901
V

+VCC_CORE
A A

14 VGATE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 60 of 62
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2 for HW PIR

Item Reason for change PG# Modify List Date Phase

1 Initial EVT
D D

2 For LVDS blacklight PWM P33 R431 change from 0ohm_short to 0ohm mount 5/7 EVT

3 For Change Audio Woofer MOSFET from Dual to single channel P15 Changer Part from SB00000EO10 to SB00000EN00
5/7 EVT

4 For OVERT# Glitch issue at Power on status P23 Add QV9 5/7 EVT
to modify R897 value from 0 ohm to 1K ohm
5 For BT&WLAN Combo Card P36 add BT_DISABLE_F_R on JWLN1.51 5/8 DVT
add R5580

6 For Factory request and cost down LVDS PIN Define P33 To Modify LVDS PIN Define 5/8 DVT
To Add PWRSHARE_EN_R on U31.38
7 For USB Charger mode control request P45 To Add EC_PWRSHARE_EN# on U31.74 5/8 DVT
P42 add R5577 and R5578, delete CHG_ON#
to change R4959 value from 200K ohm to
C 8 P42 0 ohm add R5579 0 ohm 5/8 DVT C
To change Reset IC G601
add R5581,C1331,R5572,R5583,R5584 and Q156
9 Reserved Touch Screen Power Control P42 add EC_TS_ON on U31.66 5/8 DVT
P43 add +3VS_TS,+3VS_TS_R

10 To change Speaker PIN define for ME routing request SPK_L2+ R1556 net in JSPK1.1
P41 SPK_L1- R1554 net in JSPK1.2 5/8 DVT
SPK_R1- R1555 net in JSPK1.3
SPK_R2+ R1553 net in JSPK1.4
R1123,C1134 close to U50.47
11 for Realtek Vendor recommand R5582,R1559 and C1135 Close to U73.1
P41 EXT_MIC_R 5/8 DVT

To Modify H21,H7,H18 PCB Footprint as below

for ME request P39 H21 from H_3P3 to H_4P6 5/8 DVT
12 H7 from H_2P8 to H_3P0
H18 from H_3P3 to H_3P9N

B B
13 for LAN Clock be better P37 change C990 value from 5PF to 0 ohm. 5/9 DVT

change JUSB3.11 from GND to +3VS

for Audio Vendor recommand P43 change JUSB3.12 from +3VS to AGND 5/10 DVT
14

15 for Crystal finetune Capacitor P43 C180,C181 from 18PF to 12PF 5/16 DVT

16 for DVT Board ID request P42 R695 from 33K to 18K 5/17 DVT

17 for PVT request P37 Change Reference from C990 to R5585 5/23 PVT

18 for Surge request P38 C1325,C1326,C1327 change package from 5/23 PVT
0402 to 0603

19 for Reset IC function P42, add R612,PR420,R4960,R4961 5/24 PVT

P50,P43 Delete R4959
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 61 of 62
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2 for HW PIR

Item Reason for change PG# Modify List Date Phase

D D

P18 Remove R5575,connect DGPU_PWR_EN to U31.pin89

Add diode D60;D61 11/13 PVT
20 modify N14P_GV2 GPU power sequence P46
P46 add discharge(Q157) for DGPU_PWR_EN

21 for GC6 function P23 Change RV54 from 10K to 100k 11/29 PVT

22 for GC6 function

P46 Add a 0 ohm R5597 between Q129 pin 2 and Q130 pin 12/26 Pre-MP

23 due to they are cap not resistor. P46 R1108,R1112 location change to C1108,C1112 12/26 Pre-MP
C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9603P
Date: Wednesday, January 09, 2013 Sheet 62 of 62
5 4 3 2 1
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