A B C D E

1 1

Compal Confidential

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Schematics Document

m
Intel Huron River Platform
2 2

ru
Sandy Bridge (Dual Core BGA 1023) With

Fo
Couger Point Core Logic
3
erLA-7401P 3
yb
2011-03-24
REV:1.0
C

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 1 of 56
A B C D E
 A B C D E

Compal Confidential
Model Name : PAJ80(14" UMA/Dis)/PAJ90(15.6" UMA/Dis)
File Name : LA-7401P
1 1

VRAM Intel
N12P-GV 100MHz PCI-E 2.0x16 5GT/s PER LANE DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 2
128Mx16 4pcs=1G Sandy Bridge BANK 0, 1, 2, 3
64Mx16 4pcs=512M OPTIMUS SETUP
Page 11,12

PEG(OPT) Processor
800MHz Page 29-32 Page 22-33 Dual Channel
FCBGA 1023

.ru
31mm*24mm
Optimus Page 4-10

FDI x8 DMI x4 USB connx1 CMOS Camera USB connx2 Card Reader
USB Port 2 USB port 3 USB port 0,1
RTS5129 7 in 1
USB charger
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz
USB port 10

m
Page 42 Page 34 Page 42 Page 42
Page 35 Page 36 Page 34 2.7GT/s 1GB/s x4
2 USBx12 3.3V 48MHz 2
LVDS
Intel
CRT HD Audio 3.3V 24MHz Daughter board
Cougar Point-M

ru
HDMI PCH
PCI-Express x 8 ( PCIE2.0 2.5GT/s) 100MHz 989pin BGA SPI HDA Codec
25mm*25mm ALC259
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz Page 38

Fo
Page 13-21

MINI Card x1 LAN(GbE) SPI ROM x1

WLAN 4 MB Page 13
USB Port 4
RTL8111E-VL Phone Jack x 2
Page 37 Int. Speaker
Page 41
Digital Micx1
Page 39 Page 39
SATA HDD
er SATA ODD
RJ45 Conn. Conn.
3
Page40 Page 40 LPC BUS 3

Page 37
33MHz

ENE KB930
yb
Page 44

USB/CR daughter board

Touch Pad Int.KBD
C

Page 45 Page 45

PWR BTN/Led daughter board

BIOS ROM
Page 44

15.6 ODD daughter board

4 4

T/P daughter board

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 2 of 56
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Voltage Rails
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
USB Port Table BTO Option Table
+1.05VS_DGPU +1.05VS to +1.05VS_DGPU switched power rail for GPU ON OFF OFF BTO Item BOM Structure
2 External
+1.05VS +VCCPP to +1.05VS switched power rail for CPU,PCH ON OFF OFF USB 2.0 USB 1.1 Port USB Port
Optimus OPT@

.ru
0 CONN
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF UHCI0
1 CONN
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Connector CONN@
2 CONN
+VRAM_1.5VS +1.5V to +VRAM_1.5VS power rail for GPU ON OFF OFF UHCI1 Unpop @
3 Camera
+1.8VS +5VALW to 1.8VS switched power rail to CPU,PCH ON OFF OFF EHCI1 14" PCB 14@
4 Mini Card(WLAN/BT)
+3VALW +3VALW always on power rail ON ON ON* UHCI2 15.6" PCB 15@
5 NA
+3VALW_EC +3VALW always to KBC ON ON ON* UMA PCB UMA@
6

m
+LAN_IO +3VALW to +LAN_IO power rail for LAN ON ON ON* UHCI3 Dis PCB (Optimus) OPT@
7
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* X76 512M 512M@
2 8 NA 2
+3VS +3VALW to +3VS power rail ON OFF OFF UHCI4 X76 1G 1G@
9 NA
+5VALW +5VALWP to +5VALW power rail ON ON ON*
10 Card Reader
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON* EHCI2 UHCI5

ru
11
+5VS +5VALW to +5VS switched power rail ON OFF OFF
12
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* UHCI6
+RTCVCC RTC power ON ON ON
13
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Fo
2410M mean 2.3G CPU 2540M mean 2.6G CPU 2520M mean 2.5G CPU 2310M mean 2.2G CPU 2620M mean 2.7G CPU 2330M mean 2.2G CPU PCH R3 GPU R3
PCB DAZ X7613432L03
U2 2410MR3@ U2 2540MR3@ U2 2520MR3@ U2 2310MR3@ U2 2620MR3@ U14 PCHR3@ UV1 GPUR3@
2410M CPU 2540M CPU 2520M CPU 2310M CPU 2620M CPU PCH B3 GPU ZZZ3
ZZZ1

U2 2410MR1@ U2 2540MR1@ U2 2520MR1@ U2 2310MR1@ U2 2620MR1@ U2 2330M@ U14 PCHR1@ UV1 GPUR1@ X76-VRAM
2410M CPU 2540M CPU 2520M CPU 2310M CPU 2620M CPU 2330M CPU PCH B3 GPU PCB_LA-7401P

PCH SM Bus Address

er 1G@

3
yb
Power Device HEX Address SMBUS Control Table
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b SOURCE BATT CPU SODIMM 0 WLAN LCD HDMI PCH GPU
THERMAL SODIMM 1 WWAN DDC DDC
SENSOR ROM ROM
EC_SMB_CK1
KB930
V
C

EC_SMB_DA1
EC_SMB_CK2
EC SM Bus1 Address EC SM Bus2 Address KB930 V V
EC_SMB_DA2
PCH_LCD_CLK
Power Device HEX Address Power Device HEX Address PCH
PCH_LCD_DATA V
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b SDVO_SCLK
PCH
+3VS NVIDIA GPU 9E H 1001 1110 b SDVO_SDATA V
4 4
PCH_SMBCLK
PCH
PCH_SMBDATA V V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 3 of 56
A B C D E
 5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be

shorted and routed
+1.05VS
with - max length = 500 mils - typical
D impedance = 43 mohms D

1
R18
PEG_ICOMPO signals should be routed with -
24.9_0402_1% max length = 500 mils
U2A
- typical impedance = 14.5 mohms

2
G3 PEG_COMP
PEG_ICOMPI
G1
PEG_ICOMPO
<15> DMI_CRX_PTX_N0 M2 G4
DMI_RX#[0] PEG_RCOMPO
<15> DMI_CRX_PTX_N1 P6
DMI_RX#[1]
<15> DMI_CRX_PTX_N2 P1
DMI_RX#[2] PEG_GTX_C_HRX_N15
<15> DMI_CRX_PTX_N3 P10 DMI_RX#[3] PEG_RX#[0] H22
J21 PEG_GTX_C_HRX_N14
PEG_RX#[1] PEG_GTX_C_HRX_N13
<15> DMI_CRX_PTX_P0 N3 DMI_RX[0] PEG_RX#[2] B22
<15> DMI_CRX_PTX_P1 P7 D21 PEG_GTX_C_HRX_N12

.ru
DMI_RX[1] PEG_RX#[3]

DMI
P3 A19 PEG_GTX_C_HRX_N11
<15> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
<PCH> P11 D17 PEG_GTX_C_HRX_N10
<15> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5]
B14 PEG_GTX_C_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8
<15> DMI_CTX_PRX_N0 K1 DMI_TX#[0] PEG_RX#[7] D13
M8 A11 PEG_GTX_C_HRX_N7
<15> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6
<15> DMI_CTX_PRX_N2 N4 DMI_TX#[2] PEG_RX#[9] B10
R2 G8 PEG_GTX_C_HRX_N5
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4
PEG_RX#[11] A8
K3 B6 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N[0..15]
<15> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N[0..15] <22>
<15> DMI_CTX_PRX_P1 M7 DMI_TX[1] PEG_RX#[13] H8
PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_P[0..15]
<15> DMI_CTX_PRX_P2 P4 DMI_TX[2] PEG_RX#[14] E5
PEG_GTX_C_HRX_N0
<PEG> PEG_GTX_C_HRX_P[0..15] <22>
<15> DMI_CTX_PRX_P3 T3 DMI_TX[3] PEG_RX#[15] K7

m
K22 PEG_GTX_C_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14 PEG_HTX_C_GRX_N[0..15]
PEG_RX[1] K19 PEG_HTX_C_GRX_N[0..15] <22>
C21 PEG_GTX_C_HRX_P13
PEG_RX[2] PEG_GTX_C_HRX_P12 PEG_HTX_C_GRX_P[0..15]
<15> FDI_CTX_PRX_N0 U7 FDI0_TX#[0] PEG_RX[3] D19 PEG_HTX_C_GRX_P[0..15] <22>
C PEG_GTX_C_HRX_P11 C
<15> FDI_CTX_PRX_N1 W11 FDI0_TX#[1] PEG_RX[4] C19
W1 D16 PEG_GTX_C_HRX_P10
<15> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]

PCI EXPRESS -- GRAPHICS

AA6 C13 PEG_GTX_C_HRX_P9
<15> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P8
<15> FDI_CTX_PRX_N4 W6 FDI1_TX#[0] PEG_RX[7] D12
V4 C11 PEG_GTX_C_HRX_P7
<15> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]

ru
Y2 C9 PEG_GTX_C_HRX_P6
<15> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]

Intel(R) FDI
AC9 F8 PEG_GTX_C_HRX_P5
<15> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
C8 PEG_GTX_C_HRX_P4
PEG_RX[11] PEG_GTX_C_HRX_P3
C5
PEG_RX[12] PEG_GTX_C_HRX_P2
<PCH> <15> FDI_CTX_PRX_P0 U6
FDI0_TX[0] PEG_RX[13]
H6
PEG_GTX_C_HRX_P1
<15> FDI_CTX_PRX_P1 W10 F6
FDI0_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0
<15> FDI_CTX_PRX_P2 W3 K6
FDI0_TX[2] PEG_RX[15]
<15> FDI_CTX_PRX_P3 AA7
FDI0_TX[3] PEG_HTX_GRX_N15 C16 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N15
<15> FDI_CTX_PRX_P4 W7 G22 1 2
FDI1_TX[0] PEG_TX#[0] PEG_HTX_GRX_N14 C17 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N14
<15> FDI_CTX_PRX_P5 T4 C23 1 2
FDI1_TX[1] PEG_TX#[1]

Fo
AA3 D23 PEG_HTX_GRX_N13 C18 1 2 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N13
<15> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12
AC8 F21 C19 1 2 OPT@ 0.1U_0402_16V7K
<15> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11
H19 C20 1 2 OPT@ 0.1U_0402_16V7K
PEG_TX#[4] PEG_HTX_GRX_N10 C21 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N10
<15> FDI_FSYNC0 AA11 C17 1 2
+1.05VS FDI0_FSYNC PEG_TX#[5] PEG_HTX_GRX_N9 C22 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N9
<15> FDI_FSYNC1 AC12 K15 1 2
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 C23 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N8
F17 1 2
PEG_TX#[7] PEG_HTX_GRX_N7 C24 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N7
<15> FDI_INT U11 F14 1 2
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C25 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N6
A15 1 2
PEG_TX#[9]
1

eDP_COMPIO and ICOMPO signals AA10 J14 PEG_HTX_GRX_N5 C26 1 2 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N5
<15> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R19 AG8 H13 PEG_HTX_GRX_N4 C27 1 2 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N4
should be shorted near balls <15> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% M10 PEG_HTX_GRX_N3 C28 1 2 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N3
PEG_TX#[12]
and routed with typical PEG_TX#[13]
F10 PEG_HTX_GRX_N2 C29 1 2 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N2
D9 PEG_HTX_GRX_N1 C30 1 2 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N1
impedance <25 mohms
2

PEG_TX#[14] PEG_HTX_GRX_N0 C31 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N0

B
EDP_COMP er
AF3
AD2
AG11

AG4
AF4
eDP_COMPIO
eDP_ICOMPO
eDP_HPD

eDP_AUX#
eDP_AUX
DP
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
J4

F22
A23
D24
E21
G19
B18
K17
PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
C32
C33
C34
C35
C36
C37
C38
1

1
1
1
1
1
1
1
2

2
2
2
2
2
2
2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
<PEG>
B

G17 PEG_HTX_GRX_P8 C39 1 2 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P8

PEG_TX[7] PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7
yb
AC3 E14 C40 1 2 OPT@ 0.1U_0402_16V7K
eDP_TX#[0] PEG_TX[8] PEG_HTX_GRX_P6 C41 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P6
AC4 C15 1 2
eDP_TX#[1] PEG_TX[9] PEG_HTX_GRX_P5 C42 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P5
AE11 K13 1 2
eDP_TX#[2] PEG_TX[10] PEG_HTX_GRX_P4 C43 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P4
AE7 G13 1 2
eDP_TX#[3] PEG_TX[11] PEG_HTX_GRX_P3 C44 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P3
K10 1 2
PEG_TX[12] PEG_HTX_GRX_P2 C45 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P2
AC1 G10 1 2
eDP_TX[0] PEG_TX[13] PEG_HTX_GRX_P1 C46 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P1
AA4 D8 1 2
eDP_TX[1] PEG_TX[14] PEG_HTX_GRX_P0 C47 OPT@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P0
AE10 K4 1 2
eDP_TX[2] PEG_TX[15]
AE6
eDP_TX[3]

SANDY-BRIDGE_BGA1023~D
C

Typ- suggest 220nF. The change in AC capacitor

value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 4 of 56
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

XDP_DBRESET# 2 1
R34 1K_0402_5%

PVT:Remove XDP connector for ESD request

.ru
m
This pin is for compability with future U2B
C platforms. A pull up resistor to VCCIO is C
required if connected to the DF_TVS strap J3 CLK_CPU_DMI_R 1 2
BCLK CLK_CPU_DMI <14>
on the PCH. H2 CLK_CPU_DMI#_R R44 1 2 0_0402_5% CLK_CPU_DMI# <14>

CLOCKS
BCLK#

MISC
R45 0_0402_5%
<18> H_SNB_IVB# F49 PROC_SELECT#

ru
AG3 CLK_CPU_DPLL_R 1 2
DPLL_REF_CLK CLK_CPU_DPLL#_R CLK_CPU_DPLL <14>
@ AG1 R47 1 2 0_0402_5%
DPLL_REF_CLK# CLK_CPU_DPLL# <14>
1 2 C57 R46 0_0402_5%
PROC_DETECT (Processor Detect): pulled to R813 10K_0402_5% PROC_DETECT#
ground on the processor package. There is no N59 CLK_RES_ITP
connection to the processor silicon for this BCLK_ITP CLK_RES_ITP# CLK_RES_ITP <14>
N58 CLK_RES_ITP# <14>
signal. System board designers may use this BCLK_ITP#
signal to determine if the processor is present T5 PAD H_CATERR# C49 Buffered reset to CPU
CATERR# +3VS

THERMAL

Fo
1 2 H_PECI_ISO A48 AT30 H_DRAMRST#
<18,43> H_PECI PECI SM_DRAMRST# H_DRAMRST# <6> +1.05VS
R49 0_0402_5% 1
C50
BF44 SM_RCOMP0 R74 2 1 140_0402_1% 0.1U_0402_16V4Z
SM_RCOMP[0]

1
1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 R75 2 1 25.5_0402_1%
<43,55> H_PROCHOT# PROCHOT# SM_RCOMP[1]

DDR3
MISC
R50 56_0402_5% SM_RCOMP2 R77 2
SM_RCOMP[2]
BG43 2 1 200_0402_1% R58
SN74LVC1G07DCKR_SC70-5 @ 75_0402_5%
DDR3 Compensation Signals @

5
1 2 H_THEMTRIP#_R D45 @ U3
<18> H_THRMTRIP#

2
R52 0_0402_5% THERMTRIP#
1

P
NC BUFO_CPU_RST# BUF_CPU_RST#
4 1 2
PLT_RST# Y
N53 <17,22,37,41,43> PLT_RST# 2
PRDY# A

1
R64
er PREQ#
N55
1.5K_0402_5% R69

3
L56 XDP_TCK 750_0402_1%
TCK XDP_TMS
L55
TMS
PWR MANAGEMENT
B XDP_TRST# B
J58

2
JTAG & BPM
TRST# R956
1 2 H_PM_SYNC_R C48 M60 XDP_TDI 0_0402_5%
<15> H_PM_SYNC PM_SYNC TDI XDP_TDO
R53 0_0402_5% L59 1 2
TDO
Processor Pullups
2 H_CPUPWRGD_R
yb
<18> H_CPUPWRGD 1 B46
R56 0_0402_5% UNCOREPWRGOOD XDP_DBRESET# +1.05VS
K58 XDP_DBRESET# <15>
Layout note: Route in High Speed layer to prevent EMC issue DBR#

PM_SYS_PWRGD_BUF 1 2 PM_SYS_PWRGD_BUF_R BE45 G58 2 1 H_PROCHOT#

R59 130_0402_5% SM_DRAMPWROK BPM#[0] R48 62_0402_5%
E55
BPM#[1] H_CPUPWRGD_R
E59 2 1
BPM#[2] R51 10K_0402_5%
G55
BPM#[3] @ H_CPUPWRGD_R
G59 2 1
BUF_CPU_RST# BPM#[4] C2580 220P_0402_50V7K
D44 H60
RESET# BPM#[5]
J59
BPM#[6]
J61
+3VALW BPM#[7]
C

PU/PD for JTAG signals

+3VS +1.5V_CPU_VDDQ
1
C51 +1.05VS
0.1U_0402_16V4Z
1

SANDY-BRIDGE_BGA1023~D XDP_TMS R80 @ 2 1 51_0402_5%

2 R76
U4 200_0402_5% XDP_TDI R81 @ 2 1 51_0402_5%
74AHC1G09GW_TSSOP5
5

XDP_TDO R82 @ 2 1 51_0402_5%

2

2 1 1 Layout note: Close to XDP

P

R2630 10K_0402_5% B PM_SYS_PWRGD_BUF

4
O XDP_TCK R83 @
<15> PM_DRAM_PWRGD 2 A 2 1 51_0402_5%
G

A A
1

XDP_TRST# R84 @ 2 1 51_0402_5%

3

@ R79
39_0402_5%
1 2

D
<46,50> SUSP SUSP 2
Security Classification Compal Secret Data Compal Electronics, Inc.
G Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title
S Q4
PROCESSOR(2/7) PM,XDP,CLK
3

@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2N7002_SOT23-3 Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 5 of 56
5 4 3 2 1
 5 4 3 2 1

U2C
U2D
<11> DDR_A_D[0..63]
DDR_A_D0 <12> DDR_B_D[0..63]
AG6 SA_DQ[0]
DDR_A_D1 AJ6 AU36 M_CLK_DDR0 DDR_B_D0 AL4
DDR_A_D2 SA_DQ[1] SA_CLK[0] M_CLK_DDR#0 M_CLK_DDR0 <11> DDR_B_D1 SB_DQ[0]
AP11 SA_DQ[2] SA_CLK#[0] AV36 M_CLK_DDR#0 <11> AL1 SB_DQ[1] SB_CLK[0] BA34 M_CLK_DDR2 <12>
DDR_A_D3 AL6 AY26 DDR_CKE0_DIMMA DDR_B_D2 AN3 AY34
DDR_A_D4 SA_DQ[3] SA_CKE[0] DDR_CKE0_DIMMA <11> DDR_B_D3 SB_DQ[2] SB_CLK#[0] M_CLK_DDR#2 <12>
AJ10 AR4 AR22 DDR_CKE2_DIMMB <12>
DDR_A_D5 SA_DQ[4] DDR_B_D4 SB_DQ[3] SB_CKE[0]
AJ8 AK4
D DDR_A_D6 SA_DQ[5] DDR_B_D5 SB_DQ[4] D
AL8 AK3
DDR_A_D7 SA_DQ[6] DDR_B_D6 SB_DQ[5]
AL7 AN4
DDR_A_D8 SA_DQ[7] DDR_B_D7 SB_DQ[6]
AR11 AR1
DDR_A_D9 SA_DQ[8] DDR_B_D8 SB_DQ[7]
AP6 AT40 M_CLK_DDR1 <11> AU4
DDR_A_D10 SA_DQ[9] SA_CLK[1] DDR_B_D9 SB_DQ[8]
AU6 AU40 M_CLK_DDR#1 <11> AT2 BA36 M_CLK_DDR3 <12>
DDR_A_D11 SA_DQ[10] SA_CLK#[1] DDR_B_D10 SB_DQ[9] SB_CLK[1]
AV9 BB26 DDR_CKE1_DIMMA <11> AV4 BB36 M_CLK_DDR#3 <12>
DDR_A_D12 SA_DQ[11] SA_CKE[1] DDR_B_D11 SB_DQ[10] SB_CLK#[1]
AR6 BA4 BF27 DDR_CKE3_DIMMB <12>
DDR_A_D13 SA_DQ[12] DDR_B_D12 SB_DQ[11] SB_CKE[1]
AP8 AU3
DDR_A_D14 SA_DQ[13] DDR_B_D13 SB_DQ[12]
AT13 AR3
DDR_A_D15 SA_DQ[14] DDR_B_D14 SB_DQ[13]
AU13 AY2
DDR_A_D16 SA_DQ[15] DDR_B_D15 SB_DQ[14]
BC7 BA3
DDR_A_D17 SA_DQ[16] DDR_B_D16 SB_DQ[15]
BB7 SA_DQ[17] SA_CS#[0] BB40 DDR_CS0_DIMMA# <11> BE9 SB_DQ[16]
DDR_A_D18 BA13 BC41 DDR_B_D17 BD9 BE41
DDR_A_D19 SA_DQ[18] SA_CS#[1] DDR_CS1_DIMMA# <11> DDR_B_D18 SB_DQ[17] SB_CS#[0] DDR_CS2_DIMMB# <12>
BB11 SA_DQ[19] BD13 SB_DQ[18] SB_CS#[1] BE47 DDR_CS3_DIMMB# <12>
DDR_A_D20 BA7 DDR_B_D19 BF12

.ru
DDR_A_D21 SA_DQ[20] DDR_B_D20 SB_DQ[19]
BA9 SA_DQ[21] BF8 SB_DQ[20]
DDR_A_D22 BB9 DDR_B_D21 BD10
DDR_A_D23 SA_DQ[22] DDR_B_D22 SB_DQ[21]
AY13 SA_DQ[23] BD14 SB_DQ[22]
DDR_A_D24 AV14 AY40 DDR_B_D23 BE13
DDR_A_D25 SA_DQ[24] SA_ODT[0] M_ODT0 <11> DDR_B_D24 SB_DQ[23]
AR14 SA_DQ[25] SA_ODT[1] BA41 M_ODT1 <11> BF16 SB_DQ[24] SB_ODT[0] AT43 M_ODT2 <12>
DDR_A_D26 AY17 DDR_B_D25 BE17 BG47
DDR_A_D27 SA_DQ[26] DDR_B_D26 SB_DQ[25] SB_ODT[1] M_ODT3 <12>
AR19 SA_DQ[27] BE18 SB_DQ[26]
DDR_A_D28 BA14 DDR_B_D27 BE21
DDR_A_D29 SA_DQ[28] DDR_B_D28 SB_DQ[27]
AU14 SA_DQ[29] BE14 SB_DQ[28]
DDR_A_D30 BB14 DDR_B_D29 BG14
SA_DQ[30] DDR_A_DQS#[0..7] <11> SB_DQ[29]
DDR_A_D31 BB17 AL11 DDR_A_DQS#0 DDR_B_D30 BG18
DDR_A_D32 SA_DQ[31] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D31 SB_DQ[30] DDR_B_DQS#0 DDR_B_DQS#[0..7] <12>
BA45 SA_DQ[32] SA_DQS#[1] AR8 BF19 SB_DQ[31] SB_DQS#[0] AL3
DDR_A_D33 AR43 AV11 DDR_A_DQS#2 DDR_B_D32 BD50 AV3 DDR_B_DQS#1
SA_DQ[33] SA_DQS#[2] SB_DQ[32] SB_DQS#[1]

m
DDR_A_D34 AW48 AT17 DDR_A_DQS#3 DDR_B_D33 BF48 BG11 DDR_B_DQS#2
DDR_A_D35 SA_DQ[34] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D34 SB_DQ[33] SB_DQS#[2] DDR_B_DQS#3
DDR SYSTEM MEMORY A
BC48 SA_DQ[35] SA_DQS#[4] AV45 BD53 SB_DQ[34] SB_DQS#[3] BD17
DDR_A_D36 BC45 AY51 DDR_A_DQS#5 DDR_B_D35 BF52 BG51 DDR_B_DQS#4

DDR SYSTEM MEMORY B

DDR_A_D37 SA_DQ[36] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D36 SB_DQ[35] SB_DQS#[4] DDR_B_DQS#5
AR45 SA_DQ[37] SA_DQS#[6] AT55 BD49 SB_DQ[36] SB_DQS#[5] BA59
C DDR_A_D38 DDR_A_DQS#7 DDR_B_D37 DDR_B_DQS#6 C
AT48 SA_DQ[38] SA_DQS#[7] AK55 BE49 SB_DQ[37] SB_DQS#[6] AT60
DDR_A_D39 AY48 DDR_B_D38 BD54 AK59 DDR_B_DQS#7
DDR_A_D40 SA_DQ[39] DDR_B_D39 SB_DQ[38] SB_DQS#[7]
BA49 SA_DQ[40] BE53 SB_DQ[39]
DDR_A_D41 AV49 DDR_B_D40 BF56
DDR_A_D42 SA_DQ[41] DDR_B_D41 SB_DQ[40]
BB51 SA_DQ[42] BE57 SB_DQ[41]
DDR_A_D43

ru
AY53 DDR_B_D42 BC59
DDR_A_D44 SA_DQ[43] DDR_B_D43 SB_DQ[42]
BB49 SA_DQ[44] DDR_A_DQS[0..7] <11> AY60 SB_DQ[43]
DDR_A_D45 AU49 AJ11 DDR_A_DQS0 DDR_B_D44 BE54
DDR_A_D46 SA_DQ[45] SA_DQS[0] DDR_A_DQS1 DDR_B_D45 SB_DQ[44]
BA53 AR10 BG54 DDR_B_DQS[0..7] <12>
DDR_A_D47 SA_DQ[46] SA_DQS[1] DDR_A_DQS2 DDR_B_D46 SB_DQ[45] DDR_B_DQS0
BB55 AY11 BA58 AM2
DDR_A_D48 SA_DQ[47] SA_DQS[2] DDR_A_DQS3 DDR_B_D47 SB_DQ[46] SB_DQS[0] DDR_B_DQS1
BA55 AU17 AW59 AV1
DDR_A_D49 SA_DQ[48] SA_DQS[3] DDR_A_DQS4 DDR_B_D48 SB_DQ[47] SB_DQS[1] DDR_B_DQS2
AV56 AW45 AW58 BE11
DDR_A_D50 SA_DQ[49] SA_DQS[4] DDR_A_DQS5 DDR_B_D49 SB_DQ[48] SB_DQS[2] DDR_B_DQS3
AP50 AV51 AU58 BD18
DDR_A_D51 SA_DQ[50] SA_DQS[5] DDR_A_DQS6 DDR_B_D50 SB_DQ[49] SB_DQS[3] DDR_B_DQS4
AP53 AT56 AN61 BE51
DDR_A_D52 SA_DQ[51] SA_DQS[6] DDR_A_DQS7 DDR_B_D51 SB_DQ[50] SB_DQS[4] DDR_B_DQS5
AV54 AK54 AN59 BA61
SA_DQ[52] SA_DQS[7] SB_DQ[51] SB_DQS[5]

Fo
DDR_A_D53 AT54 DDR_B_D52 AU59 AR59 DDR_B_DQS6
DDR_A_D54 SA_DQ[53] DDR_B_D53 SB_DQ[52] SB_DQS[6] DDR_B_DQS7
AP56 AU61 AK61
DDR_A_D55 SA_DQ[54] DDR_B_D54 SB_DQ[53] SB_DQS[7]
AP52 AN58
DDR_A_D56 SA_DQ[55] DDR_B_D55 SB_DQ[54]
AN57 AR58
DDR_A_D57 SA_DQ[56] DDR_B_D56 SB_DQ[55]
AN53 AK58
DDR_A_D58 SA_DQ[57] DDR_B_D57 SB_DQ[56]
AG56 AL58
DDR_A_D59 SA_DQ[58] DDR_B_D58 SB_DQ[57]
AG53 AG58
DDR_A_D60 SA_DQ[59] DDR_B_D59 SB_DQ[58]
AN55 DDR_A_MA[0..15] <11> AG59
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D60 SB_DQ[59]
AN52 BG35 AM60 DDR_B_MA[0..15] <12>
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AG55 BB34 AL59 BF32
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AK56 BE35 AF61 BE33
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
BD35 AH60 BD33
SA_MA[3] DDR_A_MA4 SB_DQ[63] SB_MA[2] DDR_B_MA3
AT34 AU30
SA_MA[4] DDR_A_MA5 SB_MA[3] DDR_B_MA4

B
<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2

<11> DDR_A_CAS#
BD37
BF36
BA28

BE39
SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
er <12> DDR_B_BS0
<12> DDR_B_BS1
<12> DDR_B_BS2
BG39
BD42
AT22
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
B

BD39 AY28 DDR_A_MA14 AV43 BD46 DDR_B_MA13

<11> DDR_A_RAS# SA_RAS# SA_MA[14] <12> DDR_B_CAS# SB_CAS# SB_MA[13]
DDR_A_MA15 DDR_B_MA14
yb
<11> DDR_A_WE# AT41 AU26 <12> DDR_B_RAS# BF40 AT26
SA_WE# SA_MA[15] SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_B_WE# BD45 AU22
SB_WE# SB_MA[15]

SANDY-BRIDGE_BGA1023~D
SANDY-BRIDGE_BGA1023~D

+1.5V
C

@ R88
1

0_0402_5%
1 2 R89
1K_0402_5%
2
S

H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<5> H_DRAMRST# DDR3_DRAMRST# <11,12>
R90 1K_0402_5%
2

Q5
R91 BSS138_NL_SOT23-3
G
2

4.99K_0402_1%
1

A A

<14> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

0.047U_0402_16V4Z

R92 0_0402_5%

1 Security Classification Compal Secret Data Compal Electronics, Inc.

C52

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 6 of 56

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

C FG2

1
R94
1K_0402_1%
D D

2
PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

CFG2 socket pin map definition
U2E 0:Lane Reversed
*

.ru
C FG4
B50 CFG[0] RSVD28 BE7
C51 CFG[1] RSVD29 BG7

1
C FG2 B54 CFG[2]
D53 CFG[3]
C FG4 A51 N42 @ R95
C FG5 CFG[4] RSVD30 1K_0402_1%
C53 CFG[5] RSVD31 L42
C FG6 C55 L45

2
C FG7 CFG[6] RSVD32
H49 CFG[7] RSVD33 L47
A55 CFG[8]
H51 CFG[9]
K49 CFG[10] RSVD34 M13

m
K53 CFG[11] RSVD35 M14
F53 CFG[12] RSVD36 U14 Display Port Presence Strap
G53 CFG[13] RSVD37 W14
L51 CFG[14] RSVD38 P13
C C
F51 CFG[15] 1 : Disabled; No Physical Display Port
D52 CFG[16] CFG4 attached to Embedded Display Port
L53 CFG[17] RSVD39 AT49
RSVD40 K24
0 : Enabled; An external Display Port device is
*

RESERVED
VCC_VAL_SENSE H43

ru
1 @ 2
+CPU_CORE
R858 2 @ 1 49.9_0402_1% VSS_VAL_SENSE K43 VCC_VAL_SENSE
AH2
connected to the Embedded Display Port
R859 49.9_0402_1% VSS_VAL_SENSE RSVD41
AG13
RSVD42
AM14
@ VAXG_VAL_SENSE H45 RSVD43
+VGFX_CORE 1 2 AM15
R860 2 @ VSSAXG_VAL_SENSE K45 VAXG_VAL_SENSE RSVD44 C FG6
1 49.9_0402_1%
R861 49.9_0402_1% VSSAXG_VAL_SENSE
N50 C FG5
RSVD45
F48
VCC_DIE_SENSE

1
Fo
@ R98 @ R99
CPU_RSVD6 H48 1K_0402_1% 1K_0402_1%
CPU_RSVD7 RSVD6
K48
RSVD7
A4

2
DC_TEST_A4
1

C4
DC_TEST_C4
BA19 D3
R96 R97 RSVD8 DC_TEST_D3
AV19 D1
1K_0402_1% 1K_0402_1% RSVD9 DC_TEST_D1
AT21 A58
RSVD10 DC_TEST_A58
BB21 A59
2

RSVD11 DC_TEST_A59
BB19 C59
RSVD12 DC_TEST_C59
AY21 A61
RSVD13 DC_TEST_A61
BA22 C61
RSVD14 DC_TEST_C61
AY22
RSVD15 DC_TEST_D61
D61 PCIE Port Bifurcation Straps

B
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
er RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
B

BE26 BG1
RSVD25 DC_TEST_BG1
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
yb
BF23 BE1
RSVD26 DC_TEST_BE1
BE24 BD1
RSVD27 DC_TEST_BD1

C FG7
SANDY-BRIDGE_BGA1023~D

1
@ R100
1K_0402_1%
C

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 7 of 56
5 4 3 2 1
 5 4 3 2 1

U2F
1.9m [ Loadline Design
SV type CPU +1.05VS
18A
+CPU_CORE AF46
Mid-Frequency Decoupling
VCCIO[1]

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
53A VCCIO[3] AG48
Mid-Frequency Decoupling A26
VCCIO[4] AG50
AG51
1 1 1 1 1 1 1 1 1 1
VCC[1] VCCIO[5]

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C53

C54

C55

C56

C57

C58

C59

C60

C61

C62
A29 VCC[2] VCCIO[6] AJ17
1 1 1 1 1 1 1 1 1 A31 VCC[3] VCCIO[7] AJ21
2 2 2 2 2 2 2 2 2 2

C761

C86

C87

C88

C89

C90

C672

C670
A34 AJ25
VCC[4] VCCIO[8]

C104
A35 AJ43
VCC[5] VCCIO[9]
A38 AJ47
D 2 2 2 2 2 2 2 2 2 VCC[6] VCCIO[10] D
A39 AK50
VCC[7] VCCIO[11]
A42
C26
VCC[8] VCCIO[12]
AK51
AL14
High-Frequency Decoupling
VCC[9] VCCIO[13]

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C27 AL15
VCC[10] VCCIO[14]
C32 AL16 1 1 1 1 1 1 1 1 1 1
VCC[11] VCCIO[15]
C34 AL20
VCC[12] VCCIO[16]

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C68

C69

C70

C71

C72

C73

C74

C75

C76

C508
C37 AL22
VCC[13] VCCIO[17]
1 1 1 1 1 1 1 1 C39 AL26
VCC[14] VCCIO[18] 2 2 2 2 2 2 2 2 2 2

C762

C95

C94

C93

C92

C91

C763

C764
C42 AL45
VCC[15] VCCIO[19]
D27 AL48
VCC[16] VCCIO[20]
D32 AM16
2 2 2 2 2 2 2 2 VCC[17] VCCIO[21]
D34 VCC[18] VCCIO[22] AM17
D37 VCC[19] VCCIO[23] AM21
D39 VCC[20] VCCIO[24] AM43

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
D42 AM47

.ru
VCC[21] VCCIO[25]
E26 VCC[22] VCCIO[26] AN20 1 1 1 1 1 1 1 1 1 1
E28 VCC[23] VCCIO[27] AN42
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C503

C527

C507

C505

C509

C506

C136

C504

C649

C529
E32 VCC[24] VCCIO[28] AN45
1 1 1 1 1 1 1 1 E34 VCC[25] VCCIO[29] AN48
2 2 2 2 2 2 2 2 2 2
C100

C99

C98

C97

C96

C101
E37 VCC[26]

C102

C103
E38 VCC[27]

CORE SUPPLY
F25 VCC[28]
2 2 2 2 2 2 2 2 F26

PEG AND DDR

VCC[29]
F28 VCC[30]
F32 VCC[31]

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
F34 VCC[32]
F37 VCC[33] VCCIO[30] AA14 1 1 1 1 1 1
F38 VCC[34] VCCIO[31] AA15

m C721

C648

C646

C655

C647

C528
F42 VCC[35] VCCIO[32] AB17
G42 VCC[36] VCCIO[33] AB20
2 2 2 2 2 2
Low-Frequency Decoupling H25
H26
VCC[37] VCCIO[34] AC13
AD16
C VCC[38] VCCIO[35] C
H28 VCC[39] VCCIO[36] AD18
330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

1 1 1 1 H29 VCC[40] VCCIO[37] AD21

H32 VCC[41] VCCIO[38] AE14 Mid-Frequency Decoupling
C105

C106

C107

C108

+ + + + Note: H34 AE15

2Pin 470uF PN SGA00004200 VCC[42] VCCIO[39]
H35 VCC[43] VCCIO[40] AF16

330U_D2_2V_Y

330U_D2_2V_Y
ru
Need confirm Type with Power Team before SMT H37 AF18 1 1
2 2 2 2 VCC[44] VCCIO[41]
H38 VCC[45] VCCIO[42] AF20

C83

C84
H40 AG15 + +
VCC[46] VCCIO[43]
J25 AG16
VCC[47] VCCIO[44]
J26 AG17
VCC[48] VCCIO[45] 2 2
J28 AG20
VCC[49] VCCIO[46]
DVT:Update C105 C106 C107 C108 footprint J29
VCC[50] VCCIO[47]
AG21
DVT:Reserved C918 (Co-layout C106) J32
VCC[51] VCCIO[48]
AJ14

POWER
J34 AJ15
VCC[52] VCCIO[49]
High-Frequency Decoupling J35
VCC[53]

Fo
J37
VCC[54]
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

J38
VCC[55]
1 1 1 1 1 1 1 1 J40
VCC[56] +1.05VS
C769

C770

C771

C772

C773

C774

C775

C776

J42
VCC[57]
K26 W16
VCC[58] VCCIO50
K27 W17 1 2
2 2 2 2 2 2 2 2 VCC[59] VCCIO51 R862 0_0805_5%
K29
VCC[60]
K32
VCC[61]
K34
VCC[62]
K35
VCC[63]
K37
VCC[64]
K39
VCC[66]
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

K42 BC22 @ T85 PAD

VCC[67] VCCIO_SEL
1 1 1 1 1 1 1 1
er L25
VCC[68]
C777

C778

C779

C780

C781

C782

C783

C784

L28
VCC[69]
L33
VCC[70] +1.05VS +1.05VS
L36
B 2 2 2 2 2 2 2 2 VCC[71] +1.05VS B
L40

QUIET RAILS
VCC[72]
N26
VCC[73]
N30 AM25
VCC[74] VCCPQE[1]

1
N34 AN22 2
VCC[75] VCCPQE[2] R102 R103
N38
VCC[76] C722 130_0402_5% 75_0402_5%
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

yb
1U_0402_6.3V6K
1
1 1 1 1 1 1 1 1

2
C785

C786

C787

C788

C789

C790

C791

C792

2 2 2 2 2 2 2 2 A44 H_CPU_SVIDALRT# 1 2
VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# <54>
B43 R104 1 2 43_0402_1%
SVID
VIDSCLK H_CPU_SVIDDAT VR_SVID_CLK <54>
C44 R105 1 2 0_0402_5%
VIDSOUT VR_SVID_DAT <54>
R106 0_0402_5%
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
C

1 1 1 1 1 1 1 1
C793

C794

C795

C796

C797

C798

C799

C800

Place the PU resistors close to CPU

2 2 2 2 2 2 2 2 1 2 +CPU_CORE
F43 VCCSENSE_R R108 1 2 0_0402_5% R107 100_0402_1%
SENSE LINES

VCC_SENSE VCCSENSE <54>

G43 VSSSENSE_R R109 1 2 0_0402_5%
VSSSENSE <54>
VSS_SENSE
1 2
R111 100_0402_1%
Place the PU resistors close to VR
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1 1 1 AN16 VCCIO_SENSE VCCIO_SENSE <51>

VCCIO_SENSE
C801

C802

C803

AN17 VSS_SENSE_VCCIO VSS_SENSE_VCCIO <51>

VSS_SENSE_VCCIO
A R954 1 A
2 10_0402_5%
2 2 2 +1.05VS
@

SANDY-BRIDGE_BGA1023~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 8 of 56
5 4 3 2 1
 5 4 3 2 1

GT2 3.9mΩ Loadline Design

U2G +1.5V_CPU_VDDQ

+VGFX_CORE
26A

1
D D
+V_SM_VREF,+V_SM_VREF_CNT should
R113
Mid-Frequency Decoupling AA46 have 20 mil trace width 1K_0402_1%
VAXG[1]

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AB47
VAXG[2]
1 1 1 1 1 1 AB50

2
VAXG[3]

C111

C112

C113

C118

C119

C120
AB51 AY43 +V_SM_VREF_CNT 2 1 +V_SM_VREF
VAXG[4] SM_VREF R112 0_0402_5%
AB52
VAXG[5]
AB53
VAXG[6]

1
2 2 2 2 2 2 AB55
VAXG[7] 1
AB56 C121 R115
VAXG[8] 0.1U_0402_16V4Z 1K_0402_1%
AB58
AB59
VAXG[9]
AJ28
5A
VAXG[10] VDDQ[1] 2
AC61 AJ33

2
VAXG[11] VDDQ[2]
AD47 VAXG[12] VDDQ[3] AJ36
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AD48 AJ40

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VAXG[13] VDDQ[4]
1 1 1 1 1 1 AD50 AL30

- 1.5V RAILS
VAXG[14] VDDQ[5] +1.5V_CPU_VDDQ +1.5VS
AD51 VAXG[15] VDDQ[6] AL34
C114

C122

C116

C115

C117

C123
AD52 VAXG[16] VDDQ[7] AL38
AD53 AL42 @
2 2 2 2 2 2 VAXG[17] VDDQ[8] JP100
AD55
AD56
VAXG[18] VDDQ[9] AM33
AM36
High-Frequency Decoupling 1 2
VAXG[19] VDDQ[10]
AD58 VAXG[20] VDDQ[11] AM40

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AD59 AN30 PAD-OPEN 4x4m
VAXG[21] VDDQ[12]
AE46 VAXG[22] VDDQ[13] AN34 1 1 1 1 1 1 1 1 1 1

C824

C825

C826

C827

C828

C829

C830

C831

C832

C833
Low-Frequency Decoupling N45 AN38 Need to open

POWER
VAXG[23] VDDQ[14]
P47 VAXG[24] VDDQ[15] AR26
P48 VAXG[25] VDDQ[16] AR28
2 2 2 2 2 2 2 2 2 2
330U_D2_2V_Y

470U_D2_2V_Y

1 1 P50 VAXG[26] VDDQ[17] AR30

m
P51 VAXG[27] VDDQ[18] AR32
C131

C132

+ + Note: P52 AR34

DDR3
2Pin 470uF PN SGA00004200 VAXG[28] VDDQ[19]
P53 VAXG[29] VDDQ[20] AR36
Need confirm Type with Power Team before SMT
C 2 2
P55
P56
VAXG[30] VDDQ[21] AR40
AV41
Mid-Frequency Decoupling C
VAXG[31] VDDQ[22]

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
P61 VAXG[32] VDDQ[23] AW26
DVT:Update C131 C132 footprint T48 VAXG[33] VDDQ[24] BA40

GRAPHICS

C133

C134

C124

C125

C126

C127

C128

C129
T58 VAXG[34] VDDQ[25] BB28 1 1 1 1 1 1 1 1
T59 VAXG[35] VDDQ[26] BG33

ru
T61 VAXG[36]
High-Frequency Decoupling U46
V47
VAXG[37] 2 2 2 2 2 2 2 2
VAXG[38]
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

V48
VAXG[39]
1 1 1 1 1 1 V50
VAXG[40]
C835

C836

C837

C838

C839

C840

V51
VAXG[41]
V52
V53
VAXG[42] Low-Frequency Decoupling
2 2 2 2 2 2 VAXG[43]
V55
VAXG[44]
V56 1
VAXG[45]

Fo
V58
VAXG[46] + C130
V59
VAXG[47] 330U_2.5V_M
W50
VAXG[48] DVT:Update C130 footprint
W51
VAXG[49] 2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

W52
VAXG[50]
1 1 1 1 1 W53
VAXG[51]
C841

C842

C843

C844

C845

W55
VAXG[52]
W56
VAXG[53]
W61
2 2 2 2 2 VAXG[54]
Y48
VAXG[55]
Y61
VAXG[56]

+1.5V_CPU_VDDQ

B
<54> VCC_AXG_SENSE
<54> VSS_AXG_SENSE
R934
R935
1
1
2 0_0402_5%
2 0_0402_5%
er
F45
G45
VAXG_SENSE
VSSAXG_SENSE
LINES
SENSE

QUIET RAILS
VCCDQ[1]
VCCDQ[2]
AM28
AN26

1
C723 Vaxg
B

+1.8VS 2
1U_0402_6.3V6K
‧ Can connect to GND if motherboard only
1.8V RAIL
yb
PVT:<Memo> supports external graphics and if GFX VR is not
10U_0603_6.3V6M

10U_0603_6.3V6M

BB3
@ VCCPLL[1]

‧
BC1
VCCPLL[2] stuffed in a common motherboard design,
330U_D2_2V_Y
C138

1U_0402_6.3V6K
C140

1U_0402_6.3V6K
C141

1 1 1 1 1 BC4
VCCPLL[3] VAX G can be left floating in a common
C916

C915

+
@
motherboard design (Gfx VR keeps VAXG from
2 2 2 2 BC43 PAD T86 floating) if the VR is stuffed
+VCCSA 2 VDDQ_SENSE PAD T87
BA43
SENSE LINES

VSS_SENSE_VDDQ
Low-Frequency Decoupling 6A L17
VCCSA[1]
C

L21
VCCSA[2]
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

N16
VCCSA[3]
1 1 1 1 1 N20
VCCSA[4]
330U_D2_2V_Y

C143

C144

C145

C146

C765

SA RAIL

1 N22
VCCSA[5]
P17
VCCSA[6]
C142

+ P20 U10 VCCSA_SENSE

2 2 2 2 2 VCCSA[7] VCCSA_SENSE VCCSA_SENSE <52>
R16
VCCSA[8]
R18
2 VCCSA[9]
R21
VCCSA[10]
U15
VCCSA[11]
V16
VCCSA[12] VCCSA_VID0
Low-Frequency Decoupling V17
VCCSA[13] VCCSA_VID[0]
D48
High-Frequency Decoupling V18 D49 VCCSA_VID1
VCCSA[14] VCCSA_VID[1] VCCSA_VID1 <52>

2
V21 VCCSA[15]
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

A R863 R124 A
W20 VCCSA[16]
1 1 1 1 10K_0402_5% @ 0_0402_5%
C846

C847

C848

C849

C850

1
2 2 2 2
2 SANDY-BRIDGE_BGA1023~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 9 of 56
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU_VDDQ Source

+1.5V Q7 +1.5V_CPU_VDDQ
B+_BIAS AO4728L_SO8
8 1 +1.5V 1 2 +1.5V_CPU_VDDQ
7 2 C2596 0.1U_0402_16V4Z

1
+3VALW 6 3 1 2

2
D U2H C2597 0.1U_0402_16V4Z D
5
R116 R117 1 2
100K_0402_5% 220_0402_5% C2598 0.1U_0402_16V4Z

4
1
1 2

2
R118 C2599 0.1U_0402_16V4Z

6 1
A13 AM38 100K_0402_5% RUN_ON_CPU1.5VS3
VSS[1] VSS[91]

3
A17 AM4
VSS[2] VSS[92]
A21 AM42

2
VSS[3] VSS[93]

1
A25 AM45 R120 Q8B 1
VSS[4] VSS[94] 0_0402_5% RUN_ON_CPU1.5VS3# 2N7002DW-T/R7_SOT363-6 RUN_ON_CPU1.5VS3#
A28 AM48 5 2
VSS[5] VSS[95] C137
A33 AM58 <43> CPU1.5V_S3_GATE 1 2
VSS[6] VSS[96]

6
A37 AN1 R119 0.1U_0402_16V4Z Q9A

1
VSS[7] VSS[97] @ R121 330K_0402_5% 2 2N7002DW-T/R7_SOT363-6
A40 AN21

2
VSS[8] VSS[98] 0_0402_5% Q8A
A45 VSS[9] VSS[99] AN25
A49 AN28 <43,46,51> SUSP# 1 2 2 2N7002DW-T/R7_SOT363-6 Q9A on P46

.ru
VSS[10] VSS[100]
A53 VSS[11] VSS[101] AN33
A9 AN36

1
VSS[12] VSS[102]
AA1 VSS[13] VSS[103] AN40
AA13 VSS[14] VSS[104] AN43
AA50 VSS[15] VSS[105] AN47
AA51 AN50 U2I
VSS[16] VSS[106]
AA52 VSS[17] VSS[107] AN54
AA53 VSS[18] VSS[108] AP10
AA55 VSS[19] VSS[109] AP51
AA56 VSS[20] VSS[110] AP55 BG17 VSS[181] VSS[251] M4
AA8 VSS[21] VSS[111] AP7 BG21 VSS[182] VSS[252] M58
AB16 VSS[22] VSS[112] AR13 BG24 VSS[183] VSS[253] M6
AB18 VSS[23] VSS[113] AR17 BG28 VSS[184] VSS[254] N1

m
AB21 VSS[24] VSS[114] AR21 BG37 VSS[185] VSS[255] N17
AB48 VSS[25] VSS[115] AR41 BG41 VSS[186] VSS[256] N21
AB61 VSS[26] VSS[116] AR48 BG45 VSS[187] VSS[257] N25
AC10 VSS[27] VSS[117] AR61 BG49 VSS[188] VSS[258] N28
C C
AC14 VSS[28] VSS[118] AR7 BG53 VSS[189] VSS[259] N33
AC46 VSS[29] VSS[119] AT14 BG9 VSS[190] VSS[260] N36
AC6 VSS[30] VSS[120] AT19 C29 VSS[191] VSS[261] N40
AD17 VSS[31] VSS[121] AT36 C35 VSS[192] VSS[262] N43
AD20 VSS[32] VSS[122] AT4 C40 VSS[193] VSS[263] N47

ru
AD4 AT45 D10 N48
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
D14
D18
VSS[194]
VSS[195]
VSS[196]
VSS[264]
VSS[265]
VSS[266]
N51
N52
AE8 AU1 D22 N56
VSS[36] VSS[126] VSS[197] VSS[267]
AF1 AU11 D26 N61
VSS[37] VSS[127] VSS[198] VSS[268]
AF17 AU28 D29 P14
VSS[38] VSS[128] VSS[199] VSS[269]
AF21 AU32 D35 P16
VSS[39] VSS[129] VSS[200] VSS[270]
AF47 AU51 D4 P18
VSS[40] VSS[130] VSS[201] VSS[271]
AF48 AU7 D40 P21
VSS[41] VSS[131] VSS[202] VSS[272]
AF50 AV17 D43 P58
VSS[42] VSS[132] VSS[203]
VSS VSS[273]

Fo
AF51 AV21 D46 P59
VSS[43] VSS[133] VSS[204] VSS[274]
AF52 AV22 D50 P9
VSS[44] VSS[134] VSS[205] VSS[275]
AF53 AV34 D54 R17
VSS[45] VSS[135] VSS[206] VSS[276]
AF55 AV40 D58 R20
VSS[46] VSS[136] VSS[207] VSS[277]
AF56 AV48 D6 R4
VSS[47] VSS[137] VSS[208] VSS[278]
AF58 AV55 E25 R46
VSS[48] VSS[138] VSS[209] VSS[279]
AF59 AW13 E29 T1
VSS[49] VSS[139] VSS[210] VSS[280]
AG10 AW43 E3 T47
VSS[50] VSS[140] VSS[211] VSS[281]
AG14 AW61 E35 T50
VSS[51] VSS[141] VSS[212] VSS[282]
AG18 AW7 E40 T51
VSS[52] VSS[142] VSS[213] VSS[283]
AG47 AY14 F13 T52
VSS[53] VSS[143] VSS[214] VSS[284]
AG52 AY19 F15 T53
VSS[54] VSS[144] VSS[215] VSS[285]
AG61 AY30 F19 T55
VSS[55] VSS[145] VSS[216] VSS[286]

B
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
er F29
F35
F40
F55
G48
G51
G6
G61
H10
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
T56
U13
U8
V20
V61
W13
W15
W18
W21
B

AJ34 BA11 H14 W46

VSS[65] VSS[155] VSS[226] VSS[296]
yb
AJ38 BA17 H17 W8
VSS[66] VSS[156] VSS[227] VSS[297]
AJ42 BA21 H21 Y4
VSS[67] VSS[157] VSS[228] VSS[298]
AJ45 BA26 H4 Y47
VSS[68] VSS[158] VSS[229] VSS[299]
AJ48 BA32 H53 Y58
VSS[69] VSS[159] VSS[230] VSS[300]
AJ7 BA48 H58 Y59
VSS[70] VSS[160] VSS[231] VSS[301]
AK1 BA51 J1
VSS[71] VSS[161] VSS[232]
AK52 BB53 J49
VSS[72] VSS[162] VSS[233]
AL10 BC13 J55
VSS[73] VSS[163] VSS[234]
AL13 BC5 K11
VSS[74] VSS[164] VSS[235]
AL17 BC57 K21
VSS[75] VSS[165] VSS[236]
AL21 BD12 K51 A5
VSS[76] VSS[166] VSS[237] VSS_NCTF_1
AL25 BD16 K8 A57
VSS[77] VSS[167] VSS[238] VSS_NCTF_2
C

AL28 BD19 L16 BC61

VSS[78] VSS[168] VSS[239] VSS_NCTF_3
AL33 BD23 L20 BD3
VSS[79] VSS[169] VSS[240] VSS_NCTF_4
AL36 BD27 L22 BD59
VSS[80] VSS[170] VSS[241] NCTF VSS_NCTF_5
AL40 BD32 L26 BE4
VSS[81] VSS[171] VSS[242] VSS_NCTF_6
AL43 BD36 L30 BE58
VSS[82] VSS[172] VSS[243] VSS_NCTF_7
AL47 BD40 L34 BG5
VSS[83] VSS[173] VSS[244] VSS_NCTF_8
AL61 BD44 L38 BG57
VSS[84] VSS[174] VSS[245] VSS_NCTF_9
AM13 BD48 L43 C3
VSS[85] VSS[175] VSS[246] VSS_NCTF_10
AM20 BD52 L48 C58
VSS[86] VSS[176] VSS[247] VSS_NCTF_11
AM22 BD56 L61 D59
VSS[87] VSS[177] VSS[248] VSS_NCTF_12
AM26 BD8 M11 E1
VSS[88] VSS[178] VSS[249] VSS_NCTF_13
AM30 BE5 M15 E61
VSS[89] VSS[179] VSS[250] VSS_NCTF_14
AM34 BG13
VSS[90] VSS[180]
A A

SANDY-BRIDGE_BGA1023~D
SANDY-BRIDGE_BGA1023~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 10 of 56
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMA +1.5V +1.5V

JDIMM0
1 VREF_DQ VSS1 2
3 4 DDR_A _D4
VSS2 DQ4 DDR _A_DQS#[0..7] <6>

2.2U_0603_6.3V6K

0.1U_0402_16V4Z
DDR_A _D0 5 6 DDR_A _D5
DQ0 DQ5

C 2023

C 2000
DDR_A _D1 7 8
DQ1 VSS3 DDR_ A_DQS[0..7] <6>
1 1 9 10 DD R_A_DQS#0
DD R_A_DM0 VSS4 DQS#0 DDR _A_DQS0
All VREF traces should 11 DM0 DQS0 12 DDR_A _D[0..63] <6>
13 VSS5 VSS6 14
have 10 mil trace width DDR_A _D2 15 16 DDR_A _D6
DDR_A_MA[0..15] <6>
2 2 DDR_A _D3 DQ2 DQ6 DDR_A _D7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_A _D8 21 22 DDR_ A_D12
DDR_A _D9 DQ8 DQ12 DDR_ A_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
D DD R_A_DQS#1 27 28 DD R_A_DM1 D
DDR _A_DQS1 DQS#1 DM1 D DR3_DRAMRST#
29 DQS1 RESET# 30 D DR3_DRAMRST# <6,12>
31 VSS11 VSS12 32
DDR_ A_D10 33 34 DDR_ A_D14
DDR_ A_D11 DQ10 DQ14 DDR_ A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38 Layout Note:
DDR_ A_D16 39 40 DDR_ A_D20
DDR_ A_D17 41
DQ16 DQ20
42 DDR_ A_D21 Place near JDIMM0
DQ17 DQ21 +1.5V
43 VSS15 VSS16 44
DD R_A_DQS#2 45 46 DD R_A_DM2
+1.5V +VREF_DQ_DIMMA DDR _A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_ A_D22
VSS18 DQ22

1U_0402_6.3V6K
C 2024

1U_0402_6.3V6K
C 2025

1U_0402_6.3V6K
C 2026

1U_0402_6.3V6K
C 2027
DDR_ A_D18 51 52 DDR_ A_D23
DDR_ A_D19 DQ18 DQ23
53 DQ19 VSS19 54 1 1 1 1
1

55 56 DDR_ A_D28
R 2017 DDR_ A_D24 VSS20 DQ28 DDR_ A_D29
57 DQ24 DQ29 58
1K_0402_1% DDR_ A_D25 59 60

.ru
DQ25 VSS21 DD R_A_DQS#3 2 2 2 2
61 VSS22 DQS#3 62
DD R_A_DM3 63 64 DDR _A_DQS3
2

DM3 DQS3
65 VSS23 VSS24 66
DDR_ A_D26 67 68 DDR_ A_D30
DDR_ A_D27 DQ26 DQ30 DDR_ A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
1

+1.5V
R 2018
1K_0402_1% <6> DDR_CKE0_DIMMA DDR_CKE0_DIM MA 73 74 DDR_CKE1_DIM MA DDR_CKE1_DIMMA <6>
CKE0 CKE1
75 76
2

VDD1 VDD2

10U_0603_6.3V6M
C 2029

10U_0603_6.3V6M
C 2030

10U_0603_6.3V6M
C 2031

10U_0603_6.3V6M
C 2032

10U_0603_6.3V6M
C 2033

10U_0603_6.3V6M
C 2034

10U_0603_6.3V6M
C 2035
77 78 DDR_A_MA 15 1
D DR_A_BS2 NC1 A15 DDR_A_MA 14
<6> D DR_A_BS2 79 BA2 A14 80 1 1 1 1 1 1 1
81 82 + C 2028

m
DDR_A_MA 12 VDD3 VDD4 DDR_A_MA 11 330U_2.5V_M
83 A12/BC# A11 84
DDR_A_M A9 85 86 DDR_A_M A7
A9 A7 2 2 2 2 2 2 2 2
87 VDD5 VDD6 88
DDR_A_M A8 89 90 DDR_A_M A6
C
DDR_A_M A5 A8 A6 DDR_A_M A4 C
91 A5 A4 92
93 VDD7 VDD8 94
+1.5V +VREF_CA_DIMMA DDR_A_M A3 DDR_A_M A2
95 A3 A2 96
DDR_A_M A1 97 98 DDR_A_M A0 DVT:Update C2028 footprint
A1 A0
99 VDD9 VDD10 100
<6> M _CLK_DDR0 M _CLK_DDR0 101 102 M _CLK_DDR1 M _CLK_DDR1 <6>
CK0 CK1

ru
1

<6> M_CLK_DDR#0 M _CLK_DDR#0 103 104 M _CLK_DDR#1 M_CLK_DDR#1 <6>

R 2609 CK0# CK1#
105 VDD11 VDD12 106
1K_0402_1% DDR_A_MA 10 107 108 D DR_A_BS1 D DR_A_BS1 <6>
D DR_A_BS0 A10/AP BA1 DD R_A_RAS#
<6> D DR_A_BS0 109 BA0 RAS# 110 DD R_A_RAS# <6>
111 112
2

DDR _A_WE# VDD13 VDD14 DDR_CS0_DIMM A#

<6> DDR _A_WE# 113 WE# S0# 114 DDR_CS0_DIMMA# <6>
<6> DD R_A_CAS# DD R_A_CAS# 115 116 M _ODT0 M_ODT0 <6>
CAS# ODT0
117 VDD15 VDD16 118
DDR_A_MA 13 119 120 M _ODT1 M_ODT1 <6>
A13 ODT1
1

DDR_CS1_DIMM A# +VREF_CA_DIMMA
<6> DDR_CS1_DIMMA# 121 S1# NC2 122 Layout Note:
123 124

Fo
R 2612 125
VDD17 VDD18
126 Place near JDIMM0.203,204
1K_0402_1% NCTEST VREF_CA
127 VSS27 VSS28 128

2.2U_0603_6.3V6K
DDR_ A_D32 129 130 DDR_ A_D36
2

DQ32 DQ36

C 2036

0.1U_0402_16V4Z
C 2037
DDR_ A_D33 131 132 DDR_ A_D37
DQ33 DQ37 +0.75VS
133 VSS29 VSS30 134 1 1
DD R_A_DQS#4 135 136 DD R_A_DM4
DDR _A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
139 140 DDR_ A_D38
DDR_ A_D34 VSS32 DQ38 DDR_ A_D39 2 2
141 DQ34 DQ39 142

1U_0402_6.3V6K
C 2038

1U_0402_6.3V6K
C 2039

1U_0402_6.3V6K
C 2040

1U_0402_6.3V6K
C 2041
DDR_ A_D35 143 144
DQ35 VSS33 DDR_ A_D44
145 VSS34 DQ44 146 1 1 1 1
DDR_ A_D40 147 148 DDR_ A_D45
DDR_ A_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DD R_A_DQS#5
VSS36 DQS#5

B
er DD R_A_DM5

DDR_ A_D42
DDR_ A_D43

DDR_ A_D48
DDR_ A_D49

DD R_A_DQS#6
DDR _A_DQS6
153
155
157
159
161
163
165
167
169
171
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
154
156
158
160
162
164
166
168
170
172
DDR _A_DQS5

DDR_ A_D46
DDR_ A_D47

DDR_ A_D52
DDR_ A_D53

DD R_A_DM6
2 2 2 2

DQS6 VSS43 DDR_ A_D54

173 174
yb
DDR_ A_D50 VSS44 DQ54 DDR_ A_D55
175 DQ50 DQ55 176
DDR_ A_D51 177 178
DQ51 VSS45 DDR_ A_D60
179 VSS46 DQ60 180
DDR_ A_D56 181 182 DDR_ A_D61
DDR_ A_D57 DQ56 DQ61 DD R_A_DM0
183 DQ57 VSS47 184
185 186 DD R_A_DQS#7 DD R_A_DM1
DD R_A_DM7 VSS48 DQS#7 DDR _A_DQS7 DD R_A_DM2
187 DM7 DQS7 188
189 190 DD R_A_DM3
DDR_ A_D58 VSS49 VSS50 DDR_ A_D62 DD R_A_DM4
191 DQ58 DQ62 192
DDR_ A_D59 193 194 DDR_ A_D63 DD R_A_DM5
DQ59 DQ63 DD R_A_DM6
195 VSS51 VSS52 196
197 198 DD R_A_DM7
SA0 EVENT# D_CK_SDATA
+3VS 199 200
C

VDDSPD SDA D_CK_SDATA <12,14,41>

201 202 D _CK_SCLK
SA1 SCL D _CK_SCLK <12,14,41>
+0.75VS 203 VTT1 VTT2 204 +0.75VS
1
0.1U_0402_16V4Z
C 2042

2.2U_0603_6.3V6K
C 2043

10K_0402_5%
R 2028

10K_0402_5%
R 2029

205 G1 G2 206
2

1 1
FOX_AS0A626-U4SN-7F

C ONN@
2

2 2
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMA
Size D ocument Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Cus tom L A-7141P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Dat e: Monday, April 11, 2011 Sheet 11 of 56
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMB +1.5V +1.5V

JDIMM1
1 VREF_DQ VSS1 2
3 4 DDR_B_D4
VSS2 DQ4

2.2U_0603_6.3V6K
C165

0.1U_0402_16V4Z
C166
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5 DDR_B_DQS#[0..7] <6>
7 DQ1 VSS3 8
All VREF traces should 1 1 9 10 DDR_B_DQS#0
DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0 DDR_B_DQS[0..7] <6>
11 12
have 10 mil trace width 13
DM0 DQS0
14 DDR_B_D[0..63] <6>
+1.5V +VREF_DQ_DIMMB DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 DQ2 DQ6 16
2 2 DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7 DDR_B_MA[0..15] <6>
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 22
DQ8 DQ12
1

DDR_B_D9 23 24 DDR_B_D13
D R165 DQ9 DQ13 D
25 26
1K_0402_1% DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# <6,11>
DQS1 RESET#
31 32
2

DDR_B_D10 VSS11 VSS12 DDR_B_D14

33 34
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15 +1.5V
37 38
DDR_B_D16 VSS13 VSS14 DDR_B_D20
39 40
DQ16 DQ20
1

DDR_B_D17 41 42 DDR_B_D21
R166 DQ17 DQ21
43 44
VSS15 VSS16

1U_0402_6.3V6K
C167

1U_0402_6.3V6K
C168

1U_0402_6.3V6K
C169

1U_0402_6.3V6K
C170
1K_0402_1% DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48 1 1 1 1
49 50 DDR_B_D22
2

DDR_B_D18 VSS18 DQ22 DDR_B_D23

51 DQ18 DQ23 52
DDR_B_D19 53 54

.ru
DQ19 VSS19 DDR_B_D28 2 2 2 2
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30 Layout Note:
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 70
71
DQ27 DQ31
72
Place near JDIMM1
VSS25 VSS26 +1.5V

+1.5V +VREF_CA_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

<6> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <6>

10U_0603_6.3V6M
C171

10U_0603_6.3V6M
C172

10U_0603_6.3V6M
C173

10U_0603_6.3V6M
C174

10U_0603_6.3V6M
C175

10U_0603_6.3V6M
C176

10U_0603_6.3V6M

330U_2.5V_M
75 VDD1 VDD2 76 1

C177
77 78 DDR_B_MA15 1 1 1 1 1 1 1
NC1 A15

C178
DDR_B_BS2 79 80 DDR_B_MA14 +
<6> DDR_B_BS2 BA2 A14
1

81 VDD3 VDD4 82
C R167 DDR_B_MA12 DDR_B_MA11 C
83 A12/BC# A11 84
1K_0402_1% DDR_B_MA9 85 86 DDR_B_MA7 2 2 2 2 2 2 2 2
A9 A7 @
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
2

DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92

ru
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99
VDD9 VDD10
100 DVT:Update C178 footprint and SMT memo
1

M_CLK_DDR2 101 102 M_CLK_DDR3

<6> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <6>
R168 M_CLK_DDR#2 103 104 M_CLK_DDR#3
<6> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <6>
1K_0402_1% 105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 <6>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<6> DDR_B_BS0 109 110 DDR_B_RAS# <6> Layout Note:
2

BA0 RAS#
111 112
VDD13 VDD14 Place near JDIMM1.203,204

Fo
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
<6> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <6>
DDR_B_CAS# 115 116 M_ODT2 +0.75VS
<6> DDR_B_CAS# CAS# ODT0 M_ODT2 <6>
117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3
119 120 M_ODT3 <6> +VREF_CA_DIMMB
DDR_CS3_DIMMB# A13 ODT1
<6> DDR_CS3_DIMMB# 121 122
S1# NC2
123 124
VDD17 VDD18

1U_0402_6.3V6K
C179

1U_0402_6.3V6K
C180

1U_0402_6.3V6K
C181

1U_0402_6.3V6K
C182
125 126 1 1 1 1
NCTEST VREF_CA
127 128
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 130
DQ32 DQ36

2.2U_0603_6.3V6K
C183

0.1U_0402_16V4Z
C184
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 2 2 2 2
133 134 1 1
DDR_B_DQS#4 VSS29 VSS30 DDR_B_DM4
135 136
DDR_B_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_B_D38

B
er DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
139
141
143
145
147
149
151
153
155
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
140
142
144
146
148
150
152
154
156
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
2 2

DDR_B_DM0
DDR_B_DM1
B

DDR_B_D42 157 158 DDR_B_D46 DDR_B_DM2

DDR_B_D43 DQ42 DQ46 DDR_B_D47 DDR_B_DM3
yb
159 160
DQ43 DQ47 DDR_B_DM4
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52 DDR_B_DM5
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53 DDR_B_DM6
165 166
DQ49 DQ53 DDR_B_DM7
167 168
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6
169 170
DDR_B_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DQ56 DQ61
C

DDR_B_D57 183 184

DQ57 VSS47 DDR_B_DQS#7
185 186
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 188
DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
VSS51 VSS52
197 198
SA0 EVENT# D_CK_SDATA
+3VS 199 200 D_CK_SDATA <11,14,41>
VDDSPD SDA D_CK_SCLK
1 2 201 202 D_CK_SCLK <11,14,41>
R177 10K_0402_5% SA1 SCL
+0.75VS 203 204 +0.75VS
VTT1 VTT2
0.1U_0402_16V4Z

2.2U_0603_6.3V6K

205 206
G1 G2
C185

C186

10K_0402_5%

A FOX_AS0A626-U8SN-7F A
1 1
1

CONN@
R178

2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 12 of 56
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2 DVT:Add U67 R987 R988 for SATA issue

R179 10M_0402_5%
+3VS
W=10mils +3VS
W=20mils SERIRQ 2 1

4
+3VLP W=20mils R202 10K_0402_5%
Y2 +RTCBATT +RTCBATT_R PCH_SATALED# 2 1

OSC

OSC
D1 +RTCVCC R203 10K_0402_5%
2 PCH_GPIO19 1 2
1 1 R892 10K_0402_5%

1
NC

NC
2 1 1
C188 C189 R235 1K_0402_5% <18> PCH_GPIO49 PCH_GPIO49 @ R988
15P_0402_50V8J 15P_0402_50V8J 3 200K_0402_5%
2

5
D 2 2 D
BAS40-04_SOT23-3 R987

OE#

2
32.768KHZ_12.5PF_Q13MC14610002 1 PCH_GPIO19 4 2 1 2 ODD_DETECT#_R
Y A ODD_DETECT#_R <40>
DVT:C188 C189 18p-->15p C194

G
1U_0603_10V4Z @ U67 0_0402_5%
74AHCT1G125GW_SOT353-5

3
+RTCVCC Place C194 close to PCH. 2
@
1 2 SM_INTRUDER#
R198 1M_0402_5%
1 2 PCH_INTVRMEN
R199 330K_0402_5%
INTVRMEN
：Integrated
* LH： Integrate d VRM enable

.ru
VR M disable
Need to open
(INTVRMEN should always be pull high.)

+3VS CMOS

1 @ 2 HDA_SPKR U14A

SHORT PADS
JCMOS1
R204 1K_0402_5%
HIGH= Enable ( No Reboot ) +RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <41,43>

1
LOW= Disable (Default) LPC_AD1
* FWH1 / LAD1 A38 LPC_AD1 <41,43>

LPC
C190 @ PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD3 LPC_AD2 <41,43>
1U_0603_10V4Z C37 LPC_AD3 <41,43>

2
FWH3 / LAD3

m
+3VALW_PCH 2 PCH_RTCRST#
1 2 D20 RTCRST#
R205 20K_0402_5% D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# <41,43>
2 @ 1 HDA_SDOUT 1 2 PCH_SRTCRST# G22
R206 1K_0402_5% R207 20K_0402_5% SRTCRST#
1 1 LDRQ0# E36
SHORT PADS
JME1

RTC
C SM_INTRUDER# &U1 C
K22 INTRUDER# LDRQ1# / GPIO23 K36
<43> HDA_SDO 2 1 C191 @
R208 0_0402_5% 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <43>
2

2 INTVRMEN SERIRQ
HDA_SDO

ru
ME debug mode,this signal has a weak internal PD SATA0RXN AM3 SATA_PRX_DTX_N0 <40>
Low = Disabled (Default) ME HDA_BIT_CLK @ 32M MX25L3206EM2I-12G SOP 8P 3V
* N34 HDA_BCLK SATA0RXP AM1 SATA_PRX_DTX_P0 <40>
HDD

SATA 6G
High = Enabled [Flash Descriptor Security Overide] AP7 SATA_PTX_DRX_N0 <40>
HDA_SYNC SATA0TXN
Need to open L34
HDA_SYNC SATA0TXP
AP5 SATA_PTX_DRX_P0 <40>
+3VALW_PCH
<38> HDA_SPKR
HDA_SPKR T10
SPKR SATA1RXN
AM10 SATA_PRX_DTX_N1 <40> SPI ROM FOR ME ( 4MByte ) +3VS
SATA1RXP
AM8 SATA_PRX_DTX_P1 <40> ODD reserved
2 1 HDA_SYNC HDA_RST# K34 AP11
HDA_RST# SATA1TXN SATA_PTX_DRX_N1 <40>
R213 1K_0402_5% AP10 PCH_SPI_WP# R209 1 2 3.3K_0402_5%
SATA1TXP SATA_PTX_DRX_P1 <40> PCH_SPI_HOLD#
This signal has a weak internal pull-down If use SPI programmer, R210 1 2 3.3K_0402_5%

Fo
HDA_SDIN0 E34 AD7 PCH_SPI_CS#_R R340 1 @ 2 3.3K_0402_5%
<38> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_PRX_DTX_N2 <40> R211 should be open
AD5 SATA_PRX_DTX_P2 <40>
On Die PLL VR Select is supplied by G34
SATA2RXP
AH5 ODD (Normal is pop) PCH_SPI_SO_R 1 2 PCH_SPI_SO
HDA_SDIN1 SATA2TXN SATA_PTX_DRX_N2 <40>
1.5V when smapled high R212 0_0402_5%
* 1.8V when sampled low C34
HDA_SDIN2
SATA2TXP
AH4 SATA_PTX_DRX_P2 <40>

IHDA
Needs to be pulled High for Huron River platfrom AB8
SATA3RXN
A34 AB10
HDA_SDIN3 SATA3RXP
AF3
SATA3TXN +3VS +3V_DSW_SPI
AF1
HDA_SDOUT SATA3TXP U15 +3V_DSW_SPI
A36
HDA_SDO

SATA
Y7 1 2 8 4
SATA4RXN R211 0_0402_5% VCC VSS
Y5 1
T90 PAD SATA4RXP PCH_SPI_WP#
C36 AD3 3
HDA_DOCK_EN# / GPIO33 SATA4TXN W C192

B
2
R222
1
T91

PCH_JTAG_TCK
51_0402_5%
PCH_JTAG_TMS
PAD er
N32

J3

H7
HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS
JTAG
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO
AD1

Y3
Y1
AB3
AB1

Y11
PVT:Reserved D28

+1.05VS_VCC_SATA
2
D28
@
1
CH751H-40PT_SOD323-2

PCH_SPI_CS# 1
R214
PCH_SPI_CLK 1
R215
PCH_SPI_SI 1
R216
2

2
PCH_SPI_HOLD#7

PCH_SPI_CS#_R
0_0402_5%
PCH_SPI_CLK_R
0_0402_5%
PCH_SPI_SI_R
0_0402_5%
1

5
HOLD

D Q
2 PCH_SPI_SO_R
2
0.1U_0402_16V4Z

PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2 64M MX25L6405DZNI-12G WSON 8P

JTAG_TDI SATAICOMPI
yb
R224 37.4_0402_1%
PCH_JTAG_TDO H1
JTAG_TDO +1.05VS_SATA3
Prevent back drive issue; +3VLAW leakage to +3VS from HDA_SYNC SATA3RCOMPO
AB12
@
+3VS AB13 SATA3_COMP 1 2 PCH_SPI_CLK_R 2 @ 1 1 2
SATA3COMPI R225 49.9_0402_1% R221 33_0402_5% C193 22P_0402_50V8J
1 2 HDA_BIT_CLK
<38> HDA_BITCLK_AUDIO
2
G

R217 33_0402_5% Q10 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2 Reserve for EMI please close to U14
BSS138_NL_SOT23-3 SPI_CLK SATA3RBIAS R230 750_0402_1%
1 2 HDA_SYNC_R 3 1HDA_SYNC PCH_SPI_CS# Y14
<38> HDA_SYNC_AUDIO SPI_CS0#
R218 33_0402_5%
S

T1
SPI_CS1#
SPI
C

2 1 P3 PCH_SATALED#
SATALED# PCH_SATALED# <44>
R220 1M_0402_5%
PCH_SPI_SI V4 V14 PCH_GPIO21
HDA_RST# SPI_MOSI SATA0GP / GPIO21 PCH_GPIO21 R226
<38> HDA_RST_AUDIO# 1 2 2 1 10K_0402_5% +3VS
R219 33_0402_5% PCH_SPI_SO U3 P1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19

<38> HDA_SDOUT_AUDIO 1 2 HDA_SDOUT

R223 33_0402_5% BD82CPMS-QMVY-A1_FCBGA989~D

+3VALW_PCH +3VALW_PCH +3VALW_PCH

1

A A
R227 R228 R229
200_0402_5% 200_0402_5% 200_0402_5%
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1

R232 R233 R234 Security Classification Compal Secret Data Compal Electronics, Inc.
100_0402_1% 100_0402_1% 100_0402_1% Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title
PCH (1/8) SATA,HDA,SPI, LPC, XDP
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 13 of 56
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH

U14B EC_LID_OUT# 1 2
R236 10K_0402_5%
<37> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 DRAMRST_CNTRL_PCH 1 2
PCIE_PRX_DTX_P1 PERN1 EC_LID_OUT# R242 10K_0402_5%
<37> PCIE_PRX_DTX_P1 BJ34 PERP1 SMBALERT# / GPIO11 E12 EC_LID_OUT# <43>
PCIE LAN 1 2 PCIE_PTX_DRX_N1 AV32 PCH_SMBCLK 1 2
<37> PCIE_PTX_C_DRX_N1 PCIE_PTX_DRX_P1 PETN1 PCH_SMBCLK
C199 1 2 0.1U_0402_10V7K AU32 H14 R237 2.2K_0402_5%
<37> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK PCH_SMBDATA
C200 0.1U_0402_10V7K 1 2
<41> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA R243 2.2K_0402_5%
PCIE_PRX_DTX_P2 PERN2 SMBDATA PCH_GPIO74
<41> PCIE_PRX_DTX_P2 BF34 PERP2
1 2
Mini Card 1 1 2 PCIE_PTX_DRX_N2 BB32 R244 10K_0402_5%
<41> PCIE_PTX_C_DRX_N2 PCIE_PTX_DRX_P2 PETN2 PCH_SML1CLK
C197 1 2 0.1U_0402_10V7K AY32 1 2
<41> PCIE_PTX_C_DRX_P2 PETP2

SMBUS
C198 0.1U_0402_10V7K A12 DRAMRST_CNTRL_PCH R245 2.2K_0402_5%
D SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <6> PCH_SML1DATA D
BG36 1 2
PERN3 PCH_SMB0CLK R246 2.2K_0402_5%
BJ36 C8
PERP3 SML0CLK PCH_SMB0CLK
AV34 1 2
PETN3 PCH_SMB0DATA R238 2.2K_0402_5%
AU34 G12
PETP3 SML0DATA PCH_SMB0DATA 1 2
BF36 R239 2.2K_0402_5%
PERN4
BE36
PERP4 PCH_GPIO74
AY34 C13
PETN4 SML1ALERT# / PCHHOT# / GPIO74
BB34
PETP4 PCH_SML1CLK
E14
SML1CLK / GPIO58

PCI-E*
BG37
BH37
PERN5
M16 PCH_SML1DATA
SMB SMBus to DDR3 DIMM/Panel/Mini Card
PERP5 SML1DATA / GPIO75
AY36 PETN5
BB36 +3VALW_PCH PCH_SMBCLK 6 1
PETP5 D_CK_SCLK <11,12,41>

.ru
BJ38 2N7002DW-T/R7_SOT363-6
PERN6 Q1A
BG38

2
PERP6

Controller
AU36 PETN6 CL_CLK1 M7
AV36 PEG_CLKREQ#_R 1 2 PCH_SMBDATA 3 4
PETP6 D_CK_SDATA <11,12,41>
R240 10K_0402_5%

Link
BG40 T11 D_CK_SCLK 1 2 +3VS
PERN7 CL_DATA1 2N7002DW-T/R7_SOT363-6 R2 4.7K_0402_5%
BJ40

5
PERP7 Q1B D_CK_SDATA
AY40 PETN7
1 2 +3VS
BB40 P10 +3VS R1 4.7K_0402_5%
PETP7 CL_RST1#
BE38 PERN8
BC38 PERP8
AW38 PETN8

m
AY38 PETP8
M10 PEG_CLKREQ#_R 2 1 VGA_CLKREQ# <22>
PEG_A_CLKRQ# / GPIO47 0_0402_5% R286
Y40 CLKOUT_PCIE0N
C C
Y39 CLKOUT_PCIE0P
AB37 CLK_VGA# 0_0402_5% 2 1 R275
CLKOUT_PEG_A_N CLK_PCIE_VGA# <22>

CLOCKS
PCH_GPIO73 J2 AB38 CLK_VGA 0_0402_5% 2 1 R276 GPU
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <22>

CLK_MINI1#

ru
1 2 AB49 AV22 CLK_CPU_DMI#
<41> CLK_PCIE_MINI1# CLK_MINI1 CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <5>
Mini Card 1 R262 1 2 0_0402_5% AB47 AU22 CPU
<41> CLK_PCIE_MINI1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5>
R264 0_0402_5%
<41> MINI1_CLKREQ# 1 2 PCH_GPIO18 M1
R266 0_0402_5% PCIECLKRQ1# / GPIO18 CLK_CPU_DPLL#
AM12 CLK_CPU_DPLL# <5>
CLKOUT_DP_N CLK_CPU_DPLL
CLKOUT_DP_P
AM13 CLK_CPU_DPLL <5> CPU
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P CLK_BUF_CPU_DMI#
BF18 1 2
PCH_GPIO20 CLKIN_DMI_N CLK_BUF_CPU_DMI R427 10K_0402_5%
V10
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
BE18 1 2 SML1 SMBus to GPU/EC

Fo
R428 10K_0402_5%
PCH_SML1CLK 6 1
CLK_LAN# CLKIN_DMI2# EC_SMB_CK2 <22,43>
<37> CLK_PCIE_LAN# 2 1 Y37 BJ30 1 2
R257 CLK_LAN CLKOUT_PCIE3N CLKIN_GND1_N CLKIN_DMI2
<37> CLK_PCIE_LAN 2 1 0_0402_5% Y36
CLKOUT_PCIE3P CLKIN_GND1_P
BG30 R263 1 2 10K_0402_5% 2N7002DW-T/R7_SOT363-6
PCIE LAN R258 0_0402_5% R265 10K_0402_5% Q11A

2
2 1 PCH_GPIO25 A8
<37> LAN_CLKREQ# PCIECLKRQ3# / GPIO25
R259 0_0402_5% G24 CLK_BUF_DREF_96M# 1 2 PCH_SML1DATA 3 4
CLKIN_DOT_96N EC_SMB_DA2 <22,43>
E24 CLK_BUF_DREF_96M R267 1 2 10K_0402_5%
CLKIN_DOT_96P R268 10K_0402_5%
Y43
CLKOUT_PCIE4N 2N7002DW-T/R7_SOT363-6
Y45

5
CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# Q11B
AK7 1 2
PCH_GPIO26 CLKIN_SATA_N CLK_BUF_PCIE_SATA R270 10K_0402_5%
L12 AK5 1 2 +3VS
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P R272 10K_0402_5%

B PCH_GPIO44
V45
V46

L14

AB42
AB40
er
CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN
XTAL25_OUT
K45

H45

V47
V49
CLK_BUF_ICH_14M

CLK_PCI_LPBACK

XTAL25_IN
XTAL25_OUT
R274
1

CLK_PCI_LPBACK <17>
2
10K_0402_5%
B

PCH_GPIO56 +1.05VS_VCCDIFFCLKN
yb
E6
PEG_B_CLKRQ# / GPIO56
Y47 XCLK_RCOMP 1 2
XCLK_RCOMP R278 90.9_0402_1%
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
PCH_GPIO45 T13 XTAL25_IN
PCIECLKRQ6# / GPIO45
V38 K43 CLK_FKEX0 T21 PAD XTAL25_OUT 1 2
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

V37 R277 1M_0402_5%

@ CLKOUT_PCIE7P CLK_27M_PCH_R @
<5> CLK_RES_ITP# 2 1 F47 1 2 CLK_27M_PCH <22>
R279 @ PCH_GPIO46 CLKOUTFLEX1 / GPIO65
<5> CLK_RES_ITP 2 1 0_0402_5% K12 R804 22_0402_5% Y3
PCIECLKRQ7# / GPIO46
C

R280 0_0402_5% H47 CLK_FKEX2 CLK_FKEX2 <37> 2 1

CLK_BCLK_ITP# CLKOUTFLEX2 / GPIO66
AK14
CLK_BCLK_ITP CLKOUT_ITPXDP_N +3VS
AK13
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
K49 1 25MHZ_20PF_7A25000012 1
+3VS C201 C202

1
2 1 PCH_GPIO18 BD82CPMS-QMVY-A1_FCBGA989~D 27P_0402_50V8J 27P_0402_50V8J
R241 2 1 10K_0402_5% PCH_GPIO20 R938 2 2
R248 10K_0402_5% 10K_0402_5%
+3VALW_PCH
DVT:C201 C202 18p-->27p
OPT@ Reserve for EMI, Need close to U14

2
PCH_GPIO67
2 1 PCH_GPIO73
R249 10K_0402_5%

1
2 1 PCH_GPIO25
A R251 10K_0402_5% R939 A
2 1 PCH_GPIO26
Project ID GPIO67 10K_0402_5% @
R253 10K_0402_5% +3VALW_PCH CLK_PCI_LPBACK @
2 1 PCH_GPIO44
UMA 0 2 UMA@
2
R285
1
33_0402_5%
1
C204
2
22P_0402_50V8J
R254 10K_0402_5% PCH_GPIO56
2 1 PCH_GPIO45 R284
2 1
10K_0402_5%
Optimus(Dis) 1
R255 10K_0402_5%
2 1 PCH_GPIO46
R256 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 14 of 56
5 4 3 2 1
 5 4 3 2 1

D D

U14C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<4> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <4>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
+3VS <4> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <4>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<4> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <4>
<4> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 <4>
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4
BC12 FDI_CTX_PRX_N4 <4>
FDI_RXN4
5

DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5

<4> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <4>
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
VCC

<4> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <4>

<43> PCH_PWROK 1 <4> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 <4>
IN1 SYS_PWROK DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7
4 <4> DMI_CTX_PRX_P3 BJ20

.ru
OUT DMI3RXP FDI_CTX_PRX_P0
2 BG14
GND

<54> VGATE IN2 FDI_RXP0 FDI_CTX_PRX_P0 <4>

U16 DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<4> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <4>
MC74VHC1G08DFT2G_SC70-5 DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<4> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <4>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <4>
<4> DMI_CRX_PTX_N2
3

DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4

AV18 BE12

DMI
FDI
<4> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <4>
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <4>
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
<4> DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 <4>
2 1 SYS_PWROK DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<4> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <4> +RTCVCC
R292 10K_0402_5% DMI_CRX_PTX_P2 AY18
<4> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI2TXP
<4> DMI_CRX_PTX_P3 AU18 DMI3TXP
AW16 FDI_INT
FDI_INT FDI_INT <4> DSWODVREN R288 2 1 330K_0402_5%
+1.05VS BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <4>

m
R289 2 @ 1 330K_0402_5%
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1

：：
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <4>
R290 49.9_0402_1% DSWODVREN - On Die DSW VR Enable
R BIAS_CPY FDI_LSYNC0
C R291
1 2
750_0402_1%
BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 <4> * H En able
L Di sable
C
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <4>
4mil width and place
SUSACK#_R 2 @ 1 SUSWARN#_R PVT:<Memo>
R299 0_0402_5%
within 500mil of the PCH

ru
A18 DSWODVREN
DSWVRMEN PCH_RSMRST#_R
1 2

System Power Management

R293 0_0402_5% +3VALW_PCH
SUSACK#_R C12 E22 PCH_DPWROK PCH_DPWROK <43>
SUSACK# DPWROK WAKE# @
1 2
R295 10K_0402_5%
<5> XDP_DBRESET# 1 2 XDP_DBRESET#_P K3 B9 WAKE# 1 2 PCH_PCIE_WAKE# <37,41> PCH_GPIO29 1 @ 2
R296 0_0402_5% SYS_RESET# WAKE# R297 0_0402_5% R298 10K_0402_5%
+3VS
SYS_PWROK P12 N3 PCH_GPIO32
SYS_PWROK CLKRUN# / GPIO32

Fo
R301 PCH_GPIO32 1 2
0_0402_5% R300 8.2K_0402_5%
PVT:Reserved R991 PCH_PWROK 1 2 PCH_PWROK_R L22 G8 SUS_STAT# T25 PAD PCH_GPIO32 1 @ 2
PWROK SUS_STAT# / GPIO61 R936 8.2K_0402_5%
1 2
R991 @ 0_0402_5% DVT:Del R303 and update net name EC request
1 2 APWROK L10 N14 SUSCLK
<43> PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK <43>
R302 0_0402_5%
T26 PAD
PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
<5> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <43>
T27 PAD
PCH_RSMRST# 1 2 PCH_RSMRST#_R C21 H4 PM_SLP_S4#
+3VS <43> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <43>
R304 0_0402_5%
T28 PAD

B
R305

+3VALW_PCH
2 1 200_0402_5% PM_DRAM_PWRGD
<43> SUSWARN#

<43> PBTN_OUT#

<22,43,44,46,48> ACIN
R306

R307

D2
1

1
er
2
2

0_0402_5%

2
SUSWARN#_R
0_0402_5%

PBTN_OUT#_R

PCH_ACIN
CH751H-40PT_SOD323-2
K16

E20

H20
SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT / GPIO31
SLP_S3#

SLP_A#

SLP_SUS#
F4

G10

G16
PM_SLP_S3#

T88

T29
PAD

PAD
PM_SLP_S3# <43>

T30 PAD
PCH_GPIO72 H_PM_SYNC
yb
E10 AP14 H_PM_SYNC <5>
R308 SUSWARN# BATLOW# / GPIO72 PMSYNCH
2 1 10K_0402_5%

R309 2 1 200K_0402_5% PCH_ACIN RI# A10 K14 PCH_GPIO29

RI# SLP_LAN# / GPIO29
R310 2 1 10K_0402_5% PCH_GPIO72
BD82CPMS-QMVY-A1_FCBGA989~D
R311 2 1 10K_0402_5% RI#

Defualt DSW Enable

C

PCH_RSMRST#
PVT:Reserved D29 D30
R312 2 1 10K_0402_5%
Note: 1.SLP_SUS and SUSACK# are NC if DSW is not supported
2.DPWROK should connect to RSMRST# if DSW not supported
3.The DSW rails must be stable for at least 10ms before DPWROK is asserted to PCH
***4.PCH_DPWROK pull up to +V3S enables DSW wupport. No install R5261 to disable DSW
@
PCH_PWROK 2 1 PCH_RSMRST#
D30 CH751H-40PT_SOD323-2

A A
<49,55> SPOK 1 2
D29 CH751H-40PT_SOD323-2
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 15 of 56
5 4 3 2 1
 5 4 3 2 1

R2613 1 2 100K_0402_5% ENBKL

D D

+3VS

R524 1 2 2.2K_0402_5% PCH_LCD_CLK U14D SDVO_SDATA 2 1

J47 AP43 R865 2.2K_0402_5%
PCH_LCD_DATA <43> ENBKL L_BKLTEN SDVO_TVCLKINN SDVO_SCLK
R525 1 2 2.2K_0402_5% M45 AP45 2 1 +3VS
<34> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP R864 2.2K_0402_5%
P45 AM42 PCH_DPB_HPD 1 2
<34> DPST_PWM L_BKLTCTL SDVO_STALLN
AM40 R866 @ 100K_0402_5%
SDVO_STALLP
T40

.ru
<34> PCH_LCD_CLK L_DDC_CLK
<34> PCH_LCD_DATA K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
CTRL_CLK T45
CTRL_DATA L_CTRL_CLK
P39 L_CTRL_DATA
2 1 LVDS_IBG AF37 P38 SDVO_SCLK
LVD_IBG SDVO_CTRLCLK SDVO_SDATA SDVO_SCLK <35>
R315 2.37K_0402_1% AF36 M39
LVD_VBG SDVO_CTRLDATA SDVO_SDATA <35>
+3VS
LVD_VREF AE48
R316 CTRL_CLK LVD_VREFH
1 2 2.2K_0402_5% 2 1 AE47 LVD_VREFL DDPB_AUXN AT49
R317 0_0402_5% AT47
R318 CTRL_DATA DDPB_AUXP PCH_DPB_HPD
1 2 2.2K_0402_5% DDPB_HPD AT40 PCH_DPB_HPD <35>
PCH_TXCLK- AK39

LVDS
<34> PCH_TXCLK- LVDSA_CLK#

m
PCH_TXCLK+ AK40 AV42
<34> PCH_TXCLK+ LVDSA_CLK DDPB_0N PCH_DPB_N2 <35>
PCH_TXOUT0- DDPB_0P AV40 PCH_DPB_P2 <35> HDMI D2
<34> PCH_TXOUT0- AN48 LVDSA_DATA#0 DDPB_1N AV45 PCH_DPB_N1 <35>

Digital Display Interface

PCH_TXOUT1- AM47 AV46 HDMI D1
C <34> PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P PCH_DPB_P1 <35> C
PCH_TXOUT2- AK47 AU48
<34> PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N PCH_DPB_N0 <35>
AJ48 LVDSA_DATA#3 DDPB_2P AU47 PCH_DPB_P0 <35> HDMI D0
DDPB_3N AV47 PCH_DPB_N3 <35>
PCH_TXOUT0+ AN47 AV49 HDMI CLK
<34> PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P PCH_DPB_P3 <35>
PCH_TXOUT1+ AM49
<34> PCH_TXOUT1+ PCH_TXOUT2+ LVDSA_DATA1

ru
<34> PCH_TXOUT2+ AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
P42
DDPC_CTRLDATA
R322 1 2 150_0402_1% PCH_CRT_B AF40
LVDSB_CLK#
AF39 AP47
R323 PCH_CRT_G LVDSB_CLK DDPC_AUXN
1 2 150_0402_1% AP49
DDPC_AUXP
AH45 AT38
R324 PCH_CRT_R LVDSB_DATA#0 DDPC_HPD
1 2 150_0402_1% AH47
LVDSB_DATA#1
AF49 AY47
LVDSB_DATA#2 DDPC_0N

Fo
AF45 AY49
LVDSB_DATA#3 DDPC_0P
AY43
DDPC_1N
AH43 AY45
LVDSB_DATA0 DDPC_1P
AH49 BA47
LVDSB_DATA1 DDPC_2N
AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 BB47
+3VS LVDSB_DATA3 DDPC_3N
BB49
DDPC_3P
R320 1 2 2.2K_0402_5% PCH_CRT_CLK
PCH_CRT_B N48 M43
PCH_CRT_DATA <36> PCH_CRT_B PCH_CRT_G CRT_BLUE DDPD_CTRLCLK
R321 1 2 2.2K_0402_5% P49 M36
<36> PCH_CRT_G PCH_CRT_R CRT_GREEN DDPD_CTRLDATA
<36> PCH_CRT_R T49
CRT_RED

er AT45

CRT
PCH_CRT_CLK DDPD_AUXN
<36> PCH_CRT_CLK T39 AT43
PCH_CRT_DATA CRT_DDC_CLK DDPD_AUXP
<36> PCH_CRT_DATA M40 BH41
CRT_DDC_DATA DDPD_HPD
B B
BB43
PCH_CRT_HSYNC DDPD_0N
<36> PCH_CRT_HSYNC M47 BB45
PCH_CRT_VSYNC CRT_HSYNC DDPD_0P
<36> PCH_CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
BE44
DDPD_1P
BF42
CRT_IREF DDPD_2N
T43 BE42
DAC_IREF DDPD_2P
yb
T42 BJ42
CRT_IRTN DDPD_3N
BG42
DDPD_3P
1

BD82CPMS-QMVY-A1_FCBGA989~D
R327
1K_0402_0.5%
2
C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 16 of 56
5 4 3 2 1
 5 4 3 2 1

U14E
+3VS AY7
RSVD1
RSVD2 AV7
RP23 BG26 AU3
PCI_PIRQA# TP1 RSVD3
8 1 BJ26 TP2 RSVD4 BG4
7 2 PCI_PIRQD# BH25
PCI_PIRQC# TP3
6 3 BJ16 TP4 RSVD5 AT10
5 4 PCI_PIRQB# BG16 BC8
TP5 RSVD6
AH38
8.2K_0804_8P4R_5% TP6
AH37 AU2
TP7 RSVD7
AK43 AT4
D RP24 TP8 RSVD8 D
AK45 AT3
PCH_WL_OFF# TP9 RSVD9
8 1 C18
TP10 RSVD10
AT1
7 2 WWAN_OFF# N30 AY3
PCH_GPIO5 TP11 RSVD11
6 3 H3 AT5
PCH_GPIO52 TP12 RSVD12
5 4 AH12 AV3
TP13 RSVD13
AM4 AV1
8.2K_0804_8P4R_5% TP14 RSVD14
AM5 BB1
TP15 RSVD15
Y13 BA3
RP25 TP16 RSVD16
K24 BB5
PCH_GPIO2 TP17 RSVD17
8 1 L24 BB3
PCH_GPIO4 TP18 RSVD18
7 2 AB46
TP19 RSVD19
BB7
6 3 ODD_DA# AB45 BE8

RSVD
TP20 RSVD20
5 4 RSVD21 BD4
RSVD22 BF6
8.2K_0804_8P4R_5%

.ru
B21 TP21 RSVD23 AV5
M20 TP22 RSVD24 AV10
AY16 TP23
BG46 TP24 RSVD25 AT8
1 2 PCH_GPIO53
R331 8.2K_0402_5% AY5
RSVD26
RSVD27 BA2
1 @ 2 BE28
R337 8.2K_0402_5% TP25
BC30 TP26 RSVD28 AT12
BE32 TP27 RSVD29 BF3
1 2 DGPU_HOLD_RST# BJ32
R332 8.2K_0402_5% TP28
BC28 TP29
BE30 TP30

m
1 2 DGPU_PWR_EN BF32
R330 1K_0402_5% TP31 USB20_N0
BG32 TP32 USBP0N C24
USB20_P0
USB20_N0 <42> Right USB-1
AV26 TP33 USBP0P A24 USB20_P0 <42>
BB26 C25 USB20_N1
C TP34 USBP1N USB20_P1 USB20_N1 <42> C
AU28 TP35 USBP1P B25
USB20_N2 USB20_P1 <42> Right USB-2
AY30 TP36 USBP2N C26 USB20_N2 <42>
AU26 A26 USB20_P2 Left USB
TP37 USBP2P USB20_N3 USB20_P2 <42>
AY26 TP38 USBP3N K28 USB20_N3 <34>
AV28 H28 USB20_P3 Came ra
TP39 USBP3P USB20_P3 <34>

ru
AW30 E28 USB20_N4
TP40 USBP4N USB20_P4 USB20_N4 <41>
Boot BIOS Strap bit1 BBS1 USBP4P D28 USB20_P4 <41> MPCIE-WLAN/BT
C28
USBP5N
Boot BIOS USBP5P
A28
C29
Bit11 Bit10 Destination USBP6N
USBP6P
B29
PCI_PIRQA# K40 N28 PCH HM65 config not support USB port 6 & 7.
PCI_PIRQB# PIRQA# USBP7N
0 1 Reserved K38 M28

PCI
PCI_PIRQC# PIRQB# USBP7P
GNT1#/ H38
PIRQC# USBP8N
L30
1 0 PCI PCI_PIRQD# G38 K30
GPIO51 PIRQD# USBP8P

Fo
G30
DGPU_HOLD_RST# C46 USBP9N +3VALW_PCH
1 1 SPI
* E30

USB
<22> DGPU_HOLD_RST# PCH_GPIO52 REQ1# / GPIO50 USBP9P USB20_N10
C44 C30 USB20_N10 <42>
DGPU_PWR_EN REQ2# / GPIO52 USBP10N USB20_P10
0 0 LPC For Optimus <45,53> DGPU_PWR_EN E40
REQ3# / GPIO54 USBP10P
A30 USB20_P10 <42> USB/CR RP26
L32 USB_OC3# 4 5
WWAN_OFF# USBP11N USB_OC0#
D47 K32 3 6
PCH_GPIO53 GNT1# / GPIO51 USBP11P USB_OC7#
E42 G32 2 7
PCH_WL_OFF# GNT2# / GPIO53 USBP12N USB_OC5#
<41> PCH_WL_OFF# F46 E32 1 8
GNT3# / GPIO55 USBP12P
C32
USBP13N 10K_1206_8P4R_5%
A32
PCH_GPIO2 USBP13P
G42
ODD_DA# PIRQE# / GPIO2
<40> ODD_DA#
PCH_GPIO4
G40
PIRQF# / GPIO3 USBRBIAS
Within 500 mils
C42 C33 1 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R333 22.6_0402_1% RP27

<14> CLK_PCI_LPBACK
CLK_PCI_LPBACK R334 2
PAD

<5,22,37,41,43> PLT_RST#

1 22_0402_5%
T31 @
er
PLT_RST#

CLK_PCI0
D44

K10

C6

H49
PIRQH# / GPIO5

PME#

PLTRST#

CLKOUT_PCI0
USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
B33

A14
K20
B17
C16
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC0# <42,43>
USB_OC1# <42,43>
USB_OC1#
USB_OC4#
USB_OC6#
USB_OC2#
4
3
2
1
5
6
7
8

10K_1206_8P4R_5%
B

CLK_PCI_LPC R335 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#

<43> CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
CLK_PCI2 USB_OC5#
yb
PAD T32 @ J48 A16
PAD T33 @ CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
K42 D14
CLK_PCI_DEBUG R953 CLK_PCI4 CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
<41> CLK_PCI_DEBUG 1 2 22_0402_5% PAD T34 @ H40 C14
CLKOUT_PCI4 OC7# / GPIO14

BD82CPMS-QMVY-A1_FCBGA989~D

2 @ 1
C

R336 0_0402_5%
+3VS
5

PLT_RST# 1
P

IN1
4 PLT_RST_BUF# <41>
O
2
IN2
G

U19 R339
3

SN74AHC1G08DCKR_SC70-5 100K_0402_5%
A A
2

DVT:<SMT memo>update U19 P/N

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB, NVRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 17 of 56
5 4 3 2 1
 5 4 3 2 1

GPIO28
+3VS
On-Die PLL Voltage Regulator Note: High - CRT Plugged
This signal has a weak internal pull up
：：On-Die

2
H voltage regu lator enable
* L On-Die PLL Voltage Reg ulator disable R342
10K_0402_5%
1 @ 2 PCH_GPIO28 +3VS
R343 1K_0402_5%

1
CRT_DET

1
D ODD_ EN# @
1 2
2 R2614 10K_0402_5%
D <36> CRT_DET# D
GPIO27 G
PCH_GPIO27 (Have internal Pull-High) S Q12

3
@ PCH_GPIO70 1 2
High: VCCVRM VR Enable 2N7002_SOT23-3 R2616 10K_0402_5%
* Low: VCCVRM VR Disable PCH_GPIO71 1 2
R2617 10K_0402_5%
GATEA20 1 2
1 @ 2 PCH_GPIO27 R346 10K_0402_5%
R344 10K_0402_5% EC_KBRST# 1 2
R345 10K_0402_5%

SATA2GP/GPIO36 & SATA3GP/GPIO37

Sampled at Rising edge of PWROK.

.ru
Weak internal pull-down. (weak internal pull-down is disabled after PLTRST# de-asserts)
NOTE: This signal should NOT be pulled high when strap is sampled
U14F
+3VS
+3VS CRT_DET T7 C40 ODD_ EN#
Project ID GPIO69
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <40>
14" 0

1
1 2 ODD_DETECT# PCH_GPIO1 A42 B41 PCH_GPIO69
R357 200K_0402_1% TACH1 / GPIO1 TACH5 / GPIO69 R2615
PCH_GPIO6 H36 C41 PCH_GPIO70
15.6" 1 10K_0402_5%
TACH2 / GPIO6 TACH6 / GPIO70
+3VS EC_SCI# E38 A40 PCH_GPIO71 15@
<43> EC_SCI#

2
TACH3 / GPIO7 TACH7 / GPIO71 PCH_GPIO69
EC_SMI#

m
<43> EC_SMI# C10
@ PCH_GPIO37 GPIO8
2 1

1
R801 1K_0402_5% PCH_GPIO12 C4
C LAN_PHY_PWR_CTRL / GPIO12 R940 C
2 1 USB30_SMI# G2 P4 10K_0402_5%
GPIO15 A20GATE GATEA20 <43>
R776 100K_0402_5%
AU16 PCH_PECI_R 1 @ 2 14@
H_PECI <5,43>

2
PCH_GPIO16 PECI R348 0_0402_5%
U2
SATA4GP / GPIO16 +1.8VS
P5 EC_KBRST# <43>
RCIN#

GPIO

ru
For Optimus <45,53> 1 2 DGPU_ PWROK_R D40 AY11

CPU/MISC
DGPU_PWROK H_CPUPW RGD <5>

1
R350 0_0402_5% TACH0 / GPIO17 PROCPWRGD
PCH_GPIO22 T5 AY10 PCH_ THRMTRIP#_R 1 2 H_THRMTRIP# <5> R328
SCLOCK / GPIO22 THRMTRIP# R351 390_0402_5% 2.2K_0402_5%
PCH_GPIO24 E8 T14
GPIO24 / MEM_LED INIT3_3V# Note: This signal has weak internal PU, can't pull low

2
PCH_GPIO27 E16 AY1 NV_ CLE 2 1 H_SNB_IVB# <5>
GPIO27 DF_TVS R329 1K_0402_5%
PCH_GPIO28 P8
GPIO28 Layout note: CLOSE TO THE BRANCHING POINT
AH8
BT_ON# TS_VSS1 Intel Anti-Theft Techonlogy

Fo
<41> BT_ON# K1
STP_PCI# / GPIO34
AK11
TS_VSS2
PCH_GPIO35 K4
GPIO35
High=Endabled
TS_VSS3
AH10 NV_ALE
ODD_DETECT# Low=Disable(floating)
<40> ODD_DETECT# V8
SATA2GP / GPIO36
TS_VSS4
AK10 *
PCH_GPIO37 M5
SATA3GP / GPIO37
PCH_GPIO38 N2 P37
SLOAD / GPIO38 NC_1
+3VS PCH_GPIO39 M3
SDATAOUT0 / GPIO39
PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15

B R421

R420

R352

R353
1

1
2

2
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
PCH_GPIO6

PCH_GPIO1

PCH_GPIO16

DGPU_ PWROK_R

PCH_GPIO22
DVT:Add PCH_GPIO49 net off page
er
<13> PCH_GPIO49
PCH_GPIO49

PCH_GPIO57
V3

D6

A4

A44
SATA5GP / GPIO49

GPIO57

VSS_NCTF_1

VSS_NCTF_2
VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20
BG48

BH3

BH47

BJ4

BJ44
B

R354 10K_0402_5%
yb
1 2 PCH_GPIO38 A45 BJ45
R347 10K_0402_5% VSS_NCTF_3 VSS_NCTF_21

NCTF
1 2 PCH_GPIO39 A46 BJ46
R356 10K_0402_5% VSS_NCTF_4 VSS_NCTF_22
A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
1 2 BT_ON# B3 C2
R358 10K_0402_5% VSS_NCTF_7 VSS_NCTF_25
1 2 PCH_GPIO48 B47 C48
R359 10K_0402_5% VSS_NCTF_8 VSS_NCTF_26
PCH_GPIO49
C

1 2 BD1 D1
R360 10K_0402_5% VSS_NCTF_9 VSS_NCTF_27
BD49 D49
+3VALW_PCH VSS_NCTF_10 VSS_NCTF_28
BE1 E1
PCH_GPIO12 VSS_NCTF_11 VSS_NCTF_29
1 2
R361 10K_0402_5% BE49 E49
USB30_SMI# VSS_NCTF_12 VSS_NCTF_30
1 2
R362 1K_0402_5% BF1 F1
PCH_GPIO28 VSS_NCTF_13 VSS_NCTF_31
1 2
R363 10K_0402_5% BF49 F49
A PCH_GPIO57 VSS_NCTF_14 VSS_NCTF_32 A
1 2
R364 10K_0402_5%
1 @ 2 PCH_GPIO24 BD82CPMS-QMVY-A1_FCBGA989~D
R429 10K_0402_5%

1 @ 2 PCH_GPIO35
R365 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C ustom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Monday, April 11, 2011 Sheet 18 of 56
5 4 3 2 1
 5 4 3 2 1

PCH Power Rail Table

S0 Iccmax
Voltage Rail Voltage
+1.05VS U14G POWER Current (A)
L5 +3VS
1300mA MBK1608221YZF_2P V_PROC_IO 1.05 0.001
Layout note: Close to AA23 AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2] 1 1 1 1

10U_0603_6.3V6M
C206

1U_0402_6.3V6K
C207

1U_0402_6.3V6K
C208

1U_0402_6.3V6K
C209

CRT

0.01U_0402_16V7K
C210

0.1U_0402_10V7K
C211
1 1 1 1 AD21 VCCCORE[3]
V5REF 5 0.001
AD23 U47 C212 C926
VCCCORE[4] VSSADAC

VCC CORE
AF21 22U_0603_6.3V6M 22U_0603_6.3V6M
VCCCORE[5] 2 2 2 2
AF23
VCCCORE[6]
V5REF_Sus 5 0.001
D 2 2 2 2 AG21 +3VS D
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9] 1mA VCCALVDS AK36 Vcc3_3 3.3 0.266
AG26
VCCCORE[10]
AG27 AK37
VCCCORE[11] VSSALVDS
AG29
VCCCORE[12]
VccADAC 3.3 0.001
AJ23

LVDS
VCCCORE[13]
AJ26 AM37
VCCCORE[14] VCCTX_LVDS[1] +1.8VS
AJ27
VCCCORE[15]
VccADPLLA 1.05 0.08
AJ29 AM38 L6
VCCCORE[16] VCCTX_LVDS[2] Layout note: Close to AM37 0.1UH_MLF1608DR10KT_10%_1608
AJ31
VCCCORE[17] +VCCTX_LVDS
+1.05VS +1.05VS_VCCDPLLEXP
60mAVCCTX_LVDS[3] AP36 2 1 VccADPLLB 1.05 0.08

0.01U_0402_16V7K

0.01U_0402_16V7K
1 1 1 0.1uH inductor, 200mA

22U_0805_6.3V6M
VCCTX_LVDS[4] AP37

C213

C214
2 1 +1.05VS_VCCDPLLEXP AN19 VccCore 1.05 1.3

.ru
VCCIO[28]

C215
R368 0_0603_5%
2 2 2
PAD T71 @ +VCCAPLLEXP BJ22 VccDMI 1.05 0.042
VCCAPLLEXP +3VS
This pin can be left as no connect in V33

HVCMOS
VCC3_3[6] +3VS_VCC3_3_6
AN16 1 2 VccIO 1.05 2.925
On-Die VR enabled mode (default). VCCIO[15] R370 0_0805_5%
AN17 VCCIO[16] 1 Layout note: Close to V33
VCC3_3[7] V34 VccASW 1.05 1.01
C216
AN21 VCCIO[17] 0.1U_0402_10V7K
2 VccSPI 3.3 0.02
AN26 VCCIO[18]

m
+1.05VS Layout note: Close to AN21,AN16,AN23 AN27 2925mA AT16 +VCCAFDI_VRM Layout note: Close to AT20 VccDSW 3.3 0.003
VCCIO[19] VCCVRM[3]
1 2 +1.05VS_VCC_EXP AP21 +VCCP_VCCDMI +1.05VS
C VCCIO[20] C
R371 0_0805_5% VccpNAND 1.8 0.19
10U_0603_6.3V6M
C217

1U_0402_6.3V6K
C218

1U_0402_6.3V6K
C219

1U_0402_6.3V6K
C220

1U_0402_6.3V6K
C221

1 1 1 1 1 AP23 AT20 +VCCP_VCCDMI 1 2

VCCIO[21] VCCDMI[1] R372 0_0805_5%
1

DMI
AP24 L2401 +1.05VS VccRTC 3.3 6 uA

VCCIO
VCCIO[22] 10UH_LB2012T100MR_20% C222
2 2 2 2 2 AB36 +VCCP_VCC_DMI_CCI

ru
AP26 20mA VCCCLKDMI 1 2 1U_0402_6.3V6K
VCCIO[23] 2
1 VccSus3_3 3.3 0.119
AT24 Layout note: Close to AB36
VCCIO[24] C223
1U_0402_6.3V6K VccSusHDA 3.3 / 1.5 0.01
AN33 2
VCCIO[25]
AN34
VCCIO[26] VCCDFTERM[1]
AG16 VccVRM 1.8 / 1.5 0.16
+3VS +VCCPNAND +1.8VS
Layout note: Close to BH29 Layout note: Close to AG16

Fo
1 2 +3VS_VCCA3GBG BH29 AG17 1 2 VccCLKDMI 1.05 0.02

DFT / SPI
R374 0_0805_5% 1 VCC3_3[3] 190mAVCCDFTERM[2] R375 0_0805_5%
C224
0.1U_0402_10V7K
VCCDFTERM[3]
AJ16 1 VccSSC 1.05 0.095
C225
+1.05VS 2 +VCCAFDI_VRM AP16 0.1U_0402_10V7K
VCCVRM[2]
VCCDFTERM[4]
AJ17 VccDIFFCLKN 1.05 0.055
2
2 @ 1 +1.05VS_VCCAPLL_FDI BG6
VccAFDIPLL
R376 0_0603_5% VccALVDS 3.3 0.001
1 2 +1.05VS_VCCDPLL_FDI AP17
+1.05VS VCCIO[27]
FDI

R377 0_0805_5% V1 +3V_VCCPSPI 1 2 +3VALW_PCH VccTX_LVDS 1.8 0.06

20mA VCCSPI R378 0_0805_5%

B
+VCCP_VCCDMI AU20
VCCDMI[2]
er
BD82CPMS-QMVY-A1_FCBGA989~D
1

Layout note: Close to V1

C227
1U_0402_6.3V6K B
yb
+1.5VS +VCCAFDI_VRM

2 1 +VCCAFDI_VRM
R379 0_0603_5%
+1.8VS
C

2 @ 1
R380 0_0603_5%

VCCVRM==>1.5V FOR MOBILE

VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 19 of 56
5 4 3 2 1
 5 4 3 2 1

+3VS Have internal VRM

+1.05VS VCC3_3 = 266mA detal waiting for newest spec
2 @ 1 +VCCACLK VCCDMI = 42mA detal waiting for newest spec
L7 Layout note: Close to T38 R382 0_0603_5%
10UH_LB2012T100MR_20% +5VALW
1 2 +3VS_VCC_CLKF33
+3VALW_PCH Layout note: Close to N26
1 1
POWER +1.05VS
2 1

10U_0603_6.3V6M
C228

1U_0402_6.3V6K
C229
Layout note: Close to T16 U14J R383 0_0603_5%
1 2 +VCCPDSW @ Q13
R384 0_0603_5% 1 AD49 N26 +1.05VS_VCCUSBCORE 2 1 AO3413_SOT23-3 +5VALW_PCH
2 2 VCCACLK VCCIO[29] R386 0_0603_5%
1

D
C231 P26 3 1
0.1U_0402_10V7K VCCIO[30] C232
T16 3mA
2 VCCDSW3_3

0.1U_0402_10V7K
C233

20K_0402_5%
R388
D 1U_0402_6.3V6K D
P28
VCCIO[31]

1
@ 2

G
1

2
2 1 +PCH_VCCDSW V12 T27 @
C230 0.1U_0402_10V7K DCPSUSBYP VCCIO[32] @
<46> PCH_PWR_EN#
T29
+3VS_VCC_CLKF33 VCCIO[33] Layout note: Close to T23 +3VALW_PCH 2
T38

2
+1.05VS VCC3_3[5]
T23 +3V_VCCPUSB 2 1
119mA VCCSUS3_3[7]

0.1U_0402_10V7K
1 2 +VCCAPLL_CPY_PCH BH23 R390 0_0603_5% 12/29 change SC1H751H010 to SCS00003500
VCCAPLLDMI2 +3VALW_PCH

C235
L8 @ 10UH_LB2012T100MR_20% T24 1
+VCCDPLL_CPY VCCSUS3_3[8] +5VALW_PCH +3VALW_PCH
1 +1.05VS 1 2 AL29
VCCIO[14]
R385 0_0603_5% V23 +3V_VCCAUBG 2 1

USB
C234 @ VCCSUS3_3[9] R391 0_0603_5%
1

2
10U_0603_6.3V6M +VCCSUS1 2 C236
AL24 DCPSUS[3] VCCSUS3_3[10] V24
2 0.1U_0402_10V7K R392 D3
1

.ru
P24 Layout note: Close to P24 10_0402_5% CH751H-40PT_SOD323-2
@ C237 VCCSUS3_3[6] 2
1U_0402_6.3V6K AA19

1
2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
DVT:Reserved C913 C914 +1.05VS VCCIO[34] T26 2 1 +1.05VS
AA21 VCCASW[2]
1010mA R393 0_0603_5% 1
Layout note: Close to AA19
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C238
VCCASW[3] 1mA V5REF_SUS

Clock and Miscellaneous

R394 0_0805_5% 1 1 0.1U_0603_25V7K
2

22U_0805_6.3V6M
C239

22U_0805_6.3V6M
C240
AA26 @
VCCASW[4] +VCCA_USBSUS C241
DCPSUS[4] AN23 1 2 1U_0402_6.3V6K
AA27 VCCASW[5]
+1.05VS 2 2 AN24 +3V_VCCPSUS Layout note: Close to M26
L9 VCCSUS3_3[1]
AA29 VCCASW[6]

m
10UH_LB2012T100MR_20%
1 2 +1.05VS_VCCA_A_DPL AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF

2
C
1 2 +1.05VS_VCCA_B_DPL +3VALW_PCH C
1 1 1
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
C242

1U_0402_6.3V6K
C243

1U_0402_6.3V6K
C244
L10 AC27 R396 D4
VCCASW[9]
220U_B2_2.5VM_R35
C248

1U_0402_6.3V6K
C249

220U_B2_2.5VM_R35
C250

1U_0402_6.3V6K
C251

10UH_LB2012T100MR_20% 1 1 N20 +3V_VCCPSUS 2 1 10_0402_5% CH751H-40PT_SOD323-2

PCI/GPIO/LPC
VCCSUS3_3[2] R395 0_0603_5%
1 1 1 1 AC29 VCCASW[10]
2 2 2
C913

C914

+ + N22 1

1
VCCSUS3_3[3]

ru
AC31 C245 +PCH_V5REF_RUN
VCCASW[11] +3VS 1U_0402_6.3V4Z
VCCSUS3_3[4] P20 1
2 2 2 2 2 2
AD29
VCCASW[12] Layout note: Close to AA16 2 2 Layout note: Close to N20 C246
P22 1
VCCSUS3_3[5] R398 0_0805_5% 1U_0603_10V6K
AD31 1
VCCASW[13] C247 2
@ @ W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
W23 W16 2 +3VS Layout note: Close to P34
VCCASW[15] VCC3_3[8]

Fo
Layout note: Close to AF17 W24 T34 +3VS_VCCPPCI 2 1
+1.05VS VCCASW[16] VCC3_3[4] R399 0_0603_5%
PVT:<Memo> 1
W26 C252
+VCCDIFFCLK VCCASW[17] 0.1U_0402_10V7K
2 1
R401 0_0603_5% 1 W29 +3VS
C254 VCCASW[18] Layout note: Close to AJ2 2 Layout note: Close to T34
1U_0402_6.3V6K W31 AJ2 +VCC3_3_2 2 1
VCCASW[19] VCC3_3[2] 0_0603_5% +1.05VS_SATA3 +1.05VS
2 1 R400
W33
VCCASW[20] C253
AF13 2 1
VCCIO[5] 0.1U_0402_10V7K R402 0_0805_5%
+VCCRTCEXT 2
N16 1
Layout note: Close to AF33 DCPRTC
1 AH13
+1.05VS +1.05VS_VCCDIFFCLKN C256 VCCIO[12] C255

B
R403
2 1
0_0603_5% 1

C257
0.1U_0402_10V7K
2
+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL
er Y49

BD47
VCCVRM[4] VCCIO[13]

VCCIO[6]
AH14

AF14
+1.05VS_SATA3
2
1U_0402_6.3V6K

Layout note: Close to AH13

L11 @ +1.05VS
10UH_LB2012T100MR_20%
B

SATA
1U_0402_6.3V6K VCCADPLLA 80mA +VCCSATAPLL
AK1 1 2
2 +1.05VS_VCCA_B_DPL VCCAPLLSATA +VCCAFDI_VRM
BF47
VCCADPLLB 80mA @
1
AF11 +VCCAFDI_VRM C258
+VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS
yb
AF17 10U_0603_6.3V6M
Layout note: Close to AG33 VCCIO[7]
AF33
+1.05VS VCCDIFFCLKN[1] +1.05VS_VCC_SATA 2
AF34 55mA
VCCDIFFCLKN[2] VCCIO[2]
AC16 2 1
+1.05VS_VCCDIFFCLKN AG34 R406 0_0805_5% Layout note: Close to AK1
+1.05VS_SSCVCC VCCDIFFCLKN[3]
2 1 AC17 1
R405 0_0603_5% 1 VCCIO[3] C260
+1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
C259 VCCSSC 95mA VCCIO[4]
1U_0402_6.3V6K 2 Layout note: Close to AC16
2 +VCCSST V16
DCPSST +1.05VS
1
C

C261 +1.05VM_VCCSUS T17 T21 +VCCME_22 2 1

0.1U_0402_10V7K DCPSUS[1] VCCASW[22] R408 0_0603_5%
V19
MISC

2 DCPSUS[2]
V21 +VCCME_23 2 1
+1.05VS Layout note: Close to BJ8 VCCASW[23] R409 0_0603_5%
CPU

1 2 +V_CPU_IO BJ8
R410 0_0603_5% V_PROC_IO 1mA +VCCME_21
T19 2 1
VCCASW[21] R411 0_0603_5%
1 1 1
+RTCVCC +3VALW_PCH
4.7U_0603_6.3V6K
C263

0.1U_0402_10V7K
C264

0.1U_0402_10V7K
C265

Layout note: Close to A22 Layout note: Close to P32

RTC

A22 P32 +VCCSUSHDA 2 1

HDA

2 2 2 VCCRTC 10mA VCCSUSHDA R412 0_0603_5%

1U_0402_6.3V6K
C266

0.1U_0402_10V7K
C267

0.1U_0402_10V7K
C268

1 1 1 1
BD82CPMS-QMVY-A1_FCBGA989~D C269
A 0.1U_0402_16V4Z A

+1.05VS 2 2 2 2

2 @ 1 +1.05VM_VCCSUS
R407 0_0603_5%
1
@ C262 Security Classification Compal Secret Data Compal Electronics, Inc.
1U_0402_6.3V6K 2010/08/23 2011/08/25 Title
2 Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 20 of 56
5 4 3 2 1
 5 4 3 2 1

U14I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 K39
VSS[162] VSS[262]
B11 K46
D U14H VSS[163] VSS[263] D
B15 K7
VSS[164] VSS[264]
H5 B19 L18
VSS[0] VSS[165] VSS[265]
B23 L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 AK4 B31 L26
VSS[2] VSS[81] VSS[168] VSS[268]
AA3 AK42 B35 L28
VSS[3] VSS[82] VSS[169] VSS[269]
AA33 AK46 B39 L36
VSS[4] VSS[83] VSS[170] VSS[270]
AA34 AK8 B7 L48
VSS[5] VSS[84] VSS[171] VSS[271]
AB11 AL16 F45 M12
VSS[6] VSS[85] VSS[172] VSS[272]
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 AL19 BB16 M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 AL26 BB28 M32

.ru
VSS[12] VSS[91] VSS[178] VSS[278]
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40

m
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4

ru
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 AP42 BF22 T47
VSS[37] VSS[116] VSS[203] VSS[303]
AD45 AP46 BF24 T8
VSS[38] VSS[117] VSS[204] VSS[304]
AD46 AP8 BF26 V11
VSS[39] VSS[118] VSS[205] VSS[305]
AD8 AR2 BF28 V17
VSS[40] VSS[119] VSS[206] VSS[306]
AE2 AR48 BD3 V26
VSS[41] VSS[120] VSS[207] VSS[307]
AE3 AT11 BF30 V27
VSS[42] VSS[121] VSS[208] VSS[308]
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
VSS[44] VSS[123] VSS[210] VSS[310]

Fo
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
VSS[46] VSS[125] VSS[212] VSS[312]
AF16 AT28 BG21 V43
VSS[47] VSS[126] VSS[213] VSS[313]
AF19 AT30 BG33 V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 AT32 BG44 W17
VSS[49] VSS[128] VSS[215] VSS[315]
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
VSS[51] VSS[130] VSS[217] VSS[317]
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 AT46 BH17 W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 AU24 H10 Y38
VSS[55] VSS[134] VSS[221] VSS[321]
AF42 AU30 BH27 Y4
VSS[56] VSS[135] VSS[222] VSS[322]
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]

B
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
er
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
B

AH36 AW2 D22 G14

VSS[67] VSS[146] VSS[233] VSS[337]
yb
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
VSS[69] VSS[148] VSS[235] VSS[340]
AH42 AW28 D30 BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 AW32 D32 BG24
VSS[71] VSS[150] VSS[237] VSS[343]
AH7 AW34 D34 C22
VSS[72] VSS[151] VSS[238] VSS[344]
AJ19 AW36 D38 AP13
VSS[73] VSS[152] VSS[239] VSS[345]
AJ21 AW40 D42 M14
VSS[74] VSS[153] VSS[240] VSS[346]
AJ24 AW48 D8 AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 AV11 E18 AP1
VSS[76] VSS[155] VSS[242] VSS[348]
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 AY22 G18 BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
C

G26 BJ28
BD82CPMS-QMVY-A1_FCBGA989~D VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
A A

BD82CPMS-QMVY-A1_FCBGA989~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 21 of 56
5 4 3 2 1
 5 4 3 2 1

UV1A

PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1

PEX_RX0 GPIO0
PEG_HTX_C_GRX_N0 AN17 K2 H PD_C H PD_C 1 OPT@ 2
PEG_HTX_C_GRX_P1 PEX_RX0_N GPIO1 RV4 100K_0402_5%
AN19 K3
LV2 OPT@ PEG_HTX_C_GRX_N1 PEX_RX1 GPIO2 EDP_HPD_R
150mA AP19 H3 1 OPT@ 2
BLM18PG330SN1D_0603 Layout note: Under GPU PEG_HTX_C_GRX_P2 PEX_RX1_N GPIO3 RV5 100K_0402_5%
AR19 H2
+ PLLVDD PEG_HTX_C_GRX_N2 PEX_RX2 GPIO4 GPU_VID0 HPD_F
+1.05VS_DGPU 1 2 AR20 H1 GPU_VID0 <53> 1 OPT@ 2
PEG_HTX_C_GRX_P3 PEX_RX2_N GPIO5 GPU_VID1 RV29 100K_0402_5%
AP20 H4 GPU_VID1 <53>
PEX_RX3 GPIO6

0.1U_0402_16V4Z

OPT@ CV11
0.1U_0402_16V4Z

OPT@ CV12
0.1U_0402_16V4Z

OPT@ CV9
0.1U_0402_16V4Z

10U_0603_6.3V6M
PEG_HTX_C_GRX_N3 AN20 H5 HDMI_HPD_VGA 2 OPT@ 1
PEX_RX3_N GPIO7

OPT@ CV8

OPT@ CV7
1 1 1 1 2 PEG_HTX_C_GRX_P4 AN22 H6 OVERT#_VGA R1436 100K_0402_5%
PEG_HTX_C_GRX_N4 PEX_RX4 GPIO8 THERM#_VGA
AP22 J7
PEG_HTX_C_GRX_P5 PEX_RX4_N GPIO9
AR22 K4
PEG_HTX_C_GRX_N5 PEX_RX5 GPIO10 D2425 @
AR23 K5
2 2 2 2 1 PEG_HTX_C_GRX_P6 PEX_RX5_N GPIO11 ACIN_VGA
AP23 H7 2 1

GPIO
PEX_RX6 GPIO12 AC IN <15,43,44,46,48>
D
PEG_HTX_C_GRX_N6 AN23 J4 D
PEG_HTX_C_GRX_P7 PEX_RX6_N GPIO13 CH751H-40PT_SOD323-2 +3VS_DGPU
AN25 J6
PEG_HTX_C_GRX_N7 PEX_RX7 GPIO14 HDMI_HPD_VGA
AP25 L1
PEG_HTX_C_GRX_P8 PEX_RX7_N GPIO15
AR25 L2
PEX_RX8 GPIO16
PEG_HTX_C_GRX_N8 AR26 L4 VGA_ EDID_CLK 1 OPT@ 2
PEG_HTX_C_GRX_P9 PEX_RX8_N GPIO17 RV6 2.2K_0402_5%
AP26 M4
PEX_RX9 GPIO18
PEG_HTX_C_GRX_N9 AN26 L7 EDP_HPD_R VGA_EDID_DATA 1 OPT@ 2
PEG_GTX_C_HRX_N[0..15] PEG_HTX_C_GRX_P10 PEX_RX9_N GPIO19 RV7 2.2K_0402_5%
<4> PEG_GTX_C_HRX_N[0..15] AN28 L5
PEX_RX10 GPIO20
PEG_HTX_C_GRX_N10 AP28 K6 HPD_F SMB_CLK_GPU 1 OPT@ 2
PEG_GTX_C_HRX_P[0..15] PEG_HTX_C_GRX_P11 PEX_RX10_N GPIO21 RV8 2.2K_0402_5%
<4> PEG_GTX_C_HRX_P[0..15] AR28 L6
PEG_HTX_C_GRX_N11 PEX_RX11 GPIO22 SMB_DATA_GPU
AR29 M6 TV6 1 OPT@ 2
PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_P12 PEX_RX11_N GPIO23 RV9 2.2K_0402_5%
<4> PEG_HTX_C_GRX_N[0..15] AP29 M7
PEG_HTX_C_GRX_N12 PEX_RX12 GPIO24 ACIN_VGA
AN29 1 OPT@ 2
PEG_HTX_C_GRX_P[0..15] PEG_HTX_C_GRX_P13 PEX_RX12_N RV32 10K_0402_5%
<4> PEG_HTX_C_GRX_P[0..15] AN31 N1
PEX_RX13 MIOA_D0_NC
PEG_HTX_C_GRX_N13 AP31 P4 THERM#_VGA 1 OPT@ 2
PEG_HTX_C_GRX_P14 PEX_RX13_N MIOA_D1_NC RV10 100K_0402_5%
AR31 P1

.ru
PEX_RX14 MIOA_D2_NC
PEG_HTX_C_GRX_N14 AR32 P2 OVERT#_VGA 1 OPT@ 2
PEG_HTX_C_GRX_P15 PEX_RX14_N MIOA_D3_NC RV37 10K_0402_5%
AR34 P3
PEX_RX15 MIOA_D4_NC
PEG_HTX_C_GRX_N15 AP34 T3 HDCP_SCL 1 OPT@ 2
PEX_RX15_N MIOA_D5_NC RV11 2.2K_0402_5%
T2
MIOA_D6_NC HDCP_SDA
T1 1 OPT@ 2
PEG_GTX_C_HRX_P0 C270 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P0 MIOA_D7_NC RV12 2.2K_0402_5%
2 AL17 U4
PEG_GTX_C_HRX_N0 C271 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N0 PEX_TX0 MIOA_D8_NC VGA_CRT_DATA 1 OPT@

PCI EXPRESS
2 AM17 U1 2
PEG_GTX_C_HRX_P1 C272 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P1 PEX_TX0_N MIOA_D9_NC RV13 2.2K_0402_5%
2 AM18 U2
C273 OPT@ 1 0.1U_0402_16V7K PEX_TX1 MIOA_D10_NC
PEG_GTX_C_HRX_N1 2 PEG_GTX_HRX_N1 AM19 U3 VG A_CRT_CLK 1 OPT@ 2
PEG_GTX_C_HRX_P2 C274 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P2 PEX_TX1_N MIOA_D11_NC RV14 2.2K_0402_5%
2 AL19 R6
C275 OPT@ 1 0.1U_0402_16V7K PEX_TX2 MIOA_D12_NC
PEG_GTX_C_HRX_N2 2 PEG_GTX_HRX_N2 AK19 T6 I2CB_SCL 1 OPT@ 2

DVO
PEG_GTX_C_HRX_P3 C276 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P3 PEX_TX2_N MIOA_D13_NC RV121 2.2K_0402_5%
2 AL20 N6
C277 OPT@ 1 0.1U_0402_16V7K PEX_TX3 MIOA_D14_NC
PEG_GTX_C_HRX_N3 2 PEG_GTX_HRX_N3 AM20 I2CB_SDA 1 OPT@ 2
PEG_GTX_C_HRX_P4 C278 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P4 PEX_TX3_N RV122 2.2K_0402_5%

m
2 AM21 Y1
PEG_GTX_C_HRX_N4 C279 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N4 PEX_TX4 MIOB_D0_NC
2 AM22 Y2
PEG_GTX_C_HRX_P5 C280 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P5 PEX_TX4_N MIOB_D1_NC
2 AL22 Y3
PEG_GTX_C_HRX_N5 C281 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N5 PEX_TX5 MIOB_D2_NC
2 AK22 AB3
PEG_GTX_C_HRX_P6 C282 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P6 PEX_TX5_N MIOB_D3_NC
2 AL23 AB2
C PEG_GTX_C_HRX_N6 C283 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N6 PEX_TX6 MIOB_D4_NC C
2 AM23 AB1
PEG_GTX_C_HRX_P7 C284 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P7 PEX_TX6_N MIOB_D5_NC
2 AM24 AC4
PEG_GTX_C_HRX_N7 C285 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N7 PEX_TX7 MIOB_D6_NC
2 AM25 AC1
PEG_GTX_C_HRX_P8 C286 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P8 PEX_TX7_N MIOB_D7_NC
2 AL25 AC2
PEG_GTX_C_HRX_N8 C287 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N8 PEX_TX8 MIOB_D8_NC +3VS
2 AK25 AC3
PEX_TX8_N MIOB_D9_NC

ru
PEG_GTX_C_HRX_P9 C290 OPT@ 1 2 0.1U_0402_16V7K PEG_GTX_HRX_P9 AL26 AE3
PEG_GTX_C_HRX_N9 C288 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N9 PEX_TX9 MIOBD_10_NC
2 AM26 AE2
PEX_TX9_N MIOB_D11_NC

5
PEG_GTX_C_HRX_P10 C291 OPT@ 1 2 0.1U_0402_16V7K PEG_GTX_HRX_P10 AM27 U6
PEG_GTX_C_HRX_N10 C292 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N10 PEX_TX10 MIOB_D12_NC DGPU_HOLD_RST#
2 AM28 W6 1

P
PEX_TX10_N MIOB_D13_NC <17> DGPU_HOLD_RST# IN1
PEG_GTX_C_HRX_P11 C294 OPT@ 1 2 0.1U_0402_16V7K PEG_GTX_HRX_P11 AL28 Y6 4 PLTRST_VGA#
PEG_GTX_C_HRX_N11 C295 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N11 PEX_TX11 MIOB_D14_NC PLT_RST# O
2 AK28 <5,17,37,41,43> PLT_RST# 2

1
PEX_TX11_N IN2

G
PEG_GTX_C_HRX_P12 C296 OPT@ 1 2 0.1U_0402_16V7K PEG_GTX_HRX_P12 AK29 N3 OPT@
PEG_GTX_C_HRX_N12 C297 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N12 PEX_TX12 MIOA_HSYNC_NC OPT@ U21 R426
2 AL29 L3

3
PEG_GTX_C_HRX_P13 C298 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P13 PEX_TX12_N MIOA_VSYNC_NC SN74AHC1G08DCKR_SC70-5 100K_0402_5%
2 AM29
PEG_GTX_C_HRX_N13 C299 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N13 PEX_TX13
2 AM30 W1
PEG_GTX_C_HRX_P14 C300 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P14 PEX_TX13_N MIOB_HSYNC_NC

Fo
2 AM31 W2

2
PEG_GTX_C_HRX_N14 C301 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N14 PEX_TX14 MIOB_VSYNC_NC
2 AM32
PEG_GTX_C_HRX_P15 C302 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_P15 PEX_TX14_N
2 AN32 N2
PEG_GTX_C_HRX_N15 C303 OPT@ 1 0.1U_0402_16V7K PEG_GTX_HRX_N15 PEX_TX15 MIOA_DE_NC
2 AP32 P5
PEX_TX15_N MIOA_CTL3_NC
MIOA_VREF_NC
N5 DVT:<SMT memo> update U21 P/N
Y5
@ R2647 @ C2581 CLK_PCIE_VGA MIOB_DE_NC
<14> CLK_PCIE_VGA AR16 W3
22_0402_5% 10P_0402_50V8J CL K_PCIE_VGA# PEX_REFCLK MIOB_CTL3_NC
<14> CLK_PCIE_VGA# AR17 AF1
XTALIN CL K_REQ_GPU# PEX_REFCLK_N MIOB_VREF_NC
2 1 1 2 AR13
PEX_CLKREQ_N
N4 1 OPT@ 2
@ PEX_TSTCLK_OUT MIOA_CLKIN_NC RV15 10K_0402_5%
1 2 AJ17 R4
Layout note: Reserve for EMI please close to UV1 Layout note: Differential signal RV16 200_0402_1%
PEX_TSTCLK_OUT# PEX_TSTCLK_OUT MIOA_CLKOUT_NC
AJ18
PEX_TSTCLK_OUT_N
AE1 1 OPT@ 2

B
RV28

XTALIN 3
4
1

YV1
@

1 XTAL_OUT
2
2
10M_0402_5%
PLTRST_VGA#
RV18

RV19
1 OPT@

1 OPT@
2

+ PLLVDD
er PLTRST_VGA_R#
0_0402_5%

2.49K_0402_1%

60mA
45mA
AM16
AG21

AE9

AF9
PEX_RST_N
PEX_TERMP

PLLVDD

SP_PLLVDD
MIOB_CLKIN_NC
MIOB_CLKOUT_NC

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

MIOACAL_PD_VDDQ_NC
MIOACAL_PU_GND_NC

MIOBCAL_PD_VDDQ_NC
V4

T4
W4

U5
T5

AA7
RV17

RV131
1OPT@

1 OPT@
10K_0402_5%

2
10K_0402_5%
B

27MHZ_16PF_7M27070004 AA6 RV132 10K_0402_5%

MIOBCAL_PU_GND_NC
yb
1 1 45mA AD9
VID_PLLVDD
CV45 CV46
CLK

OPT@
18P_0402_50V8J OPT@ 2 @ 1 XTALIN B1
OPT@ 18P_0402_50V8J <14> CLK_27M_PCH R894 22_0402_5% XTAL_OUT XTAL_IN
B2 AM15
2 2 XTAL_OUT DACA_RED
AM14
DACA_GREEN
2 OPT@ 1 XTALOUT D1 AL14
RV26 2 OPT@ XTAL_OUTBUFF DACA_BLUE
1 10K_0402_5% XTALSSIN D2
RV25 10K_0402_5% XTAL_SSIN
AM13
DACA_HSYNC
AL13
DACA_VSYNC
SMB_CLK_GPU E2 AJ12 1 OPT@ 2
+3VS_DGPU Note: Internal Thermal Sensor SMB_DATA_GPU E1 I2CS_SCL DACA_VDD RV130 10K_0402_5%
AK12
I2CS_SDA DACA_VREF
C

AK13
VGA_ EDID_CLK E3 DACA_RSET
I2CC_SCL
DACs

VGA_EDID_DATA E4 AK4
I2CC_SDA DACB_RED
2

AL4
I2CB_SCL DACB_GREEN
G3 AJ4
SMB_CLK_GPU I2CB_SDA I2CB_SCL DACB_BLUE
1 6 G2
I2C

EC_SMB_CK2 <14,43> I2CB_SDA

AM1
5

Q14A OPT@ VG A_CRT_CLK G1 DACB_HSYNC

AM2
2N7002DW-T/R7_SOT363-6 VGA_CRT_DATA G4 I2CA_SCL DACB_VSYNC
SMB_DATA_GPU I2CA_SDA
4 3 EC_SMB_DA2 <14,43> AG7
HDCP_SCL DACB_VDD
F6 AK6
Q14B OPT@ HDCP_SDA I2CH_SCL DACB_VREF
G6 AH7
2N7002DW-T/R7_SOT363-6 I2CH_SDA DACB_RSET

N12P-GS1-A1_BGA_973P OPT@
A A
+3VS_DGPU +3VS_DGPU
1

OPT@
R442
10K_0402_5%
2
G

Security Classification Compal Secret Data Compal Electronics, Inc.

2

1 3 CL K_REQ_GPU# 2010/08/23 2011/08/25 Title

<14> VGA_CLKREQ# Issued Date Deciphered Date
VGA_PCIE/DAC/GPIO
D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Q15 OPT@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2N7002_SOT23-3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
D ate: Monday, April 11, 2011 Sheet 22 of 56
5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
AM11 IFPA_TXC NC_0 A2
AM12 IFPA_TXC_N NC_1 A7
AM8 IFPA_TXD0 NC_2 B7
AL8 C5 OPT@
IFPA_TXD0_N NC_3 RV134
AM10 IFPA_TXD1 NC_4 C7 1 2 20K_0402_1%
AM9 IFPA_TXD1_N NC_5 D5
AK10 D6 OPT@
IFPA_TXD2 NC_6 RV133
AL10 IFPA_TXD2_N NC_7 D7 1 2 4.99K_0402_1%
AK11 IFPA_TXD3 NC_8 E5
AL11 E7 RV135 1 OPT@ 2 10K_0402_5%
D IFPA_TXD3_N NC_9 D
NC_10 F4
NC_11 G5
AP13 IFPB_TXC NC_12 H32
AN13 IFPB_TXC_N NC_13 J25
AN8 IFPB_TXD4 NC_14 J26
AP8 P6 RV136 1 OPT@ 2 40.2K_0402_1%
IFPB_TXD4_N NC_15
AP10 IFPB_TXD5 NC_16 U7
AN10 IFPB_TXD5_N NC_17 V6
AR11 IFPB_TXD6 NC_18 Y4
AR10 IFPB_TXD6_N NC_19 AA4
AN11 IFPB_TXD7 NC_20 AB4
AP11 IFPB_TXD7_N NC_21 AB7
NC_22 AC5

NC
NC_23 AD6
AM7 IFPC_L0 NC_24 AF6

.ru
AM6 IFPC_L0_N NC_25 AG6
AL5 IFPC_L1 NC_26 AG20
AM5 IFPC_L1_N NC_27 AJ5
AM3 IFPC_L2 NC_28 AK15
AM4 IFPC_L2_N NC_29 AL7
AP1 IFPC_L3
AR2 IFPC_L3_N

AR8 IFPD_L0
AR7 IFPD_L0_N
AP7 IFPD_L1
AN7 IFPD_L1_N

m
AN5 IFPD_L2

LVDS/TMDS
C AP5 IFPD_L2_N
C
AR5 IFPD_L3
AR4 IFPD_L3_N

AH6 IFPE_L0
AH5 IFPE_L0_N
AH4 IFPE_L1

ru
AG4 IFPE_L1_N
AF4 IFPE_L2
AF5 IFPE_L2_N
AE6 IFPE_L3
AE5 IFPE_L3_N

VDD_SENSE_0 D35 +VGASENSE <53>

AL2 IFPF_L0 VDD_SENSE_1 P7
AL3 IFPF_L0_N VDD_SENSE_2 AD20
AJ3 IFPF_L1

Fo
AJ2 IFPF_L1_N
AJ1 IFPF_L2
AH1 IFPF_L2_N GND_SENSE_0 AD19
AH2 IFPF_L3 GND_SENSE_1 E35
AH3 IFPF_L3_N GND_SENSE_2 R7

AP2 IFPC_AUX_I2CW _SCL

AN3 IFPC_AUX_I2CW _SDA_N TEST
B B
AP4 AP35 TESTMODE 1 OPT@ 2
IFPD_AUX_I2CX_SCL TESTMODE
er AN4

AE4
AD4

AF3
AF2
IFPD_AUX_I2CX_SDA_N

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

SERIAL
AP14
AN14
AN16
AR14
AP16
RV47

RV41
TV2
TV3
TV4
TV5
1 OPT@ 2
10K_0402_5%

10K_0402_5%

+3VS_DGPU
yb
C3 ROM_CS# 2 @ 1
ROM_CS_N ROM_SI RV44 10K_0402_5%
ROM_SI D3 ROM_SI <33>
C4 ROM_SO
ROM_SO ROM_SO <33>
D4 ROM_SCLK ROM_SCLK <33>
ROM_SCLK

GENERAL A5
NC/SPDIF_NC
A4 BUFRST_N
MULTI_STRAP_REF0_GND N9 1 OPT@ 2
+3VS_DGPU 1 OPT@ 2 AB5 CEC
RV48 40.2K_0402_1%
RV49 10K_0402_5% M9 1 OPT@ 2
C

STRAP0 MULTI_STRAP_REF1_GND RV50 40.2K_0402_1%

<33> STRAP0 W5 STRAP0
STRAP1 W7 B5
<33> STRAP1 STRAP1 THERMDP
<33> STRAP2 STRAP2 V7 B4
STRAP2 THERMDN

A N12P-GS1-A1_BGA_973P OPT@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
D ate: Sunday, April 10, 2011 Sheet 23 of 56
5 4 3 2 1
 5 4 3 2 1

D D

Layout note: Close to Power

+VGA_CORE +VGA_CORE

.ru
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
+VGA_CORE +VGA_CORE

330U_D2_2V_Y
@

330U_D2_2V_Y
OPT@ CV58

@
1 1 2 2 2
UV1G
+ +

CV57

CV225

CV226

CV227
AB11 VDD_0 VDD_56 P21
Part 7 of 7 1 1 1
AB13 VDD_1 VDD_57 P23
2 2
AB15 VDD_2 VDD_58 P25
AB17 VDD_3 VDD_59 R11
AB19 VDD_4 VDD_60 R12
AB21 VDD_5 VDD_61 R13

m
AB23 VDD_6 VDD_62 R14
AB25 VDD_7 VDD_63 R15 DVT:<SMT memo>CV57 SMT-->@
C AC11 VDD_8 VDD_64 R16 C
AC12 VDD_9 VDD_65 R17
AC13 R18 +VGA_CORE
VDD_10 VDD_66
AC14 VDD_11 VDD_67 R19
AC15 VDD_12 VDD_68 R20
AC16 VDD_13 VDD_69 R21

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0603_6.3V6K

22U_0805_6.3V6M

47U_0805_4V6
AC17 R22

ru
VDD_14 VDD_70

OPT@ CV61

OPT@ CV60

OPT@ CV212

OPT@ CV43

OPT@ CV10
AC18 VDD_15 VDD_71 R23 2 2 1 1 1
AC19 VDD_16 VDD_72 R24
AC20 VDD_17 VDD_73 R25
AC21 VDD_18 VDD_74 T12
1 1 2 2 2
AC22 VDD_19 VDD_75 T14
AC23 VDD_20 VDD_76 T16
POWER

AC24 VDD_21 VDD_77 T18

AC25 VDD_22 VDD_78 T20

Fo
AD12 VDD_23 VDD_79 T22
AD14 VDD_24 VDD_80 T24
AD16 VDD_25 VDD_81 V11
AD18 V13 Layout note: Under GPU
VDD_26 VDD_82
AD22 VDD_27 VDD_83 V15
AD24 V17 +VGA_CORE
VDD_28 VDD_84
L11 VDD_29 VDD_85 V19
L12 VDD_30 VDD_86 V21
0.047U_0402_25V6K

0.047U_0402_25V6K

0.047U_0402_25V6K

0.022U_0402_25V7K

0.022U_0402_25V7K

0.022U_0402_25V7K
L13 VDD_31 VDD_87 V23

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V4Z
L14 VDD_32 VDD_88 V25
OPT@ CV64

OPT@ CV65

OPT@ CV66

OPT@ CV123

OPT@ CV70

OPT@ CV71

OPT@ CV59

OPT@ CV63

OPT@ CV62
L15 VDD_33 VDD_89 W11 1 1 1 1 1 1 1 1 1
L16 W12
B L17
L18
L19
L20
L21
L22
L23
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
W13
W14
W15
W16
W17
W18
W19
2
er 2 2 2 2 2 2 2 2
B

L24 VDD_42 VDD_98 W20

yb
L25 VDD_43 VDD_99 W21
M12 VDD_44 VDD_100 W22
M14 W23 +VGA_CORE
VDD_45 VDD_101
M16 VDD_46 VDD_102 W24
M18 VDD_47 VDD_103 W25
0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K
M20 VDD_48 VDD_104 Y12
M22 VDD_49 VDD_105 Y14
OPT@ CV74

OPT@ CV75

OPT@ CV76

OPT@ CV77

OPT@ CV78

OPT@ CV79

OPT@ CV124

OPT@ CV125

OPT@ CV44

OPT@ CV52

OPT@ CV55
M24 VDD_50 VDD_106 Y16 1 1 1 1 1 1 1 1 1

1
P11 VDD_51 VDD_107 Y18
P13 VDD_52 VDD_108 Y20
P15 Y22
C

2
VDD_53 VDD_109 2 2 2 2 2 2 2 2
P17 VDD_54 VDD_110 Y24
P19 VDD_55

N12P-GS1-A1_BGA_973P OPT@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VGA CORE
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 24 of 56
5 4 3 2 1
 5 4 3 2 1

UV1E
Layout note: Under GPU
3.5A Part 5 of 7 2200mA
+VRAM_1.5VS J23
1600mA AG11 +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K

10U_0603_6.3V6M

22U_0805_6.3V6M
J24 AG12
FBVDDQ_1 PEX_IOVDDQ_1

OPT@ CV82

OPT@ CV83

OPT@ CV67

OPT@ CV68

OPT@ CV87

OPT@ CV88

OPT@ CV89

OPT@ CV90

OPT@ CV91

OPT@ CV92

OPT@ CV3
1 1 1 1 J29 AG13 1 1 1 1 1 1 1
FBVDDQ_2 PEX_IOVDDQ_2
AA27 FBVDDQ_3 PEX_IOVDDQ_3 AG15
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16
AA31 AG17
2 2 2 2 FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 2
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
AC27 FBVDDQ_8 PEX_IOVDDQ_8 AG23
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24
D AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25 D
Layout note: Under GPU AJ28 AG26
FBVDDQ_11 PEX_IOVDDQ_11 +1.05VS_DGPU

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K

10U_0603_6.3V6M

22U_0805_6.3V6M
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14

OPT@ CV93

OPT@ CV94

OPT@ CV95

OPT@ CV96

OPT@ CV97

OPT@ CV98

OPT@ CV4
+VRAM_1.5VS E21 FBVDDQ_13 PEX_IOVDDQ_13 AJ15 1 1 1 1 1 1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
G17 AJ19
FBVDDQ_14 PEX_IOVDDQ_14

OPT@ CV99

OPT@ CV100

OPT@ CV101

OPT@ CV102

OPT@ CV103

OPT@ CV104

OPT@ CV126

OPT@ CV86
1 G18 FBVDDQ_15 PEX_IOVDDQ_15 AJ21
1 1 1 1 1 1 1 G22 FBVDDQ_16 PEX_IOVDDQ_16 AJ22
G8 AJ24 2 2 2 2 2 2 2
FBVDDQ_17 PEX_IOVDDQ_17
G9 FBVDDQ_18 PEX_IOVDDQ_18 AJ25
2 H29 AJ27
2 2 2 2 2 2 2 FBVDDQ_19 PEX_IOVDDQ_19

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
J15 FBVDDQ_21 PEX_IOVDDQ_21 AK20
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26
LV4 OPT@

.ru
J20 FBVDDQ_24 PEX_IOVDDQ_24 AL16
J21 BLM18PG121SN1D_0603
FBVDDQ_25
J22 FBVDDQ_26
2 1 +1.05VS_DGPU

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
N27 FBVDDQ_27 600mA

OPT@ CV105

OPT@ CV107

OPT@ CV108

4.7U_0603_6.3V6K
P27 FBVDDQ_28 PEX_IOVDD_0 AK16 1 1 1

OPT@ CV109
R27 FBVDDQ_29 PEX_IOVDD_1 AK17 1
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
U29 AK27 2 2 2
FBVDDQ_32 PEX_IOVDD_4 2
V27 FBVDDQ_33
V29 FBVDDQ_34 120mA
V34
W27
FBVDDQ_35 120mA AG14 +PEX_PLLVDD

m
FBVDDQ_36 PEX_PLLVDD
Y27 FBVDDQ_37 +3VS_DGPU
120mA
1 OPT@ 2 +IFPAB_PLLVDD AK9 IFPAB_PLLVDD PEX_SVDD_3V3 AG19
C RV1231 @ 2 10K_0402_5% AJ11 F7 C
RV96 1K_0402_1% IFPAB_RSET PEX_SVDD_3V3_NC OPT@ 1 1 OPT@
CV110 CV111
1 OPT@ 2 +IFPAB_IOVDD AG9 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
RV124 10K_0402_5% IFPA_IOVDD
AG10 J10

ru
IFPB_IOVDD VDD33_0 2 2
VDD33_1 J11
J12
+IFPD_PLLVDD VDD33_2
1 OPT@ 2 AJ9 J13 120mA
RV1251 @ IFPC_PLLVDD VDD33_3
2 10K_0402_5% AK7 J9 +3VS_DGPU
IFPC_RSET VDD33_4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
RV51 1K_0402_1%

OPT@ CV217

OPT@ CV216

OPT@ CV112

OPT@ CV113

OPT@ CV114
1 OPT@ 2 +IFPD_IOVDD AJ8 1 1 1 1 1
RV126 10K_0402_5% IFPC_IOVDD
P9
+IFPD_PLLVDD MIOA_VDDQ_NC_0
AC6 R9
@ IFPD_PLLVDD MIOA_VDDQ_NC_1 2 2 2 2 2

Fo
1 2 AB6 T9
RV52 1K_0402_1% IFPD_RSET MIOA_VDDQ_NC_2
U9
+IFPD_IOVDD MIOA_VDDQ_NC_3
AK8
IFPD_IOVDD
1 OPT@ 2 +IFPEF_PLLVDD
MIOB_VDDQ_NC_0
AA9
RV127 10K_0402_5% AJ6 AB9
@ IFPEF_PLLVDD MIOB_VDDQ_NC_1
1 2 AL1 W9
RV53 1K_0402_1% IFPEF_RSET MIOB_VDDQ_NC_2
Y9
+IFPE_IO VDD MIOB_VDDQ_NC_3
1 OPT@ 2 AE7
RV128 10K_0402_5% IFPE_IOVDD
AD7
IFPF_IOVDD

B
er N12P-GS1-A1_BGA_973P OPT@

B
yb
C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 25 of 56
5 4 3 2 1
 5 4 3 2 1

UV1F

B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
B27 GND_7 GND_103 Y13
B30 GND_8 GND_104 Y15
B33 GND_9 GND_105 Y17
D
C2 GND_10 GND_106 Y19 D
C34 GND_11 GND_107 Y21
E6 GND_12 GND_108 Y23
E9 GND_13 GND_109 Y25
E12 GND_14 GND_110 AA2
E15 GND_15 GND_111 AA5
E18 GND_16 GND_112 AA11
E24 GND_17 GND_113 AA12
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 AA19

.ru
GND_24 GND_120
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 AB20

m
GND_36 GND_132
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
C M31 GND_40 GND_136 AD2 C
M34 GND_41 GND_137 AD5

GND
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15

ru
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 GND_52 GND_148 AE12
N22 GND_53 GND_149 AE13
N23 AE14

Fo
GND_54 GND_150
N24 GND_55 GND_151 AE15
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17
P14 GND_58 GND_154 AE18
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 GND_62 GND_158 AE22
P24 GND_63 GND_159 AE23
R2 GND_64 GND_160 AE24
R5 GND_65 GND_161 AE25
R31 AG2

B
er
R34
T11
T13
T15
T17
T19
T21
T23
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
B

GND_74 GND_170
T25 GND_75 GND_171 AL6
yb
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 AP3
C

GND_86 GND_182
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

A A
N12P-GS1-A1_BGA_973P OPT@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 26 of 56
5 4 3 2 1
 5 4 3 2 1

UV1B

Part 2 of 7 CMDA0
MDA[0..63] MDA0 L32
FBA_CMD0 U30
V30
CMDA0 <29> GB2-128
D <29,30> MDA[0..63] FBA_D0 FBA_CMD1 D
MDA1 CMDA2
MDA2
N33
L33
FBA_D1 FBA_CMD2 U31
V32 CMDA3
CMDA2 <29> Mode E - Mirror Mode Mapping
FBA_D2 FBA_CMD3 CMDA3 <29>
MDA3 N34 T35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 <29,30>
MDA4 N35 U33 CMDA5 DATA Bus
FBA_D4 FBA_CMD5 CMDA5 <29,30>
MDA5 P35 W 32 CMDA6
FBA_D5 FBA_CMD6 CMDA6 <29,30>
MDA6 P33 W 33 CMDA7
CMDA7 <29,30> Address 0..31 32..63
MDA7 FBA_D6 FBA_CMD7 CMDA8
P34 FBA_D7 FBA_CMD8 W 31 CMDA8 <29,30>
MDA8 K35 W 34 CMDA9 CMD3 CKE_L
FBA_D8 FBA_CMD9 CMDA9 <29,30>
MDA9 K33 U34 CMDA10
FBA_D9 FBA_CMD10 CMDA10 <29,30>
MDA10 K34 U35 CMDA11 CMD8 A8 A8
FBA_D10 FBA_CMD11 CMDA11 <29,30>
MDA11 H33 U32 CMDA12
FBA_D11 FBA_CMD12 CMDA12 <29,30>
MDA12 G34 T34 CMDA13 CMD2 CS0#_L
FBA_D12 FBA_CMD13 CMDA13 <29,30>
MDA13 G33 T33 CMDA14
FBA_D13 FBA_CMD14 CMDA14 <29,30>
MDA14 E34 W 30 CMDA15 CMD21 A7 A6

.ru
FBA_D14 FBA_CMD15 CMDA15 <29,30>
MDA15 E33 AB30 CMDA16
FBA_D15 FBA_CMD16 CMDA16 <30>
MDA16 G31 AA30 CMD24 A2 A1
MDA17 FBA_D16 FBA_CMD17 CMDA18
F30 FBA_D17 FBA_CMD18 AB31 CMDA18 <30>
MDA18 G30 AA32 CMDA19 CMD23 A11 A9
FBA_D18 FBA_CMD19 CMDA19 <30>
MDA19 G32 AB33 CMDA20
FBA_D19 FBA_CMD20 CMDA20 <29,30>
MDA20 K30 Y32 CMDA21 CMD26 A5 A4
FBA_D20 FBA_CMD21 CMDA21 <29,30>
MDA21 K32 Y33 CMDA22
FBA_D21 FBA_CMD22 CMDA22 <29,30>
MDA22 H30 AB34 CMDA23 CMD7 A0 A12
FBA_D22 FBA_CMD23 CMDA23 <29,30>
MDA23 K31 AB35 CMDA24
FBA_D23 FBA_CMD24 CMDA24 <29,30>
MDA24 L31 Y35 CMDA25 CMD15 CAS# CAS#
FBA_D24 FBA_CMD25 CMDA25 <29,30>
MDA25 L30 W 35 CMDA26
FBA_D25 FBA_CMD26 CMDA26 <29,30>
MDA26 M32 Y34 CMDA27 CMD13 BA1 A3

MEMORY INTERFACE

m
FBA_D26 FBA_CMD27 CMDA27 <29,30>
MDA27 N30 Y31 CMDA28
FBA_D27 FBA_CMD28 CMDA28 <29,30>
MDA28 M30 Y30 CMDA29 CMD4 A9 A11
FBA_D28 FBA_CMD29 CMDA29 <29,30>
MDA29 P31 W 29 CMDA30
FBA_D29 FBA_CMD30 CMDA30 <29,30>
C MDA30 R32 Y29 CMD18 CS0#_H C
MDA31 FBA_D30 FBA_CMD31
R30 FBA_D31 DQMA[7..0] <29,30>
MDA32 AG30 P32 DQMA0 CMD29 BA0 BA0
+1.05VS_DGPU FBA_D32 FBA_DQM0 DQSA#[7..0] <29,30>
MDA33 AG32 H34 DQMA1
FBA_D33 FBA_DQM1 DQSA[7..0] <29,30>
LV6 OPT@ MDA34 AH31 J30 DQMA2 CMD27 BA2 A15
100mA FBA_D34 FBA_DQM2

ru
BLM18PG330SN1D_0603 MDA35 AF31 P30 DQMA3
+FB_AVDD0 MDA36 FBA_D35 FBA_DQM3 DQMA4
1 2 AF30 FBA_D36 FBA_DQM4 AF32 CMD6 A3 BA1
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

MDA37 AE30 AL32 DQMA5

FBA_D37 FBA_DQM5
OPT@ CV106

OPT@ CV69

OPT@ CV149

OPT@ CV84

OPT@ CV229

2 2 1 1 1 MDA38 AC32 AL34 DQMA6 CMD17 CS1#_H

MDA39 FBA_D38 FBA_DQM6 DQMA7
AD30 FBA_D39 FBA_DQM7 AF35
MDA40 AN33 CMD19 ODT_H
MDA41 FBA_D40 DQSA#0
AL31 FBA_D41 FBA_DQS_RN0 L35
1 1 2 2 2

A
MDA42 AM33 G35 DQSA#1 CMD22 A4 A5
MDA43 FBA_D42 FBA_DQS_RN1 DQSA#2
AL33 FBA_D43 FBA_DQS_RN2 H31
MDA44 AK30 N32 DQSA#3 CMD12 A13 A14

Fo
MDA45 FBA_D44 FBA_DQS_RN3 DQSA#4
AK32 FBA_D45 FBA_DQS_RN4 AD32
MDA46 AJ30 AJ31 DQSA#5 CMD28 WE# A10
MDA47 FBA_D46 FBA_DQS_RN5 DQSA#6
AH30 FBA_D47 FBA_DQS_RN6 AJ35
MDA48 AH33 AC34 DQSA#7 CMD10 A1 A2
+1.05VS_DGPU MDA49 FBA_D48 FBA_DQS_RN7
AH35 FBA_D49
LV9 OPT@ MDA50 AH34 L34 DQSA0 CMD25 A10 WE#
BLM18PG330SN1D_0603 100mA MDA51 FBA_D50 FBA_DQS_W P0 DQSA1
AH32 FBA_D51 FBA_DQS_W P1 H35
1 2 +FB_AVDD1 MDA52 AJ33 J32 DQSA2 CMD9 A12 A0
FBA_D52 FBA_DQS_W P2
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

MDA53 AL35 N31 DQSA3

FBA_D53 FBA_DQS_W P3
OPT@ CV137

OPT@ CV121

OPT@ CV150

OPT@ CV136

OPT@ CV230

2 2 1 1 1 MDA54 AM34 AE31 DQSA4 CMD1 CS1#_L

MDA55 FBA_D54 FBA_DQS_W P4 DQSA5
AM35 FBA_D55 FBA_DQS_W P5 AJ32
MDA56 AF33 AJ34 DQSA6 CMD11 RAS# RAS#

B
1 1 2 2 2
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
er
AE32
AF34
AE35
AE34
AE33
AB32
AC35
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DQS_W P6
FBA_DQS_W P7

FBA_W CK0
FBA_W CK0_N
FBA_W CK1
FBA_W CK1_N
FBA_W CK2
AC33

P29
R29
L29
M29
AG29
AH29
DQSA7
CMD0
CMD5
CMD16
CMD20
ODT_L
A6

RST
A7
CKE_H
RST
B

+FB_AVDD0 FBA_W CK2_N

AG27 FB_DLLAVDD_0 FBA_W CK3 AD29
yb
AF27 FB_PLLAVDD_0 FBA_W CK3_N AE29 CMD14 A14 A13
+FB_AVDD1 J19 CMD30 A15 BA2
FB_DLLAVDD_1 CLKA0
J18 FB_PLLAVDD_1 FBA_CLK0 T32 CLKA0 <29>
T31 CLKA0#
FBA_CLK0_N CLKA0# <29>
J27 FB_VREF_NC
+VRAM_1.5VS 2 OPT@ 1 T30 FBA_DEBUG0 FBA_CLK1 AC31 CLKA1
CLKA1 <30>
RV101 2 OPT@ 1 60.4_0402_1% T29 AC30 CLKA1#
FBA_DEBUG1 FBA_CLK1_N CLKA1# <30>
RV57 10K_0402_5%

N12P-GS1-A1_BGA_973P OPT@
C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_MEM Interface A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Monday, April 11, 2011 Sheet 27 of 56
5 4 3 2 1
 5 4 3 2 1

UV1C

Part 3 of 7 F18
FBC_CMD0
B13 FBC_D0 FBC_CMD1 E19
D13 FBC_D1 FBC_CMD2 D18
A13 FBC_D2 FBC_CMD3 C17
A14 FBC_D3 FBC_CMD4 F19
C16 FBC_D4 FBC_CMD5 C19
D B16 FBC_D5 FBC_CMD6 B17 D
A17 FBC_D6 FBC_CMD7 E20
D16
C13
FBC_D7 FBC_CMD8 B19
D20
GB2-128
FBC_D8 FBC_CMD9
B11
C11
FBC_D9 FBC_CMD10 A19
D19
Mode E - Mirror Mode Mapping
FBC_D10 FBC_CMD11
A11 FBC_D11 FBC_CMD12 C20 DATA Bus
C10 FBC_D12 FBC_CMD13 F20
C8 B20 Address 0..31 32..63
FBC_D13 FBC_CMD14
B8 FBC_D14 FBC_CMD15 G21
A8 FBC_D15 FBC_CMD16 F22 CMD3 CKE_L
E8 FBC_D16 FBC_CMD17 F24
F8 FBC_D17 FBC_CMD18 F23 CMD8 A8 A8
F10 C25

.ru
FBC_D18 FBC_CMD19
F9 FBC_D19 FBC_CMD20 C23 CMD2 CS0#_L
F12 FBC_D20 FBC_CMD21 F21
D8 FBC_D21 FBC_CMD22 E22 CMD21 A7 A6
D11 FBC_D22 FBC_CMD23 D21
E11 FBC_D23 FBC_CMD24 A23 CMD24 A2 A1
D12 FBC_D24 FBC_CMD25 D22
E13 FBC_D25 FBC_CMD26 B23 CMD23 A11 A9
F13 C22

MEMORY INTERFACE C
FBC_D26 FBC_CMD27
F14 FBC_D27 FBC_CMD28 B22 CMD26 A5 A4
F15 FBC_D28 FBC_CMD29 A22
E16 FBC_D29 FBC_CMD30 A20 CMD7 A0 A12

m
F16 FBC_D30 FBC_CMD31 G20
F17 FBC_D31 CMD15 CAS# CAS#
C D29 FBC_D32 FBC_DQM0 A16 C
F27 FBC_D33 FBC_DQM1 D10 CMD13 BA1 A3
F28 FBC_D34 FBC_DQM2 F11
E28 FBC_D35 FBC_DQM3 D15 CMD4 A9 A11
D26 FBC_D36 FBC_DQM4 D27
F25 FBC_D37 FBC_DQM5 D34 CMD18 CS0#_H
D24 A34

ru
FBC_D38 FBC_DQM6
E25 FBC_D39 FBC_DQM7 D28 CMD29 BA0 BA0
E32 FBC_D40
F32 FBC_D41 FBC_DQS_RN0 B14 CMD27 BA2 A15
D33 FBC_D42 FBC_DQS_RN1 B10
E31 FBC_D43 FBC_DQS_RN2 D9 CMD6 A3 BA1
C33 FBC_D44 FBC_DQS_RN3 E14
F29 FBC_D45 FBC_DQS_RN4 F26 CMD17 CS1#_H
D30 FBC_D46 FBC_DQS_RN5 D31

Fo
E29 FBC_D47 FBC_DQS_RN6 A31 CMD19 ODT_H
B29 FBC_D48 FBC_DQS_RN7 A26
C31 FBC_D49 CMD22 A4 A5
C29 FBC_D50 FBC_DQS_WP0 C14
B31 FBC_D51 FBC_DQS_WP1 A10 CMD12 A13 A14
C32 FBC_D52 FBC_DQS_WP2 E10
B32 FBC_D53 FBC_DQS_WP3 D14 CMD28 WE# A10
B35 FBC_D54 FBC_DQS_WP4 E26
B34 FBC_D55 FBC_DQS_WP5 D32 CMD10 A1 A2
A29 FBC_D56 FBC_DQS_WP6 A32
B28 FBC_D57 FBC_DQS_WP7 B26 CMD25 A10 WE#
A28
B C28
C26
D25
B25
A25
er
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
G14
G15
G11
G12
G27
G28
G24
CMD9
CMD1
CMD11
CMD0
A12
CS1#_L
RAS#
ODT_L
A0

RAS#
B

+VRAM_1.5VS 1 OPT@ 2 K27 FBCAL_PD_VDDQ FBC_WCK3_N G25

RV58 40.2_0402_1% CMD5 A6 A7
yb
1 OPT@ 2 L27 FBCAL_PU_GND
RV59 40.2_0402_1% E17 CMD16 CKE_H
FBC_CLK0
1 OPT@ 2 M27 FBCAL_TERM_GND FBC_CLK0_N D17
RV60 60.4_0402_1% CMD20 RST RST
+VRAM_1.5VS 2 OPT@ 1 G19 FBC_DEBUG0 FBC_CLK1 D23
RV105 2 OPT@ 1 60.4_0402_1% G16 E23 CMD14 A14 A13
RV61 10K_0402_5% FBB_DEBUG1 FBC_CLK1_N
CMD30 A15 BA2
N12P-GS1-A1_BGA_973P OPT@
C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_MEM Interface C
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 28 of 56
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits MDA[0..63] <27,30>

CMDA[30..0] <27,30>

DQMA[7..0] <27,30>
UV5 UV6
DQSA[7..0] <27,30>
+VRAM_1.5VS +FBA_VREF0 M8 E3 MDA3 +FBA_VREF0 M8 E3 MDA19
VREFCA DQL0 VREFCA DQL0 DQSA#[7..0] <27,30>
H1 F7 MDA6 H1 F7 MDA17
VREFDQ DQL1 MDA1 VREFDQ DQL1 MDA18
DQL2 F2 DQL2 F2
1

D CMDA7 N3 F8 MDA4 CMDA7 N3 F8 MDA16 Group2 D

RV62 CMDA10 A0 DQL3 MDA2 CMDA10 A0 DQL3 MDA20
P7 A1 DQL4 H3 Group0 P7 A1 DQL4 H3
1.1K_0402_1% CMDA24 P3 H8 MDA7 CMDA24 P3 H8 MDA22
OPT@ CMDA6 A2 DQL5 MDA0 CMDA6 A2 DQL5 MDA21
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA22 P8 H7 MDA5 CMDA22 P8 H7 MDA23
2

+FBA_VREF0 CMDA26 A4 DQL7 CMDA26 A4 DQL7

P2 A5 P2 A5
CMDA5 R8 CMDA5 R8
A6 A6
1

CMDA21 MDA29 CMDA21 MDA14

RV63
1
CV151 CMDA8
R2
T8
A7 DQU0 D7
C3 MDA26 CMDA8
R2
T8
A7 DQU0 D7
C3 MDA9 GB2-128
1.1K_0402_1% 0.01U_0402_25V7K CMDA4 A8 DQU1 MDA30 CMDA4 A8 DQU1 MDA12
OPT@ OPT@ CMDA25
R3
L7
A9 DQU2 C8
C2 MDA24 CMDA25
R3
L7
A9 DQU2 C8
C2 MDA11 Mode E - Mirror Mode Mapping
2 CMDA23 A10/AP DQU3 MDA27 CMDA23 A10/AP DQU3 MDA13
R7 A7 Group3 R7 A7 Group1 DATA Bus
2

CMDA9 A11 DQU4 MDA25 CMDA9 A11 DQU4 MDA8

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDA12 T3 B8 MDA31 CMDA12 T3 B8 MDA15 Address 0..31 32..63

.ru
CMDA14 A13 DQU6 MDA28 CMDA14 A13 DQU6 MDA10
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDA30 M7 CMDA30 M7 CMD3 CKE_L
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD8 A8 A8
CMDA29 M2 B2 CMDA29 M2 B2
CMDA13 BA0 VDD CMDA13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CLKA0 CMDA27 M3 G7 CMDA27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD24 A2 A1

OPT@ CLKA0 J7 N9 CLKA0 J7 N9
<27> CLKA0 CK VDD CK VDD
160_0402_1% CLKA0# CLKA0#

m
<27> CLKA0# K7 CK VDD R1 K7 CK VDD R1 CMD23 A11 A9
RV64 CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
C CMD26 A5 A4 C
1

CLKA0# CMDA0 K1 A1 CMDA0 K1 A1 CMD7 A0 A12

CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD15 CAS# CAS#
CMDA15 RAS VDDQ CMDA15 RAS VDDQ CMDA0
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDA28 L3 D2 CMDA28 L3 D2 CMD13 BA1 A3

ru
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 CMDA3 CMD4 A9 A11
DQSA0 VDDQ DQSA2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSA3 C7 H9 DQSA1 C7 H9 CMD18 CS0#_H
DQSU VDDQ DQSU VDDQ

2
RV98 RV102 CMD29 BA0 BA0
DQMA0 E7 A9 DQMA2 E7 A9 10K_0402_5% 10K_0402_5%
DQMA3 DML VSS DQMA1 DML VSS OPT@ OPT@
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15

Fo
E1 E1

1
VSS VSS
VSS G8 VSS G8 CMD6 A3 BA1
DQSA#0 G3 J2 DQSA#2 G3 J2
DQSA#3 DQSL VSS DQSA#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD17 CS1#_H
VSS M1 VSS M1
VSS M9 VSS M9 CMD19 ODT_H
VSS P1 VSS P1
CMDA20 T2 P9 CMDA20 T2 P9 CMD22 A4 A5
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD12 A13 A14
CMD28 WE# A10
er
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
RV65 RV66 L1 B9 RV67 L1 B9 CMD10 A1 A2
10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
OPT@ OPT@ L9 D8 OPT@ L9 D8 CMD25 A10 WE#
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD9 A12 A0
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD1 CS1#_L
yb
VSSQ G9 VSSQ G9
CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
128MX16 H5TQ2G63BFR-11C 128MX16 H5TQ2G63BFR-11C
@ @ CMD5 A6 A7
CMD16 CKE_H
+VRAM_1.5VS +VRAM_1.5VS
CMD20 RST RST
C
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
CMD14 A14 A13
OPT@ CV231

OPT@ CV232

OPT@ CV152

OPT@ CV153

OPT@ CV154

OPT@ CV155

OPT@ CV156

OPT@ CV157

OPT@ CV158

OPT@ CV233

OPT@ CV234

OPT@ CV159

OPT@ CV160

OPT@ CV161

OPT@ CV162

OPT@ CV163

OPT@ CV164

OPT@ CV165
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CMD30 A15 BA2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_A Lower
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 29 of 56
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

MDA[0..63] <27,29>

CMDA[30..0] <27,29>
UV8 UV7
+VRAM_1.5VS
DQMA[7..0] <27,29>
+FBA_VREF1 M8 E3 MDA38 +FBA_VREF1 M8 E3 MDA58
VREFCA DQL0 MDA33 VREFCA DQL0 MDA59
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSA[7..0] <27,29>
1
F2 MDA39 F2 MDA57
RV68 CMDA9 DQL2 MDA35 CMDA9 DQL2 MDA61
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQSA#[7..0] <27,29> D
1.1K_0402_1% CMDA24 P7 H3 MDA36 Group4 CMDA24 P7 H3 MDA60 Group7
OPT@ CMDA10 A1 DQL4 MDA34 CMDA10 A1 DQL4 MDA62
P3 A2 DQL5 H8 P3 A2 DQL5 H8
CMDA13 N2 G2 MDA37 CMDA13 N2 G2 MDA56
2

+FBA_VREF1 CMDA26 A3 DQL6 MDA32 CMDA26 A3 DQL6 MDA63

P8 A4 DQL7 H7 P8 A4 DQL7 H7
CMDA22 P2 CMDA22 P2
A5 A5
1

1 CMDA21 R8 CMDA21 R8
RV69 CV166 CMDA5 A6 MDA42 CMDA5 A6 MDA51
1.1K_0402_1% 0.01U_0402_25V7K CMDA8
R2
T8
A7 DQU0 D7
C3 MDA45 CMDA8
R2
T8
A7 DQU0 D7
C3 MDA52 GB2-128
OPT@ OPT@ CMDA23 A8 DQU1 MDA40 CMDA23 A8 DQU1 MDA48
2 CMDA28
R3
L7
A9 DQU2 C8
C2 MDA46 CMDA28
R3
L7
A9 DQU2 C8
C2 MDA53 Mode E - Mirror Mode Mapping
2

CMDA4 A10/AP DQU3 MDA41 CMDA4 A10/AP DQU3 MDA49

R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6 DATA Bus
CMDA7 N7 A2 MDA47 CMDA7 N7 A2 MDA54
CMDA14 A12 DQU5 MDA43 CMDA14 A12 DQU5 MDA50 Address
T3 B8 T3 B8 0..31 32..63

.ru
CMDA12 A13 DQU6 MDA44 CMDA12 A13 DQU6 MDA55
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDA27 M7 CMDA27 M7 CMD3 CKE_L
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD8 A8 A8
CMDA29 M2 B2 CMDA29 M2 B2
CMDA6 BA0 VDD CMDA6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CLKA1 CMDA30 M3 G7 CMDA30 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD24 A2 A1

RV70 CLKA1 J7 N9 CLKA1 J7 N9
<27> CLKA1 CK VDD CK VDD
CLKA1# CLKA1#

m
160_0402_1% <27> CLKA1# K7 CK VDD R1 K7 CK VDD R1 CMD23 A11 A9
OPT@ CMDA16 K9 R9 CMDA16 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
C CMD26 A5 A4 C
1

CLKA1# CMDA19 K1 A1 CMDA19 K1 A1 CMD7 A0 A12

CMDA18 ODT/ODT0 VDDQ CMDA18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD15 CAS# CAS#
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDA25 L3 D2 CMDA25 L3 D2 CMD13 BA1 A3

ru
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD4 A9 A11
DQSA4 F3 H2 DQSA7 F3 H2
DQSA5 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD18 CS0#_H
CMDA19 CMD29 BA0 BA0
DQMA4 E7 A9 DQMA7 E7 A9
DQMA5 DML VSS DQMA6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15

Fo
E1 E1 CMDA16
VSS VSS
VSS G8 VSS G8 CMD6 A3 BA1
DQSA#4 G3 J2 DQSA#7 G3 J2
DQSA#5 DQSL VSS DQSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD17 CS1#_H

2
VSS M1 VSS M1
M9 M9 RV100 RV104 CMD19 ODT_H
VSS VSS 10K_0402_5% 10K_0402_5%
VSS P1 VSS P1
CMDA20 T2 P9 CMDA20 T2 P9 OPT@ OPT@ CMD22 A4 A5
RESET VSS RESET VSS
T1 T1

1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD12 A13 A14
CMD28 WE# A10
er
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
RV71 L1 B9 RV72 L1 B9 CMD10 A1 A2
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
OPT@ L9 D8 OPT@ L9 D8 CMD25 A10 WE#
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD9 A12 A0
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD1 CS1#_L
yb
VSSQ G9 VSSQ G9
CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
128MX16 H5TQ2G63BFR-11C 128MX16 H5TQ2G63BFR-11C
@ @ CMD5 A6 A7
+VRAM_1.5VS +VRAM_1.5VS CMD16 CKE_H
CMD20 RST RST
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C
OPT@ CV235

OPT@ CV236

OPT@ CV167

OPT@ CV168

OPT@ CV169

OPT@ CV170

OPT@ CV171

OPT@ CV172

OPT@ CV173

OPT@ CV237

OPT@ CV238

OPT@ CV174

OPT@ CV175

OPT@ CV176

OPT@ CV177

OPT@ CV178

OPT@ CV179

1 1
2 2
1 1
2 2
1 1
2 2
OPT@ CV180
CMD14 A14 A13
1 1 1 1 1 1 1 1 1 1 1 1
CMD30 A15 BA2
2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_A Upper
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 30 of 56
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits

D D

GB2-128
Mode E - Mirror Mode Mapping
DATA Bus
Address 0..31 32..63
CMD3 CKE_L
CMD8 A8 A8

.ru
CMD2 CS0#_L
CMD21 A7 A6
CMD24 A2 A1
CMD23 A11 A9
EVT:Del B ch VRAM CMD26 A5 A4

m
CMD7 A0 A12
C CMD15 CAS# CAS# C

CMD13 BA1 A3
CMD4 A9 A11
CMD18 CS0#_H

ru
CMD29 BA0 BA0
CMD27 BA2 A15
CMD6 A3 BA1
CMD17 CS1#_H

Fo
CMD19 ODT_H
CMD22 A4 A5
CMD12 A13 A14
CMD28 WE# A10
CMD10 A1 A2
CMD25 A10 WE#
B er CMD9
CMD1
CMD11
A12
CS1#_L
RAS#
A0

RAS#
B

CMD0 ODT_L
yb
CMD5 A6 A7
CMD16 CKE_H
CMD20 RST RST
CMD14 A14 A13
CMD30 A15 BA2
C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_C Lower
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 31 of 56
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

D D

GB2-128
Mode E - Mirror Mode Mapping
DATA Bus

.ru
Address 0..31 32..63
CMD3 CKE_L
CMD8 A8 A8
CMD2 CS0#_L
CMD21 A7 A6
CMD24 A2 A1
EVT:Del B ch VRAM

m
CMD23 A11 A9
C C
CMD26 A5 A4
CMD7 A0 A12
CMD15 CAS# CAS#

ru
CMD13 BA1 A3
CMD4 A9 A11
CMD18 CS0#_H
CMD29 BA0 BA0

Fo
CMD27 BA2 A15
CMD6 A3 BA1
CMD17 CS1#_H
CMD19 ODT_H
CMD22 A4 A5
CMD12 A13 A14
B er CMD28
CMD10
CMD25
CMD9
WE#
A1
A10
A12
A10
A2
WE#
A0
B

CMD1 CS1#_L
yb
CMD11 RAS# RAS#
CMD0 ODT_L
CMD5 A6 A7
CMD16 CKE_H
CMD20 RST RST
C

CMD14 A14 A13

CMD30 A15 BA2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_C Upper
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 32 of 56
5 4 3 2 1
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VS_DGPU
ROM_SO +3VS_DGPU XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM
ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]

2
RV87 RV85 RV86 STRAP2 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
45.3K_0402_1% 34.8K_0402_1% 15K_0402_1%
OPT@ @ @ STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
D D

1
STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]
<23> STRAP0 STRAP0
<23> STRAP1 STRAP1
STRAP2
<23> STRAP2
2
Note: RV89 = 5K for set N12P-GV ,ID=1050)

2
RV84 RV88 RV89
45.3K_0402_1%
@
34.8K_0402_1%
OPT@
4.99K_0402_1%
OPT@ ROM_SI net for VRAM strap
1

1
Resistor Values Pull-up to +3VS Pull-down to Gnd

.ru
5K 1000 0000
10K 1001 0001
15K 1010 0010
+3VS_DGPU 20K 1011 0011
25K 1100 0100

m
30K 1101 0101
2

C 35K 1110 0110 C

RV90 RV91 RV92
4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 45K 1111 0111
@ OPT@ OPT@
1

ru
<23> ROM_SI ROM_SI
<23> ROM_SO ROM_SO
ROM_SCLK
<23> ROM_SCLK SUB_VENDOR XCLK_417
2

0 No VBIOS ROM (Default) 0 277MHz (Default)

2

RV93

Fo
15K_0402_1% RV94 RV95
@ 4.99K_0402_1% 15K_0402_1% 1 BIOS ROM is present 1 Reserved
@ @
1

FB_0_BAR_SIZE USER Straps

X76 strap pin for VRAM vender and size
0 256MB (Default) User[3:0]

GPU Project

PAJ80(14")
VRAM size CH
512M(X4) CHA
Description
DDR3 Hynix 64Mx16 1.5V
er
Compal VRAM P/N
SA0000324C0
VRAM description
H5TQ1G63DFR-12C 800MHz
ROM_SI net setup
0010
PD or PU
(RV93)
PD 15K
R P/N
SD034150280(15K)
1

3GIO_PADCFG
Reserved 1000-1100 Customer defined

PEX_PLL_EN_TERM
B

512M(x4) CHA DDR3 Samsung 64Mx16 1.5V SA00004HS00 K4W1G1646G-BC12 800MHz 0011 PD 20K SD034200280(20K) 3GIO_PADCFG[3:0] 0 Disable (Default)
N12P-GV (29x29) 64bit
yb
(Layout 4pcs only) 1G(x4) CHA DDR3 Hynix 128Mx16 1.5V SA00003VS00 H5TQ2G63BFR-12C 800MHz 0110 PD 35K SD034348280(34.8K)
PAJ90(15.6") 0110 Notebook Default 1 Enable
1G(x4) CHA DDR3 Samsung 128Mx16 1.5V SA00003MQ40 K4W2G1646C-HC12 800MHz 0111 PD 45K SD034453280(45.3K)

SLOT_CLOCK_CFG
0 GPU and MCH don't share a common reference clock
C

1 GPU and MCH share a common reference clock (Default)

SMBUS_ALT_ADDR VGA_DEVICE
0 0x9E (Default) 0 3D Device
A A

1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_MSIC
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Sunday, April 10, 2011 Sheet 33 of 56
5 4 3 2 1
 5 4 3 2 1

PVT:Add L1 for ESD reuqest

LCD POWER CIRCUIT
+LCDVDD +3VS +LCDVDD Need closed to JLVDS1
+3VS +3VS +INVPWR_B+
B+
W=60mils

1
W=60mils L18
L1
1 1 1 FBMA-L11-201209-221LMA30T_0805

1
R521 1 C463 C464 C465 2 1 1 2
300_0603_5% R522 C462 L19
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z FBMA-L11-201209-221LMA30T_0805

6 2
2 2 2 2 1 1.2UH_1231AS-H-1R2N-P3_2.9A_30%
D 2 D

2
R523 1 1

3
Q16A 1K_0402_5% S Q17 C466 C467 SM010014520 3000ma
2N7002DW-T/R7_SOT363-6 2 2 1 2 AO3413L_SOT23-3 680P_0402_50V7K 68P_0402_50V8J 220ohm@100mhz
G
D 2 2 DCR 0.04
1

1
C468 +LCDVDD
0.047U_0402_16V7K W=60mils
2

3
1 1
C471
C469 0.1U_0402_16V4Z
5 Q16B 4.7U_0805_10V4Z
<16> PCH_ENVDD
2N7002DW-T/R7_SOT363-6 2 2
LCD/LED PANEL Connector

.ru
4
2

R319
100K_0402_5%
1

+3VS +LCDVDD

m
JLVDS1
1 1
2 2 D26
3 3
C FB1 C
<16> PCH_LCD_CLK 4 4 2
<16> PCH_LCD_DATA 5 5 1
6 FB2 3
6
<16> DPST_PWM 1 2 INVTPWM INVTPWM <56> Driver IC <16> PCH_TXOUT0+ 7 7
R532 0_0402_5% 8
<16> PCH_TXOUT0- 8 PJDLC05C_SOT23-3

ru
9 9
10 @
<16> PCH_TXOUT1+ 10
<16> PCH_TXOUT1- 11
11
12
12
1

<16> PCH_TXOUT2+ 13 D27

R536 13
<16> PCH_TXOUT2- 14
@ 14 FB3
10K_0402_5% 15 2
15
<16> PCH_TXCLK+ 16 1
16 FB4
<16> PCH_TXCLK- 17 3
2

17
18
18

Fo
FB1 19
<56> FB1 FB2 19 PJDLC05C_SOT23-3
<56> FB2 20
FB3 20 @
<56> FB3 21
FB4 21
<56> FB4 22
+3VS 22
+LG_VOUT 23
23
24
24
25
@ 25
26
26
1

R992 1 2 0_0402_5% +3VS 27

R540 USB20_CMOS_N3 27
28
4.7K_0402_5% USB20_CMOS_P3 28
29
D6 29
30
RB751V_SOD323 30
2

B
<43> BKOFF#
BKOFF# 1 2 DISPOFF# er DISPOFF# <56> Driver IC

@
31
32
33
34
35
GND
GND
GND
GND
GND
B
1

R542 R533 1 2 0_0402_5% STARC_111H30-000000-G4-R

10K_0402_5% CONN@
WCM2012F2SF-900T04_0805
2

USB20_CMOS_N3
yb
<17> USB20_N3 3 4
3 4

2 USB20_CMOS_P3
<17> USB20_P3 2 1 1
L51 DVT:<EMI>L51 @-->SMT
R534 1 2 0_0402_5%
@

FB1 C909@ 1 2 22P_0402_50V8J

C

USB20_CMOS_N3 @ 1 2 FB2 C910@ 1 2 22P_0402_50V8J

C483 22P_0402_50V8J
USB20_CMOS_P3 @ 1 2 FB3 C911@ 1 2 22P_0402_50V8J
C482 22P_0402_50V8J
FB4 C912@ 1 2 22P_0402_50V8J

D5
6 1 USB20_CMOS_P3
I/O4 I/O1

+3VS 5 2
REF2 REF1
A USB20_CMOS_N3 A
4 I/O3 I/O2 3
DVT:<EMI>D5 @-->SMT
PJUSB208H_SOT23-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 34 of 56
5 4 3 2 1
 5 4 3 2 1

+3VS

+5VS
D 12
CH491DPT_SOT23-3
HDMI Connector

1
2 1
R569
+HDMI_5V_OUT 1M_0402_5%
W=40mils

2
JHDMI1

2
HDMI_DETECT 19
+HDM I_5V HDMI_DETECT HP_DET
+5VS 2 1 1 2 <16> PC H_DPB_HPD 1 6 +HDMI_5V_OUT 18
F1 1.1A_6V_SMD1812P110TF +5V
17
D8 HDMI_SDATA DDC/CEC_GND
1 16
Q23A SDA

1
HDMI_SC LK 15
SCL

1
D 2N7002DW-T/R7_SOT363-6 D
CH491DPT_SOT23-3 C501 R566 14
0.1U_0402_16V4Z C903 Reserved
20K_0402_5% 13
2 220P_0402_25V8J HDMI_R_C K- CEC
12 20

2
@ CK- GND
11 21

2
HDMI_R_CK+ CK_shield GND
10 22
HDMI_R_D0- CK+ GND
9 23
D0- GND
8
HDMI_R_D0+ D0_shield
7
HDMI_R_D1- D0+
6
D1-
5
+3VS HDMI_R_D1+ D1_shield
4
+HDMI_5V_OUT HDMI_R_D2- D1+
3
D2-
2
HDMI_R_D2+ D2_shield
1
D2+
SUYIN_100042MR019S153ZL

2
C O NN@

.ru
D 13 D 14
RB751V_SOD323 RB751V_SOD323

1 1

1 1
R546 R545
2.2K_0402_5% 2.2K_0402_5%

2
DVT:<EMI>L20 L23 L24 L25 @-->SMT

2
<16> SDVO_SDATA SDVO_SDATA 1 6 HDMI_SDATA

Q93A SM070001310 400ma 90ohm@100mhz DCR 0.3

5 2N7002DW-T/R7_SOT363-6
@
SDVO_SC LK HDMI_SC LK HDMI_CLK+ R547 1 0_0402_5% HDMI_R_CK+

m
<16> SDVO_SCLK 4 3 2

Q93B 1 1 4 3
2N7002DW-T/R7_SOT363-6 4 3
C490 C491 WCM2012F2SF-900T04_0805
10P_0402_50V8J L20
C
2 2
10P_0402_50V8J Note: Reresve for RF 1
1 2
2 C
@ @
HDMI_C LK- R548 1 2 0_0402_5% HDMI_R_C K-
@

@
HDMI_TX0+ HDMI_R_D0+

ru
R549 1 2 0_0402_5%

4 3
4 3
WCM2012F2SF-900T04_0805
L23 1 2
1 2
HDMI_TX0- R550 1 2 0_0402_5% HDMI_R_D0-
@
C 497 2 1 0.1U_0402_16V7K HDMI_TX2+ HDMI_TX2+ R945 1 2 680_0402_5% @
<16> PCH_DPB_P2 C 496
<16> PCH_DPB_N2 2 1 0.1U_0402_16V7K HDMI_TX2- HDMI_TX2- R944 1 2 680_0402_5% HDMI_TX1+ R552 1 2 0_0402_5% HDMI_R_D1+

Fo
C 495 2 1 0.1U_0402_16V7K HDMI_TX1+ HDMI_TX1+ R947 1 2 680_0402_5% 4 3
<16> PCH_DPB_P1 C 494 4 3
<16> PCH_DPB_N1 2 1 0.1U_0402_16V7K HDMI_TX1- HDMI_TX1- R946 1 2 680_0402_5%
WCM2012F2SF-900T04_0805
C 493 1 0.1U_0402_16V7K HDMI_TX0+ HDMI_TX0+ R949 1 2 680_0402_5% L24
Lane Reversed on Page 16 <16> PCH_DPB_P0 C 492
2 1
1 2
2
<16> PCH_DPB_N0 2 1 0.1U_0402_16V7K HDMI_TX0- HDMI_TX0- R948 1 2 680_0402_5%
HDMI_TX1- R557 1 2 0_0402_5% HDMI_R_D1-
HDMI_CLK+ R951 1 2 680_0402_5% @
C 499 2 1 0.1U_0402_16V7K HDMI_CLK+ HDMI_CLK- R950 1 2 680_0402_5% @
<16> PCH_DPB_P3 C 498
<16> PCH_DPB_N3 2 1 0.1U_0402_16V7K HDMI_C LK- HDMI_TX2+ R560 1 2 0_0402_5% HDMI_R_D2+

4 3
4 3
WCM2012F2SF-900T04_0805

3
L25 1 2
1 2

er +3VS 5 Q23B
2N7002DW-T/R7_SOT363-6
HDMI_TX2- R563 1
@
2 0_0402_5% HDMI_R_D2-

4
B B
yb
C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 35 of 56
5 4 3 2 1
 A B C D E

CRT Connector +HDMI_5V_OUT

W=40mils

DVT:Del F2 and chnage D12 to P35

2
DVT:+CRT_VCC_-->+HDMI_5V_OUT
D10
D9 PJDLC05C_SOT23-3
DVT:Update L28~L33 footprint
PJDLC05C_SOT23-3
1 1

DVT:Add T7
PVT:<Memo>

1
JCRT1
L28 L29 6
0_0402_5% NBQ100505T-800Y_0402 T7 PAD 11
1 2 CRT_R_1 1 2 CRT_R_2 1
<16> PCH_CRT_R
L30 L31 7
0_0402_5% NBQ100505T-800Y_0402 12
1 2 CRT_G_1 1 2 CRT_G_2 2
<16> PCH_CRT_G
L32 L33 8
0_0402_5% NBQ100505T-800Y_0402 13
1 2 CRT_B_1 1 2 CRT_B_2 3
<16> PCH_CRT_B
9

.ru
2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
14 G 16
1

1
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 1 1 1 4 17
G
10
R570

R571

R572

C511

C512

C513

C514

C515

C516

C517

C518

C519
15
5
2 2 2 2 2 2 2 2 2
2

2 SUYIN_070546FR015S293ZR
CONN@
@ @ @
CRT_DET# <18>

PCH_CRT_DATA_R

2
m
PCH_CRT_CLK_R R574

100P_0402_50V8J
100K_0402_5%

68P_0402_50V8J

68P_0402_50V8J
1 1 1

C520
DVT:+CRT_VCC_-->+HDMI_5V_OUT

1
C524

C525
2 2

2 2 2
+HDMI_5V_OUT +HDMI_5V_OUT

ru
1 2 R573 2 1 10K_0402_5%
C521 0.1U_0402_16V4Z SM010012010 300ma 120ohm@100mhz DCR 0.4
U42
5

74AHCT1G125GW_SOT353-5 L34
MBC1608121YZF_0603
OE#
P

2 4 CRT_HSYNC_1 1 2 CRT_HSYNC_2 DVT:+CRT_VCC_-->+HDMI_5V_OUT

<16> PCH_CRT_HSYNC A Y
G

10P_0402_50V8J
1
3

C522
+HDMI_5V_OUT

Fo
DVT:+CRT_VCC_-->+HDMI_5V_OUT 2
1 2
C526 0.1U_0402_16V4Z U43
5

74AHCT1G125GW_SOT353-5 L35
MBC1608121YZF_0603
OE#
P

2 4 CRT_VSYNC_1 1 2 CRT_VSYNC_2
<16> PCH_CRT_VSYNC A Y
G

10P_0402_50V8J
1

C523
3

3
er +HDMI_5V_OUT
DVT:+CRT_VCC_-->+HDMI_5V_OUT 3

+3VS
yb
1

1
R575 R576
4.7K_0402_5% 4.7K_0402_5%
2

2
2

PCH_CRT_DATA 1 6 PCH_CRT_DATA_R
<16> PCH_CRT_DATA
5

Q25A
C

2N7002DW-T/R7_SOT363-6
<16> PCH_CRT_CLK PCH_CRT_CLK 4 3 PCH_CRT_CLK_R

Q25B
2N7002DW-T/R7_SOT363-6

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 36 of 56
A B C D E
 5 4 3 2 1

W=60mils W=60mils
+3VALW 1 @ 2 +LAN_IO

Layout note: Close to U44.12

Layout note: Close to U44.27

Layout note: Close to U44.39

Layout note: Close to U44.42

Layout note: Close to U44.47

Layout note: Close to U44.48

Layout note: Close to U44.3

Layout note: Close to U44.6

Layout note: Close to U44.9

Layout note: Close to U44.13

Layout note: Close to U44.29

Layout note: Close to U44.41

Layout note: Close to U44.45

R577 0_1206_5% +LAN_VDD

1.5A

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
3 1

D
1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
Q57 1 1 1 1 1 1 1

C538

C539

C540

C541

C542

C543

C544
AO3413L_SOT23-3 1 1 1 1 1 1

C532

C533

C534

C535

C536

C537
1

2
C531
2 2 2 2 2 2 2
2 2 2 2 2 2
2
D D

B+_BIAS

2
R578 +LAN_VDD
470K_0402_5% Note: +LAN_IO Rising time (10%~90%) >1mS and <100mS 1 2 +LAN_EVDD10
W=60mils W=60mils R581 0_0603_5%
1

0.1U_0402_16V7K

1U_0402_6.3V6K
EN_WOL
L36 +LAN_VDD 1 1

C548

C549
2.2UH +-5% NLC252018T-2R2J-N
1

2
D

0.1U_0603_25V7K
+LAN_SROUT1.05 1 2

.ru
4.7U_0603_6.3V6K

0.1U_0402_16V7K
2 R579 1
<43> WOL_EN 2 2

C545
G 1.5M_0402_5% 1 2

C552

C553
S Q88
3

2N7002E-T1-GE3_SOT23-3

1
2
2 1

Layout note: All components close to U44.36 within 200mils +LAN_IO

1 2 +LAN_VDDREG
R580 0_0603_5%

4.7U_0603_6.3V6K

0.1U_0402_16V7K
1 1

C546

C547
U44
C C
C550 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 22 31 2 2
<14> PCIE_PRX_DTX_P1 HSOP LED3/EEDO
LED1/EESK 37
C551 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 23 40
<14> PCIE_PRX_DTX_N1 HSON LED0

ru
17 30 R582 1 2 10K_0402_5%
<14> PCIE_PTX_C_DRX_P1 HSIP EECS/SCL
18 32 R583 1 2 10K_0402_5%
<14> PCIE_PTX_C_DRX_N1 HSIN EEDI/SDA

1 2 LAN_CLKREQ#_R 16 1 LAN_MDIP0
<14> LAN_CLKREQ# CLKREQB MDIP0 LAN_MDIN0
R895 0_0402_5% 2 DVT:Add R590 R957
MDIN0 LAN_MDIP1
<5,17,22,41,43> PLT_RST# 25 4
PERSTB MDIP1 LAN_MDIN1 +LAN_IO
5
MDIN1 LAN_MDIP2
<14> CLK_PCIE_LAN 19 7
REFCLK_P NC/MDIP2 LAN_MDIN2
<14> CLK_PCIE_LAN# 20 8
REFCLK_N NC/MDIN2

Fo
10 LAN_MDIP3
NC/MDIP3 LAN_MDIN3 @
DVT:PC_PME# PU on P43 XTLI NC/MDIN3
11 <14> CLK_FKEX2 1 2
@ 43 R957 22_0402_5%
CKXTAL1 LAN_CLKREQ#_R @
+LAN_IO 1 2 1 2
R2680 10K_0402_5% XTLO 44 13 R2677 10K_0402_5%
CKXTAL2 DVDD10 +LAN_VDD
1 2 29 1 2 2 1 XTLI
<43> EC_PME# DVDD10
R584 0_0402_5% 41 C554 27P_0402_50V8J R590 0_0402_5%
@ LANWAKEB DVDD10
<15,41> PCH_PCIE_WAKE# 1 2 28
R585 0_0402_5% LANWAKEB

1
1 2 ISOLATEB 26 27
+3VS ISOLATEB DVDD33 25MHZ_20PF_7A25000012
R586 1K_0402_5% 39
DVDD33 Y5
DVT:Update Y5 source
14 12 +LAN_IO

2
NC/SMBCLK AVDD33
2

B
R587
15K_0402_5%

+LAN_IO R2678 2
2 @
+LAN_IO
1
1 0_0402_5%
R589
1
R588 1
2
2 10K_0402_5%
1K_0402_5%
er 15
38

33
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
42
47
48 C555
1 2
27P_0402_50V8J
XTLO

B
1

R591 0_0402_5% ENSWREG +LAN_EVDD10

21
Note: 3.3V - Enable switching regulator EVDD10
34
0V - Disable switching regulator +LAN_VDDREG VDDREG
35 3 +LAN_VDD
VDDREG AVDD10
6
AVDD10
9
AVDD10
yb
1 2 46 45
R592 2.49K_0402_1% RSET AVDD10
24 36 +LAN_SROUT1.05
GND REGOUT
49
PGND JLAN1 conn@
RJ45_TX0+ 1
RTL8111E-VL-CGT_QFN48_6X6 PR1+
9
RJ45_TX0- LED_YELLOW_A1
2
PR1-
10
RJ45_RX1+ LED_YELLOW_A2
L12 3
PR2+
1 2 RJ45_TX2+ 4
PR3+
C

11
TS1 100UH_SSC0301101MCF_0.18A_20% RJ45_TX2- LED_GREEN_B1
5
PR3-
12
+V_DAC RJ45_RX1- LED_GREEN_B2
1 24 1 2 6
LAN_MDIN3 R995 1 LAN_MDIN3_R TCT1 MCT1 RJ45_TX3- PR2-
2 0_0402_5% 2 23 R594 75_0402_5% D15
LAN_MDIP3 R996 1 LAN_MDIP3_R TD1+ MX1+ RJ45_TX3+ RJ45_TX3+ LAN_GND
2 0_0402_5% 3
TD1- MX1-
22 PJDLC05C_SOT23-3 7
PR4+ GND
13
2 14
+V_DAC RJ45_TX3- GND
4 21 1 2 1 8
LAN_MDIN2 R997 1 LAN_MDIN2_R TCT2 MCT2 RJ45_TX2- PR4-
2 0_0402_5% 5 20 R595 75_0402_5% 3
LAN_MDIP2 R998 1 LAN_MDIP2_R TD2+ MX2+ RJ45_TX2+
2 0_0402_5% 6 19 SANTA_130451-F
TD2- MX2-
+V_DAC 7 18 1 2
LAN_MDIN1 R999 1 LAN_MDIN1_R TCT3 MCT3 RJ45_RX1- LAN_GND
2 0_0402_5% 8
TD3+ MX3+
17 R597 75_0402_5% 1 2
LAN_MDIP1 R1000 1 2 0_0402_5% LAN_MDIP1_R 9 16 RJ45_RX1+ C2600 0.1U_0402_16V7K
A TD3- MX3- A
1 2
+V_DAC 10 15 1 2 C2601 0.1U_0402_16V7K
LAN_MDIN0 R1001 1 LAN_MDIN0_R 11 TCT4 MCT4 RJ45_TX0-
2 0_0402_5% TD4+ MX4+ 14 R598 75_0402_5%
LAN_MDIP0 R1002 1 2 0_0402_5% LAN_MDIP0_R 12 13 RJ45_TX0+ 2
TD4- MX4- C557
1000P_1206_2KV7K

TAIMAG _IH-160 LAN_24P 1

2
C556
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title
1
0.01U_0402_16V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Realtek RTL8111E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-7401P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 37 of 56
5 4 3 2 1
 A B C D E

1 2
+5VS RA54 0_0603_5%
UA2 @ +AVDD
1 IN 40mil 600 mA 0.1U_0402_16V7K RA2

4.7U_0805_10V4Z
5 +5VS_PVDD 2 1 0.1U_0402_16V7K +5VS
OUT 0_0603_5%
2 GND 1 1 1 1 1

CA75
1 @ 2 3 SHDN CA61 CA57 CA56 CA44 CA43
@ RA55 10K_0402_5% BP 4 10U_0805_10V6K 10U_0805_10V6K
1
0.1U_0402_16V7K 2 2 2 2 2

0.01U_0402_16V7K
APL5151-475BC-TRG_SOT23-5
CA3
2 @
2

CA77
10U_0805_10V6K
1 @ 1
1 Pre MP:CA19,CA20,CA25,CA26-->SMT

+3VS_DVDD

+3VS 1 2 0.1U_0402_16V7K 35 mA
+AVDD
Speaker Connector
RA1 FBMH1608HM601-T 1 1 1
68 mA 10U_0805_10V6K
CA8 CA7 CA1
10U_0805_10V6K 0.1U_0402_16V7K RA13
2 2 2 SPKL+ 2 1 SPK_L1

39

46

25

38
1 1 1 SPK_L1 <39>

9
UA1 CA4 CA5 0_0603_5% 1

.ru
CA6 0.1U_0402_16V7K

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
CA19
2 2 2 680P_0402_50V7K
2 2
0.1U_0402_16V7K CA24
1 1U_0402_6.3V4Z
23 40 SPKL+ @
LINE1_L SPK_OUT_L+ SPKL- CA20 1
24 LINE1_R SPK_OUT_L- 41
RA14 680P_0402_50V7K
14 45 SPKR+ SPKL- 2 1 2 SPK_L2
LINE2_L SPK_OUT_R+ SPKR- SPK_L2 <39>
15 44 0_0603_5%
4.7U_0805_10V6K CA21 LINE2_R SPK_OUT_R- RA15
MIC1_LINE1_R_L 2 1 MIC_L 21 32 SPKR+ 2 1 SPK_R1
<39> MIC1_LINE1_R_L MIC1_L HP_OUT_L HP_L <39> SPK_R1 <39>
Ext. Mic 22 33 0_0603_5% 1
MIC1_R HP_OUT_R HP_R <39>

m
MIC1_LINE1_R_R 2 1 MIC_R
<39> MIC1_LINE1_R_R
16 CA25
4.7U_0805_10V6K CA22 MIC2_L 680P_0402_50V7K
17 MIC2_R 2
10 HDA_SYNC_AUDIO 2 CA27
2 SYNC HDA_SYNC_AUDIO <13> 2
1 1U_0402_6.3V4Z
DMIC_DATA 2 6 HDA_BITCLK_AUDIO @
<42> DMIC_DATA GPIO0/DMIC_DATA BCLK HDA_BITCLK_AUDIO <13> 1
CA26
DMIC_CLK_R 3 RA16 680P_0402_50V7K
GPIO1/DMIC_CLK HDA_SDOUT_AUDIO SPKR- 2 SPK_R2
SDATA_OUT 5 HDA_SDOUT_AUDIO <13> 2 1 SPK_R2 <39>

ru
0_0603_5%
EC_MUTE# 4 8 HDA_SDIN0_R 2 1
<43> EC_MUTE# PD# SDATA_IN HDA_SDIN0 <13>
RA6 33_0402_5%

HDA_RST_AUDIO# 11 47 2 1
<13> HDA_RST_AUDIO# RESET# EAPD RA53 0_0402_5%
EAPD <43> Beep sound
EC Beep
1

48
MONO_IN SPDIFO RA7
1 2 12
PCBEEP <43> BEEP# 1 2
RA40 CA11 CA12 100P_0402_50V8J 20 47K_0402_5%
100K_0402_5% 0.01U_0402_25V7K MONO_OUT

Fo
@ @ SENSE_A 13
2

SENSE A
For EMI 29
18
SENSE B
MIC2_VREFO
CA23
PCI Beep RA8
CA13
30 +MIC1_VREFO_R 10U_0805_10V6K 1 2 1 2 MONO_IN
MIC1_VREFO_R <13> HDA_SPKR
1 2 36 28 1 2 47K_0402_5%
CA15 CBP LDO_CAP
2.2U_0603_6.3V6K AC_VREF 0.1U_0402_16V7K
35 27
CBN VREF
31 19 AC_JDREF 2 RA9 1 20K_0402_1% EVT:CA16 SMT-->@
+MIC1_VREFO_L MIC1_VREFO_L JDREF
1

1
EC_MUTE# 43 34 CPVEE 1 2 @ 1
PVSS2 CPVEE CA14 2.2U_0603_6.3V6K CA17 CA16 RA12
42
PVSS1 0.1U_0402_16V7K 2.2U_0603_6.3V6K CA18
49 26

2
DVSS2 AVSS1
1

2 4.7K_0402_5%
RA45
7
DVSS1 er AVSS2
37
2
100P_0402_50V8J

2
4.7K_0402_5% ALC259-VB5-GR_QFN48_7X7
3
place close to chip 3
DGND AGND
2

EC control EC_MUTE# behavior: High-state / low-state

For EMI HDA_BITCLK_AUDIO 1 2 CA62 1 2
yb
RA42 22_0402_5%
RA47 27P_0402_50V8J
DMIC_CLK_R @ CA48 1 2 0.1U_0603_50V7K
<42> DMIC_CLK
FBMA-10-100505-301T
@ CA49 1 2 0.1U_0603_50V7K
1 Pre MP:RA42-->SMT and CA62-->SMT
CA74 @ CA50 1 2 0.1U_0603_50V7K
27P_0402_50V8J
@ 1 2
2 RA18 FBMH1608HM601-T
C

place close to chip

Sense Pin Impedance Codec Signals Function
<39> MIC_SENSE MIC_SENSE 2 1 SENSE_A
39.2K PORT-I (PIN 32, 33) Headphone out RA10 20K_0402_1%

20K PORT-B (PIN 21, 22) Ext. MIC

SENSE A
<39> NBA_PLUG
10K PORT-C (PIN 23, 24) RA21 39.2K_0402_1%
4 4

5.1K (PIN 48)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/04/28 Deciphered Date 2011/04/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio ALC259
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-7401P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 38 of 56
A B C D E
 5 4 3 2 1

< SPK connector >

DA7
3 JSPK1
1 E&T_3806-F04N-02R
2
6 GND2
D PJDLC05C_SOT23-3 5 GND1 D

SPK_R1 4
<38> SPK_R1 4
SPK_R2 3
<38> SPK_R2 3
SPK_L1 2
<38> SPK_L1 2
SPK_L2 1
<38> SPK_L2 1
DA6
3 CONN@
1
2

PJDLC05C_SOT23-3

.ru
m
RA46 2 1 +MIC1_VREFO_R
1K_0402_5% RA36 2.2K_0402_5%
C
<38> MIC1_LINE1_R_R
MIC1_LINE1_R_R 2 1 MIC1_R < JMIC1 Jack> C

MIC1_LINE1_R_L 2 1 MIC1_L
<38> MIC1_LINE1_R_L
1K_0402_5%

ru
RA35 2 1 CONN@
+MIC1_VREFO_L SINGA_2SJ2285-112252_6P-T
RA29 2.2K_0402_5%

4 SHLD1

MIC_SENSE 6
<38> MIC_SENSE
5

Fo
MIC1_R LA2 1 2 FBM-11-160808-601-T_0603 M IC1_R_1 2

MIC1_L LA1 1 2 FBM-11-160808-601-T_0603 MIC1_L_1 1

2
DA8 JMIC1
1 1 PJDLC05C_SOT23-3 1
CA68 CA69 CA63
33P_0402_50V8J 33P_0402_50V8J 0.1U_0402_16V4Z
2 2 2
@ 1

er CA64

1
0.1U_0402_16V4Z
2

B B

<JHP2 Head phone >

yb
CONN@
SINGA_2SJ2285-112252_6P-T

4 SHLD1

<38> NBA_PLUG NBA_PLUG 6

5
C

HP_R RA52 1 2 82_0402_1% HP_R_R LA4 1 2 FBM-11-160808-601-T_0603 PR 2

<38> HP_R
HP_L RA51 1 2 82_0402_1% HP_L_R LA3 1 2 FBM-11-160808-601-T_0603 PL 1
<38> HP_L
3

2
DA9 JHP2
1 1 PJDLC05C_SOT23-3
@
0.1U_0402_16V4Z CA70 CA71
33P_0402_50V8J 33P_0402_50V8J 1
2 2
2 1
CA66
CA67 0.1U_0402_16V7K

1
2 ESD request
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/07 Deciphered Date 2012/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPK/Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7401P
Date: Monday, April 11, 2011 Sheet 39 of 56
5 4 3 2 1
 5 4 3 2 1

SATA HDD1 Connector

D D

JHDD1
+5VS 1 1
2

.ru
2
3 3
4 4
SATA_PTX_DRX_P0 C612 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 5
<13> SATA_PTX_DRX_P0 5 +5VS
<13> SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C613 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 6 6
7 7
SATA_PRX_DTX_N0 C614 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 8 100mils
<13> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C611 1 SATA_PRX_C_DTX_P0 8
2 0.01U_0402_16V7K 9 9 G11 11
<13> SATA_PRX_DTX_P0
10 10 G12 12

10U_0805_10V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K
ACES_87212-10G0 1 1 1 1

C616

C617

C618

C619
CONN@

m
2 2 2 2

C C

ru
SATA@ C922 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P2
<13> SATA_PTX_DRX_P1

Fo
SATA@ C923 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N2
<13> SATA_PTX_DRX_N1 <14" SATA ODD Connector>
SATA@ C924 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N2
+5VS_ODD <13> SATA_PRX_DTX_N1
+5VS SATA@ C925 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P2
<13> SATA_PRX_DTX_P1
JODD1 CONN@
B+_BIAS 1 @ 2 1
R677 0_0805_5% SATA_PTX_C_DRX_P2 GND
<13> SATA_PTX_DRX_P2 1 2 2
C621 1 SATA_PTX_C_DRX_N2 TX+
<13> SATA_PTX_DRX_N2 2 0.01U_0402_16V7K 3
TX-
D

6 C620 0.01U_0402_16V7K 4
S

GND
2

1U_0402_6.3V6K

5 4 1 2 SATA_PRX_C_DTX_N2 5
<13> SATA_PRX_DTX_N2 SATA_PRX_C_DTX_P2 RX-
R678 1 2 C622 1 2 0.01U_0402_16V7K 6
<13> SATA_PRX_DTX_P2 RX+
C624

470K_0402_5% 1 Q30 C623 0.01U_0402_16V7K 7

SI3456DDV-T1-GE3_TSOP6 GND
er
G

<13> ODD_DETECT#_R
1

2 1 2 ODD_DETECT#_R 8
<18> ODD_DETECT# DP
R679 0_0402_5% +5VS_ODD 9
B ODD_EN 5V B
10
ODD_DA#_R 5V
<17> ODD_DA# 1 2 11 14
R680 0_0402_5% MD GND
12 15
GND GND
3

2
1.5M_0402_5%

0.1U_0402_16V4Z

13
GND
1
R681

C629

yb
5 Q31B SANTA_202801-1_13P
<18> ODD_EN#
2N7002DW-T/R7_SOT363-6
1

2
4

Q31A on P41
C

+5VS_ODD
80mils

1000P_0402_50V7K
10U_0805_10V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z
1 1 1 1

C625

C626

C627

C628
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 40 of 56
5 4 3 2 1
 A B C D E

Mini Card Power Rating

Wireless LAN 60mil
+3VS_WLAN +1.5VS +1.5VS_WLAN
60mil Power Primary Power (mA) Auxiliary Power (mA)
1 2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
RM4 0_0603_5% Peak Normal Normal

CM3

CM5

CM6
1 1 1 1 1 1 +3VS 1000 750

CM2

CM4

CM7
+3V 330 250 250 (wake enable)
2 2 2 2 2 2
+1.5VS 500 375 5 (Not wake enable)

1 1
+1.5VS_WLAN +3VS_WLAN

JMIN1 conn@
1 @ 2 1 2 +3VS_WLAN
<15,37> PCH_PCIE_WAKE# 1 2
RM5 0_0402_5% T89 PAD 3 4
BT_CTRL 3 4
5 6
5 6 LPC_FRAME#
<14> MINI1_CLKREQ# 7 8 LPC_FRAME# <13,43>
7 8

1
9 10 LPC_AD3
9 10 LPC_AD3 <13,43>
11 12 LPC_AD2 RM12
<14> CLK_PCIE_MINI1# 11 12 LPC_AD1 LPC_AD2 <13,43>
13 14 10K_0402_5%
<14> CLK_PCIE_MINI1 13 14 LPC_AD0 LPC_AD1 <13,43>
15 15 16 16 LPC_AD0 <13,43>
PLT_RST# 17 18 RM7 1 2 0_0402_5%
<5,17,22,37,43> PLT_RST# PCH_WL_OFF# <17> DM1

2
CLK_PCI_DEBUG 17 18 RM8 1 @
<17> CLK_PCI_DEBUG 19 20 2 0_0402_5% WL_OFF# <43>
19 20
21 22 2 1

.ru
21 22 PLT_RST_BUF# <17>
<14> PCIE_PRX_DTX_N2 23 23 24 24
<14> PCIE_PRX_DTX_P2 25 26 CH751H-40PT_SOD323-2
25 26
27 27 28 28
29 30 D_CK_SCLK <11,12,14> RM11 1 @ 2 0_0402_5%
29 30
<14> PCIE_PTX_C_DRX_N2 31 31 32 32 D_CK_SDATA <11,12,14>
<14> PCIE_PTX_C_DRX_P2 33 33 34 34
35 35 36 36 USB20_N4 <17>
37 37 38 38 USB20_P4 <17>
+3VS_WLAN 39 39 40 40
41 42 RM9 1 @ 2 0_0402_5%
41 42 MINI1_LED#
43 43 44 44
45 45 46 46
47 47 48 48

m 1
BT_CTRL E51TXD_P80DATA 49 50
<43> E51TXD_P80DATA E51RXD_P80CLK 49 50
51 52 RM10
<43> E51RXD_P80CLK 51 52
6

100K_0402_5%
53 GND1 GND2 54 (9~16mA)

1
2 Q31A 2

2
2 BT_CTRL 2 1 E51RXD_P80CLK MOLEX_67910-5700
<18> BT_ON#
1K_0402_5% RM6
2N7002DW-T/R7_SOT363-6 RM13 100K_0402_5% +3VS_WLAN
1

ru
Q31A on P41

+3VS +3VS
CLK_PCI_DEBUG 1 2 1 2

Fo
R955 10_0402_5% C908
@ 12P_0402_50V8J
2

@ 2
RM2 CM1

1
100K_0402_5% 0.1U_0402_16V7K
RM1 @

3
RM3 1 S QM1 0_0805_5%
1

<43> WLAN_PWR_EN# 1 2 WLAN_PWR_EN#_R 2 AO3413L_SOT23-3

47K_0402_5% G

2
D

1
3
er +3VS_WLAN

3
yb
C

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD WLAN & WWAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 41 of 56
A B C D E
 A B C D E

JPCR1
+3VS 1 1
2 2
3
USB20_N10 3
<17> USB20_N10 4
+5VALW USB20_P10 4
<17> USB20_P10 5
1 5 1
6
6
7
7
8
+5VALW 8
9
9
10
10
11
USB20_N0 11
DVT:Add R560 and update JPCR1 pin18 net <17> USB20_N0 12
12

2
USB20_P0 13
<17> USB20_P0 13
DVT:Update USB_OC1#-->USB_OC0# R960 14
USB20_N1 14
100K_0402_5% <17> USB20_N1 15
USB20_P1 15
<17> USB20_P1 16
16
17

1
USB_EN# 17
<43> USB_EN# 18 18
R993 1 2 0_0402_5% 19
<17,43> USB_OC0# 19
20

.ru
DMIC_CLK 20
PVT:Add R993 <38> DMIC_CLK DMIC_DATA
21 21
22 22
<38> DMIC_DATA

23 GND1
24 GND2
ACES_87213-2200G

CONN@

m
DMIC_CLK CA72 1 2 33P_0402_50V8J

@
2 DMIC_DATA 2
1 2
CA73 10P_0402_50V8J

Layout note: Close to JMIC2

ru
Pre MP:Add C923 C924

Fo
+5VALW +USB_VCCB 150U_B2_6.3VM_R35M

10U_0805_10V4Z

1000P_0402_50V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
1
0.1U_0402_16V4Z

1 1 1 1
C667

C2543

C669
+
1
C2507

C927

C928
2 2 2 2 2
2
+USB_VCCB

3
PVT:Update net USB_CHARGE_EN#-->USB_CHARGE_EN

<17,43> USB_OC1#

<PCH> <17>
<17>
R994 1

USB20_N2
USB20_P2
2 0_0402_5%
USB20_N2
USB20_P2
1

13

2
3
U2415
IN

FAULT#

DM_OUT DM_IN
DP_OUT DP_IN
OUT

NC
12

11
10
er U2D_DN2
U2D_DP2
<CONN>
R716
2 1
@

0_0402_5%
WCM2012F2S-900T04_0805
USB20_N2_R
USB20_P2_R
1
2
3
4
JUSB1
VCC
D-
D+
GND
3

R2600 1 2 0_0402_5% 4 15 Check footprint

ILIM_SEL ILIM1 USB20_N2_R
yb
<43> USB_CHARGE_EN 5 16 2 1 4 3 5
EN ILIM0 R2498 19.1K_0402_1% U2D_DN2 4 3 GND1
6
U2D_DP2 GND2
<43> USB_CTL1 6 7
CTL1 USB20_P2_R GND3
<43> USB_CTL2 7 14 1 2 8
CTL2 GND 1 2 GND4
<43> USB_CTL3 8 17
CTL3 GPAD L48 ACON_UARBG-4K1926_4P
TPS2540RTER_QFN16_3X3 2 1 CONN@
<BOM Structure> R717 0_0402_5%
@

PVT:Remove R2664 R2499 R2500 R2501 for DFX issue

C

DVT:<EMI>L48 D20 @-->SMT

D20
6 3 USB20_P2_R
CH3 CH2

+USB_VCCB 5 2
Vp Vn

4 USB20_N2_R 4
4 CH4 CH1 1

PJUSB208H_SOT23-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Combo Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 42 of 56
A B C D E
 5 4 3 2 1

PCH_PWR_EN R961 1 2 0_0402_5% PCH_PWR_EN_R +3VALW_EC

<46> PCH_PWR_EN EC_PME# R962 1 9012@ 2 0_0402_5% KB930 KB9012
<37> EC_PME# EC_MUTE# @
2 1
R720 10K_0402_5%
ON/OFF R963 1 2 0_0402_5% ON /OFF_R +3VLP PWR_LED#
<44> ON/OFF EAPD
+ 3VALW +3VLP + 3VALW +3VLP 1 2
R964 1 9012@ 2 0_0402_5% R943 @ R2650 10K_0402_5%
<38> EAPD 0_0805_5% EC_PME#
+3VALW_EC
R718 SMT @ SMT @ R723
2 1
10K_0402_5%
1 2
ENBKL R965 1 9012@ 2 0_0402_5% ENBKL_9012
<16> ENBKL +3VALW C679 PWR_BTN_LED#
R718 L49 R943 @ SMT @ SMT 2 @ 1
0_0805_5% FBMA-L11-160808-800LMT_0603 0.1U_0402_16V4Z +3VLP R1005 10K_0402_5%
H_PROCHOT#_EC R979 1 2 0_0402_5% H_PROCHOT#_EC_R 1 2 +3VALW_EC 1 2 +EC_VCCA 1 2 ECAGND

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K
PCH_PWROK R966 1 9012@ 2 0_0402_5% R985 SMT SMT @ SMT +5VS
1 1 1 1 2 2 R985 R986

C673

C674

C675

C676

C677

C678
1 2 1 2
D BATT_LOW_LED# R980 1 BATT_LOW_LED#_R TP_CLK D
<44> BATT_LOW_LED# 2 0_0402_5% R986 @ @ SMT @ 1 2
0_0402_5% 0_0402_5% R724 4.7K_0402_5%
PWR_LED# R967 1 9012@ 2 0_0402_5% 2 2 2 2 1 1 @ TP_DATA 1 2
R725 4.7K_0402_5%
R981 1 2 0_0402_5% PWR_LED#_R +3VS
<44> PWR_LED#

111
125
22
33
96

67
U64

9
BATT_LOW_LED# R982 1 9012@ 2 0_0402_5% GFX_CORE_PWRGD 1 2
R727 10K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
H_PROCHOT#_ECR968 1 9012@ 2 0_0402_5% H_PROCHOT#_EC_R_2
DVT:Add WLAN_PWR_EN# PCH_PWROK 2 1
R928 10K_0402_5%
GATEA20 1 21 WLAN_PWR_EN# VR_ON 1 2
PM_SLP_S4# PM_SLP_S4#_R <18> GATEA20 EC_KBRST# GATEA20/GPIO00 PWM0/GPIO0F BEEP# WLAN_PWR_EN# <41>
R969 1 2 0_0402_5% 2 23 R931 10K_0402_5%
<15> PM_SLP_S4# EC_ACIN <18> EC_KBRST# SERIRQ KBRST#/GPIO01 BEEP#/PWM1/GPIO10 PCH_DPWROK BEEP# <38> PCH_APWROK
R970 1 9012@ 2 0_0402_5%
<13> SERIRQ
3 SERIRQ# PWM Output FANPWM0/GPIO12 26 PCH_DPWROK <15> 1 2
LPC_FRAME# 4 27 ACOFF R930 10K_0402_5%

.ru
ENBKL ENBKL_R <13,41> LPC_FRAME# LPC_AD3 LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF <48> PCH_DPWROK
R971 1 2 0_0402_5% 5 1 2
EC_ON <13,41> LPC_AD3 LPC_AD2 LPC_AD3/LAD3
R972 1 9012@ 2 0_0402_5%
<13,41> LPC_AD2 7 LPC_AD2/LAD2
C682 2 1 100P_0402_50V8J ECAGND R929 @ 10K_0402_5%
LPC_AD1 8 63 BATT_TEMP PLT_RST# 1 2
<13,41> LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMP <55>
EAPD R973 1 2 0_0402_5% EAPD_R LPC_AD0 10 64 T93 PAD R927 100K_0402_5%
ON/OFF <13,41> LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39 ADP_I
R974 1 9012@ 2 0_0402_5% LPC & MISC ADP_I/AD2/GPI3A 65 ADP_I <48,55>
CLK_PCI_LPC 12 66
EC_PME# EC_PME#_R <17> CLK_PCI_LPC PLT_RST# CLK_PCI_EC/PCICLK AD3/GPI3B
R975 1 2 0_0402_5% <5,17,22,37,41> PLT_RST# 13 PCIRST#/GPIO05 AD Input AD4/GPI42 75
LID_SW# R976 1 9012@ 2 0_0402_5% EC_RST# 37 76 IMON_R R726 2 1 0_0402_5%
<44> LID_SW# EC_SCI# EC_RST#/ECRST# AD5/GPI43 IMVP_IMON <54> +3VALW_EC
<18> EC_SCI# 20 EC_SCI#/GPIO0E
EC_ACIN R977 1 2 0_0402_5% EC_ACIN_R 38
PM_SLP_S4# R978 1 9012@ 2 0_0402_5% <42> USB_CHARGE_EN CLKRUN#/GPIO1D T95 PAD R733
DAC_BRIG/DA0/GPO3C 68 2 1 200K_0402_5%
PVT:Update net name USB_CHARGE_EN 70 EN_DFAN1
EN_DFAN1/DA1/GPO3D IR EF EN_DFAN1 <45>
DA Output IREF/DA2/GPO3E 71 IREF <48>

m
KSI0 55 72 CHGVADJ 2 1
KSI0/GPIO30 DA3/GPO3F CHGVADJ <48> ACIN <15,22,44,46,48>
2 1 R983 1 2 0_0402_5% EC_PECI_R KSI1 56 D22
<5,18> H_PECI KSI1/GPIO31
R743 KSI2 57 DVT:Add USB_EN# CH751H-40PT_SOD323-2
43_0402_1% PECI_KB9012 R984 1 9012@ 2 0_0402_5% PECI_KB9012_R KSI3 KSI2/GPIO32 EC_MUTE# EC_ACIN C684
58 83 2 1 100P_0402_50V8J
C KSI4 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN# EC_MUTE# <38> C
59 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 84 USB_EN# <42>
KSI5 60 85 USB_CTL1
KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C USB_CTL1 <42>
KSI6 61 PS2 Interface 86 H_PROCHOT#_EC_R DVT:Add USB_CTL1
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK <44>
KSO0 39 88 TP_DATA
GFX_CORE_PWRGD GFX_CORE_PWRGD_R KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <44> +3VALW_EC

ru
R989 1 2 0_0402_5% 40
<54> GFX_CORE_PWRGD PCH_PWR_EN KSO2 KSO1/GPIO21
R990 1 9012@ 2 0_0402_5% 41 PVT:Fine tune for KB9012
KSO3 KSO2/GPIO22 GFX_CORE_PWRGD_R LID_SW#
42 97 1 2
KSO4 KSO3/GPIO23 SDICS#/GPXIOA00 WOL_EN R2653 100K_0402_5%
PVT:Fine tune for KB9012 KSO5
43
KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01
98
HDA_SDO WOL_EN <37>
KSO5/GPIO25 Int. K/B
44 99 HDA_SDO <13>
KSO6 ME_EN/SDIMOSI/GPXIOA02 LID_SW#
45 109
KSI[0..7] KSO7 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00
<44> KSI[0..7] 46
KSO7/GPIO27 SPI Device I/F
KSO8 47
@ C680 @ R719 KSO[0..17] KSO9 KSO8/GPIO28 FRD#_R R736 0_0402_5% FR D# R740
<44> KSO[0..17] 48 119 1 2
22P_0402_50V8J 33_0402_5% KSO10 KSO9/GPIO29 SPIDI/MISO FWR#_R R737 33_0402_5% FWR# 0_0402_5%
49 120 1 2
KSO10/GPIO2A SPIDO/MOSI

Fo
2 1 2 1 CLK_PCI_LPC KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK_R R738 1 2 33_0402_5% SPI_CLK VR_HOT# 2 1 H_PROCHOT# <5,55>
KSO12 KSO11/GPIO2B FSEL#_R <54> VR_HOT#
51 128 R739 1 2 33_0402_5% FSEL#
KSO12/GPIO2C SPICS#

3
KSO13 52
R721 2 EC_RST# KSO14 KSO13/GPIO2D
+3VALW_EC 1 47K_0402_5% 53
KSO14/GPIO2E
KSO15 54 73 ENBKL_9012
C681 2 0.1U_0402_16V4Z KSO16 KSO15/GPIO2F GPIO40 EC_PECI_R H_PROCHOT#_EC 2N7002DW-T/R7_SOT363-6
1 81
KSO16/GPIO48 H_PECI/GPIO41
74 5
KSO17 82 GPIO 89 FSTCHG Q34B
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG <48>
90 USB_CTL2 Q34B on P46
USB_CTL2 <42>

4
BATT_CHG_LED#/GPIO52 USB_CTL3
+3VALW_EC EC_SMB_CK1 CAPS_LED#/GPIO53
91
BATT_LOW_LED#_R USB_CTL3 <42> DVT:Add USB_CTL2 and USB_CTL3
<55> EC_SMB_CK1 77 92
Note: ENE Recommand EC_SMB_DA1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54 PWR_LED#_R
<55> EC_SMB_DA1 78 93
EC_SMB_CK2 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 SYSON
<14,22> EC_SMB_CK2 79 95 SYSON <46,50>
EC_SMB_DA2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 VR_ON
<14,22> EC_SMB_DA2 80 121 VR_ON <54>
EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 EC_ACIN_R

B
R728
R730
R731
R732

R734
@ C683
1
1
1
1
1
2
2
2
2
47K_0402_5%
47K_0402_5%
10K_0402_5%
2.2K_0402_5%

2 2.2K_0402_5%
@ R735
KSO1
KSO2
EC_SMI#
EC_SMB_DA1

EC_SMB_CK1
<15> PM_SLP_S3#
<15> PM_SLP_S5#
<18> EC_SMI#
<17,42> USB_OC0#
<17,42> USB_OC1#
<41> WL_OFF#
er
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
USB_OC0#
USB_OC1#
WL_OFF#
6
14
15
16
17
18
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C GPIO
AC_IN/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
EC_ON/GPXIOA05
EC_SWI#/GPXIOA06
ICH_PWROK/GPXIOA07
BKOFF#/GPXIOA08
S M Bus
127

100
101
102
103
104
105
PCH_RSMRST#
EC_LID_OUT#
EC_ON
H_PROCHOT#_EC_R_2
PCH_PWROK
BKOFF#
PCH_RSMRST# <15>
EC_LID_OUT# <14>
EC_ON <44>

PCH_PWROK <15>
BKOFF# <34>
+3VALW_EC
SPI ROM 128KB B

22P_0402_50V8J 33_0402_5% SUSWARN# 19 G PO RF_OFF#/GPXIOA09 106 CPU1.5V_S3_GATE

<15> SUSWARN# SUS_PWR_DN_ACK/GPIO0D CPU1.5V_S3_GATE <10>
PCH_APWROK
yb
2 1 1 2 DVT:Add USB_OC0# on pin16 PAD T96 25 107 U52
FAN_SPEED1 INVT_PWM/PWM2/GPIO11 GPXIOA10 SA_PGOOD PCH_APWROK <15> 20mils
Add USB_OC1# on pin17 28 108 SA_PGOOD <52> 8 4
<45> FAN_SPEED1 PCH_PWR_EN_R FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 VCC VSS
29 1
Layout note: Reserve for EMI please close to U64 E51TXD_P80DATA FANFB1/GPIO15 C685
<41> E51TXD_P80DATA 30 3
E51RXD_P80CLK EC_TX/GPIO16 PM_SLP_S4#_R 0.1U_0402_16V4Z W
<41> E51RXD_P80CLK 31 110
+3VS ON /OFF_R EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 ENBKL_R
32 112 7
PWR_BTN_LED# ON_OFF/GPIO18 ENBKL/GPXIOD02 EAPD_R 2 HOLD
<44> PWR_BTN_LED# 34 114
SUSP_LED#/GPIO19 EAPD/GPXIOD03 EC_PME#_R FSEL#
36
NUM_LED#/GPIO1A GPI EC_THERM#/GPXIOD04 115 1
S
R741 1 2 2.2K_0402_5% EC_SMB_CK2 SUSP#/GPXIOD05
116 SUSP#
SUSP# <10,46,51>
R742 1 2 2.2K_0402_5% EC_SMB_DA2 Pre MP:Add PWR_BTN_LED# 117 PBTN_OUT#
PBTN_OUT# <15>
SPI_CLK 6
PBTN_OUT#/GPXIOD06 C
R744 1 2 10K_0402_5% EC_SCI# 118 PECI_KB9012_R
EC_XCLK1 EC_PME#/GPXIOD07 FWR# FR D#
122 5 2
XCLK1 D Q
C

1 2 EC_XCLK0 123 124 +V18R

<15> SUSCLK XCLK0 V18R
R746 0_0402_5% 1 DVT:Add PECI_KB9012_R MX25L1005AMC-12G_SO8
AGND

C688
GND
GND
GND
GND
GND

SA00002C100 (S IC FL 1MB MX25L1005AMC-12G SOP 8P

4.7U_0805_10V4Z 3.3V)
1

KB930QF-A1_LQFP128_14X14 2
1
11
24
35
94
113

69

PV T:<Memo> R958 C917 20mil

100K_0402_5% 20P_0402_50V8J L50
ECAGND 2 1 @ R747 @ C689
2 FBMA-L11-160808-800LMT_0603 22_0402_5% 100P_0402_50V8J
DVT :Update net name SUSCLK_R-->SUSCLK
2

SPI_CLK_R 2 1 1 2

EC_XCLK1 EC_XCLK0
A Layout note: Reserve for EMI please close to U64 A
DVT:Add R958 C917
1 1
@ C686 C687 PV T:<Memo>
1

@
22P_0402_50V8J 22P_0402_50V8J
OSC

OSC

2 2

@
Security Classification Compal Secret Data Compal Electronics, Inc.
NC

NC

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

EC ENE-KB930
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
X1 DVT :C686 C687 15p-->22p Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
32.768KHZ_12.5PF_Q13MC14610002 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 43 of 56
5 4 3 2 1
INT_KBD Connector Pin1
New key board <T/P conn>
+5VS +5VS

Key board pin define (Down)

0.1U_0402_16V4Z
JTP1
1 1 1

C690
2
CIS symbol (DVT) Pin1
<43>
<43>
TP_CLK
TP_DATA 3
2
3
4 @
4 2

100P_0402_50V8J

100P_0402_50V8J
KSI[0..7]
CIS symbol (PVT need reverese pin define) KSI[0..7] <43>
1 @ 1 @
5
6
G1
KSO[0..17] G2
KSO[0..17] <43>

C694

C692
@ ACES_85201-0405N
Pin1 KSO16 1 2 CONN@
C691 @ 100P_0402_50V8J 2 2
@ KSO17 1 2
KSO7 C693 @ 100P_0402_50V8J
28
27
GND1 C695
1
@
2
100P_0402_50V8J KSO15 1 2
PVT:Update JTP1 footprint
GND2 KSO16 KSO6 C696 @ 100P_0402_50V8J
26 26
1 2
KSO15 C697 @ 100P_0402_50V8J KSO14
25 25 KSO14 KSO5 C698
1
@
2
100P_0402_50V8J
24 24 KSO13 C699
1
@
2
100P_0402_50V8J KSO13
23 23
1 2
KSO12 KSO4 C700 @ 100P_0402_50V8J TP_CLK
22 22 KSO11 C701
1 2
100P_0402_50V8J KSO12 EVT:Check pin define
21 21 KSO10 @ C702
1 2
100P_0402_50V8J TP_DATA
Key board Pin 1 is KSO16 20 20 KSO9 KSO3 @
19 19
1 2
Pin 2 is KSO15

2
KSO8 C703 @ 100P_0402_50V8J KSI0
18 18 1 2

.ru
KSO7 KSI4 C704 @ 100P_0402_50V8J D24
... 17 17 KSO6 C705
1
@
2
100P_0402_50V8J KSO11
16 16 KSO5 KSO2 C706
1
@
2
100P_0402_50V8J
PJDLC05C_SOT23-3
15 15 KSO4 C707
1
@
2
100P_0402_50V8J KSO10
14 14 KSO3 KSO1 C708
1
@
2
100P_0402_50V8J
13 13 KSI0 C709
1 2
100P_0402_50V8J KSI1
12 12 KSI1 @ C710
1 2
100P_0402_50V8J
11 11 KSO2 KSO0 @
10 10
1 2

1
KSI2 C711 @ 100P_0402_50V8J KSI2
9 9 KSI3 KSI5 C712
1
@
2
100P_0402_50V8J
8 8 KSI4 C713
1
@
2
100P_0402_50V8J KSO9
7 7 KSI5 KSI6 C714
1
@
2
100P_0402_50V8J
6 6 KSO1 C715
1
@
2
100P_0402_50V8J KSI3
5 5 1 2

m
KSO0 KSI7 C716 @ 100P_0402_50V8J
4 4 KSI6 C717
1 2
100P_0402_50V8J KSO8
3 3
1 2
KSI7 C718 100P_0402_50V8J
2 2
1 1
JKB1
ACES_88514-02601-071
CONN@ PVT:Update JKB1 footprint

ru
<Power Button/Lid B conn> <Power on LED>
LED3
JPWR1
R1003 1 2 0_0402_5% 1 7 1 2 2 1 PWR_LED#
+5VALW 1 G1 +5VALW PWR_LED# <43>

Fo
PWR_BTN_LED# 2 R752 330_0402_5%
<43> PWR_BTN_LED# 2
+5VS R1004 1 2 0_0402_5% +3VALW_EC 3
3 HT-110TW_WHITE
<43> LID_SW# 4
ON/OFFBTN# 4
@ 5
Pre MP:Add R1003 R1004 6
5
6 G2
8 <AC in LED>
1 1 1
C921 C920 C919 ACES_88231-06001
1 2 BATT_LOW_LED# <43>
100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J CONN@ R959 0_0402_5%
2 2 2
DVT:Add R959 for DC in LED control ACIN <15,22,43,46,48>

2
er

G
Power Button DVT:Update JPWR1 footprint and pin define 1 2 2
LED4
1 1 3
+5VALW
R753 330_0402_5%

S
HT-110TW_WHITE @
DVT:R759 pin1 +3VALW-->+3VALW_EC
Pre MP:Update JPWR1 pin define Q39
+3VALW_EC <HDD LED> 2N7002_SOT23-3
yb
LED5
2

1 2 2 1 PCH_SATALED#
+5VS PCH_SATALED# <13>
R759 R952 330_0402_5%
100K_0402_5%
HT-110TW_WHITE
1

2 ON/OFF <43>
ON/OFFBTN# 1
C

3 51ON#
51ON# <47>
D25
CHN202UPT_SC70-3
1

D
EC_ON 2
<43> EC_ON
G
DVT:Del R937
2

S Q36
3

R764 2N7002E-T1-GE3_SOT23-3
10K_0402_5%
1

EC requirement

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/LED/FUNC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 44 of 56
 +1.05VS to +1.05VS_DGPU FAN Connector
+1.05VS +5VALW

+1.05VS_DGPU

2
OPT@ R2639

2
Vgs=4.5V,Id=3A,Rds<22mohm 47K_0402_5%
OPT@ R2640

1
D 470_0805_5%

1
2

0.01U_0402_25V7K
OPT@ C2572
G

1
OPT@ Q85 S 2

3
AO3416_SOT23-3

3
1 +5VS
4.7U_0603_6.3V6K

1U_0402_6.3V4Z
OPT@
2 DGPU_PWR_EN# 5 Q86B
+1.05VS_DGPU 2N7002DW-T/R7_SOT363-6 1A

OPT@ C2574
Q86A

4
@
1 1 2N7002DW-T/R7_SOT363-6
OPT@
C2573

2 2 2
C904 JFAN1
10U_0805_10V6K +FAN1 1

.ru
1 1
2 2 G1 4
2 3 3 G2 5
U66 C906
1 8 1000P_0402_50V7K ACES_85204-03001
EN GND @
2 7
+3VS TO +3VS_DGPU +FAN1 3
4
VIN
VOUT
GND
GND 6
5
1
CONN@
+3VS <43> EN_DFAN1 VSET GND
1
+3VALW APL5607KI-TRG_SO8
R2651
C905
10U_0805_10V6K 2 1 +3VS
2
2

2 10K_0402_5%

m
OPT@ R2633 C2564 Vgs=-4.5V,Id=3A,Rds<97mohm FAN_SPEED1 <43>
100K_0402_5% 0.1U_0402_16V7K 2
OPT@
OPT@ R2634 1 @ C907
1

47K_0402_5% S Q50 0.01U_0402_25V7K

DGPU_PWR_EN# 1 2 2 AO3413L_SOT23-3 1
G OPT@
D +3VS_DGPU
2
1
6

ru
OPT@ C2565
1U_0402_6.3V4Z

0.01U_0402_25V7K
1
OPT@ C2566

<17,53> DGPU_PWR_EN 2 1
1
Q80A @ C2567
1

2N7002DW-T/R7_SOT363-6 4.7U_0805_10V4Z
OPT@ 2
2

Fo
+3VS_DGPU +VGA_CORE
2

OPT@ R2631 OPT@ R2632

470_0805_5% 470_0805_5%
3 1

6 1

OPT@
Q84A
OPT@
Q80B 5 DGPU_PWR_EN#
2N7002DW-T/R7_SOT363-6
2
2N7002DW-T/R7_SOT363-6 er H7
H_4P7
H8 H9
H_4P2X4P7 H_4P2
H10
H_4P2X4P7
H5
H_4P2
H6
H_4P2
4

CPU screw hole @ @ @ @ @ @

1
yb
+1.5V to +VRAM_1.5VS H1 H2 H4
H_2P8 H_2P8 H_2P8
+1.5V +VRAM_1.5VS
@ @ @

1
Vgs=10V,Id=14.5A,Rds=6mohm
1U_0402_6.3V4Z
OPT@ C2568

4.7U_0805_10V4Z
OPT@ C2569

1 1
OPT@ Q82
C

8 1
D S
2

7 2 H11 H12 H13 H14 H15

D S 2 2 OPT@ R2635 H_2P8 H2P8 H_2P8 H_2P8 H_2P8
6 3
D S B+_BIAS 470_0805_5% H20 H21
5 4
D G H_3P2N H_4P3X3P3N
FDS6676AS_SO8 1 OPT@ 2 @ @ @ @ @
3 1

1
4.7U_0805_10V4Z

0.1U_0402_25V6

1 1 R2636 220K_0402_5% FD1 FD2

1

6
OPT@ C2570

OPT@ C2571

OPT@ @ @

1
OPT@ R2637 Q83A
820K_0402_5% 2N7002DW-T/R7_SOT363-6 @ @

1
2 2
2 VGA_PWROK# 5 Q83B
2N7002DW-T/R7_SOT363-6 FIDUCIAL_C40M80 FIDUCIAL_C40M80 H22 H23 H24 H25 H26 H27 H28 H29
2

OPT@ H_2P8 H_2P8 H_2P8 H_2P8 H_5P5 H_3P2x4P2N H_6P0N H_2P0N

1

FD3 FD4

@ @ @ @ @ @ @ @

1
@ @
1

1
1 OPT@ 2 +5VALW
R2638 100K_0402_5% FIDUCIAL_C40M80 FIDUCIAL_C40M80
3

Security Classification Compal Secret Data Compal Electronics, Inc.

5 Q84B Issued Date 2010/08/23 2011/08/25 Title
<18,53> DGPU_PWROK
2N7002DW-T/R7_SOT363-6 Deciphered Date
OPT@ Optimus Power/FAN/Screw Hole
4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 45 of 56
 A B C D E

+3VALW TO +3VALW(PCH AUX Power) PVT:R780 R772 +5VALW-->VL

Short J1 for PCH VCCSUS3.3
+3VALW J1 need to open VL VL
+3VALW_PCH
J1 @
1 1 2 2

2
JUMP_43X79 40mil R772 R780
U57 100K_0402_5% 100K_0402_5%
1 SI4800BDY-T1-GE3_SO8 1
PVT:<Memo>Fine tune +3VALW_PCH power
8 1

3 1

6 1
10U_0603_6.3V6M

1U_0603_10V4Z
7 2 SYSON# SUSP
<5,50> SUSP

10U_0603_6.3V6M
6 3 1 1

2
C735

C736
1 5

C734
Q90A
R774 SYSON 5 Q90B 2
<43,50> SYSON <10,43,51> SUSP#

1
2 2 470_0603_5% 2N7002DW-T/R7_SOT363-6

1
2 R783 2N7002DW-T/R7_SOT363-6

1
R775 10K_0402_5%
100K_0402_5%

6
20mil 10mil

2
2
B+_BIAS 2 1 3V_GATE Q95A
R778 200K_0402_5% 2 PCH_PWR_EN#

.ru
0.1U_0603_25V7K
1

1
3
2N7002DW-T/R7_SOT363-6

C738
PCH_PWR_EN# 5 Q95B 2
2N7002DW-T/R7_SOT363-6
4

+0.75VS
+1.8VS +1.05VS +1.5V

m
+5VALW TO +5VS

2
R793 R798 R794 @ R799
2 +5VALW 22_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 2
U56 +5VS

2
SI4800BDY-T1-GE3_SO8

3 1

6 1

1 1
8 1

3
D
10U_0805_10V4Z

1U_0603_10V4Z

7 2 2 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
10U_0805_10V4Z

10U_0805_10V4Z

ru
6 3 1 1 2 SYSON#
C732

C733

1 1 5 Q9B Q92A G
C730

C731

R773 2N7002DW-T/R7_SOT363-6 5 SUSP Q92B 5 SUSP 2 SUSP S @ Q54

3
680_0603_5% 2N7002E-T1-GE3_SOT23-3
4

2 2
Q9A on P10
1

1
2 2
6

10mil Q38A

Fo
2 1 5VS_GATE 2 SUSP
B+_BIAS
R777 100K_0402_5%
0.1U_0603_25V7K

1
3

1 2N7002DW-T/R7_SOT363-6
C737

SUSP 5 Q38B
2
2N7002DW-T/R7_SOT363-6
4

+1.5V to +1.5VS

3
+3VALW TO +3VS
er 10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z
+1.5V
U63
SI4800BDY-T1-GE3_SO8
8 1
+1.5VS

0.1U_0402_16V4Z

10U_0603_6.3V6M

1U_0603_10V4Z
7 2
1 1 1 1 6 3 1 1

2
C743

C744

C745

C746

C747

C748
5
+3VALW +3VS R784
U61 470_0603_5%

4
2 2 2 2 2 2 +5VALW
yb
SI4800BDY-T1-GE3_SO8
8 1

1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

7 2

2
1U_0603_10V4Z

1 1 6 3 1 1
2
C739

C740

5 R786

3
C741

C742

R781 2N7002DW-T/R7_SOT363-6 100K_0402_5%

330_0603_5%
4

2 2 2 2
10mil

1
2 1 1.5VS_GATE Q40B 5 SUSP PCH_PWR_EN#
B+_BIAS <20> PCH_PWR_EN#
1

0.1U_0603_25V7K
R787 750K_0402_1%
510K_0402_5%
10mil @ 1

4
1

6
C750
6

6
C

R785 2 1 200K_0402_5% 3VS_GATE

B+_BIAS
R788

Q34A
2
0.1U_0603_25V7K

Q40A <43> PCH_PWR_EN 2

3

1 2 SUSP SUSP 2 2N7002DW-T/R7_SOT363-6

2

1
C749

2N7002DW-T/R7_SOT363-6

1
Q79A R789 Q34A on P43
1

SUSP 5 Q79B 2N7002DW-T/R7_SOT363-6 100K_0402_5%

2N7002DW-T/R7_SOT363-6 2
1

D
4

2
AC IN 2
<15,22,43,44,48> ACIN
G @ Q43
S 2N7002E-T1-GE3_SOT23-3
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 46 of 56
A B C D E
 5 4 3 2 1

@ PR1
1K_1206_5%
ADPIN VIN 1 2
@ PJP1
PL1 @ PR2
SMB3025500YA_2P 1K_1206_5%
1 N3
D 1 1 2
VIN 2 1 1 2
B+ D

@ PD1 @ PR3
2 LL4148_LL34-2 1K_1206_5%
2 1 2

100P_0402_50V8J

100P_0402_50V8J
1

1
3 3

PC1

PC3
PC2 PC4
1000P_0402_50V7K 1000P_0402_50V7K

2
4 4

1
5
2

@ PR4
VL 2 1 2 1

.ru
6 PD5 @ PR30 @ PR29
PJSOT24C_SOT23-3 2 1 100K_0402_1% 2.2M_0402_5% 511K_0402_1%
PR35

2
ACES_88290-044G 0_1206_5%
Pre-V
1

@ PU2A

8
@ PD2 LM393DT_SO8
2 3

P
<49> EN0 +
1 1 O

1
<48> ACON 3 - 2

1
m 1
RB715F_SOT323-3 @ PR7 @ PR5 @ PC14
VIN

4
@ PC15 150K_0402_1% 255K_0402_1% 1000P_0402_50V7K

2
1000P_0402_50V7K

2
C C

2
@ PQ807
SSM3K7002FU_SC70-3
D

1
PD3
LL4148_LL34-2
6251VREF 1
@ PR31
2
2 2 1 PACIN <48>

ru
1
34K_0402_1% G @ PR6

1
@ PR32 S 47K_0402_5%

1
@ PC16
2 1 66.5K_0402_1% 1000P_0402_50V7K PQ3
BATT+

2
1

1
68_1206_5%
PDTC115EU_SOT323-3

2
PD4 @

PR8
LL4148_LL34-2 PR9
PQ4 68_1206_5%
2
+5VALW
TP0610K-T1-E3_SOT23-3 VS

Fo
@ PU2B

8
Pre-V 3 1 LM393DT_SO8

3
0.22U_0603_25V7K

+ 5

P
100K_0402_5%

7 O
1

- 6

G
1

1
P R10

PC5

PC6

4
0.1U_0603_25V7K
2

2
2

<44> 51ON# 1 2
PR11

B
22K_0402_1% er B

RTC Battery
yb
- PBJ1 + PR33
560_0603_5%
PR34
560_0603_5%
2 1 1 2 1 2
+RTCBATT
C

@ MAXEL_ML1220T10

X7999651L01

A A

Security Classification Compal Secret Data

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / Pre-Charge / RTC
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
D ate: Monday, April 11, 2011 Sheet 47 of 56
5 4 3 2 1
 A B C D

PR102
PQ101 P2 PQ102 P3 B+ PL102 CHG_B+ B+ PQ103
SI4459ADY-T1-GE3_SO8
AO4407A_SO8 0.015_2512_1% 1.2UH_1231AS-H-1R2N=P3_2.9A_30% AO4407A_SO8
VIN 8 1 1 8 1 4 1 2 1 8
7 2 2 7 2 7

4.7U_0805_25V6-K

4.7U_0805_25V6-K

10U_0805_25V6K

10U_0805_25V6K

4.7U_0805_25V6-K
6 3 3 6 CSIP 2 3 CS IN 3 6
5 5 5

1
PC138

PC139

PC103

PC104

PC105
VIN

4
1 1

2
2 1
PR103 VIN
1

200K_0402_1%

1
0.1U_0603_25V7K
PR101 47K 6251VDD 1 2 ACOFF

1
200K_0402_1% PC102

PC101
2 47K PR104 @5600P_0402_25V7K PD101 PR105 PR106 PD102

1
200K_0402_1% RB751V-40_SOD323-2 191K_0402_1% 47K_0402_1% 1SS355_SOD323-2
2

2
PR107

1 2
200K_0402_1%
1

1
PC106 ACSETIN 2 1
2.2U_0603_6.3V6K PQ106 VIN
1

PQ104 PDTC115EU_SOT323-3

2
1

1
PDTA144EU_SOT323-3

.ru
2 2 1 2

0.1U_0603_25V7K
PR111 PR108 PR109 PC107
PQ105 150K_0402_1% ACSETIN 10_1206_5% 14.3K_0402_1% 1000P_0402_50V7K PD104

2
PDTC115EU_SOT323-3 PD103 PU101 1SS355_SOD323-2
2

1
D

PC111
1SS355_SOD323-2 PC109
3

3
1 2 1 24 D CIN 1 2 2 PACIN
<43> FSTCHG VDD DCIN
6

100K_0402_1%
.1U_0402_16V7K
PQ109
G

2
1
0.1U_0603_25V7K S SSM3K7002FU_SC70-3

3
1

PC108

PR113
PQ107A PQ107B 1 2 2 23 ACPRN @ PR114
DMN66D0LDW -7 2N SOT363-6 DMN66D0LDW -7 2N SOT363-6 PR110 ACSET ACPRN 100K_0402_1%
2 5
10K_0402_5% BATT_ON 1 2

2
6251_EN 3 22 1 2CSON
1

2
EN CSON

5
6
7
8
PR112 PR115

m
0_0402_5% PC112 20_0402_5% PQ110
2 1 4 21 0.047U_0402_16V7K
1 2CSOP

1
CELLS CSOP PR116
PC115 PC113 20_0402_5%
2
PR123 2 1 2 1 2 1 5 ICOMP CSIN 20 2 1CS IN 4 2

2
47K_0402_5% PR118 PR117
PACIN 1 2 0.01U_0402_25V7K 10K_0402_1% 6800P_0402_25V7K PC114 20_0402_5%
2 1 6 19 0.1U_0603_25V7K 1 2 CSIP TCR=50ppm / C

1
@ PC116 PR120 VCOMP CSIP PR119 AO4466L_SO8 PL101

3
2
1
ru
100P_0402_50V8J 100_0402_1%
2 1 7 18 LX_CHG
2_0402_5% 10UH_SIL104R-100PF_4.4A_30%
1 2 C HG 1 4
BATT+
<43,55> ADP_I ICM PHASE
<47> ACON
1

5
6
7
8
PR136 2 3
1

1
PC117 6251VREF 8 17 DH_CHG 1 2 PQ112
VREF UGATE

10U_0805_25V6K

10U_0805_25V6K
PR124 .1U_0402_16V7K 0_0603_5% PR121
2

80.6K_0402_1% 6251VREF PR125 PC118 PR122 0.02_1206_1%

1
PC120

PC121
2 1 9 16 BST_CHG 1 2 BST_CHGA 1 2 4.7_1206_5%
<43> IR EF CHLIM BOOT

1
0.01U_0402_25V7K

ACOFF 2 2.2_0603_5% 4 CSOP

<43> ACOFF

2
100K_0402_1%

0.1U_0603_25V7K

Fo

2
1

PQ113 6251VREF 1 2 6251ACLIM 10 15 6251VDDP PD105 CSON

ACLIM VDDP
1

1
PR126

PC119

PDTC115EU_SOT323-3 PR127 RB751V-40_SOD323-2

1

53.6K_0402_1% 1 26251VDD AO4466L_SO8 PC123

3

3
2
1
11 14 DL_CHG PR128 680P_0402_50V7K
2

2
VADJ LGATE

1
PR129 4.7_0603_5%
2

20K_0402_1% PC125
12 13 4.7U_0603_6.3V6M
2

2
GND PGND

ISL6251AHAZ-T_QSOP24
PR130
15.4K_0402_1%

3
<43> CHGVADJ
er 1 2
1
2

PR131
31.6K_0402_1%
3
yb
6251VDD
B+
For RF team
1

1 2
C

ACIN <15,22,43,44,46>
PR134
PR133 10K_0402_1%
1

10K_0402_1%
2

PR132 PACIN
PACIN <47>
47K_0402_1%
1
2

PQ114
1

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
PDTC115EU_SOT323-3

ACPRN 2 PR135

1
14.3K_0402_1%
PC126

PC127

PC128

PC129

PC130

PC131

PC132

PC133

PC134

PC135

PC136

PC137
2

2
4 4
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
Date: Monday, April 11, 2011 Sheet 48 of 56
A B C D
 5 4 3 2 1

2VREF_51125

1U_0603_10V6K
1

PC301
2
D D

PR301 PR302
13K_0402_1% 30K_0402_1%
1 2 1 2

PR303 PR304
20K_0402_1% 20K_0402_1%
TPS51125_B+
B+ TPS51125_B+ Typ: 175mA
1 2 1 2

PL304 PL301
1 2 1 2 +3VLP

.ru
ENTRIP2

ENTRIP1
4.7U_0805_25V6-K

0.1U_0603_25V7K

2200P_0402_50V7K

10U_0805_25V6K

0.1U_0603_25V7K

2200P_0402_50V7K
1.2UH_1231AS-H-1R2N=P3_2.9A_30% HCB2012KF-121T50_0805 PR305 PR306
110K_0402_1% 130K_0402_1%
1

1
PC303

PC304

PC305

PC306

PC309

PC310
@ PC302 1 2 1 2

680P_0402_50V7K
2

2
6

1
4.7U_0805_10V6K
PU301

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
5

5
PC307
25 P PAD PQ302

m
2
7 VO2 VO1 24 SPOK <15,55>
PQ301 4
8 VREG3 PGOOD 23 4
C SIS412DN-T1-GE3_POW ERPAK8-5 PC311 PC312 C
1 2 3V_BST_1 1 23V_BST 9 22 5V_BST 1 25V_BST_1 1 2
PR307 BOOT2 BOOT1 PR308
1
VFB=2.0V
2
3
0.1U_0603_25V7K 0_0603_5% 3 V_DH 10 21 5 V_DH 0_0603_5% 0.1U_0603_25V7K SIS412DN-T1-GE3_POW ERPAK8-5

3
2
1
PL302 UGATE2 UGATE1 PL303

ru
3V_LX 5V_LX +5VALWP
+3VALWP 1 2
4.7UH_PCMC063T-4R7MN_5.5A_20%
11 PHASE2 PHASE1 20 1 2
4.7UH_PCMC063T-4R7MN_5.5A_20%
1

1
4.7_1206_5%

3V_DL 12 19 5V_DL
LGATE2 LGATE1

5
PR309

PQ303

SKIPSEL
PQ304 PR310

VREG5
1
4.7_1206_5%

GND

VIN
+ PC313

NC
EN
<47> EN0 1
13V_SNB 2

15V_SNB 2
220U_6.3V_M 4 RT8205EGQW _W QFN24_4X4
PR311 4 + PC314

13

14

15

16

17

18
Fo
2
680P_0402_50V7K

499K_0402_1% 220U_6.3V_M
1 2 MAINPW ON
TPS51125_B+ 2
PC315

1
2
3

PC316

3
2
1
100K_0402_1%

1U_0603_10V6K
SI7716ADN-T1-GE3_POW ERPAK8-5 680P_0402_50V7K
2

2
1
SI7716ADN-T1-GE3_POW ERPAK8-5
Typ: 175mA
VL

1
PR313

PC317

1
PC318

2
PJP301 4.7U_0805_10V6K PJP302

2
+3VALWP 2 2 1 1
+3VALW +5VALWP 2 2 1 1
+5VALW
JUMP_43X118 er TPS51125_B+ JUMP_43X118

1
PC319
3.3VALWP
ENTRIP1

ENTRIP2

B 0.1U_0603_25V7K B
5VALWP

2
TDC A
2VREF_51125 TDC A
Peak Current A
Peak Current A
OCP current A
3

yb
PQ305B PQ305A OCP current A
DMN66D0LDW -7 2N SOT363-6 DMN66D0LDW -7 2N SOT363-6
5 2
4

VL 1
PR316
2
C

100K_0402_1%

<55> VS_ON 1 2
1

PR317
0_0402_5% PQ306
PDTC115EU_SOT323-3

VS 1
PR318
2 2
40.2K_0402_1%

2.2U_0603_16V5K

100K_0402_1%
1

1
PR319

PC320

A A
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-3VALWP/5VALWP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
D ate: Monday, April 11, 2011 Sheet 49 of 56
5 4 3 2 1
 A B C D

PJP401
1.5_51117_B+ 2 2 1 1
B+
JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.1U_0603_25V7K
5
6
7
8
1 1

1
PC402

PC403

PC404
1 2
PR402 PC405 @ PC406
267K_0402_1% 2200P_0402_50V7K

2
680P_0402_50V7K
4
PR401
0_0402_5% PC407 PQ401
1 2 BST_1.5V 1 2BST_1.5V-1 1 2 SI4128DY-T1-GE3_SO8
<43,46> SYSON
PR403

3
2
1
0_0603_5% 0.1U_0603_25V7K
1 @ PC401 PL401
1UH_PCMC063T-1R0MN_11A_20%

15

14
1
.1U_0402_16V7K PU401 1 2
+1.5VP
2

.ru
EN/DEM

NC

BOOT

220U_D2_2VY_R15M
5
6
7
8

10U_0805_6.3V6M
.1U_0402_16V7K
1.5V_TON 2 13 1. 5V_DH 1
TON UGATE PQ402 PR404

1
@ PC411

@ PC408

PC409
1.5V_VOUT 3 12 1.5V_LX 4.7_1206_5% +
VOUT PHASE

11.5V_SNB 2
1 2 1. 5V_VDD 4 VFB=0.75V 11 1.5V_CS 1 2
+5VALW +5VALW

2
VDD CS 2
1U_0603_10V6K

PR406 PR405 4
316_0402_1% 1.5V_FB 5 10 1.5V_VDDP14K_0402_1%
FB VDDP
1

PC412

1
6 9 1.5V_DL PJP402
PGOOD LGATE

PGND
PC413 FDS6690AS-G_SO8 1 2

GND
2

3
2
1
4.7U_0805_10V6K PC414 1 2

m
680P_0402_50V7K JUMP_43X118

2
@ PC415 RT8209BGQW _W QFN14_3P5X3P5
+1.5VP +1.5V

8
1 2
PJP403
2
47P_0402_50V8J 1 2 2

1 2
JUMP_43X118

1.5VP

ru
1 2
PR408
10K_0402_1%
TDC 10 A
1

Peak Current 13 A
PR409 OCP current 16.9 A
10K_0402_1%
2

Fo
+1.5V_CPU_VDDQ +1.5V
2

PJP406 PJP405
er
2

JUMP_43X118 JUMP_43X118
1

1
1

3 3

PU402 PJP404
0. 75V_VIN 60.75V_VCNTL
1 VIN VCNTL +3VALW +0.75VSP 1 1 2 2 +0.75VS
1

1
1K_0402_1%

1K_0402_1%

2 5 JUMP_43X118
GND NC
2

yb PR410

PR413

PC416 0.75V_VREF 3
VREF NC 7 +0.75VSP

1
4.7U_0805_6.3V6K
1

4 8 PC417 Thermal Design Current:0.7A

2

VOUT NC 1U_0603_10V6K

2
TP 9 Peak current:1A
APL5336KAC-TRL_SO8 Vout=VDDQSNS/2=1.5V/2=0.75V
.1U_0402_16V7K

+0.75VSP
1

D
1

PC418

<5,46> SUSP 1 2 2
1

PR411 G PR412
1

100K_0402_1% S 1K_0402_1% PC419

C 3

PC420 PQ403 10U_0603_6.3V6M

2

1U_0402_16V6K SSM3K7002F_SC59-3
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.5VP/0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 50 of 56
A B C D
 5 4 3 2 1

PJP501
VCCP_51117_B+ 2 1
2 1
B+

10U_0805_25V6K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
JUMP_43X118

0.1U_0603_25V7K
1 2
PR502

1
PC502

PC503

PC506

PC507
267K_0402_1%
PC504

5
2200P_0402_50V7K

2
D PQ501 D
PC505
1 2 VCCP_BST1 2VCCP_BST_11 2
<10,43,46> SUSP#
PR501 PR503
20K_0402_1% 0_0603_5% 0.1U_0603_25V7K

15

14
4

1
PC501 PU501

EN/DEM

NC

BOOT
2 1U_0402_16V6K
VCCP_TON 2 13 VCCP _DH TPCA8065-H_PPAK56-8-5 PL501

3
2
1
TON UGATE 1UH_PCMC063T-1R0MN_11A_20%

TPCA8059-H_SOP-ADVANCE8-5
PR504 VCCP_VOUT-1 2 VCCP_VOUT VCCP_LX
316_0402_1% PR519
1 3 VOUT PHASE 12 1 2
+1.05VS

150U_B2_1.5VM_R15M
0_0402_5% VCC P_VDD VC CP_CS
+5VALW 1 2 4 VDD CS 11 1 2
1U_0603_10V6K

PR505
+5VALW 1

.ru 0.1U_0402_10V7K
VC CP_FB 5 FB VFB=0.75V VDDP 10 VC CP_VDDP 6.98K_0402_1%
+1.05VS
1

5
PC508

PC510
PR506 +

1
V CCP_PGD 6 9 VC CP_DL 4.7_1206_5% Peak Current 16.2 A

1VC CP_SNB 2
PGOOD LGATE

1
PGND

PC521
PC509

GND
2

2
4.7U_0805_10V6K OCP current 21A

2
RT8209BGQW _W QFN14_3P5X3P5 4

PQ502
PC513

3
2
1
680P_0402_50V7K

m 2
C C
2 1 VCCP_VOUT-1 2 1 VCCIO_SENSE <8>
PR508 PR511
+3VS 4.02K_0402_1% 100_0402_1%
1

ru
2 1 VSS_SENSE_VCCIO <8>
1

PR510 PR513
10K_0402_1% 0_0402_5%
PR512 Close to PU501.7
2

10K_0402_1%
2

VTTPWRGOOD <52>

Fo
B
er PU502 PL502 B
4

PJP505 1UH_PCMC063T-1R0MN_11A_20% PJP506

1.8V_VIN 1.8V_LX
+5VALW 1 2 10 2 1 2
+1.8VSP +1.8VSP 1 2
+1.8VS
PG

1 2 PVIN LX 1 2
1
JUMP_43X79 9 3 JUMP_43X79
PVIN LX
yb
1

1
PC514 PC515 PR514
10U_0805_10V6K 10U_0805_10V6K
8 SVIN
4.7_1206_5% PC516 PC517
1.8VSP
6 1.8V_FB 22U_0805_6.3VAM 22U_0805_6.3VAM TDC 2 A
21.8V_SNB
2

2
1.8V_EN FB
5 EN
Peak Current 3 A
NC

NC
11 TP
7

<10,43,46> SUSP# 1 2
PR515 PC518
1

510K_0402_1% 680P_0603_50V7K
1
1
C

SY8033BDBC_DFN10_3X3
@ PR516 PC519
1M_0402_5% 0.47U_0402_6.3V6K
2

1 2
2

PR517
1

28.7K_0402_1%

PR518 @ PC520
14.3K_0402_1% 2 1
2

22P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VCCPP/1.8VSP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
D ate: Monday, April 11, 2011 Sheet 51 of 56
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

1
PR704
10K_0402_5%

.ru
1 2 SA_PGOOD <43>
PR703
0_0402_5%

PJP701 PL701

4
JUMP_43X79 1UH_PCMC063T-1R0MN_11A_20% PJP702
V CCSA_VIN 10 VCCSA_LX
+5VALW 1 2 2 1 2
+VCCSAP +VCCSAP 1 2
+VCCSA

PG
1 2 PVIN LX 1 2
9 3 JUMP_43X118
PVIN LX

1
1

1
PC702 PC703 PR706
10U_0805_10V6K 10U_0805_10V6K
8
SVIN
4.7_1206_5% PC708 PC709
+VCCSAP
6 V CCSA_FB 22U_0805_6.3VAM 22U_0805_6.3VAM TDC 4.8A
2

2
V CCSA_EN FB

m
5

1 VCCSA_SNB2
EN PU701 Peak Current 6A

SS
TP

LX

0.1U_0402_10V7K
SY8035DBC_DFN10_3X3

11

1
<51> VTTPWRGOOD 1 2

PC715
C PR701 C
1

0_0402_5% @ PC701

2
1
@ PR702 @ PC704

1
0.47U_0402_6.3V6K PC713
1M_0402_5% 0.47U_0402_6.3V6K 680P_0603_50V7K
2

2
2

ru
Need to check
for <1.8ms SS time PR708 PR715
2 1 1 2
+3VS VCCSA_SENSE <9>
3.48K_0402_1%
100_0402_1%

1
1

PR709
PR716 21.5K_0402_1% @ PC712
10K_0402_5% 2 1
2

Fo
PR712 22P_0402_50V8J
2

10K_0402_5% D
1 2 2 PR711
PR713 G 10.2K_0402_1%
1

.1U_0402_16V7K

10K_0402_5% S PQ703
3

2
1

<9> VCCSA_VID1 1 2 2 SSM3K7002F_SC59-3

1

@ PC714

PR717
1

PQ704 100K_0402_5%
3

PR718 PMBT2222A_SOT23-3
2

10K_0402_5%
2
2

B
VID[1]
0
1
VCCSA Vout
0.9V
0.8V
Required Require on 2012
Yes
Yes
Yes
Yes
er B
yb
C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VCCSAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
Date: Monday, April 11, 2011 Sheet 52 of 56
5 4 3 2 1
 5 4 3 2 1

PL801
+VGA_B+ 2 1
D +3VS HCB4532KF-800T90_1812 B+ D

10U_0805_25V6K

10U_0805_25V6K

0.1U_0603_25V7K
1

1
PC802

PC803

PC806
PR820

5
10K_0402_5% PC807
PQ801 2200P_0402_50V7K

2
+3VS

2
DGPU_PWROK <18,45>
4
2

PR819 PR802
@ PR801 0_0402_5% PU801 2.2_0603_5% PC808

.ru
2 1 VGA_PGD 1 10 VGA_BST 1 2 VGA_BST_1 1 2 TPCA8065-H_PPAK56-8-5

3
2
1
10K_0402_5% PGOOD VBST
1 2 VGA_TRIP 2 9 VGA_DH 0.22U_0603_25V7K PL802
1

PR803 TRIP DRVH 0.36UH_FDU1040D-R36M-P3_26A_20%

1 2 78.7K_0402_1% VGA_EN 3 8 VGA_LX 1 2
<17,45> DGPU_PWR_EN EN SW +VGA_COREP

TPCA8057-H_SOP-ADVANCE8-5

10U_0805_6.3V6M

10U_0805_6.3V6M

330U_2VYD2_R7M

330U_2VYD2_R7M
0.1U_0402_10V7K
PR804 VGA_FB 4 7 +5VALW 1 1
VFB V5IN
1

0_0402_5% @ PC801 1 1

PC809

PC810

PC813

PC811

PC812
VGA_RF 5 6 VGA_DL PR806 + +
.1U_0402_16V7K RF DRVL 4.7_1206_5%
1
2

1
11

2
TP 2 2 2 2

0.1U_0402_10V7K
PC814
PR805 TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M

m VGA_SNB

1
2

PC818
470K_0402_5% 4

PQ802
2

2
C C

3
2
1

1
PC815
680P_0603_50V7K

ru 2
VFB=0.7V
2 1 2 1 +VGASENSE <23>
PR807 PR810
1

2.37K_0402_1% 100_0402_1%
PR809
12.7K_0402_1%
1

Fo
2

PR811 PJP802
75K_0402_1% 1 1 2 2
2

+3VS JUMP_43X118

PJP803
GVID1-2

1 2
+VGA_COREP 1 2 +VGA_CORE
1

JUMP_43X118
PR812
10K_0402_5% PJP804
1

D
er GPIO5 GPIO6 N12P-GV 1 2
2

1 2
<22> GPU_VID1 1 2 2
0.01UF_0402_25V7K

G JUMP_43X118
100K_0402_5%

PR813 S PQ806 GPU_VID0 GPU_VID1 Core Voltage Level

3
1

B 4.7K_0402_5% SSM3K7002FU_SC70-3 B
1
@ PR814

PC816

1 1 1.025V
VGA_COREP
TDC:TBC A
2
2

1 0 1.000V Peak Current:21.56 A

yb
OCP current:TDB A
0 0 0.850V
1

PR815
+3VS 11K_0402_1%
2

C GVID0-2
1

PR816
10K_0402_5%
1

D
2

<22> GPU_VID0 1 2 2
0.01UF_0402_25V7K

G
100K_0402_5%

PR817 S PQ805
3
1

10K_0402_5% SSM3K7002FU_SC70-3
1
@ PR818

PC817
2
2

A A

Security Classification Compal Secret Data

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
Date: Monday, April 11, 2011 Sheet 53 of 56
5 4 3 2 1
 5 4 3 2 1

@ PC260 @ P H201 CPU_B+

10U_0805_25V6K

10U_0805_25V6K

0.1U_0603_25V7K
100P_0402_50V8J 470K +-5% ERTJ0EV474J 0402
2 1 2 1 2 1 2 1 N TCG

5
@ P R257 @ PR201

1
PC202

PC203

PC204
2K_0402_1% 3.83K_0402_1% PQ201 PC205
PC208 2200P_0402_50V7K
68P_0402_50V8J PC210 1 2

2
2 1 2 1 2 1 PR258
PR208 @ P R203 UGATEG 2 1 4
422_0402_1% 680P_0402_50V7K 27.4K_0402_1% +VGFX_CORE 0_0603_5%
PC212
2 1 2 1 2 1 2 1

330P_0402_50V7K
PR211 PR212 P C206 P R204 TPCA8065-H_PPAK56-8-5 PL201

3
2
1
150P_0402_50V8J 475K_0402_1% 2.87K_0402_1% 1 2 10_0402_1% 0.36UH_ETQP4LR36WHC_24A_20%
PHA SEG
VCC_AXG_SENSE <9> 4 1
+VGFX_CORE

PC209

TPCA8057-H_SOP-ADVANCE8-5
2 1 330P_0402_50V7K

4.7_1206_5%
D @ PR209 PC207 3 2 D

1
499K_0402_1% BOOTG 1 2B OOTG_1 1 2

2
1

P R206
P C211 PR205
VSS_AXG_SENSE <9>
PR202 PC201 2 1 2.2_0603_5% 0.22U_0603_10V7K

1
8.06K_0402_1% 1000P_0402_50V7K

2
1000P_0402_50V7K 2 1 LGATEG 4

1GFX_SNB 2
PQ202
P R213 PR210 P R207
10_0402_1% 10K_0402_1% 1_0402_5%
+5VALW

680P_0402_50V7K
GFXVR_IMON

2
2
22.6K_0402_1%

0.047U_0603_16V7K
PR217 PR214
+1.05VS

3
2
1
1

16.5K_0402_1% 7.5K_0402_1% P H202

1
P R216

P C215

P C214
1 2 1 2

1
.1U_0402_16V7K
10K_0402_5%_TSM0A103J4302RE
2

2
1

UGATEG

PHA SEG
130_0402_1%
@ P R221 PC213

LGATEG
BOOTG
2

@ PC217

PR218
VSS_AXG_SENSE PR219

N TCG
.1U_0402_16V7K

IS NG
ISPG

2
54.9_0402_1% 0_0402_5% 1 2

.ru
PR215
+3VS
1

IS NG 2
Parallel and tune length 11K_0402_1%
2

49

48

47

46

45

44

43

42

41

40

39

38

37
+VGFX_CORE

1.91K_0402_1%
1

12P_0402_50V8J

12P_0402_50V8J

12P_0402_50V8J

12P_0402_50V8J

12P_0402_50V8J

12P_0402_50V8J
1 2

GND

COMPG

FBG

VSENG

RTNG

ISPG

ISNG

NTCG

PROG2

BOOTG

UGG

PHG

LGG
<8> VR_SVID_DAT

P R220
1 36 BOOT2 PC216
<8> VR_SVID_ALRT# VWG BOOT2

1
.1U_0402_16V7K

@ PC219

@ PC220

@ PC221

@ PC222

@ PC223

@ PC224
2 35 UGATE2
<8> VR_SVID_CLK

2
IMONG UG2 ISPG
<43> GFX_CORE_PWRGD 1 2

2
Alert# PU resister need close CPU, 3 34 PHA SE2
PGOODG PH2

1
so the PU resister in HW schematic. @ PC218
SVID_SDA 4 33 0.01U_0402_16V7K
but DAT and CLK need close PWM-IC, SDA VSSP2 P R222

m
so the PU resister in POWER schematic. SVID_A LERT# 5 32 LGATE2 549_0402_1%
ALERT# LG2

2
SVID_SCLK IS NG
6 SCLK VDDP 31 1
PR224
2
+5VS 2
PR223
1
C C

2.2U_0603_10V6K
VSS SENSE 1 2 7 30 0_0603_5% 0_0402_5%
<43> VR_ON VR_ON PWM3
0.033U_0603_16V7K

+3VS1 P R225

1
P C225
33.2K_0402_1%

2 0_0402_5% 8 29 LGATE1
PGOOD LG1
1

PR226 ISL95831CRZ-T_TQFN48_6X6 P C226

1
PR227

PC227

1.91K_0402_1% 9 28 2.2U_0603_10V6K CPU_B+

2
IMON VSSP1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0603_25V7K
ru
5
10 27 PHA SE1
2

VR_HOT# PH1 PQ203

VGATE <15>
2

1
PC230

PC231

PC232

PC233
11 26 UGATE1 PC264

ISEN3/ FB2
NTC UG1 2200P_0402_50V7K
<43> IMVP_IMON
12 25 BOOT1 PR259

PROG1
ISUMN

ISUMP

2
VW BOOT1
COMP

ISEN2

ISEN1

VSEN
UGATE2 2 1 4

VDD
RTN
<43> VR_HOT#

VIN
P H203 0_0603_5%
FB
1

2 1
P C229
+1.05VS 1 2 PU201
13

14

15

16

17

18

19

20

21

22

23

24
@ P R228 47P_0402_50V8J 470K +-5% ERTJ0EV474J 0402 TPCA8065-H_PPAK56-8-5 PL202
2

3
2
1
499_0402_1% 2 1 0.36UH_ETQP4LR36WHC_24A_20%

Fo
I SEN2

I SEN1

P R229 PHA SE2 4 1

+CPU_CORE

4.7_1206_5%
3.83K_0402_1%

1
2 1 I SEN2 2 1 3 2 2 1I SEN1

PR238
P R230 P R236 PC235 P R233 PR234
27.4K_0402_1% BOOT2 2 1 2 1 10K_0603_1% 10K_0402_1%

1
2.2_0603_5%
2 1 CPU_B+ PR232 0.22U_0603_10V7K

1CP U_SNB12
1

PR231 7.87K_0402_1%
1

0_0603_5% LGATE2 4 V SUM+ 2 1

680P_0402_50V7K
PR235 P C234 P R239

2
8.06K_0402_1% 1000P_0402_50V7K 2 1 +5VS PQ204 3.65K_0603_1%
2

PC236 PR237 TPCA8059-H_SOP-ADVANCE8-5

2

PC241
1U_0603_10V6K

2 1 1_0603_5%

3
2
1
1

22P_0402_50V8J
er P C238

V SUM- 2 1

2
PC237 P C239 P R241
2 1 0.22U_0603_25V7K 1_0402_5%
2

B B
0.22U_0402_6.3V6K
@ P R240 PC240 P C242 V SUM- V SUM+

2.61K_0402_1%

10KB_0603_5%_ERTJ1VR103J
1 2 2 1 2 1 2 1 PC243

1
PR242 2 1

PR243
0.33U_0603_10V7K

0.022U_0402_16V7K

499K_0402_1% 10P_0402_50V8J 499_0402_1% 470P_0402_50V7K PL203

PC244 0.22U_0402_6.3V6K HCB4532KF-800T90_1812
1

11K_0402_1% CPU_B+
2 1 2 1 2 1 2 1
B+
yb 1

1
P C245

@ P C246

P R247

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0603_25V7K

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
P R244 PR245

1 2

100U_25V_M
150P_0402_50V8J 412K_0402_1% 3.01K_0402_1% 1 1
2

1
PH204

PC250

PC252

PC253

PC254

PC261

PC255

PC267

PC268
@ PC259 @ P R256 + + P C256
2

2 1 2 1 PC247 PQ205 100U_25V_M

330P_0402_50V7K

2 1

2
100P_0402_50V8J 2K_0402_1% 2 2
<8> V CCSENSE
2
1
PC248

330P_0402_50V7K 2 1 V SUM- P R260

PR248 UGATE1 2 1 4
1

1.5K_0402_1% 0_0603_5%
2

PC251 P C249
<8> VSSSENSE
2 1 .1U_0402_16V7K
2

TPCA8065-H_PPAK56-8-5 PL204
C

3
2
1
1000P_0402_50V7K 0.36UH_ETQP4LR36WHC_24A_20%
PHA SE1 4 1
+CPU_CORE

4.7_1206_5%
1
I SEN1 2 1 3 2 2 1I SEN2

PR253
P R250 P C257 P R251 P R252
BOOT1 2 1 2 1 10K_0603_1% 10K_0402_1%
2.2_0603_5%
*Iccmax in Turbo Mode for SV (35W) is 53A 0.22U_0603_10V7K

1CP U_SNB22
LGATE1 4 V SUM+ 2 1

680P_0402_50V7K
+CPU_CORE +VGFX_COREP P R254
PQ206 3.65K_0603_1%
TPCA8059-H_SOP-ADVANCE8-5
Icc-max=53A Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A

PC258
3
2
1
A A
Rdson=3.6~4.5m ohm Rdson=3.6~4.5m ohm
DCR=1.1m ohm DCR=1.1m ohm V SUM- 2 1

2
P R255
HW output cap: HW output cap: 1_0402_5%
(1)10U_0805_4V *10 (1)22U_0805_6.3V *12
(2)22U_0805_6.3V *15 (2)470U_D2_2V *2(ESR=4.5m ohm)
(3)470U_D2_2V *4(ESR=4.5m ohm)
Security Classification Compal Secret Data
Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title
*OCP setting value=71.5A *OCP setting value=37A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE/GFX_CORE
Size D ocument Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0 .1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
Dat e: Monday, April 11, 2011 Sheet 54 of 56
5 4 3 2 1
 5 4 3 2 1

PH1 under CPU botten side :

BATT++ BATT+
PL2
CPU thermal protection at 92 degree C
HCB2012KF-121T50_0805 VL
1 2
Recovery at 56 degree C
PL3 BATT+
HCB2012KF-121T50_0805

1
D D
1 2

1
PC8
1000P_0402_50V7K PC7 PC9

1
0.01U_0402_25V7K 0.1U_0603_25V7K

2
@ PR13 VL PR12
1 2 21K_0402_1%
100K_0402_1% +3VALW
PJPB1 battery connector

2
2
@ PR15 PU1

1
1 8
100K_0402_1% VCC TMSNS1
@ PJP2 PR14 2 7 1 2
1K_0402_1% GND RHYST1 PR16

1
SUYIN_200275MR008G15QZR 3 6 9.53K_0402_1%
<49> VS_ON

2
OT1 TMSNS2

.ru
PH1
GND 10
9 PR17 +3VS 2
PR28
1 4 OT2 RHYST2 5
100K_0402_1%_NCP15WF104F03RC
GND 100K_0402_1% G718TM1U_SOT23-8
8 1 2
+3VALW

2
8 6.49K_0402_1%
7 7
6 6 <5,43> H_PROCHOT#
5 5
4 4 Place clsoe to EC pin @ PQ5
3 3

1
D
2 2 1 2 BATT_TEMP BATT_TEMP <43> SSM3K7002FU_SC70-3
1 1 2
2

2
PR18 G
1K_0402_5% PC10 S

3
PD6 .1U_0402_16V7K

m
PJSOT24C_SOT23-3 2 1 2 1 ADP_I <43,48>
@ PR20 @ PR21
1 2 EC_SMB_CK1 <43> 47K_0402_1% 10K_0402_1%
1

1
C PR19 C
100_0402_5% @ PR23

1 2 EC_SMB_DA1 <43> 10K_0402_1%

2
ru
PR22
100_0402_5%

Fo
PQ6
TP0610K-T1-E3_SOT23-3

B+ 3 1
B+_BIAS
100K_0402_1%

0.22U_0805_16V7K
1

1
PR24

@ PC11

@ PC12

0.1U_0603_25V7K
2

er
2

+5VALWP 1 2
B B
PR25
2

22K_0402_1%

PR26
100K_0402_1%
1

D
yb
1

1 2 2 PQ7
<15,49> SPOK
.1U_0402_16V7K

G SSM3K7002FU_SC70-3
PR27 S
3
1

@ PC13

0_0402_5%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
Date: Monday, April 11, 2011 Sheet 55 of 56
5 4 3 2 1
 5 4 3 2 1

PAD-OPEN 2x2m~D
PJP901
2 1
D D

@ PQ901

P5103EMG_SOT23-3 4.7UH_PCMC063T-4R7MN_5.5A_20%
PL901

D
SW
+INVPWR_B+ 3 1 1 2 2 1
+LG_VOUT

10_1206_1%
0.1U_0603_25V7K

2.2U_0805_25V6K

2.2U_1206_50V7K

2.2U_1206_50V7K

0.1U_0603_50V7K

0.1U_0805_50V7K
PD901

1
PR901
B160-13-F_SMA2

G
2

1
1

220P_0603_50V8J
PC901

@ PC902

PC903

PC904

PC905

PC906
2

2
.ru
2

1 2

PC907
91K_0402_1%

2
PR902
1 2

510_0402_1% 0.1U_0603_50V7K
C
PR903 PC908 C

m
1 2 1 2

0.001U_0402_50V7M~D
@ PC909

29

28

27

26

25

24

23

22
1 2

GND

GND

GND

GND

AGND
TP

COMP
FSET
1U_0603_25V6K 11K_0402_1%
PC910 PR904

ru
10K_0402_1% 2 1 1 21 1 2
PR905 REGOUT ISET

<34> DISPOFF# 1 2 2 EN PGND3 20

3 PGATE PU901 PWM 19

+INVPWR_B+ 4 TB62758FTG_VQON24_3P8X3P8 18
VIN OUT6 FB4 <34>
1000P_0402_50V7K

2.2U_0805_25V6K

Fo
5 MONITOR OUT5 17
1

1
PC911

FB3 <34>
PC912

6 PGND1 OUT4 16
2

7 NC OUT3 15 FB2 <34>

PGND2
VOUT

OUT1

OUT2
SW

NC

NC
B FB1 <34> B

10

11

12

+INVPWR_B+ 13

+INVPWR_B+ 14
er
+LG_VOUT
+3VS
PR906 PR908
60.4K_0402_1% @0_0402_5%

SW
1 2 1 2
5

PD902 PR909
yb
@RB751V-40_SOD323-2 @1.1K_0402_1%
P

<34> INVTPWM 1 2 1 2 2 I O 4
NC 1
G
2

PU902
3
1

PR907 PC913 TC7SZ17F_SOT23-5

1
@100K_0402_1% .001U_0402_50V7-M PC914
@0.015U_0402_16V7K
2
1

2
C

A A

Security Classification Compal Secret Data

Issued Date 2009/08/23 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-LED Converter
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DB-806P
Date: Sunday, April 10, 2011 Sheet 56 of 56
5 4 3 2 1