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Janakiraman V
Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology Madras
Chennai
September 3, 2018
◮ Switch Model
◮ Transfer Characteristics
◮ Switching Threshold
◮ Noise Margin
◮ Supply Voltage Scaling
◮ Propagation Delay
◮ Power
◮ Dynamic
◮ Short circuit
◮ Leakage
VDD
0 → VDD − VT n 0 → VDD
VDD
IDSp = −IDSn
VGSn = Vin
VGSp = Vin − VDD
VDSn = Vout
VDSp = Vout − VDD
Vin = 0.7VDD
Vin = 0.4VDD
Vin = VDD Vin = 0
Vout
Figure: Solid lines- NMOS, Dashed lines - PMOS
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 6/37
Voltage Transfer Characterisitcs
Vout
CL
1 2 3 4 5 Vin
Vout
CL
1 2 3 4 5 Vin
IDSp = −IDSn
VGSn = Vin
VGSp = Vin − VDD
VDSn = Vout
VDSp = Vout − VDD
Vin = Vout
Vout
Vin = VOut = VM
Increasing r
Vin
Wp
Ratio of Wn
determines VM
VOH
VOH
NMH
VIH
VOL
VIL VIH Vin VIL
NML
VOL
VM
VIL Vin
VIH
no−clm
IDSn = IDSn (1 + λn Vout )
no−clm
IDSp = IDSp (1 + λp (Vout − VDD ))
1 kn VDSATn + kp VDSATp
g =−
ID (VM ) λn − λp
1+r
g≈
(VM − VTn − VDSATn /2)(λn − λp )
kp VDSATp
r=
kn VDSATn
Rp
Vin Vout
Rn
CL
◮ The high and low logic levels are VDD and GND(0)
◮ Logic levels are independent of sizes - Ratioless Logic
◮ Low output impedance (kΩ) - Immune to noise
◮ Large input impedance - Infinite fanout
◮ No conduction path from supply to ground in steady state
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 17/37
Switch Model Dynamic Behaviour
Vin ↓ 0 Vin ↑ VDD
Rp
Rn
CL CL
τrise = Rp CL
τfall = Rn CL
Vin Vout
Vin Vout
tpHL tpLH
CL
t
Figure: Delay
tpHL = Reqn CL
tpLH = Reqp CL
Reqn + Reqp
tp = CL
2
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 20/37
Transistor Sizing - Symmetric delay
◮ Rising propagation delay should be identical to falling
propagation delay.
◮ This also ensures a symmeteric VTC
tpHL = tpLH
Reqn = Reqp
CL VDD CL VDD
=
2IDSATn 2IDSATp
W n µn = W p µp
Wp ≈ 2Wn
Reqn + Reqp
tp = CL
2
α
tp = (0.5)[(1 + β)(Cgn2 + Cdn1 ) + Cwire ]Reqn (1 + )
β
Reqp Wp
α= @Wp = Wn ; β =
Reqn Wn
∂tp
=0
∂β
s
Cwire
βopt = α 1 +
Cdn1 + Cgn2
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 22/37
Power Dissipation
Rp
Rn
CL CL
L↑H
Z ∞
EVDD = iVDD (t)VDD dt
0
Z ∞
EC = iVDD (t)Vout dt
0
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 24/37
Dynamic Power
L↑H
Z ∞
EVDD = iVDD (t)VDD dt
0
Z ∞
dvout
EVDD = CL VDD dt
0 dt
Z VDD
EVDD = CL VDD dvout
0
2
EVDD = CL VDD
2
CL VDD
EC =
2
2
Pdyn = CL VDD f0→1
2
Pdyn = CL VDD P0→1 f
ON Isubp
0 VDD VDD 0
Isubn ON
0 VDD 0 I1
0
VX
0 VDD I2
0
VGS = 0
MANUFACTURING
Le
M EAS
ID,2
M EAS
ID,3
NA
WAFER : 200mm (8 in) or 300mm (12 in)
SIMULATION
SHOULD MATCH
IDSIM
M EAS
ID,1
M EAS
ID,2
CHIP 1
CHIP 2
M EAS
ID,1
M EAS
ID,2
SAME
FAST N
M EAS
IDP,2
SLOW N
CHIP 1
SLOW P
CHIP 2
FAST P
M EAS
IDN,1
M EAS
IDN,2
2N + 1 Inverters
TP
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 35/37
Ring Oscillators
2N + 1 Inverters
EN
TP
TP ≈ 2x(2N + 1)τinv