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Faizah Amir
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2/24/2014
When Vin is high and equal to VDD, the NMOS transistor is ON, while the
PMOS is OFF. A direct path exists between Vout and the ground node,
resulting in a steady-state value of 0V.
When the input voltage is low (0 V), NMOS transistor is OFF, while PMOS
transistors in ON. A direct path exists between VDD and Vout, resulting in a
steady-state value of VDD.
CMOS Properties
1. High noise margins : output high level = VDD
output low level = 0V
2. Ratioless gate – gates will work correctly for any ratio of
PMOS size to NMOS size , so the transistors can be minimum
size.
3. Low output impedance (output resistance in kΩ range) which
makes it less sensitive to noise and disturbances.
4. Extremely high input resistance (MOS transistor gate is a
virtually perfect insulator and draws no dc input current.) ⇒
large fan-out.
5. Low static power consumption because no direct path exists
between the supply and ground rails under steady-state
operating conditions .
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IDSp = -IDSn
VGSn = Vin ; VGSp = Vin - VDD
VDSn = Vout ; VDSp = Vout - VDD
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We can see
the precise
switching
Logic ‘0’ output
between ON
and OFF.
We cannot
see the precise
switching
between ON
and OFF.
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2/24/2014
CMOS INVERTER
Switching Threshold
VM , The switching
Vout = Vin threshold is defined as the
point where the intersection
of the VTC curve and the
line given by Vout = Vin.
At switching threshold,
Vin= Vout= VM
CMOS INVERTER
Input Low Voltage, VIL
Noise Margin – VIL is at point ‘a’ on the plot where
the slope dVin/dVout = -1
– Vin such that Vin< VIL= logic 0
●a
Input High Voltage, VIH
– VIH is at point ‘b’ on the plot where
the slope dVin/dVout = -1
– Vin such that Vin> VIH= logic 1
Noise Margin
– measure of how stable inputs are
with respect to signal interference
●b – NMH= VOH -VIH
– NML= VIL-VOL
– large NMH and NML is desired for
noise immunity :
Typical inverter transfer characteristics
NMH = VDD –VIH
NML = VIL - 0
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NOISE MARGIN
NOISE MARGIN
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CMOS INVERTER
Effect of Transistor Size on VTC
When designing static CMOS circuits, it is advisable to
balance the driving strengths of the transistors by
making the width of the PMOS two or three times
than the width of NMOS .
Ideally :
CMOS INVERTER
Effect of Transistor Size on VTC
If :
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2/24/2014
CMOS INVERTER
Impact of process variation on VTC Curve
The “good” transistor has:
smaller oxide thickness
smaller length
higher width
smaller threshold voltage
Conclusion:
The variations cause a small shift
in the switching threshold, but that
the operation of the gate is not
affected.
Process variations (mostly) cause a
shift in the switching threshold.
CMOS INVERTER
Impact of process variation on VTC Curve
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CMOS INVERTER
Impact of supply voltage scaling
• The inverter characteristic can still
be obtained although the supply
voltage is small (not even large
enough to turn the transistors on.)
• How does this happen?
Because of sub-threshold
operation of the transistors.
The sub-threshold currents are
sufficient to switch the gate
between low and high levels,
and provide enough gain to
produce acceptable VTCs.
• However, the very low value of the
switching currents will slow down
the operation of the transistor.
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Intrinsic Capacitances
Intrinsic Capacitances
Overlap Capacitance
CGS(overlap) = Cox W LD
CGD(overlap) = Cox W LD
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Intrinsic Capacitances
Intrinsic Capacitances
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Intrinsic Capacitances
Intrinsic Capacitances
Source Junction View
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Extrinsic Capacitance
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Summary
1. When designing static CMOS circuits, the width of PMOS
must be made two or three times than the width of NMOS
in order to obtain symmetrical switching threshold, VM and
noise margin.
2. The variations of NMOS and PMOS in CMOS cause a small
shift in the switching threshold, but that the operation of the
gate is not affected.
3. The inverter characteristic can still be obtained although the
supply voltage is scaled down, as long as the minimum
supply voltage is higher than thermal voltage
4. Parasitic capacitances slower the switching speeds
=>Bigger capacitance means more charges are needed to change
voltage.
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