Karnatak Law Society's

Vishwanathrao Deshpande Institute of Technology, Haliyal

DEPARTMENT Electronics and Communication Engineering

CLASS Sixth Sem B div/ Parallel Batch
NAME OF FACULTY Prof. Deepak Sharma
SUBJECT AND SUBJECT CODE VLSI Design, 17EC63/15EC63
MODULE No. Module-5:
LESSON NO. Lesson number 1, System timing Considerations

Topics covered in previous class The concept and analysis of circuits based on PLA,
drawing stick diagram and layout of the same was
taken as an example of structured design.

Topics planned to be covered in - Introduction

the present class - System timing Considerations
Bloom’s Level : L3

Introduction:
The question of data storage is an important one after designing the subsystems/ any
system. It raises the question of the choice of storage elements or memory cells as well as
the questions of configuring arrays of such cells and the selection of a given cell or group of
cells in an array. Some ground rules should be established so that a uniform approach to
'reading, writing and refreshing the memory is set.

SYSTEM TIMING CONSIDERATIONS

1. A two-phase non-overlapping clock signal is assumed to be available, and this clock
alone will be used throughout the system.
2. Clock phases are to be identified as φ1 and φ2 where φ1 is assumed to lead φ2.
3. Bits (or data) to be stored a),"e written to registers, storage elements, and subsystems on
φ1 of the clock; that is, write signals WR are Anded with φ1.
4. Bits or data written into storage elements may be assumed to have settled before the
immediately following φ2 signal, and φ2 signals may be used to refresh stored data where
appropriate.
5. In general, delays through data paths, combinational logic, etc. are assumed to be less
than the interval between the leading edge of φ1 of the clock and the leading edge of the
following φ2 signal.
6. Bits or data may be read from storage elements on the next φ1 of the clock; that is, read
signals RD are Anded with φ1• Obviously, RD and WR are generally mutually exclusive to
any one storage element.
7. A general requirement for system stability is that there must be at least one clocked
storage element in 'series with every closed loop signal path.

SOME COMMONLY USED STORAGE/MEMORY ELEMENTS

In order to make a comparative assessment of some possible storage elements, we will
consider the following factors:
• area requirement;
• estimated. dissipation per bit stored;
• volatility.
Summary of the topics covered We have studied about the introduction of
memory cell. Calculations of area, power
dissipation and volatility based on different
circuits.

Applications/significance/Import Memory is a storing device, used in every

ance of today’s topics covered processor and controller.

Questions for practice/ 1.Explain 3T DRAM cell with circuit & stick diagram
Assignment (from course file) 2. Explain the 1T dynamic memory cell with schematic and
stick diagram emphasizing 3 plate capacitor

Additional learning tools Basic VLSI Design by Pucknell by Pucknell and

Books with Page No.s/NPTEL Eshraghian, 3rd edition, page number 235
course reference with
link/Relevant video lecture link