Fault Models PDF

Fault Models
1
Design for Reliable Data Processing and Storage M Cecilia Metra
Fault Models: Summary
 Fault Models:
 Stuck-at (SA)
 Transistor Stuck-On (SON)
 Resistive Bridging (BF)
 Delay faults (DF)
 Crosstalk (CF)
 Transistor Stuck-Open (SOP)
 Transient faults (TF)
 Fault equivalence & fault collapsing
 Fault dominance & fault collapsing
2
Fault Models
 Goal: to reduce the numerous multiplicity of
physical defects to a more limited number.
 Idea: to target not the physical defect itself, but its

effect on the circuit behavior (static and/or
dynamic)
Introduction of fault models, which become the

testing target
3
Stuck-At (SA) Faults
 STUCK-AT Fault (model): Describes all physical
defects whose effect on the IC behavior is to make
it behave as if one of its lines/nodes were stuck-at
the high (stuck-at 1), or low (stuck-at 0) logical
value.
4
Convention
 We talk about “stuck-at faults, etc” referring to all
physical defects describable by the stuck-at fault
model, etc.
 Example:
 Testing is thus oriented to detect the possible

presence of stuck-at faults, ecc.
5
Single Stuck-At Faults
 The fault can be on each possible node/line of the
IC.
 The fault can be of the SA1 or SA0 kind.
 Example: 12 possible fault locations ( ) = 24
(single) SA
Incorrect Value
Correct Value
c j
0(1)
SA0
a d 1(0)
g h
z
1 i
b e 1
f k
Courtesy of V. D. Agrawal, Agere (USA)
6
Multiple Stuck-at Faults
 Multiple SA fault = single SAs simultaneously

present.
A single SA may be not detected due to the

presence of another single SA => masking
phenomenon
 Statistically,
tests for single SAs can detect also a
high number of multiple SAs.
7
IC Testing
 The (traditional) testing methodology for an IC
consists in :
1. apply a proper sequence of test vectors able to:
 activate each fault
 propagate the fault effects to the IC primary
outputs
2. Compare the produced outputs with those
expected for the fault-free IC.
 If the produced outputs are different from the

expected ones, then the IC is faulty.
8
IC Testing: Basic Principle
Courtesy of V. D. Agrawal, Agere (USA)
These steps are performed with the help of an

Automatic Test Equipment (ATE).
9
Testing for SAs: Example (I)
 Activation:(A,B)=(1,1)  W1=1, rather than W1=0

 Propagation: (C,D)=(0,0)  W2=1  OUT=1
rather than OUT=0 output logic error
10
Testing for SAs: Example (II)
h stuck-at 0
 Possible test vector (activation + propagation):
(a, b) = (1, 0)
Erroneous value
Correct value
c j
0(1)
SA0
a d
1 g h 1(0)
z
0 1 i
b e 1
f k
Example test vector h SA0 Courtesy of V. D. Agrawal, Agere (USA)
11
Fault Equivalence & Fault Collapsing
 Fault Equivalence: two faults f1 and f2 are equivalent

if all tests which detect f1 detect also f2.
 If faults f1 and f2 are equivalent, then the

correspondent incorrect functions are equal.
 Fault collapsing: All single faults of an IC can be

grouped in disjointed equivalence sets, such that all
faults in a set are mutually exclusive => single fault
for each set.
12
Equivalence: Example
sa0 sa0
sa1 sa1
sa0 sa1 sa0 sa1 WIRE
sa0 sa1 sa0 sa1
AND OR
sa0 sa1 sa0 sa1
sa0 sa1
NOT
sa1 sa0
sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0
NAND NOR
sa1
sa0
sa0 sa1 sa0 sa1
sa1
sa0
FANOUT sa1
13
Fault Collapsing: Example
Faults in cyan
can be eliminated by
Equivalence &
sa0 sa1
sa0 sa1 Collapsing
sa0 sa1
sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32 14
Fault Dominance &
Fault Collapsing
 If all tests for a fault f1 detect also fault f2, then f2

dominates f1.
 If two faults dominate each others, then they are

equivalent.
 Fault collapsing: if f2 dominates f1=> f2 can be

removed from the fault list.
15
Dominance: Example
F2 dominates F1
Test per F2  F2 removed
F1
s-a-1 001
F2
s-a-1 110 010
000
101 011
100
s-a-1 Test for F1

s-a-1 s-a-0
s-a-1
Test set to be considered after fault collapsing

(for equivalence and dominance). 16
Resistive Bridging (BF) Faults
 Describes all physical defects whose effect on the IC behavior
is to make it behave as if two of its lines/nodes were shorted
together through a resistive path, with a resistance equal to the
bridging fault one.
 Physical defects describable by this model can be undesired

shorts between two metal lines, active areas, etc.
 Depending on the physical defect to be described, a different

value of R has to be considered (for a good correspondence of the
model to the physical defect).
17
Effects due to BFs
In a CMOS IC, when a BF is activated  conductive
path between power supply and ground.
Thus:
 static current absorbed from the circuit;

 intermediate voltage values (X) on the nodes/lines
involved by the fault, which depend on the
conductances of the involved networks and the BF
resistance value.
18
Testing for BFs
 It is possible to detect the presence of the fault by:
 Measuring the static current flowing through the

IC (IDDQ testing);
 Comparing the produced output logic value and

the expected one, if the produced intermediate
voltage value lays, with respect to the logic
threshold of the fan out gate, on the opposite side
of the expected logic value.
19
Testing for BFs: Example
 Example Test vector: (IN1,IN2)=(1,1) :

 IDDQ  0
 V(Z) = VX = f (R), 0 < VX < VDD 0  Logical
error for R  1.8 k
20
Transistor stuck-on (SON) Faults
 TRANSISTOR STUCK-ON Fault (model): Describes all
physical defects whose effect on the IC behavior is to
make it behave as if one of its transistors were always
ON (independently of the value of its gate voltage).
 Transistor stuck-on faults can be considered like
particular resistive bridging faults.
 In a CMOS circuit, when a SON is activated 
conductive path between power supply and ground 
 Static current absorbed by the circuit
 “Intermediate” output voltage value (X) of the faulty
gate, depending on the ratio between the
conductances of the networks erroneously ON (due to
the fault), and correctly ON. 21
Testing for SONs
 It is possible to detect the fault by:
Measuring the IC static current (IDDQ testing)
Comparing the produced output logic value

with the expected one, if the produced
intermediate voltage value lays on the opposite
side of the expected value, with respect to the
logic threshold of the fan out gate.
22
Detection Problems for SONs and BFs
 Since the detectability of transistor stuck-on and
resistive bridging depends on conductance ratios,
some faults are not detectable as logical errors.
 Static current measurements can detect the faults,

but limit the frequency at which testing can be
performed, since all transients should be
extinguished prior to current measurement.
 Additionally, they become useless with technology

scaling.
23
Transistor Stuck-Open (SOP) Faults
 Describes all physical defects whose effect on the IC

behavior is to make it behave as if one of its
transistors were always OFF (independently of the
value of its gate voltage).
 In a CMOS circuit, when a SOP is activated 

output in a high impedance state.
 Thus, SOPs make a combinational circuit behave as

if it were a sequential circuit.
24
Open Cause Defect: Example (I)
Courtesy of Jerry Soden, Sandia Lab (USA)

25
Open Cause Defect: Example (II)
Courtesy of Jerry Soden, Sandia Lab (USA)

26
Testing for SOPs
Two test vectors are needed:
The former (namely the initialization one)
initializes the gate output at a logical value opposite
to that driven by the network including the faulty
transistor
The latter (namely the activation one) activates the
fault, trying to remove the initialization value
through a conductive path including the faulty
transistor  output logic error  fault detection
27
Testing for SOPs: Example (I)
 Example sequence of 2 test vectors : (IN1,IN2)=(1,1), (1,0)

 Fault free case: Z=0  1
 Faulty case: Z=0  0  fault detection
 Example sequence of 2 test vectors : (IN1,IN2)=(0,0),(1,0)
 Fault free case: Z=1  1
 Faulty case: Z=1  1  fault not detected
28
Testing for SOPs: Example (II)
VDD
A
1 0
Stuck-
open
0 0
B
C
0  1(0)
Circuit OK
Faulty Circuit
29
Delay Faults
 Describes all physical defects whose effect on the IC
behavior is to affect its dynamic characteristics.
Particularly, there are two delay fault models:
 gate delay (transition fault): represents those

delay faults that affect the rising/falling time of
the input/output signal of a gate;
 path delay: represents those delay faults that,

affecting signal propagation delays accumulating
through a signal propagation path, make the IC
violate its timing constraints. 30
Crosstalk (CT) Faults
 Describes all physical defects whose effect on the

IC behavior is to make it behave as if two or more
of its lines were capacitively coupled.
 Possible model (for 2 lines) :
 The undesired capacitive coupling is described by

the mutual capacitance C12
31
Effects due to CTs
 Case of a CT between two lines such that, in the case of fault
absence, the signal on one line (e.g. s1) has a transition, while
that on the other line (e.g. s2) is stable
 EFFECT:
 Delayed transition of s1 and undesired transition of s2
 Case of a CT between two lines, whose signals, in the absence

of faults, have both transitions
 EFFECT:
 If transitions in the same direction  anticipated
transitions
 If transitions in opposite directions  delayed
transitions
32
Interconnect Scaling and CTs
High H/W (2-2.2) ratios   lateral coupling capacitance
with respect to the substrate capacitance   crosstalk 
impact on performance.
 The highest C is among parallel lines at the same metal
layer.
R. Kumar, Int.Techn.J, Q1 - 2001 33

Interconnect Scaling, CTs and Performance
 Reduction of the # long lines (in M5) (despite > chip
dimensions)  fundamental to  performance.

Wide use of
Repeaters:
Example

 To reduce CT impact  to increase line spacing, or to
use schields.

Transient Faults (TF)
 Describes all physical defects whose effect is to

cause the (undesired) occurrence of a fast
transition (spike or glitch) on a signal line.
 Faults of this kind are generally due to

radiations,  particles.
37
Radiations and Alpha Particles
 Radiative decay of Uranium and Thorium
impurities present in packages  generation of Alpha
particles (= Helium atoms which lost the electrons).
E.g., the Thorium 232 decays generating Radium

228 + Alpha particles.
 Cosmic Rays (usually neutrons emitted from the

sun).
38
Radiations and Alpha Particles (cnt’d)
Alpha particle (neutron) hitting the Si  penetration
in the Si and generation of electron – hole coupes 
droop of energy along the path.
The penetration depth is a function of the initial
energy and of the material and circuit characteristics.
 Distortion of the depleted region (funneling). 
Change of the charge in the n+ zone

p n+
39
Radiations and Alpha Particles (cnt’d)
 If the Alpha particle penetrates in a region
interested by an electric field (e.g., the depleted region
of the a pn junction)  generation of e– hole couples:
e- go (for transport) towards the region at higher

potential
the holes go (for transport) towards the region at

lower potential
Change of the state of charge in the

depleted region and potential change.
40
Alpha Particle Energy
 The emitted Alpha particles usually have energies of
4-5 MeV.
[Baumann2001] 41
Cosmic Rays and Altitude
 The sensitivity to cosmic rays increases with the
altitude.
[Ogorman94] 42
Fault Probability
 It has been verified that the the most likely faults in VLSI
CMOS ICs (for general applications) are:
 stuck-at
 transistor stuck-on and resistive bridging
 delay
 stuck-open
 Transient faults are the most likely for VLSI CMOS ICs
for space and avionic applications.
 Crosstalk and transient faults are very likely for VLSI
CMOS ICs implemented by technologies below 0.1m
(Very Deep Sub-Micron (VDSM) technologies) also for
general applications
43
Faults Affecting Memory Arrays
44
Review of Memory Operation
Address
 Cells to be read/written
Column Decoder
are selected by
activating their row and
column, by decoding the
address bits
Decoder
Memory
Row
Memory
Cell Array
Cell Array
Once the cells are selected:

Address  For read operations
Decoder (R/#W Enable = 1)
Read/Write
Sense Write
Drivers  the content of the
Logic
Amp
selected cells is
R/#W read by the sense
Data Registers amplifiers and
Enable
transferred to the
Data out/in data registers 45
Review of Memory Operation (cnt’d)
Address
 Cells to be read/written
Column Decoder
are selected by
activating their row and
column, by decoding the
address bits
Decoder
Memory
Row
Memory
Cell Array
Cell Array
 Once the cells are selected:
Address  For write operations
Decoder (R/#W Enable = 0)
Read/Write
Sense Write
Drivers  the content of the
Logic
Amp
data registers is
R/#W written into the
Data Registers selected cells by
Enable
the write drivers
Data out/in 46
Faults Affecting Memory Arrays [1]
 Stuck-At Faults (SAs)
 Effect: the logic value of a cell, or a line, is SA0 or 1
 Transition Faults (TFs)

 Effect: a cell, or a line, that fails to undergo a 01 or a
10 transition
 Coupling Fault (CFs)

 Effect: a write operation to one cell changes the
content of a second cell (usually an adjacent cell)
[1] A. Van De Goor, “”, IEEE Design and Test of computers, 2003. 47
Faults Affecting Memory Arrays [1] (cnt’d)
 Data Retention Faults (DRFs)
 Effect: the stored logic value in a cell is lost after a certain
period of time during which the cell is not accessed.
 Address Decoder Faults (AFs)

 Refers to any fault affecting the address decoder and
generally cause one of the following effects:
Given an address, no cell is accessed
Given an address, multiple cells are simultaneously
accessed
A given cell is accessed by more than a single address
[1] A. Van De Goor, “”, IEEE Design and Test of computers, 2003. 48

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Fault Models

 Idea: to target not the physical defect itself, but its

Introduction of fault models, which become the

 Testing is thus oriented to detect the possible

 Multiple SA fault = single SAs simultaneously

A single SA may be not detected due to the

 If the produced outputs are different from the

Courtesy of V. D. Agrawal, Agere (USA)

These steps are performed with the help of an

 Activation:(A,B)=(1,1)  W1=1, rather than W1=0

 Fault Equivalence: two faults f1 and f2 are equivalent

 If faults f1 and f2 are equivalent, then the

 Fault collapsing: All single faults of an IC can be

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

 If all tests for a fault f1 detect also fault f2, then f2

 If two faults dominate each others, then they are

 Fault collapsing: if f2 dominates f1=> f2 can be

s-a-1 Test for F1

Test set to be considered after fault collapsing

 Physical defects describable by this model can be undesired

 Depending on the physical defect to be described, a different

 static current absorbed from the circuit;

 It is possible to detect the presence of the fault by:

 Measuring the static current flowing through the

 Comparing the produced output logic value and

 Example Test vector: (IN1,IN2)=(1,1) :

 It is possible to detect the fault by:

Measuring the IC static current (IDDQ testing)

Comparing the produced output logic value

 Static current measurements can detect the faults,

 Additionally, they become useless with technology

 Describes all physical defects whose effect on the IC

 In a CMOS circuit, when a SOP is activated 

 Thus, SOPs make a combinational circuit behave as

Courtesy of Jerry Soden, Sandia Lab (USA)

Courtesy of Jerry Soden, Sandia Lab (USA)

 Example sequence of 2 test vectors : (IN1,IN2)=(1,1), (1,0)

 gate delay (transition fault): represents those

 path delay: represents those delay faults that,

 Describes all physical defects whose effect on the

 The undesired capacitive coupling is described by

 Case of a CT between two lines, whose signals, in the absence

R. Kumar, Int.Techn.J, Q1 - 2001 33

R. Kumar, Int.Techn.J, Q1 - 2001 34

R. Kumar, Int.Techn.J, Q1 - 2001 35

R. Kumar, Int.Techn.J, Q1 - 2001 36

 Describes all physical defects whose effect is to

 Faults of this kind are generally due to

E.g., the Thorium 232 decays generating Radium

 Cosmic Rays (usually neutrons emitted from the

Change of the charge in the n+ zone

e- go (for transport) towards the region at higher

the holes go (for transport) towards the region at

Change of the state of charge in the

 Transition Faults (TFs)

 Coupling Fault (CFs)

 Address Decoder Faults (AFs)

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