A Q-Enhanced LC Bandpass Filter using CAIRO+

Diomadson Belfort1 , Nicolas Beilleau1 , Hassan Aboushady1 , Marie-Minerve Louërat1 and Sebastian Catunda2
1 University Pierre & Marie Curie, LIP6 Laboratory, Paris, France
2 Federal University of Maranhão - UFMA, Department of Electrical Engineering, São Luı́s, MA, Brazil

Abstract—In this paper, we present a systematic design proce- intrinsic resistance of the employed metal, interconnections,
dure for Q-enhanced integrated LC filters, which does not require skin effect at high frequencies and lossy substrate.
any simulations and is thus suitable for design automation. The The inductor with these parasitics can be modeled in
design procedure has been described in the CAIRO+ analog
design environment, containing the BSIM3v3 models of the MOS function of the inductor layout and material parameters using
transistors. Precise estimations of the quality factor and the the π-model shown in Fig.2, where RS represent the total
resonance frequency were made possible by adding the integrated loss in the inductor, CSub is the capacitance between the
inductance π-model into the design environment. Several design trace and the substrate and RSub is the substrate loss [7].
examples of 2.4 GHz Q-enhanced LC filters are given in a 0.13 To enhance the quality factor, we have to insert an active
µm CMOS process.
negative resistance in series [8] with the lossy inductor or a
I. I NTRODUCTION series-to-parallel impedance transformation can be performed
Advances in highly integrated wireless communication on the lossy inductor and a negative resistance can be added
transceivers provide applications for integrated RF bandpass in parallel mode [9] as shown in Fig.3.
filters. Active filters can achieve a high quality factor but with In this work the parallel solution was used.
a poor dynamic range when operating at gigahertz frequencies. As shown in Fig.4, we transform this π-model to a parallel
Passive LC filters can achieve high dynamic range at very model.
low power consumption but on-chip inductors have very low In this case we take:
quality factor Q. Q-enhanced LC filters are a good compromise Rpl = RS (1 + Q2rl ) Rpc = RSub (1 + Q2rc )
between these two types of filters [1]. Q-enhanced LC filters
are not only used to realize integrated RF bandpass filters Q2rc 1 + Q2rl
Cp = CSub Lp = LS
[2] but they are also used in the design of RF bandpass Σ∆ 1 + Q2rc Q2rl
modulators [3], [4]. Fig.1 presents a popular implementation Rp = Rpl //Rpc (1)
of a Q-enhanced LC filter using a differential negative resistor.
1 ω0 LS
The design of such a circuit usually requires a significant Qrc = Qrl =
amount of simulation iterations with a SPICE-like circuit ω0 RSub CSub RS
simulator. where
In this work, we propose a systematic design procedure for Qrc is the quality factor of the series-RC circuit;
a Q-enhanced LC filter that provides the desired quality factor Qrl is the quality factor of the series-RL circuit;
and resonance frequency and does not require any iterations Rpl is the resistance in parallel-RL circuit equivalent to
with a circuit simulator. In this procedure, the quality factor the series-RL circuit;
and the resonance frequency of the LC filter are calculated Rpc is the resistance in parallel-RC circuit equivalent to
using the π-model for the inductor and the BSIM3v3 models the series-RC circuit;
for the transistors. The design procedure is described in the Cp is the capacitance in the parallel-RC circuit equiva-
analog design environment CAIRO+ [5]. lent to the series-RC circuit;
In section II-A, we present the procedure used to size the Lp is the inductance in the parallel-LC circuit equivalent
transistors of the negative resistance based on the estimation to the series-LC circuit.
of the quality factor of the original lossy LC tank. In section Then we can replace the π-model by a RLC bridge with Rp
II-B, it is shown how the resonance frequency is adjusted resistor, Cp capacitor and Lp inductor. From the parallel re-
based on a empirical model [6] and accurate estimation of sistor and parallel capacitor, the quality factor of the resonator
the transistors parasitic capacitance. The complete design can be derived as:
automation procedure is presented in section III. Comparisons s
between predicted performances and simulation results for CPC + Cp
Q0 = Rp (2)
several design examples are given in section IV. Lp
II. D ESIGN M ETHOD I NCLUDING PARASITICS where CPC is the capacitance needed to adjust to resonance
A. Quality Factor Enhancement frequency. The effective quality factor can be found from [9]
as
Due to its nature, an integrated inductor presents some Q0
Qenh = (3)
parasitics resistances and capacitances. Resistances are due to 1 − Gm0 Rp

978-1-4244-5091-6/09/$25.00 ©2009 IEEE 860

 Vdd iin

CSub Ls

C PC CP c -1/Gm0
C PC
RSub Rs
Iin+ Iin-
L π-model

Fig. 3. LC filter with Q-enhancement

M1 M2
Lp
Lp
Rs Ls Rpl
Vbias M3 Rp

Rsub Csub Cp Cp

Rpc
Fig. 1. Q-enhanced LC filter with differential negative resistance.

Fig. 4. π-model to parallel model transformation in small signal.

where Gm0 is the equivalent transconductance of the differ-

ential negative resistance. So, choosing an appropriate value
for Gm0 one can improve the value of the quality factor of are easily obtained from the transistors BSIM3v3 model. Csub
the original lossy LC tank from Q0 to a desired quality factor is extracted from the inductor π-model. Both models are
Qenh . Gm0 is calculated using the approximations: integrated, available in the CAIRO+ design environment.
Gm0 = Gm − Gds (4) III. D ESIGN AUTOMATION AND P ERFORMANCE
E VALUATION
where Gm and Gds are respectively the transconductance
and the output conductance of transistor M1 Fig.1. In the A. CAIRO+ Design Environment
CAIRO+ analog design environment, it is possible to perform CAIRO+, is a framework, developed at the LIP6 laboratory,
an accurate sizing of a transistor in order to obtain a certain which aims to help analog circuit designers to describe their
transconductance Gm . Once the dimensions of the transistor design procedure [5]. It provides a library of functions to
are known, it is also possible to extract accurate value of Gds . describe the netlist template, layout template, specification
A few iterations are then required to size transistors M1 and template, design space exploration procedure and layout gen-
M2 according to the required overall Gm0 of the differential eration. The general method in CAIRO+ is to design modules
negative resistance. using devices. Each module has a list of defined parameters,
and one or more procedures. In the case of designing a
B. Resonance frequency
bandpass Q-enhanced LC filter, the input parameters are: the
Vdd
desired quality factor, the resonance frequency, the input bias
+
Rs Ls Ls Rs voltage, and the value of the inductor with its geometrical
Iin Iin-
parameters. The procedure will calculate and return the sizes
Csub CsubM Csub of the transistors, and the value of the capacitor, CPC , of the
resonator.
Rsub RsubM Rsub
B. Thermal Noise
The method we have implemented to compute the noise
generated by the filter is described as follows. The noise in
Fig. 2. Simplified π-model for a differential center-tapped spiral inductor. the circuit are presented in Fig. 6. The thermal noise generated
by transistors (In2M ) is computed using CAIRO+ transistor
device, which includes a procedure to compute thermal noise.
In order to calculate CPC the required capacitor value for a The thermal noise of the resonator is computed using the total
desired resonance frequency ω0 , the following relation is used: parallel resistor as approximated in section II-A so:
Cpar = Cp + Cdg + Cgd + Cgs + Cds (5) 4kT
In2R = (7)
1 Rp
CPC = − Cpar (6)
ω02 Lp Considering we have two current noise sources and that they
where Cpar is the total parasitic capacitance, due to the are uncorrelated we add the two spectral noise density to
inductor and the transistors. The MOS parasitic capacitance obtain the total current noise spectral density at the input. The

861
 Vdd Qenh Inductance Geometrical Parameters Resonance Frequency

CAIRO+

Pi Model (Fig. 2)

L,Rs,Csub,Rsub

Parallel Approximation
equ. (1)

Rp

Transconductance Computation
equ. (3) and (4)

Gmo

BSIM3v3

Noise Computation Cpar Capacitance Filter Computation

Transistors Sizing
equ. (7) and (8) equ. (6)

Output Noise Ibias Transistors Width Capacitance

Fig. 5. Q-enhanced LC filter design procedure based on Cairo+ design environment including BSIM3v3 models.

Vdd
frequency of 2.442 GHz and different quality factors (Q=30,
R
C L L C
R 60, 80). Table II shown the comparison between the perfor-
InR InR
mances calculated by CAIRO+ and the simulation results.
In Fig.7, simulation results of the impedance versus input
Iin+ Iin- frequency are presented. Effective Q and resonance frequency
can be extracted from Fig. 7. The parameters of the inductance
InM
M1 M2
InM are: 5 nH inductor (4 turns, 12 µm width and 10 µm spacing,
which give a Q0 = 15) for a 130 nm technology. The bias
conditions are : Vdd = 0.9 V, Vbias = 0.3 V. As we can see, the
Vbias M3
automatic design procedure is precise for the effective quality
factor and the resonance frequency.

Fig. 6. Thermal Noise Circuit B. Linearity

Using this systematic design procedure it is easily possible
to study the importance of the input bias voltage on the
equivalent voltage noise can be computed at the output by linearity of the filter. Several filters with different input bias
multiplying it by the total gain (the total impedance at the voltages have been designed. Their linearities can be measured
given frequency of the filter) and integrated over the useful from the output versus input power graphs (Vbias is set to
bandwidth (BW) to have the output noise power : 0.3V). In Fig. 8 we show the intermodulation distortion (IM3)
with a two-tone signal. Its also possible to measure the third-
Z
Pn = 2 |Z(jω)|2 (In2R + In2M )df . (8) order intercept point (IP3) of each filter.
BW
As shown in section IV, the approximation by a parallel C. Process Variations
resistor is sufficiently accurate for the quality factor and
The center frequency f0 of a Q-enhanced LC resonator
resonance frequency computations.
is a function of the inductance, of the capacitance of the
A flowchart of the proposed design procedure, described
spiral inductor, number of turns and connected circuitry. The
in section II-A and II-B, using the CAIRO+ environment is
inductance value is defined by inductor dimensions and is
presented in Fig.5.
IV. SIMULATION RESULTS
TABLE I
Once the filter is sized, CAIRO+ can generate the netlist file, T RANSISTORS DIMENSIONS AND CAPACITOR VALUE CALCULATED BY
CAIRO+ FOR A 130 nm TECHNOLOGY
which can be simulated. Simulations results are presented in
the following.
Q CPC (pF) M1 /M2 (W/L)µm M3 (W/L)µm
A. Quality factor and resonance frequency 30 1.519 1.21/0.13 39.5/0.13
60 1.518 1.93/0.13 60.4/0.13
In table I, the calculated transistors dimensions and the 80 1.517 2.10/0.13 65.8/0.13
values of the resonator capacitors are listed, for a resonance

862
 TABLE II
C OMPARISON BETWEEN CAIRO+ AND SIMULATION RESULTS . 50

Noise Power (Vdd=0.9)

IM3 Power (Vdd=0.9)
CAIRO Simulation Output (Vdd=0.9)

f0 (GHz) Q Pn (dBm) f0 (GHz) Q Pn (dBm) Noise Power (Vdd=0.6)

IM3 Power (Vdd=0.6)
2.442 30 -71.07 2.4422 30.15 -71.50 Output (Vdd=0.6)
0
2.442 60 -66.17 2.4404 60.29 -66.53 IP3 (Vdd=0.9)
IP3 (Vdd=0.6)
2.442 80 -64.72 2.4401 79.10 -64.97

Pout (dBm)
2.442 100 -63.63 2.4397 99.33 -63.77

−50

Noise Floor

6000 Qenh 30
Qenh 60
Qenh 80

5000
−100
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
Impedance (Ohms)

Pin (dBm) IP3 (Vdd=0.6) IP3 (Vdd=0.9)

4000

3000 Fig. 8. Input output power of fundamental, output noise floor and IM3 versus
Input power for different values of inductor biasing voltage, Vdd (Simulation
2000 results)(Fig. 1).

1000
2.36 2.38 2.4 2.42 2.44 2.46 2.48 2.5 2.52 2.54
Frequency (Hz)
x 10
9
the estimated performances of the circuits generated using the
proposed design procedure and the performances measured
Fig. 7. Total impedance for different values of Q (Simulation results). from simulation.
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In this paper, we have presented a systematic design proce- Journal of , vol.37, no.8, pp. 967-977, Aug 2002
dure for Q-enhanced LC filters using the analog design envi-
ronment CAIRO+. The procedure is based upon the inductor
π-model and the BSIM3v3 transistor’s model. Several design
examples have been presented to demonstrate the validity of
the approach. Very little difference has been observed between

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