Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
OFSOLID-STATE
CIRCUITS,
VOL.28,NO.12,DECEMBER
1993 1273
I. INTRODUCTION low supply voltages. Another issue critical to the overall preci-
RECISE delay generation is a necessary function in state- sion of the array oscillator is the method in which the various
P of-the-art single-chip testers [1]. When testing digital
integrated circuits, it is necessary to supply digital waveforms
outputs are read from the array core. Section V will present
the output channel circuits and related implementation issues,
as input, which requires accurate delays referenced to some The paper will also present experimental results demonstrating
clock signal. The delay resolution needed in order to accurately the ability of an array oscillator to produce precise delays with
measure parameters such as setup and hold times is often a resolution equal to one seventh of a buffer delay.
finer than that of an intrinsic gate delay of the device under
test. Presently, this fine delay control isobtained using higher II. RING OSCILLATORDELAY GENERATORS
speed integrated circuit technology for the tester than for the
Precise delays can be generated with ring oscillators by
device under test. A more cost-effective approach would be
taking advantage of the symmetry in a ring. Since all buffer
to limit the IC technology used for the tester to one no more
sta,ges are identical, the relationship between a buffer delay and
advanced than that used for the device under test. However,
the period is set by the number of stages. Once phase locked to
generating precise delays with significantly finer resolution
an established clock period, the delay between the ring outputs
than an intrinsic gate delay has been difficult to achieve in this
wil 1 be precisely known. Different delays can be generated
manner. This paper describes an array oscillator comprised of
by accessing different ring outputs with multiplexer. Fig.
a series of coupled ring oscillators that can achieve a delay
1 illustrates the phase relationship among individual buffer
resolution equal to a buffer delay divided by the number of
outputs. Rising transitions are indicated by dots, and falling
rings [2]. Using a 2-pm N-well CMOS technology, a delay
transitions are indicated by circles. If a ring contains five
resolution of 101 ps is achieved with a peak error of 58 ps at
differential buffers as shown, utilizing both inverted and non-
a frequency of 141 MHz.
inverted outputs, ten different output phases are available,
Because an array oscillator is based on a series of ring
which uniformly span the output period. The limitation of
oscillators, this paper will begin with a description of precise
using ring oscillators as delay generators is that the delay
delay generation using ring oscillators. The concept of a ring
resolution is limited to a buffer delay. The only way to add
oscillator will then be extended to an array oscillator in Section
more output phases is to add more buffers, which in turrt
III. This section will also include a description of the general
decreases the maximum oscillation frequency. Thus, the delay
issues related to the operation and implementation of an, array
resolution remains unchanged. Ideally, it would be desirable
oscillator. The generation of precise delays requires low-noise
to be able to add more buffers to a ring-like structure without
buffer stages to prevent an effective loss of precision due to
changing the oscillation frequency and thereby increase the
jitter in the output signals. Section IV will describe the buffer
dellay resolution to a fraction of a buffer delay.
circuit design used in an implementation of the array oscillator
for high supply noise immunity while being able to operate at
III. ARRAY OSCILLATOR
ManuscriptreceivedMay 19, 1993;revisedJuly 24, 1993.This work was
supported by the Advanced Research Projects Agency under Contract NOO039- An array oscillator is a structure based on a series of
91-C-0138. coupled ring oscillators. By coupling several rings together it
The authors are with the Center for Integrated Systems, Stanford University,
Stanford, CA 94305.
is possible to break the dependence of the oscillation frequency
IEEE Log Number 9212118. on the number of buffers. With the oscillation frequency
{ P12
IEEEJOURNAL
OFSOLID-STATE
—N—
TO
CIRCUITS,
T,
VOL.28, NO.12,DECEMBER
T2 Ts
1993
T4
h
) I
v,,
N12
Ring
= Oscillator
v~
y; :. :. :. :.
P12
V,*
{ lw2
Single-lrrput Dual-Input
1~ BO B, B2 B3 B4
from zero because of the large absolute delay between the C + 2N. Thus, the fractional delay between corresponding
ring and coupling input transitions. SPICE simulations show ring nodes in adjacent rings ~ must satisfy the inequality
that in practice the number of stable modes is typically $$,
C–N
with equally sized ring and coupling inputs. —<$<= (9)
2NM
The oscillation frequency of the array changes with coupling
factor C due to changes in the buffer delay of all buffers. for the array oscillator to enter the mode with coupling factor
Because the array will not oscillate when the delay between C after the reset operation. The reset operation is most easily
ring and coupling input transitions becomes large, a simple accomplished by switching off the bias voltages in one or more
linear model can be used to approximate how the buffer of the rings so that the array of coupled rings no longer forms
delay changes with the phase difference between the ring and a closed loop. Switching the buffer outputs is undesirable
coupling inputs. With equally sized ring and coupling inputs, because these switches would need to be added to all buffer
the buffer delay, from ring input to output, will be equal to the outputs in order to maintain the symmetry of the array, which
delay of a buffer with simultaneous ring and coupling inputs, would add excessive loadlng to the buffer output nodes. The
less one half of the time the coupling input transition occurs desired boundary conditions can then be forced on the array
before the ring input transition. Thus by adjusting the bias voltages in the first ring. Modes with
C close to zero are readily achieved with buffer stage designs
D(c) = D(o) – +3t(c) = D(o) – ;D(c); (5) based on differential pairs or current switching in general. With
these buffer stages, all of the rings in an open array tend to
oscillate in phase without any adjustment to the bias voltages
so that
in the first ring. The inactive coupling inputs on the first ring
‘CTRL
vo. — — Vo+
v~~ +
:. ::
.. ::
● ☛
::
✎ ✎
::
✎ ✎
:
●
I I I I I ~
t QE%i22!! 4
Fig. 7.
Controlled
....+....ys ......==m
~......sss..==...== .......s.......\rs.sssss...s=s .....s...ssss..
............m.ss
$ v~RL \
~
I I
Flg.6. Hoorplm of themaycore, illuskating tieinterleaved buffers in boti
horizontal and vertical directions and the single buffer shift in every ring. The
numbered buffers indicate consecutive buffers along a single lQgical column.
buffer delays to be the same, the interconnect capacitance Amplifier Biaa Differential Amplifier Half-Buffer Replica
at each buffer output node must be carefully balanced. This Fig. 8. Schematic of the self-biasedreplica-feedbackcurrent source bias
requirement implies that both the buffers in each ring and the circuit.
rings in the array should be interleaved so that adjacently con-
nected buffers are separated by a single buffer and adjacently of buffers per ring and is largely independent of the number
connected rings are separated by a single ring, as illustrated of rings in the array. More output phases can be added, and
in Fig. 6. the delay resolution can be increased simply by adding rings
The interconnect capacitance at the array closing connec- to the array. In addition, the precision of the array oscillator
tions performing the shift by k buffers and at all is ideally similar to that of a simple ring oscillator.
other output nodes in the array must also be balanced. This Ile coupled-ring structure of an array oscillator addresses
problem can be solved through shifting by a single buffer only some of the issues that must be resolved to make a precise
in every ring of the array so that no shift is necessary in delay generator that has a delay resolution equal to a fraction
the interconnect at the boundary of the array. The shift is of a buffer delay. The oscillator must be able to operate over a
accomplished by connecting the coupling inputs of the buffers large frequency range and provide high supply noise immunity.
in one ring to the ring inputs of the buffers shifted one buffer These issues must be addressed by the buffer design.
forward in the previous ring, or equivalently to the ring outputs
at the same buffer positions as illustrated in Fig. 6. In order to IV. BUFFER DESIGN
achieve a net shift of k buffers through M rings after possibly An array oscillator can be realized with any single-ended or
wrapping around the N buffer rings an arbitrary number of differential inverting buffer. In order to provide precision de-
times, the number of rings &f must be constrained so that lay, at high resolution, the buffer outputs must have low phase
M=yN–k (11) jitter, since phase jitter can reduce the effective precision and
resolution of any delay generator. Low phase jitter, however,
for some positive integer y. With the single buffer shift, all is difficult to achieve in the noisy environment of a digital
connecting wires travel only in the horizontal and vertical integrated circuit, as it requires high supply noise immunity.
directions between adjacent interleaved buffers in all rows and In addition, state-of-the-art digital technologies typically have
columns of the array also illustrated in Fig. 6. limited supply voltages due to thin gate oxides. The differential
buffer stage described in this section is designed to have
G. Summary high supply noise immunity while being able to operate at
In summary, in contrast to a simple ring oscillator, the array low supply voltages. The key components of the buffer stage
oscillator has achieved a delay resolution equal to a buffer design that achieve these objectives are the symmetric load
delay divided by the number of rings and a number of period ele~ments and the self-biased replica-feedback current source
divisions equal to two times the total number of buffers in the bias circuit shown in Fig. 7 and Fig. 8, respectively.
array independent of the desired oscillation frequency. The Supply noise sensitivity has both static and dynamic com-
oscillation frequency is determined primarily by the number ponents. Static supply sensitivity is dominated by the output
1278 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 12, DECEMBER 1993
1.6
resistance of the current sources used. Achieving high static r
.............................
supply rejection is typically incompatible with low-voltage i .4 -
provide for high dynamic supply rejection through a first-order 1.50 2.50
0.00 0.25 0.50 0,75 1.00 1.25 1,75 2.00 2,25
cancellation of noise coupling. v~~~ (v)
1.!2!wd
generated from the same NMOS current source bias through a
stage mirroring the half-buffer replica so that amplifier supply
+EEl
output
voltage requirements are similar to those of the buffers and the
amplifier bias current is highly independent of supply voltage.
Fig. 10. Simplified block diagram of a single port of the output channel,
This replica bias stage is necessary because otherwise the input The column and column output multiplexer are distributed structures and
offset of the amplifier will vary with supply voltage, causing are ~epresented as buffers with output enables. All wires in the signal path
the output current of the NMOS current source to also change represent differential signals.
v~~
4
I
VCTRL
vrJ.— — v~+
s, r IT
I s~ K
I
● **
I
vc~ +
EL
=
Fig. 11. Schematicof the.multiplexer used h output channel.
v~~ +
1
7
+-;
-* b in Fig. 12, so that only the output of the second buffer connects
$ To Output Of
Col. Output MUX to the output of the column output multiplexer. If the second
L--l < ‘1’ “ buffer is of the same size as the column output multiplexer,
the offset at the output of the second buffer will be equal
to one half the original differential-mode offset at the output
of the column output multiplexer. When refe~ed to the input
of the first buffer, this offset will be equal to one half the
Fig. 12. Block diagram of the differential offset cancellation circuit. original differential-mode offset divided by the product of the
gain of the two buffers. With the feedback path closed, the
differential-mode offsets will become a larger fraction of the negative feedback will drive the output of the column output
decreasing swing. In addition, differential-mode offsets are multiplexer to this input-referred offset. With the second buffer
amplified by the dc gain of the multiplexer, unlike the output the same size as the column output multiplexer, its gain will
signals, which experience little if any amplification, suggesting be one half that of the first buffer. Thus, the differential-mode
that differential offsets originating early in the output channel offset at the output of the column output multiplexer is reduced
will result in larger differential offsets later in the output by the square of the buffer gain with thk circuit.
channel. When signals with differential-mode offsets are am-
plified to the static swing limits by low-fanout buffers, the
differential-mode offsets are converted into differential duty VI. EXPERIMENT& RESULTS
cycle variations. The result is that bandwidth limitations in An array oscillator with seven rings of five buffers per ring
the output channel allow random device mismatches to cause has been fabricated in a 2-pm N-well technology with nodes
address-dependent duty cycle variations among the output T; connected to nodes B~+2, as previously described. This
phases. Since the delays of the output phases are referenced configuration gives rise to two possible modes of oscillation
at the output transitions, these duty cycle variations cause the with different frequencies, where the phase difference across
delays to have an address-dependent error. all corresponding ring nodes is – 2 or – 12 buffer delays. The
way is selectively reset in a particular mode by switching the
C. Dr$ferential Offset Cancellation Circuit ring bias lines. A micrograph of the fabricated array oscillator
As long as the output channel is linear, no information about with a superimposed floor plan is shown in Fig. 14.
the delays of the output phases will be lost due to address- The differential offset cancellation circuit was not designed
dependent differential-mode offsets. The output channel will in time to be a part of this 5 x 7 array oscillator implementa-
be very linear as long as the signal swings are small. These tion. However, on a comparison chip containing two identical
facts suggest that a circuit can be added to the output of arrays of a larger size with one utilizing the differential
the column output multiplexer to cancel out the random offset cancellation circuit, the peak error in output delays was
differential-mode offsets and prevent them from turning into reduced by more than a factor of two. Further improvement
duty cycle variations. Such a circuit would allow the delays was limited by other sources of delay error in the output
of the output phases to be referenced at the output transitions channel and array core.
without an address-dependent error.
The block diagram for such a differential offset cancellation
circuit is shown in Fig. 12, while the schematic is shown in Fig. A. Output Accuracy
13. It contains two differential buffers in a feedback loop with The measured output accuracy of the 5 x 7 array oscillator
two NMOS capacitors to remove the ac signal components is summarized in Fig. 15. The plot shows the error in delays
and allow feedback only for the dc signal components. The for the 70 output phases as a function of the percentage of the
operation of the circuit is most easily analyzed with the period. The results indicate that with a period of 7 ns and an
feedback path broken at the input to the first buffer as indicated LSB of 101 ps, the peak error is slightly greater than a half
1281
.100 I
0.0
1
0.1
1
0.2
1
0.3
I
0,4 0.5
I 1
0.6
1
0.7
1
0.6 0.9
1 I
i ,0
Deley (period)
Fig. 15. Measured output accuracy of the 5 x 7 array oscillator. The plot
shows the error in delays for the 70 output phases as a function of the
percentage of the period.
200
v~~~~
180
— 3.50 v
— 3.25 V
160
— 3.00 v
— 2,75 V
140
g — 2.50 V
— 2.25 V
g 120
— 2,00 v
> — 1.75V
~ 100
— 1.50V
% ,-- 1.25 V
= 80
1.00 v
!!
L 60
1/
40
t
1 1 1 I 1 1 1 1 .
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5,5 6.o
Vcc (v)
Fig. 16. Measured frequency as a function of static supply voltage for the
5 x 7 array oscillator. At higher control voltages, thermal effects dominate
the results due to increased power dissipation.
TABLE I
PERFORMANCESUMMARYOFTHE 5 x 7 ARRAY
OSCILLATORAS A VOLTAGE-CONTROLLED
OSCILLATOR
VII. CONCLUSION
This paper has described a new delay generator based on
a series of coupled ring oscillators for producing delays with
resolution equal to a buffer delay divided by the number of
rings. By coupling several ring oscillators together, the delay
1282 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 12, DECEMBER 1993
generator breaks the dependence of the oscillation frequency [3] I. Young et al., “A PLL clock generator with 5 to 110 MHz lock range
for microprocessors,” in ISSCC 1992 Dig. Tech. Papers, pp. 5(L51, Feb.
on the number of buffers in a ring oscillator. The delay
1992.
generator achieves aprecision intrinsically ashighas that for
a ring oscillator. However, the precision actually realizable
Jotm G. Maneatis was born in San Francisco, CA,
can be limited if care is not taken to address such external on November 7, 1965, He received the B.S. degree
issues as jitter performance and delay errors due to bandwidth in electrical engineering and computer science from
limitations in the output channel. The delay generator also the University of Cahfomia, Berkeley, in 1988
and the M.,% degree in electrical engineering from
utilizes a differential buffer stage with high supply noise Stanford University, Stanford, CA, in 1989. He is
rejection while operating at low supply voltages. The dynamic currently a Ph.D. candidate in electrical engineering
supply noise sensitivity of the differential buffer stage is very at Stanford University.
He worked at Hewlett-Packard Laboratories, Pafo
small, making its static supply noise sensitivity the dominant Alto, CA, during the summer of 1989 on high-speed
factor in the phase-locked jitter performance of the delay analog-to-digital
. . conversion and monolithic clock
generator. Experimental results from a 2-~m N-well CMOS recovery, and at Digital Equipment Corporation Western Research Laboratory,
Palo Alto, CA, during the summer of 1990 on CAD tool development and
implementation of the delay generator indicate that it can ECL circuit design. His research interests include high-performance circuit
achieve an output delay resolution of 101 ps while operating design for phase-locked loops, microprocessors, and d~ta ;onversion. He is a
at 141 MHz with a peak error of 58 ps. These results confirm Registered Professionat Electrical Engineer in the State of California.
Mr. Maneatis is a member of Tau Beta Pi, Eta Kappa Nu, and Phi Beta
that the delay generator can be used in single-chip testers as a Kappa.
cost-effective solution for producing precise delays with high
resolution to test chips designed with higher speed integrated
circuit technologies.
Mark A. Horowitz received the B.S. and M.S. de-
grees in electrical engineering from Massachusetts
ACKNOWLEDGMENT Institute of Technology, Cambridge, MA, in 1978
and the Ph.D. degree in the same field from Stanford
The authors thank T. Chanak and D. Ramsey for their University, Stanford, CA, in 1984.
assistance during the final stages of the layout effort for the He is currently an Associate Professor of Electri-
cal Engineering at Stanford University, where his
fabricated chip. research interests are in digital integrated circuit
design. He has led a number of processor design
projects at Stanford, including MIPS-X, one of the
REFERENCES first processors to include an on-chip instruction
cache, and TORCH, a statically scheduled superscalar proces;or. In 1990
[1] J. Gasbarro and M. Horowitz, “A single-chip, functional tester for VLSI he took leave from Stanford to help start Rambus, Inc., a company designing
circuits,” in ISSCC 1990 Dig. Tech. Papers, pp. 84-85, Feb. 1990. high-bandwidth memory interface technology. His current research includes
[2] J. Maneatis, and M. Horowitz, “Precise delay generation using coupled work in both high-speed and low-power circuits, memory design, processor
oscillators,” in ISSCC 1993 Dig, Tech. Papers, pp. 118–1 19, Feb. 1993. architecture, and IC CAD tools.