Analog Electronic Circuit Engineering PDF

2019 First Edition
Analog
Electronics
Circuit
engineering handbook Ravi Kumar
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Contents
Preface xiv
Acknowledgement xv
Syllabus xvi
Chapter-1 Bipolar Junction Transistor (BJT) 1-23

1.1 INTRODUCTION 1
1.2 BJT (BIPOLAR JUNCTION TRANSISTOR) 1
1.3 TRANSISTOR TERMINALS 2
1.4 BJT SYMBOLS 3
1.5 TRANSISTOR CURRENTS 4
1.6 IMPORTANT POINTS REGARDING WORKING OF TRANSISTORS 4
1.7 TRANSISTOR AS AN AMPLIFIER 6
1.8 TRANSISTOR AS A SWITCH 6
1.9 TRANSISTOR CONFIGURATION 9
1.10 CHARACTERISTICS OF TRANSISTOR CONFIGURATION 10
1.10.1 Input characteristics 10
1.10.2 Output characteristics 10
1.11 COMMON BASE (CB) CONFIGURATION 10
1.11.1 Input Characteristic 11
1.11.2 Output Characteristic 11
1.11.3 Current Amplification factor (a) 13
1.12 COMMON - EMITTER CONFIGURATION (CE) 13
1.12.1 Input Characteristic 13
1.12.2 Output characteristics 14
1.12.3 Current amplification factor (b) 16
1.12.4 Relation between a, b and ICEO, ICBO 16
1.13 COMMON COLLECTOR CONFIGURATION 16
1.14 RELATION BETWEEN a, b & g 17
1.15 DC AND AC LOAD LINES 17
Short Question and Answers 20
Exercise 23
Chapter-2 BJT Biasing & Stabilisation 24-55
2.1 INTRODUCTION 24
2.2 BIASING 24
2.2.1 Transistor Biasing 24
2.3 NECESSITY OF BIASING 25
2.4 TRANSISTOR BIASING CIRCUITS 26
2.4.1 Fixed bias circuit 26
2.4.2 Self / Emitter-Stabilized bias circuit 29
2.4.3 Voltage - Divider biasing 31
2.4.4 DC feedback biasing 34
2.5 BIAS STABILIZATION 45
2.6 NEED FOR BIAS STABILIZATION 45
2.7 STABILITY FACTOR 46
2.7.1 General Expression for SI CO 46
2.7.2 General Expression for Sb 46
2.7.3 Stability factors in different Bias Circuit 47
2.8 DESIGN GUIDELINES OF TRANSISTORS BIASING CIRCUITS 51
Exercise 55
Chapter-3 Field Effect Transistors & Biasing 56-94

3.1 INTRODUCTION 56
3.2 DIFFERENCE BETWEEN BJT & FET 56
3.3 CLASSIFICATION OF FETs 57
3.4 JUNCTION FIELD EFFECT TRANSISTOR (JFET) 57
3.4.1 Standard notations 58
3.4.2 Operations of JFET 58
3.5 JFET PARAMETERS 60
3.6 JFET BIASING 61
3.6.1 Fixed biasing :- (Rs = 0) 61
3.6.2 Self / Source Stabilized biasing 63
3.6.3 Voltage divider biasing 64
3.7 MOSFET 77
3.8 D-MOSFET (Depletion MOSFET) 77
3.9 E-MOSFET (ENHANCEMENT - MOSFET) 80
3.10 CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) 87
3.10.1 CMOS Construction 88
3.10.2 CMOS Inverter Layout 88
3.10.3 CMOS Inverter 89
3.10.4 CMOS Inverter Operation 89
3.10.5 CMOS Voltage Transfer Characteristics 90
Exercise 94
Chapter-4 Small Signal Operation of BJT 95-155
4.1 INTRODUCTION 95
4.2 TWO-PORT DEVICES AND THE HYBRID MODEL 95
4.2.1 Hybrid Parameters or h-parameters 96
4.2.2 Hybrid Model 98
4.3. TRANSISTOR HYBRID MODEL 98
4.4 DETERMINATION OF h-PARAMETERS FROM STATIC CHARACTERISTICS 100
4.4.1 Determination of Hybrid Parameters hfe and hoe 101
4.4.2 Determination of Hybrid Parameters hre and hie 102
4.5 TYPICAL VALUES OF h-PARAMETERS FOR A TRANSISTOR 102
4.6 CONVERSION OF HYBRID PARAMETERS IN TRANSISTOR
THREE CONFIGURATIONS 103
4.7 TRANSISTOR AMPLIFIER CIRCUIT PERFORMANCE IN h-PARAMETERS 106
4.8 LIMITATIONS OF h-PARAMETERS 112
4.9 STEPS FOR DRAWING SMALL SIGNAL MODEL 112
4.10 STEPS FOR ANALYSIS OF TRANSISTOR CIRCUIT 112
4.11 re - TRANSISTOR MODEL 113
4.11.1 Common base configuration 113
4.11.2 Common emitter configuration 114
4.12 COMPARISON BETWEEN HYBRID MODEL & re - MODEL 115
4.13 BJT SMALL-SIGNAL ANALYSIS 115
4.14 VOLTAGE-DIVIDER BIAS 120
4.15 CE EMITTER-BIAS CONFIGURATION 125
4.16 EMITTER-FOLLOWER CONFIGURATION 135
4.17 APPROXIMATE HYBRID EQUIVALENT CIRCUIT 142
4.17.1 Fixed-Bias Configuration 143
4.17.2 Voltage-Divider Configuration 144
4.17.3 Unbypassed Emitter-Bias Configuration 145
Exercise 155
Chapter-5 Small Signal Analysis of FET 156-185

5.1 INTRODUCTION 156
5.2 FET SMALL SIGNAL MODEL 156
5.3 COMPARISON OF LOW FREQUENCY MODELS OF FET AND BJT 157
5.4 JFET FIXED-BIAS CONFIGURATION 157
5.5 JFET SELF-BIAS CONFIGURATION 159
5.6 JFET VOLTAGE-DIVIDER CONFIGURATION 164
5.7 JFET SOURCE-FOLLOWER (COMMON-DRAIN) CONFIGURATION 166
5.8 JFET COMMON-GATE CONFIGURATION 168
5.9 DEPLETION-TYPE MOSFETs 171
5.10 ENHANCEMENT-TYPE MOSFETS 171
Exercise 185
Chapter-6 System Approach, Effect of RS & RL 186-209
6.1 TWO-PORT SYSTEMS 186
6.2 EFFECT OF A LOAD IMPEDANCE (RL) 187
6.3 EFFECT OF THE SOURCE IMPEDANCE (Rs) 190
6.4 COMBINED EFFECT OF Rs AND RL 193
6.5 BJT CE NETWORKS 195
6.6 BJT EMITTER-FOLLOWER NETWORKS 200
6.7 FET NETWORKS 204
Exercise 208
Chapter-7 Frequency Response of Amplifiers 210-258

7.2 AMPLIFIER FREQUENCY RESPONSE 211
7.3 TRANSISTOR CUT-OFF FREQUENCIES 212
7.3.1 Alpha Cut-off Frequency 212
7.3.2 Beta Cut-off Frequency 213
7.3.3 The fT Parameter of a Transistor 213
7.3.4 Gain-Bandwidth Product 213
7.4 BODE PLOT 214
7.5 LOW-FREQUENCY ANALYSIS 215
7.6 LOW-FREQUENCY RESPONSE-BIT AMPLIFIER 219
7.7 LOW-FREQUENCY RESPONSE-FET AMPLIFIER 222
7.8 MILLER EFFECT CAPACITANCE 224
7.9 HIGH-FREQUENCY RESPONSE 226
7.10 BJT HIGH FREQUENCY RESPONSE 227
7.11 HIGH-FREQUENCY RESPONSE-FET AMPLIFIER 232
7.12 MULTISTAGE FREQUENCY EFFECTS 250
7.13 SQUARE-WAVE TESTING 251
Exercise 258
Chapter-8 Compound Configurations 259-289

8.2 CASCADE CONNECTION 259
8.3 CASCODE CONNECTION 264
8.4 DARLINGTON CONNECTION 266
8.5 CURRENT MIRROR CIRCUITS 271
8.6 DIFFERENTIAL AMPLIFIER CIRCUIT 275
Exercise 289
Chapter-9 Feedback Amplifiers 290-326
9.2 THE FEEDBACK CONCEPT 290
9.3 TYPES OF FEEDBACK 292
9.4 PRINCIPLE OF FEEDBACK IN AMPLIFIERS 293
9.5 ADVANTAGES OF NEGATIVE FEEDBACK 296
9.5.1 Stabilization of gain with negative feedback 297
9.5.2 Reduction in Frequency Distortion with Negative Feedback 299
9.5.3 Reduction in Non-linear Distortion with Negative Feedback 299
9.5.4 Reduction in Noise with Negative Feedback 301
9.5.5 Effect of Negative Feedback on Input Impedance 301
9.5.6 Effect of Negative Feedback on Output Impedance 302
9.5.7 Effect of Negative Feedback on Bandwidth 303
9.6 TYPES OF NEGATIVE FEEDBACK CONNECTIONS 307
9.6.1 Input resistance 308
9.6.2 Output Resistance 310
9.7 METHOD OF ANALYSIS OF A FEEDBACK AMPLIFIER 312
9.8 VOLTAGE-SERIES FEEDBACK 313
9.9 CURRENT-SERIES FEEDBACK 318
9.10 CURRENT-SHUNT FEEDBACK 322
9.11 VOLTAGE-SHUNT FEEDBACK 323
Exercise 325
Chapter-10 Sinusoid Oscillators 327-351

10.2 SINUSOIDAL OSCILLATOR 327
10.3 TYPES OF ELECTRICAL OSCILLATIONS 328
10.4 OSCILLATORY CIRCUIT 329
10.5 UNDAMPED OSCILLATIONS FROM AN L-C CIRCUIT 331
10.6 POSITIVE FEEDBACK AMPLIFIER AS AN OSCILLATOR 331
10.7 TRANSISTOR OSCILLATOR 333
10.8 ESSENTIALS OF A TRANSISTOR OSCILLATOR 333
10.9 DIFFERENT TYPES OF TRANSISTOR OSCILLATORS 334
10.10 TUNED COLLECTOR OSCILLATORS 334
10.11 HARTLEY OSCILLATOR 336
10.12 COLPITT’S OSCILLATOR 338
10.13 PRINCIPLE OF PHASE SHIFT OSCILLATORS 339
10.14 R-C PHASE SHIFT OSCILLATOR 341
10.15 WEIN BRIDGE OSCILLATOR 344
10.16 LIMITATIONS OF RC AND LC OSCILLATORS 346
10.17 PIEZOELECTRIC EFFECT AND CRYSTALS 346
10.18 CHARACTERISTICS OF CRYSTAL 347
10.19 TRANSISTOR CRYSTAL OSCILLATOR 348
Exercise 351
Chapter-11 Operational Amplifier 352-369

11.2 CHARACTERISTICS OF OP-AMP 352
11.3 BLOCK DIAGRAM OF A TYPICAL OPERATIONAL AMPLIFIER 352
11.4 SCHEMATIC SYMBOL OF AN OP-AMP 355
11.5 IDEAL OP-AMP 356
11.6 EQUIVALENT CIRCUIT OF AN OP-AMP 356
11.7 IDEAL VOLTAGE TRANSFER CURVE 357
11.8 BASIC OP-AMP CIRCUIT 357
11.9 COMMON-MODE REJECTION RATIO (CMRR) 359
11.10 OP-AMP SPECIFICATIONS 362
11.10.1 DC Offset parameters 362
11.10.2 AC offset parameters of Frequency Parameters 364
Exercise 368
Chapter-12 Application of Op-amp 370-394

12.2 OPEN-LOOP OP-AMP CONFIGURATIONS 370
12.3 CLOSED-LOOP OP-AMP CONFIGURATIONS 370
12.4 OP-AMP AS INVERTING AMPLIFIER 371
12.5 OP-AMP AS NON-INVERTING AMPLIFIER 372
12.6 VOLTAGE FOLLOWER / VOLTAGE BUFFER / UNITY FOLLOWER 372
12.7 ADDER OR SUMMING AMPLIFIER 374
12.8 SUBTRACTER 375
12.9 INTEGRATOR / LOW PASS FILTER 376
12.10 SUMMING INTEGRATOR CIRCUIT 377
12.11 DIFFERENTIATOR / HIGH PASS FILTER 377
12.12 INSTRUMENTATION AMPLIFIER 380
12.13 CONTROLLED SOURCES 382
12.14 CLASSIFICATION OF FILTERS 385
12.15 CLASSIFICATION OF ACTIVE FILTERS 387
12.16 FIRST-ORDER LOW-PASS BUTTERWORTH FILTER 388
12.17 SECOND-ORDER LOW-PASS BUTTERWORTH FILTER 390
12.18 FIRST-ORDER HIGH-PASS BUTTERWORTH FILTER 391
12.19 SECOND-ORDER HIGH-PASS BUTTERWORTH FILTER 393
Exercise 393
Chapter-13 Power Amplifier 395-423
13.2 VOLTAGE AND POWER AMPLIFIERS 396
13.2.1 Voltage amplifier 396
13.2.2 Power amplifier 396
13.3 COMPARISON OF VOLTAGE AND POWER AMPLIFIERS 397
13.4 PROCESS OF POWER AMPLIFICATION 398
13.5 SINGLE-ENDED TRANSISTOR POWER AMPLIFIER 398
13.6 PERFORMANCE OF POWER AMPLIFIERS 399
13.6.1 Collector efficiency 399
13.6.2 Distortion 400
13.6.3 Power dissipation capability 400
13.7 CLASSIFICATION OF POWER AMPLIFIERS 401
13.7.1 Class-A Amplifiers 401
13.7.2 Class-B Amplifiers 402
13.7.3 Class-C Amplifiers 402
13.7.4 Class-AB Amplifiers 403
13.8 EFFICIENCY RATING 404
13.9 CALCULATIONS FOR MAXIMUM COLLECTOR EFFICIENCY OF
A CLASS-A POWER AMPLIFIER 406
13.10 TRANSISTOR TEMPERATURE CONTROL BY HEAT SINKS 410
13.11 COLLECTOR DISSIPATION CURVE AND ITS IMPORTANCE 412
13.12 STAGES OF A PRACTICAL POWER AMPLIFIER 413
13.13 DRIVER STAGE 414
13.14 OUTPUT STAGE 415
13.15 PUSH-PULL AMPLIFIER 415
13.15.1 Circuit analysis 415
13.15.2 Operation 416
13.15.3 Advantages 416
13.15.4 Disadvantages 417
13.16 COMPLEMENTARY-SYMMETRY PUSH-PULL AMPLIFIER 417
13.17 HARMONIC DISTORTION IN POWER AMPLIFIERS 418
13.18 DISTORTION IN PUSH-PULL AMPLIFIERS 419
Exercise 422
Semester Questions with Answer 424
Bibliography
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Bipolar Junction Transistor (BJT)
1.1 INTRODUCTION
It is a solid state device whose operation depends upon the flow of electric charge
carriers within the solid. It is the electronic device that transfers the input signal from one
resistance circuit to other resistance circuit. So it is called transfer resistor or transistor.
The transistors are the current device that may be current or voltage controlled. The
transistors can be used as amplifier or as switch.
There are mainly two types of transistor.
1) BJT (Bipolar Junction Transistor)
2) FET (Field Effect Transistor)
Presently the transistors are used in
i) High speed computers
ii) Vehicles
iii) Satellites
iv) Communication systems
v) Power systems
vi) Switching.
1.2 BJT (BIPOLAR JUNCTION TRANSISTOR)
A simple diode is made up from two pieces of semiconductor material, either silicon or
germanium. Now if we join together two individual signal diodes back to back, this will give
us two P-N junctions connected together in series that share a common P or N terminal.
The fusion of these diodes produces a three layer, two junction and a three terminal device
known as BJT.
2 Analogue Electronics Circuits
BJT is three terminal active device that can act as either an insulator or conductor by
the application of a small signal voltage. The transisters ability to change between these
two states enables it to have two basic functions known as “switching” (in digital electronics)
or “amplification” (in analogue electronics).
So BJT are current regulating device that control the amount of current Flauing through
them in proportion to the amount of biasing voltage applied to their base terminal acting like
a current controlled switch.
The transistor is a solid state device and is an essential ingredient of every electronic
circuit. This is analogous to a vacuum triode. The main difference between a transistor
and a vacuum triode is that transistor is a current device while a vacuum triode is a voltage
device. The advantages of a transistor over a vacuum triode are long life, high efficiency,
light weight, smaller in size, smaller power consumption, etc. The transistor was invented
by John Bardeen and W.H. Brattain in 1948. A transistor is commonly known as Bipolar
junction transistor (BJT). This is due to the fact that the current conduction in BJT is due
to both types of charge carriers i.e, electrons and holes. Bipolar junction transistor is a
three terminal, two junction device.
A junction transistor is simply a sandwich of one type of semiconductor material be-
tween two layers of the other type. Accordingly, there are two types of transistors:
1. P-N-P transistor. 2. N-P-N transistor and
i) P-N-P transistor :
A transistor in which two blocks of type semiconductor are separated by a thin layer
of n-type semiconductor.
ii) N-P-N transistor :
A transistor in which two blocks of n-type semiconductor are separated by this layer
of p-type semiconductor.
1.3 TRANSISTOR TERMINALS
Every transistor has three terminals called emitter, collector and base.
i) Emitter : The section on one side of the transistor that supplies a large number of
majority carriers is called emitter. The emitter is always forward biased w.r.t. base
so that it can supply a large number of majority carriers to its junction with the base.
The biasing of emitter-base junction of npn transistor and pnp transistor is shown in
Fig. 1.1 and 1.2 respectively. Since emitter is to supply or inject a large amount of
majority carriers into the base, it is heavily doped but moderate in size.
Fig. 1.1. Biasing of npn transistor Fig. 1.2. Biasing of pnp transistor
Bipolar Junction Transistor (BJT) 3
ii) Collector : The section on the other side of the transistor that collects the major
portion of the majority carriers supplied by the emitter is called collector. The collector-
base junction is always reverse biased. Its main function is to remove majority carriers
(or charges) from its junction with base. The biasing of collector-base junction of npn
transistor and pnp transistor is shown in Fig. 1.1 and 1.2 respectively. The collector is
moderately doped but larger is size so that it can collect most of the majority carriers
supplied by the emitter.
iii) Base : The middle section which forms two junctions between emitter and collector
is called base. The base forms two circuits, one input circuit with emitter and the
other output circuit with collector. The base-emitter junction is forward biased, providing
low resistance for the emitter circuit. The base-collector junction is reversed biased,
offering high resistance path to the collector circuit. The base is lightly doped and
very thin so that it can pass on most of the majority carriers supplied by the emitter to
the collector.
- So as per width, collector > Emitter > Base and as per doping, Emitter >
Base > Collector.
The collector is made large to dissipate much power. So collector and emitter can not
be interchanged due to width difference. But if widths are made equal then they can
be interchanged.
1.4 BJT SYMBOLS
C(n) C(p)
B(p) B(n)
E(n) Fig. 1.3 E(p) Fig. 1.4

(n-p-n) (p-n-p)
Ø The arrow mark is given on the basis of direction of conventional current flow which
is opposite to electron flow & same as hole flow.
Ø Generally n-p-n transistors are widely used because electrons have greater mobility
than holes.
BJT Construction
PNP Transistor NPN Transistor
P N P N P N
Emitter Collector Emitter Collector
Base a) Construction Base

E C E C
B b) Two-diode Analogy B
VEC VCE
+ – – +
E C
E C
+ IE IC – – IE +
VEB IB VBE
VBC VCE
– + + –
B B
c) Symbols
Fig. 1.5
The directions shown here are showing the direction of “conventional current flow” between
the base & the emitter terminals. The direction of current is aloways from P-type to
N-type region.
Transister resistance values for a PNP transistor and a NPN transistor
Between transistor terminals PNP NPN
Collector Emitter RHigh RHigh
Collector Base RLow RHigh
Emitter Collector RHigh RHigh
Emitter Base RLow RHigh
Base Collector RHigh RLow
Base Emitter RHigh RLow
1.5 TRANSISTOR CURRENTS
The emitter supplies the majority carriers, giving rise emitter current, IE.
Few of majority carriers are neutralized in base region, giving base current, IB.
The rest are collected at collector region, giving rise to collector current IC.
So IE = IC + IB
But I C = I C maj + I C min
The minority collector current is due to reverse biasing between collector & base
junction. The minority current is also known as collector leakage current
So I C = I C maj + I CO .
1.6 IMPORTANT POINTS REGARDING WORKING OF TRANSISTORS
The worthnoting points regarding working of transistors are summarized below.
1. Current conduction in N-P-N transistor is by electrons and the conventional current
flow will be in the opposite direction. Current conduction in P-N-P transistor is by
holes but in external leads, the current will be by flow of electrons.
2. The collector current IC is always less than emitter current IE, being the difference of
emitter current IE and base current IB.
3. The base current is only a small fraction (usually 5%) of emitter current.
4. As a standard convention, all the currents entering into the transistor are considered
to be positive. Conversely currents that flow out of the transistor are taken to be
negative. It means that if the actual conventional current flows in the outward direction,
a negative sign is included along with its magnitude. Thus in an N-P-N transistor, the
emitter current IE is to be taken negative because it flows out of the transistor while
both the base current IB and collector current IC are to be taken a positive because
they flow into the transistor. Similarly in a P-N-P transistor IE is to be taken positive
and both base current IB and collector current Ic are to be taken negative. However,
to avoid confusion, the actual direction of flow of current is indicated in the diagrams.
5. Emitter-base junction is always forward-biased and collector-base junction is always
reverse-biased.
6. The input circuit (i.e. emitter-base junction), because of forward bias, offers low
resistance and so needs usually very small bias (approximately 0.7 V for Si and 0.3 V
for Ge). The output circuit (i.e. collector-base junction), because of reverse bias,
offers high resistance and, therefore, needs much higher bias (3 to 20 V).
7. Transistor transfers the input signal from a low resistance circuit to a high resistance
circuit, therefore, it is called the TRANSFER RESISTOR (TRANS-ISTOR).
8. Since both of the charge carriers (holes as well as electrons) are involved in current
flow through a transistor (may be either P-N-P or N-P-N), so these devices are
sometimes called the bipolar junction transistors (BJTs).
D1 D2
9. Although, it is said that a transistor
is a device with two PN diodes
connected back-to-back, but it does +
–
not mean that two discrete diodes VCB VEB
connected back-to-back, as shown +
in fig 1.6, can work as a transistor. –
In such a case, each diode has two
equally doped regions, so that the Two Diodes Connected Back-To-Back
overall circuit has four equally Fig.1.6
doped regions. This would not work as base region is not the same as in a transistor.
The key to the transistor action is the lightly doped thin base between the
heavily doped emitter and moderately doped collector.
In an N-P-N transistor, the free electrons passing through the base to the collector
region have a short life time. As long as the base is thin, the free electrons can reach the
collector. But in case of two discrete back-to-back connected diodes there are four doped
regions instead of three and there is nothing that resembles a thin base region between an
emitter and a collector. Hence two discrete diodes connected back-to-back can never
work as a transistor.
10. The choice of N-P-N transistor is made more often because majority charge carriers
are electrons whose mobility is much more than that of holes.
1.7 TRANSISTOR AS AN AMPLIFIER
A transistor is a device which raises the strength of a weak signal and thus acts as an
amplifier. The basic transistor amplifier circuit is shown in Fig. 1.6. The input (weak signal)
is applied across emitter-base and the output (amplified signal) is obtained across the load
resistor RC connected in the collector circuit. It may be noted that a d.c. voltage V EE is
applied in the input circuit in addition to the signal to achieve faithful amplification. This d.c.
voltage VEE keeps the emitter-base junction under forward biased condition regardless of
the polarity of the signal and is known as *bias voltage.
When a weak signal is applied at the
input, a small change in signal voltage
causes an appreciable change in emitter
current (say a change of 0.1 V in signal
voltage causes a change of 1 mA in the
emitter current) as the input circuit has
very low resistance. This causes almost
the same change in collector current due
to transistor action. In the collector circuit
Fig. 1.6
a load resistor RC of **high value (say 10
kW) is connected. When collector current flows through such a high resistance, it produces
a large voltage drop (V0 = 10 kW × 1 mA = 10 V) across it.
Thus, a weak signal (0.1 V) applied at the input circuit appears in the amplified
form (10 V) in the collector circuit.
1.8 TRANSISTOR AS A SWITCH
When used as an AC signal amplifier, the transistors Base biasing voltage is applied so that
it always operates within its "active" region, that is the linear part of the output characteristics
curves are used. However, both the NPN & PNP type bipolar transistors can be made to
operate as an "ON/OFF" type solid state switch by biasing its Base differently to that of an
amplifier. Solid state switches are one of the main applications of transistors. Transistor
switches are used for controlling high power devices such as motors, solenoids or lamps,
but they can also used in digital electronics and logic gate circuits.
If the circuit uses the Bipolar Transistor as a Switch, then the biasing of the transistor,
either NPN or PNP is arranged to operate at the sides of the V-I characteristics curves
we have seen previously. The areas of operation for a transistor switch are known as the
Saturation Region and the Cut-off Region. This means then that we can ignore the
operating Q-point biasing and voltage divider circuitry required for amplification, and use
the transistor as a switch by driving it back and forth between "fully-OFF" (cut-off region)
and "fully-ON" (saturation region) as shown below.
Operating Regions
IC
(mA) Saturation Region
(Transistor “fully-ON”)
When VCE = 0
V
IC = CE
RL A
60
50
Q-point
(active region)
40
30 Cut-off Region
(transistor “fully-OFF”)
20
10 B
IB = 0
0 VCE (V)
1 2 3 4 5 6
VCE(sat)
When ICE = 0
Fig. 1.7 VCE = VCC
The shaded area at the bottom of the curves represents the "Cut-off" region while the
shaded area to the left represents the "Saturation" region of the transistor. Both these
transistor regions are defined as:
1. Cut-off Region
Here the operating conditions of the transistor are zero input base current ( IB ), zero
output collector current ( IC ) and maximum collector voltage ( VCE ) which results in a
large depletion layer and no current flowing through the device. Therefore the transistor is
switched "Fully-OFF".
Cut-off Characteristics
· The input and Base are
grounded (0v)
· Base-Emitter voltage
VCC VCC
VBE < 0.7V
· Base-Emitter junction is reverse
RL
biased
RL
· Base-Collector junction is
Vout Vout reverse biased
Rin C
B · Transistor is "fully-OFF"
Vin Switch
“open” (Cut-off region)
E
· No Collector current flows
0v 0v
( IC = 0 )
Fig. 1.8 · VOUT = VCE = VCC = "1"
· Transistor operates as an "open
switch"
Then we can define the "cut-off region" or "OFF mode" of a bipolar transistor switch as
being,both junctionsreversebiased,IB < 0.7V and IC = 0. For a PNP transistor, the Emitter
potential must be negative with respect to the Base.
2. Saturation Region
Here the transistor will be biased so that the maximum amount of base current is
applied, resulting in maximum collector current resulting in the minimum collector emitter
voltage drop which results in the depletion layer being as small as possible and maximum
current flowing through the transistor. Therefore the transistor is switched "Fully-ON".
Saturation Characteristics
· The input and Base are
connected to VCC
· Base-Emitter voltage
VBE > 0.7V
· Base-Emitter junction is
VCC VCC forward biased
· Base-Collector junction is
RL RL forward biased
· Transistor is "fully-ON"
Vout Vout (saturation region)
Rin C
B
Switch · Max Collector current flows
Vin
“closed” (IC = Vcc/RL)
E
0v · VCE = 0 (ideal saturation)
0v
· VOUT = VCE = "0"
Fig. 1.9 · Transistor operates as a "closed
switch"
Then we can define the "saturation region" or "ON mode" of a bipolar transistor
switch as being, both junctions forward biased, IB > 0.7V and IC = Maximum. For a PNP
transistor, the Emitter potential must be positive with respect to the Base.
Then the transistor operates as a "single-pole single-throw" (SPST) solid state switch.
With a zero signal applied to the Base of the transistor it turns "OFF" acting like an open
switch and zero collector current flows. With a positive signal applied to the Base of the
transistor it turns "ON" acting like a closed switch and maximum circuit current flows
through the device.
An example of an NPN Transistor as a switch being used to operate a relay is given
below. With inductive loads such as relays or solenoids a flywheel diode is placed across
the load to dissipate the back EMF generated by the inductive load when the transistor
switches "OFF" and so protect the transistor from damage. If the load is of a very high
current or voltage nature, such as motors, heaters etc, then the load current can be controlled
via a suitable relay as shown.
Example -1.1
Using the transistor values from the previous tutorials of: b = 200, Ic = 4mA and Ib =
20uA, find the value of the Base resistor (Rb) required to switch the load "ON" when the
input terminal voltage exceeds 2.5v.
Vin - VBE 2.5v - 0.7v
RB = = = 90kW
IB 20 ´ 10-6
The next lowest preferred value is: 82kW, this guarantees the transistor switch is always
saturated.
Example-1.2
Again using the same values, find the minimum Base current required to turn the
transistor "fully-ON" (saturated) for a load that requires 200mA of current when the input
voltage is increased to 5.0V. Also calculate the new value of Rb.
transistor Base current:
IC 200mA
IB = = = 1mA
b 200
transistor Base resistance:
Vin - VBE 5.0v - 0.7v
RB = = = 4.3kW
IB 1 ´ 10-3
Transistor switches are used for a wide variety of applications such as interfacing
large current or high voltage devices like motors, relays or lamps to low voltage digital logic
IC's or gates like AND gates or OR gates. Here, the output from a digital logic gate is only
+5v but the device to be controlled may require a 12 or even 24 volts supply. Or the load
such as a DC Motor may need to have its speed controlled using a series of pulses (Pulse
Width Modulation). transistor switches will allow us to do this faster and more easily than
with conventional mechanical switches.
1.9 TRANSISTOR CONFIGURATION
Ø Transistor has three terminals. But we require four terminals - two for input & two
for output for connecting it in a circuit.
Ø So one of the terminals is made common to input as well as output of the circuit.
So there are three types of configurations
i) Common Base (CB) : It has voltage gain but no current gain.
ii) Common Emitter (CE) : It has both voltage and current gain.
iii) Common Collector (CC) : It has current gain but no voltage gain.
Ø Generally common end is grounded but not always.
Ø Most commonly CE configuration is used.
1.10 CHARACTERISTICS OF TRANSISTOR CONFIGURATION

There are mainly two types of characteristics,
1) Input characteristics
2) Output characteristics
1.10.1 Input characteristics
This graph is plotted between input voltage and input current at constant output voltage.
Because input junction is forward biased, the input characteristics is similar to diode forward
bias characteristics.
This characteristics is used to determine input impedance of transistor.
1.10.2 Output characteristics
This graph is plotted between output voltage and output current at constant input
current.Because output junction is reverse biased, so the curve is analogue to diode reverse
bias characteristic.
There are three regions of transistor operation in output characteristic curve.
a) Active region
b) Saturation region
c) Cut-off region
a) Active Region
This is the region where input junction is forward and output junction is reverse
biased.
Here the transistor is used as an amplifier.
b) Saturation region
Here both the junctions are forward biased. So it is like a closed switch.
Here output current becomes independent of input current.
c) Cut-off region
Here both the junctions are reverse biased. So it is like an open switch.
Here very few current will flow, due to minority carriers.
1.11 COMMON BASE (CB) CONFIGURATION
In this type of configuration, input is
E C IC
connected between base & emitter
and output is collected between IE
collector and emitter.
So in common base, input is at emitter
and output is at collector. IB B V CB
Here Input current = IE
Output current = IC
input voltage = VBE V BE
Output voltage = VCB Fig. 1.10

1.11.1 Input Characteristic

Ø It is plotted between VBE & IE at constant VCB.
V
=1 V
=0
B 6V
CB
CB
V
VC =
V
10
EMITTER CURRENT, IE
6
IN mA
4
0.5 1.0 1.5

EMITTER-BASE VOLTAGE,
VBE IN VOLTS
Fig. 1.11
Input Characteristics For common Base NPN Transistor
Ø Here with increase in base to emitter voltage, emitter current increases. It resembles
to diode characteristics.
Ø Here by increasing the collector to base voltage, the input graph bends towards current
axis i.e slope increases i.e. input resistance decreases.
1.11.2 Output Characteristic
SATURATION ACTIVE REGION

REGION
4 IE= 4 m A
COLLNECTOR CURRENT
ICIN mA
3 IE= 3 m A
2 IE= 2 m A
1 IE= 1 m A
CUT-OFF
IE= 0 m A REGION
ICBO
–1 1 2 3 4
COLLECTOR BASE VOLTAGE, V CB IN VOLTS
Fig. 1.12
Output Characteristics For common Base NPN Transistor
The curve drawn between collector current IC and collector-base voltage VCB for
a given value of emitter current IE is known as output characteristic,
(i) The collector current IC varies with VCB only for very low voltage (below 1 V) but
transistor is never operated in this region.
(ii) In active region emitter forward biased and collector reverse biased) collector current
IC is almost equal to IE and appears to remain constant when VCB is increased. In
fact, there is very small increase in IC with increase in VCB. This is because the
increase in VCB expands the collector-base depletion region and thus shortens the
distance between the two depletion regions. With emitter current IE held constant
however, the increase in Ic is so small that it is usually noticeable only for large
variations in VCB. IC is slightly lesser than IE in magnitude. Transistor is normally
operated in active region.
(iii) Although the collector current Ic is practically independent of VCB over the transistor
operating range. However if VCB is increased beyond a certain value, IC eventually
increases rapidly because of avalanche or Zener (or both ) effects. This condition is
known as punch-through or reach-through. When it occurs large currents can
flow, possibly destroying the device. The extension of the depletion region is, of
course, the direct consequence of the increase in VCB. Thus it is very essential to
maintain VCB below the maximum safe limit specified by the manufacturer of the
device.
(iv) A very large change in collector voltage causes a very small change in collector
current i.e. output resistance of CB configuration is very high (of the order of few
hundred kW)-the dynamic output resistance r0 being given as the ratio of DVCB and
DlC for a given value of IE.
(v) In cut-off region (emitter and collector junctions both reverse-biased) small collector
current IC flows even when emitter current IE = 0. This is the collector leakage
current ICBO or IC0.
(vi) In saturation region ( both emitter and collector junctions forward-biased) collector
current Ic flows even when VCB ~ 0. Even when the externally applied bias voltage
is reduced to zero, there is still a barrier potential existing at the collector-base
junction, and this assists in the flow of IC. To stop it the collector-base junction has to
be forward biased. Consequently, collector current IC is reduced to zero when VCB
is increased negatively.
We have already determined that a small signal voltage impressed in the low-
resistance input (emitter) circuit of a transistor causes a relatively large emitter
current. Almost the same amount of current will flow in the high-resistance output
(collector) circuit of transistor, where the voltage may be very high. Evidently, then,
both the output voltage and power can be quite large, as compared to the tiny input
voltage and power present at the emitter.
CB configuration is rarely used in audio-frequency (AF) circuits because its current
gain is less than unity and its input and output resistances are quite different.
1.11.3 Current Amplification factor (a)

It is the ratio of output majority collector current to the input emitter current.
I C maj
a=
IE
Þ I C maj = aI C
Due to output junction is reverse biased, there is some minority collector current flows.
Here I C min = I CBO (Collector to base minority current when emitter is open)
so I C = I C maj + I C min
Þ I C = aI E + I C BO ...(1)
1.12 COMMON - EMITTER CONFIGURATION (CE)
IC
C
B
IB V CE
V BE E
IE
Fig. 1.13
In common emitter configuration, input is given at base w.r.t emitter and output is
collected at collector w.r.t. emitter.
So emitter is common to input as well as to the output.
1.12.1 Input Characteristic
It is plotted between input voltage VBE & input current IB at constant output voltage
V CE .
(i) The input characteristics of CE transistors are quite similar to those of a forward
biased diode because the base-emitter region of the transistor is a diode and it is
forward biased.
(ii) In comparison to common base (CB) arrangement base (or input) current increases
less rapidly with the increase in base-emitter voltage, VBE. This
indicates that input resistance is larger in common emitter configuration than that in
common base configuration.
Due to initial non-linearity of the curve,
input resistance varies from point-to-
2V
= 6V
200
VC =
point in the initial part of the
CE
V
characteristic. Its value over the linear
BASE CURRENT IB IN mA
part of the curve is of the order of few 150
hundred ohms.
(iii) An increment in value of VCE causes 100
the input current IB to be lower for a
given level of VBE. This is because the
50
higher levels of VCE provide greater
collector-base junction reverse bias,
causing greater depletion region
0.5 10 15
penetration into the base and thus BASE EMITTER VOLTAGE V IN VOLTS BE
reducing the distance between the Fig. 1.14 : Input Characterestics For Common
collector-base and emitter-base Emitter NPN Transistor
regions. As a result more of the charge carriers from the emitter flows across the
collector-base junction, and few flow out through the base lead. Usually effect of
changein VCE on the input characteristic is ignored.
The ratio of change in base-emitter voltage (DVBE) to the resulting change in base
current (DIB) at constant collector-emitter voltage (VCE) is known as dynamic input
resistance (ri). It is calculated as the reciprocal of the slope of the input characteristic
at a given VBE.
DVBE
ri =
DI E VCE = Cons tan t
1.12.2 Output characteristics

Output characteristic for a common emitter transistor is the curve drawn between
collector current Ic and collector-emitter voltage VCE for a given value of base
current IB.
(i) The collector current Ic varies with VCE for VCE between 0 and 1 V and then becomes
almost constant and independent of VCE. The transistors are always operated above
1 V.
(ii) Output characteristic in CE configuration has some slope while CB configuration
has almost horizontal characteristics. This indicates that output resistance in case of
CE configuration is less than that in CB configuration.
(iii) In active region (collector junction reverse biased and emitter junction forward biased),
for small values of base current IB the effect of collector voltage VC over IC is
small but for large values of IB this effect increases.
The shape of the characteristic is same as in CB configuration but with the difference
that collector current IC is larger than input current (base current IB). Thus the
current gain for this configuration is iB = 1

00 mA
larger than unity. The transistor must

G IO N
SATURATION REGION
6 E RE
always be operated in the active AC TIV
iB = 80 mA
region, when employed as an
COLLECTOR CURRENT IC IN mA
5
amplifying device.
iB = 60 mA
4
(iv) With low values (ideally zero) of VCE
the transistor is said to be operated in 3 iB = 40 mA BREAK
DOWN
saturation region and in this region
2
base current IB does not cause a iB = 20 mA
corresponding change in collector 1

iB = 0 mA
current IC. CUT-OFF REGION
1 2 3 4 5 6
(v) With much higher VCE, the collector- COLLECTOR-EMITTER VOLTAGE VCE IN VOLTS
base junction completely breaks down Fig. 1.15

and because of this avalanche Output Characterestics For Common
breakdown collector current I C Emitter NPN Transistor
increases rapidly and the transistor gets damaged.
(vi) In cut-off region, small amount of collector current IC flows even when base current
IB = 0. This is called ICEO. Since main current IC is zero so the transistor is said to be
cut-off.
(vii) Moderate output to input impedance ratio makes this configuration an ideal one for
coupling between various transistor stages.
The ratio of change in collector-emitter voltage (DVCE) to the change in collector
current (DIC) at constant base current is known as dynamic output resistance.
It is calculated as the reciprocal of the slope of output characteristic at a given VCE.
DVCE
i. e., r0 =
DI C I B = Cons tan t
The output resistance of CE configuration is less than that of CB configuration as the

slope of the output characteristic is more in this case. Its value is of the order of 50 kW.
The output characteristics may also be used to determine the dc current gain p and ac
current gain b 0 as follows
IC
DC current gain, b DC =
IB
DI C
AC current gain, b ac =
DI B VCE = cons tan t
1.12.3 Current amplification factor (b)
It is the ratio of Majority Collector current to the input base current.
I C maj
So b=
IB
Þ I C maj = b I B
Due to reverse biasing of collector & base, there is minority collector current.
I C min = I CEO = Collector to emitter minority- Current when base is open.
So I C + I C maj + I C min = BI B + I CEO
1.12.4 Relation between a, b and ICEO, ICBO
It is known that, I C = aI E + I CBO
b g
Þ IC = a I C + I B + I CBO
b g
Þ I C 1- a = aI B + I CBO
F a IJ I
I =G
I CBO
Þ C
H1- aK I-a
B +
Comparing it with equation IC = bIB + ICEO

a b
b= or a = i.e. a < < b
1- a 1+ b
& I CEO =
I CBO
1- a
b g
= b + 1 I CBO i.e. I CBO > I CBO
1.13 COMMON COLLECTOR CONFIGURATION

Here collector is common to both input and output circuit.
IE
Here input current = IB
input voltage = VBE E
output voltage = VBC
B
output current = IC
So here current amplification factor is g. IB V EC
IE C
g= Þ I E = gI B VBC IC
IB
Comparison between the CB, CE & CC configurations Fig. 1.16
Characteristics CB CE CC
Input impedance Low Medium High
Output impedance Very high High Low
Phase angle 0° 180° 0°
Voltage gain High Medium Low
Current gain Low Medium High
Power gain Low Very high Medium
1.14 RELATION BETWEEN a, b & g

I E = gI B
Also b g
I E = I C + I B = bI B + I B = b + 1 I B
So g = b + 1
a 1
Also b = Þ b + 1=
1- a 1- a
1
So g = b +1=
1- a
1.15 DC AND AC LOAD LINES
A transistor amplifier circuit can more easily be analysed with the help of dc and ac
load lines. It is known as a load line analysis.
As discussed earlier, in a transistor circuit both dc and ac conditions prevail, therefore,
there are two types of load lines namely ; dc load line and ac load line.
DC load line
A line drawn on the output characteristics of a transistor circuit which gives the
values of IC and VCE corresponding to zero signal conditions (i.e. dc conditions) is
known as dc load line.
Consider a transistor amplifier circuit shown in Fig. 1.17.
Fig. 1.17
The input signal is given to the base (connected across base and emitter) through capaci-
tor Cin and the output is taken across the resistor RL. The dc equivalent circuit of the amplifier
is shown in Fig. 1.18. Applying Kirchhoff s voltage law to the output (collector) circuit, we
get,
VCC = IC R C + VCE + I E R E
VCE = VCC - IC (R C + R E ) .... (i) (QIC @ I E )
Fig. 1.18 Fig. 1.19

Where VCC and (RC + RE) are constant, hence exp. (j) shows a first, degree equation
and can be represented by a straight line on the output characteristics. This is known as dc
load line. To plot this line, the two end points can be located as under :
Value of VCE will be maximum when IC = 0
Substituting this value in exp. (i), we get,
VCE = VCC ...(ii)
This locates the first point A (OA = VCC) of dc load line.
Value of IC will be maximum when VCE = 0
Substituting Ibis value in exp. (i), we get,
O = VCC – IC (RC + RE)
VCC
or IC = ...(iii)
(R C + R E )
This locates the second point B (OB = VCC /(RC + RE)) of dc load line, by joining point
A and B as shown in Fig. 1.19.
By constructing dc load line on the output characteristics, we can obtain the required
information about the output circuit of transistor amplifier in the zero signal conditions. In
fact, all the points showing zero signal IC and VCE lie on this dc load line. Therefore, the
actual operating conditions in the circuit will be represented by the point where dc load line
intersects the base current curve under study. For instance, if the operating point is to be
set by the base current IB = IB1 by the base circuit then Q is the required operating point
(VCE = OX, IC = OY) since curve of base current IB1 intersects the dc load line at this point.
AC load line
A line drawn on the output characteristics of a transistor circuit which gives the
values of IC and VCE when signal is applied (i.e. ac conditions) is known as ac load
line.
Fig. 1.20 shows the ac equivalent circuit of a transistor amplifier shown in Fig. 1.17.
To plot ac load line on the output characteristics, again two end points are required to be
located. One of them is the collector-emitter voltage point and the other is maximum
collector current point.
Under the application of ac signal :
Max. collector-emitter voltage = VCE - *IC R AC ... (iv)
This locates the first point C(OC = VCE - I C R AC ) of the ac load line.
VCE
Max. collector current = ** IC + ... (v)
R AC
æ VCE ö
This locates the second point D ç OD = IC + ÷ of the ac load line.
è R AC ø
IC
VCC D AC LOAD
IC + LINE
RAC
IB3
IB2
Y IB1
C
VCE
0 VCE – ICRAC
Fig. 1.20 Fig. 1.21

*ICRAC represents the maximum positive swing of ac collector-emitter voltage. Here IC is
the maximum value of collector current due to signal only.
**IC represents the maximum positive swing of ac collector current.
In the expression (iv) and (v) RAC represents the effective resistance of the output
circuit. From Fig 13.10, it is clear that RC and RL are in parallel, therefore,
RCR L
R AC = R C || R L =
RC + RL
The ac load line is plotted by joining point C and D as shown in Fig. 1.21.
Note. It may be noted that when ac signal is applied, the value of maximum collector-
emitter voltage OC (OC = VCE – IC RAC) is less than the value of maximum collection-
emitter voltage OA (OA = VCC) when no signal is applied. On the other hand the value of
æ V ö
maximum collector current when ac signal is applied OD ç OD = IC + CE ÷ is more than
è R AC ø
the value of maximum collector current OB (OB = IC) when no signal is applied as shown
in Fig. 1.22. By joining point A and B, a dc load line is constructed. While joining point C
and D, an ac load line is obtained. These two lines always intersect each other at a
point Q called operating point (See Fig. 1.22).
Fig. 1.22
SHORT QUESTION AND ANSWERS
Q.1 Explain why an ordinary junction transistor is called bipolar?

Ans. Because the transistor operation is carried out by two types of charge carriers (majority
and minority carriers), an ordinary transistor is called bipolar.
Q.2 What is done to the base region of a transistor to improve its operation ?
Ans. Base is made thin and very lightly doped in comparison to either emitter or collector so that
it may pass most of the injected charge carriers to the collector.
Q.3 Why transistor is called current controlled device ?
Ans. The output voltage, current or power is controlled by the input current in a transistor so it is
called the current controlled device.
Q.4 Why collector is made larger than emitter and base ?
Ans. Collector is made physically larger than emitter and base because collector is to dissipate
much power.
Q.5 Why the width of the base region of a transistor is kept very small compared to other
regions ?
Ans. Base region of a transistor is kept very small and very lightly doped so as to pass most of
the injected charge carriers to the collector..
Q.6 Why emitter is always forward biased ?
Ans. Emitter is always forward biased w.r.t. base so as to supply majority charge carriers to the
base.
Q.7 Why collector is always reverse-biased w.r.t. base ?
Ans. Collector is always reverse-biased w.r.t. base so as to remove the charge carriers away
from the base-collector junction.
Q.8 Can a transistor be obtained by connecting two semiconductor diodes back-to-back ?
Ans. No. Because in case of two discrete back-to-back connected diodes there are four doped
regions instead of three and there is nothing that resembles a thin base region between an
emitter and a collector.
Q.9 What is adc ?
Ans. adc is the dc current gain and is equal -to the ratio of collector current to the emitter
current.
Q.10 How a and b are related to each other ?
Ans. a and b are related as below :
b a
a= or b =
1+ b 1- a
Q.11 Define beta of a transistor.
Ans. The b factor of a transistor is the common emitter current gain of that transistor and is
defined as the ratio of collector current to base current.
Q.12 Why is there a maximum limit of collector supply voltage for a transistor ?
Ans. Although collector current is practically independent of collector supply voltage over the
transistor operating range, but if VCB is increased beyond a certain value collector current
Ic eventually increases rapidly and possibly destroys the device.
Q.13 Explain why ICEO >> ICBO ?
Ans. The collector cut-off current denoted by ICEO is much larger than ICBO. ICEO is given as
1
I CEO = I CBO = (b + 1) I CBO
1- a
Because a is nearly equal to unity (slightly less than unity), ICEO >> ICBO .
Q.14 Why CE configuration is most popular in amplifier circuits ?
Ans. CE configuration is mainly used because its current, voltage and power gains are quite high
and the ratio of output impedance and input impedance arc quite moderate.
Q.15 Why is CC configuration seldom used ?
Ans. CC configuration is seldom used because its voltage gain is always less than unity.
Q.16 What are the main purposes for which a common collector amplifier may be used ?
Ans. For common collector configuration current gain is high (about 100) but voltage gain is less
than unity, input impedance is the highest and output impedance is the lowest. This circuit
finds wide application as a buffer amplifier between a high impedance source and a low
impedance load.
Q.17 Which configuration among CE, CB, CC gives highest input impedance and no voltage
gain ?
Ans. Common collector configuration has the highest input impedance and voltage gain less than
unity.
Q.18 Which of the configurations (CB, CE, CC) has the (i) highest Ri (ii) lowest Ri (iii) highest
R0 (iv) lowest R0 (v) lowest Ai
Ans. Characteristic Configuration
(i) Highest input resistance, Ri CC
(ii) lowest input resistance, Ri CB
(iii) Highest output resistance, R0 CB
(iv) Lowest output resistance, R0 CC
(v) Lowest current gain, Ai CB
Q.19 Explain base width modulation (Early effect).
Ans. The modulation of the effective base width by the collector voltage is known as Early
effect. An increase in collector voltage increases the space charge width at the output
junction diode and thus the effective base width Wb is reduced.
Q.20 What do you understand by collector reverse saturation ? In which configuration does it
have a greater value ?
Ans. When input current (IE in case of CB configuration and IB in case of CE configuration) is
zero, collector current Ic is not zero although it is very small. In fact this is the reverse
leakage current or collector reverse saturation current (ICBO or simply ICO in CB configuration
and ICEO in CE configuration). In case of CE configuration it is much more than that in
case of CB configuration.
Q.21 What is quiescent point ?
Ans. Quiescent point is a point on the dc load line which represents VCE and IC in the absence of
ac signal and variations in VCE and IC take place around this point when ac signal is applied.
Q. 22 What is transistor biasing ?
Ans. The proper flow of zero signal collector current and the maintenance of proper collector-
emitter voltage during the passage of signal is called the transistor biasing.
Q.23 What is faithful amplification ?

Ans. The process of raising the strength of a weak signal without any change in its general shape
is referred to as faithful amplification.
Q.24 What is thermal runaway in transistor amplifier circuit?
Ans. The collector current Ic increases with the increase in temperature. This leads to increased
power dissipation. Being a cumulative process it can lead to thermal runaway resulting in
burn-out of the transistor.
Q.25 What is bias stabilization?
Ans. The maintenance of the operating or quiescent point stable (independent of temperature
variations or variations in transistor parameters) is known as bias stabilization.
Q.26 State the condition for thermal stability of operating point of a BJT amplifier.
Ans. The operating point should not shift with temperature variations.
EXERCISE
1. For a transistor connected in common base configuration, if IC = 0·95 mA and IB = 50 mA,

find the value of a. [Ans. 0·95]
2. In a grounded base configuration, the voltage drop across load resistance of 4 kW is 3.2 V.
Determine collector current, emitter current and base current if a = 0-96.
[Ans. 0·8 mA, 0·8333 mA and 0·0333 mA]
3. In a CB configuration, the value of a = 0·96. A voltage drop of 1·92 V is obtained across
a resistor of 2 K when connected in collector circuit. Find the base current.
[Ans. 40 mA]
4. In CB configuration, the emitter current is 1 mA. If collector current is 30 mA when the
emitter circuit is open. Determine the total current when a = 0·95. Also calculate the base
current. [Ans. 0·98 mA, 0·02 mA]
5. In CE configuration, if the voltage drop across 1 kW resistor connected in the collector
circuit is 2 V, determine the base current when b = 40. [Ans. 40 mA]
6. A change of 200 mV in base-emitter voltage causes a change of 60 mA in base current.
Determine its input resistance. [Ans. 3·33 kW]
7. Increase in collector-emitter voltage from 4 V to 8 V causes increase in collector current
from 5 mA to 6 mA. Determine the output resistance. [Ans. 4 kW]
8. In a common emitter circuit, the collector supply voltage is 12 V. When a resistor is connected
in the collector circuit RL = 2 kW, the voltage drop across it is 2 V. For a = 0·96, determine
(i) collector-emitter voltage,
(ii) collector current
(iii) base current [Ans. (i) 10 V,(ii) 1 mA, (iii) 41·67 mA]
ppp
BJT Biasing & Stabilisation

2.1 INTRODUCTION
The foremost function of a transistor is to do amplification (i.e., amplitude of a weak
signal is amplified). Usually, a weak signal is given to the base circuit of a transistor and an
amplified output is obtained at the collector. While doing amplification, care is to be taken
that the shape of the signal must remain the same. This amplification of the signal without
the change in its shape is known as faithful amplification.
In order to achieve faithful amplification, we have to provide some means by which the
emitter-base junction is kept in forward-biased and the collector-base junction is kept in
the reverse-biased condition during all parts of the signal. This is known as transistor
biasing.
In fact, to obtain faithful amplification, the quiescent (Q) point is set usually in the
middle of the dc load line. To achieve this some means (circuitry) are provided known as
transistor biasing. In this chapter, we shall discuss the various methods of providing
transistor biasing.
2.2 BIASING
Ø It means to give external dc to a device for a specific operation.
Ø It is also known as dc analysis.
Ø During this analysis all ac sources are made zero.
Ø It is needed to set a proper operating point of the device.
2.2.1 Transistor Biasing
Among the basic functions of a transistor is its amplification. For faithful amplification
(amplified magnitude of signal without any change in shape), the following three conditions
must be satisfied :
BJT Biasing & Stabilisation 25
(i) the emitter-base junction should be forward biased, (ii) the collector-base junction should
be reverse biased, and (iii) there should be proper zero signal collector current.
The proper flow of zero signal collector current (proper operating point of a transistor)
and the maintenance of proper collector-emitter voltage during the passage of signal
is known as transistor biasing.
When a transistor is not properly biased, it works inefficiently and produces distortion
in the output signal. Hence a transistor should be biased correctly. A transistor is biased
either with the help of battery or associating a circuit with the transistor. The latter method
is generally employed. The circuit used with the transistor is known as biasing circuit.
2.3 NECESSITY OF BIASING
For most of the applications, transistors are required to operate as linear amplifiers
(i.e. to amplify output voltage as a linear function of the input voltage). To achieve this, it
is necessary to operate the transistor over region of its characteristic curves which are
linear, parallel and equi-spaced for equal increments of the parameter. Such an operation
can be ensured by proper selection of zero signal operating point and limiting the operation
of the transistor over the linear portion of the characteristics. For proper selection of zero
signal operating point, proper biasing i.e. application of dc voltages at emitter-to-base junction
and collector-to-base junction is required.
If the transistor is not biased properly, it would work inefficiently and produce distortion
in the output signal.
Example-2.1
For the circuit shown in Fig. 2.1, find
(i) The maximum collector current that can be allowed to flow through it during the
application of signal for faithful amplification assuming that the transistor is a
silicon transistor.
(ii) The minimum zero signal collector current required.
(ii) The peak value of base current when b = 50.
Fig. 2.1 Fig. 2.2

Solution :
Here, VCC = 9 V ; RC = 4 kW
i) For faithful amplification, VCE = 1 V for silicon transistor.
\ Maximum voltage allowed across RC = 9 – 1 = 8 V
8V
Maximum allowed collector current = 4kW = 2mA
The maximum collector current should not be allowed to rise above this value other-
wise it will result in unfaithful amplification.
ii) When the signal is applied, the collector current can at the most be allowed to fall to
zero during the negative peak of the signal.
2mA
\ Zero signal collector current, IC = = 1 mA
2
At positive peak of the signal, iC = IC + ic = 1 + 1 = 2 mA
At negative peak of the signal, iC = 1 – 1 = 0
iii) Peak value of the signal collector current = 1 mA
iC 1 mA
Peak value of the signal base current, i B = = = 20 mA (Q i C = b i B )
b 50
2.4 TRANSISTOR BIASING CIRCUITS
There are four types of transistor biasing circuit :-
i) Fixed bias circuit
ii) Self / emitter - stabilized bias circuit. V CC
iii) Voltage divider bias circuit
iv) DC feedback bias circuit.
2.4.1 Fixed bias circuit
RB RC
Here the emitter resistance must be zero
i.e. RE = 0
C ac o/p
Biasing analysis means CO signal
dc analysis. So f = 0 ac i/p B
Ci
1 signal
Þ XC = ®¥
2pfc E
Thus capacitors can be replaced by
open circuit.
Fig. 2.3
V CC
Ib
RC
RB
o/p loop
C
+
So the circuit becomes ® B
VCE
+
V BE –
i/p loop – E
Fig. 2.4
The loop that covers, input junction is known as input loop & The loop that covers
output junction, know as output loop.
Input loop
Applying KVL in input loop, IB
VCC - I B R B - VBE = 0 RB +
–
VCC - VBE V CC
V BE
Þ IB =
RB
Fig. 2.5
Because VCC, VBE & RB are constant for a circuit, so IB is fixed. So it is fixed biasing.
Output loop IC
Here IC = bIB +
RC
Apply KVL in output loop,
V CE
VCC - I C R C - VCE = 0
– V CC
Þ VCE = VCC - I C R C
This is known as load line equation
Here VE = 0V Fig. 2.6
Now VCE = VC - VE
Þ VC = VCC – ICRC
VBE = VB – VE
= VB.
Advantage
Ø It is very simple.
Ø Circuit, has simple calculation and there is no loading of source, as no emitter
resistor.
Disadvantage :
Ø This method provides poor stability
Ø There is good chances of thermal runaway.
Example-2.2
Determine the following for the fixed-bias configuration of Fig.2.7.
(a) I BQ and I C Q
VCC=+12V
(b) VCE Q
(c) VB and VC
(d) VBC.
RC
2.2 kW
RB
240 kW C2
ac
10mF
output
C1
ac VCE
input
10mF
Fig. 2.7
Solution :
VCC - VBE 12 V - 0.7 V
(a) I BQ = RB
=
240kW
= 47.08mA
I C Q = bI BQ = (50)( 47.08mA ) = 2.35mA
(b) VCE Q = VCC - I C R C

= 12 V – (2.35 mA) (2.2 kW)
= 6.83 V
(c) VB = VBE = 0.7 V
VC = VCE = 6.83 V
(d) Using double-subscript notation yields
VBC = VB - VC = 0.7 V - 6.83 V
= – 6.13 V
with the negative sign revealing that the junction is reversed-biased, as it should be for
linear amplification.
V CC
2.4.2 Self / Emitter-Stabilized bias circuit

This circuit contains an emitter RB RC
resistor to improve the stability level.
IE C V0
So this is known as emitter-stabilized IB + C0
bias circuit. V CE
Vi
Ci B + –
V BE– E
Input loop IE
RE
Applying KVL,
Fig. 2.8
VCC – IBRB – VBE – IERE = 0
Now IE = IC + IB
= bIB + IB
= (b + 1) IB
So VCC – IBRB – VBE – (b + 1) IBRE = 0 IB RB
IE
VCC - VBE V CC RE
IB =
Þ b g
RB + b + 1 RE Fig. 2.9
Here input loading effect due to RE is
Ri = (b +1) RE
Output loop
IC = bIB ~ IE
RC
Applying KVL in output loop,
+
VCC – ICRC – VCE – ICRE = 0 V CE IC
Þ VCE = VCC – IC (RC + RE) ® Load line equation V CC
–
IE
Here VE = IERE
VCE = VC – VE Þ VC = VCE + VE = VCC – ICRC RE
VBE = VB – VE Þ VB = VBE + VE
VCC Fig. 2.10

The saturation current ICsat =
RC + RE
Example-2.3
For the emitter bias network of Fig. 2.11, determine.
(a) IB . +20 V
(b) IC.
(c) V CE
(d) V C
(e) V E 2 kW
(f) V B 430 kW 10 mF
v0
(g) V BC
10 mF b = 50
vi
1kW 40 mF
Fig. 2.11
Solution :
VCC - VBE 20V - 0.7 V

(a) I B = R + (b + 1) R = 430 kW + (51)(1kW)
B E
19.3 V
= = 401
. mA
481 kW
(b) IC = bIB
= (50) (4.1 mA)
@ 2.01 mA
(c) VCE = VCC – IC (RC + RE)
= 20 V – (2.01 mA)(2kW + 1kW) = 20 V – 6.03 V
= 13.97 V
(d) V C = VCC – ICRC
= 20 V – (2.01 mA)(2kW) = 20 V – 4.02 V
= 15.98 V
(e) V E = VC – VCE
= 15.98 V – 13.97 V
= 2.01 V
or VE = IERE @ ICRE
= (2.01 mA)(1 kW)
= 2.01 V
(f) VB = VBE + VE
= 0.7 V + 2.01 V
= 2.71 V
(g) VBC = VB – VC
= 2.71 V – 15.98 V
= – 13.27 V (reverse-biased as required)
2.4.3 Voltage - Divider biasing
VCC
Since b is temperature sensitive, the
Q-point is not stable. So a bias circuit is
designed so that Q-point will be R1 RC
independent of b. V0
C0
Here two resistors are used at input Vi
side so whole dc supply is not given to Ci
input, rather a part of it is given. So it is
R2
voltage divider bias. Circuit.
There are two types of analysis : RE CE
i) Exact analysis
ii) Approximate analysis.
Fig. 2.12
Exact analysis
VCC
First using Thivenin’s theorem, the input
circuit connected between base to emitter RC
can be replaced by single voltage VTh,
series with RTh,
R1
VCC R2 RE
Fig. 2.13
VTh = Voltage across R2 i.e at open end.
R2 +
= VCC R1
R1 + R 2
V CC VTh
R2
–
Fig. 2.14
RTh = Resistance observed from open
end with dc sources = 0. R1
R1R 2
= R2
R1 + R 2
RTh
Input loop
By KVL Fig. 2.15
b g
TTh - I B R Th - VBE - b + 1 I B R E = 0
IB B
VTh - VBE
Þ IB = R + b + 1 R
Th Eb g RTh
+
V BE
IE
E
VTh –
RE
Fig. 2.16
Output loop
Here IC = bIB ~ IE IC
So by applying KVL, RC
VCC – ICRC – VCE – ICRE = 0
+
Þ VCE = VCC – IC (RC + RE)
VCE
V CC
V E = IERE = Voltage at emitter terminal.
–
VCE= VC – VE Þ VC = VCE + VE = VCC – ICRC IE
VBE= VB – VE Þ VB = VBE + VE RE
Fig. 2.17
Approximate analysis :
V CC
This analysis is applicable if it satisfies following condition :-
bR E ³ 10R 2 i. e R i ³ 10R 2
RC
Under this condition there will be
approximately no base current to the C +
IB~ 0 RTh
transistor. B
V CE
Now VB = VTh + –
Then VE = VB – VBE V BE – E
VE VTh RE
and IE = ~ IC
RE
Fig. 2.18
So VC = VCC – ICRC
& VCE = VC – VE
This makes analysis easier
Example-2.4
Determine the levels of I CQ and VCE Q 18 V

for the voltage-divider configuration of
Fig. 2.19 using the exact and
approximate techniques and compare
5.6 kW
solutions. 82 kW
I CQ
Solution : 10 mF
v0
+
Exact Analysis vi VCEQ b = 50
bRE > 10R2 10 mF –
(50)(1.2 kW) > 10 (22 kW) 22 kW 1.2 kW

60 kW ³/ 220 kW (not satisfied)
RTh R1|| R2 = 82 kW || 22 kW = 17.35 kW Fig. 2.19
R 2 VCC 22 kW (18 V)
E Th = = = 381
. V
R1 + R 2 82 kW + 22 kW
E Th - VBE . V - 0.7 V
381 311
. V
IB = = = = 39.6 mA
b g
R Th + b + 1 R E 17.35 kW + (51)(12
. kW) 78.55 kW
I C Q = bI B = (50)( 39.6 mA ) = 1.98 mA
b
VCE Q = VCC - I C R C + R E g
= 18 V – (1.98 mA)(5.6 kW + 1.2 kW)
= 4.54 V
Approximate Analysis
VB = ETh = 3.81 V
VE = VB – VBE = 3.81 V – 0.7 V = 3.11 V
VE 311. V
I CQ @ I E = = = 2.59 mA
. kW
R E 12
b
VCE Q = VCC - I C R C + R E g
= 18 V – (2.59 mA)(5.6 kW + 1.2 kW)
= 3.88 V
Tabulating the results, we have :
I CQ ( mA ) VCE Q ( V)
Exact 198
. 4.54
Approximate 2.59 388
.
2.4.4 DC feedback biasing

Feedback means to give some part of output to the input of same circuit. It is given to
increase the stability. V CC
Here RB is feedback component.
RC
i/p
IC+IB=IE
loop IC
IB
RB V0
C
Input loop V CE C 0
Vi B
V BE O/p
Applying KVL, E loop
VCC – IERC – IBRB – VBE – IERE = 0 RE
b g b g
Þ VCC - b + 1 I B R C - I B R B - VBE - b + 1 I B R E = 0 I E
Fig. 2.20
VCC - VBE
Þ IB = R + b + 1 R + R
B b gb
C E g
Þ IB ~ IB = VCC - VBE
b
R B + b RC + R E g
Output loop
IC ~ IE @ bI B
Applying KVL,
VCC – ICRC – VCE – ICRE = 0
Þ VCE = VCC – IC (RC + RE)
Here VE = IERE
VC = VCE + VE
VB = VBE +VE
Example-2.5 18 V
Determine the dc level of IB and VC
for the network of Fig. 2.21. 3.3 kW
91 kW 110 kW 10 mF
v0
R1 R2
10 mF 10 mF
Solution : vi b = 75
In this case, the base resistance for the dc analysis
is composed of two resistors with a capacitor
510 W 50 mF
connected from their junction to ground. For the dc
mode, the capacitor assumes the open-circuit
equivalence and RB = R1 + R2. Fig. 2.21
Solving for IB gives
VCC - VBE
IB =
b
R B + b RC + R E g
18V - 0.7 V
=
(91kW + 110kW) + (75)(3.3kW + 0.51kW)
17.3 V 17.3 V
= =
201 kW + 285.75 kW 486.75 kW
= 35.5 mA
IC = bIB
= (75)(35.5 mA)
= 2.66 mA
VC = VCC – I ' C R C @ VCC - I C R C
= 18 V – (2.66 mA)(3.3 kW)
VCC = 20 V
= 18 V – 8.78 V
= 9.22 V 4.7 kW
RC
Example-2.6 RB 10 mF
v0
For the network of Fig. 2.22 : 680 kW C2
10 mF
(a) Determine I C Q and VCE Q .
vi
b = 120
(b) Find VB, VC, VE, and VBC. C1
Fig. 2.22
Solution :
(a) The absence of RE reduces the reflection of resistive levels to simply that of RC and
the equation for IB reduces to
VCC - VBE
IB =
R B - bR C
20 V - 0.7 V 19.3 V
= =
680 kW + (120)(4.7 kW) 1244
. MW
= 15.51 mA
I C Q = bI B = (120)(15.51mA )
= 1.86 mA
VCE Q = VCC - I C R C
= 20 V – (1.86 mA)(4.7 kW)

= 11.26 V
VB = VBE = 0.7 V
VC = VCE = 11.26 V
VE = 0 V
VBC = VB – VC = 0.7 V – 11.26 V
= – 10.56 V
Example-2.7
Determine
RC, RE, RB, VCE, VB in figure 2.23
Solution : 12V IC=2mA
Here VE = 2.4 V
Þ ICRE = 2.4 Þ 2.RE = 2.4 Þ RE = 1.2 KW RB RC
VC = 7.6 V Þ VCC– ICRC = 7.6
7.6V
Þ 12 – 2RC = 7.6
12 - 7.6 B b = 80
Þ RC = = 2.2 KW
2
By input KVL E 2.4V
12 – IBRB – VBE – ICRE = 0 RE
2
Þ 12 - RB - 0 × 7 - 2 ´ 4 = 0 Fig. 2.23
80
8 × 9 ´ 80
Þ RB = = 356 KW
2
VCE = VC – VE = 7 × 6 – 2 × 4 = 5 × 2 V
VBE = VB – VE
Þ VB = VBE + VE = 0 × 7 + 2 × 7 = 3 × 1 V
Example 2.8 VCC
In a voltage divider bias circuit
RC = 2 × 7 KW, RE = 1 × 2 KW, R2= 8 × 2 KW, VC=10 × 6V,, R1 RC
IB = 20 mA & b = 100. Then Find VCC, VB, R1.
b = 100
Solution : R2
RE
VC = VCC – ICRC = 10.6
Þ VCC – bIBRC = 10.6 Fig. 2.24
Þ VCC = (100 × 20 × 10 × 2.7) + 10.6
–3
VCC
= 5.4 + 10.6
Þ VCC = 16 V. RC = 2.7KW
So VE = ICRE = bIBRE IC
VC=10.6V
= 2 × 1.2 IB +
= 2.4 V + VCE
RTh
Þ VB = VBE + VE – –
= 0.7 + 2.4
VTh
VB = 3.1V RE=12KW
Þ VTh – IBRTh = 3.1
R 2 VCC R 1R 2 Fig. 2.25

Þ R + R - I B R + R = 31.
1 2 1 2
8.2 ´ 16 R ´ 8.2
Þ - 0.02 1 = 31
. Þ 131.2 – 0.164 R = 25.42 + 3.1R
8.2 + R1 8.2 + R1 1 1
Þ 3.264 R1 = 105.78
Þ R1 = 32.4 KW Ans.
Example-2.9
Find the range of VC due to potentiometer 12V
of 1MW.
1MW 4.7KW
Solution : 150KW
There is a potentiometer of 1mW i.e it can
b= 180
vary from 0 to 1MW.
When potentiometer is at 0W
Now by input KVL,
12 - I C ( 4.7) - 150 I B - 0.7 - I C (33) = 0 3.3K W
Þ 12 – 180 IB × 4.7 – 150 IB – 0.7 – 180 IB × 33 = 0
Fig. 2.26
Þ 12 – 846IB – 150 IB – 0.7 – 594 IB = 0
12V
11.3
Þ IB = = 7.1mA IE ~ IC
1590
IC = bIB = 1.279 mA 4.7KW
So VC = 12 – ICRC VC
150KW
= 12 – 1.279 × 4.7
= 5.987 V IB
IE ~ IC
3.3KW
When potentiometer is at 1MW = 1000 KW
Fig. 2.27
12 - 0.7
IB =
1150 + 180(4.7 + 3.3)
12V
= 4.36 mA
I C = bIB = 180 × 4.36 mA 4.7KW
= 0.785 mA
V C = VCC – ICRC VC
1150KW
= 12 – 0.785 × 4.7
= 8.3 V
So range of VC is 5.987 V – 8.3V
3.3KW
Fig. 2.28
Example-2.10 18V
Find IB, IC, VE, VCE
9.1KW
510KW
b = 130
510KW 7.5KW
Solution : Fig. 2.29
– 18V
The circuit can be redrawn as :-
18V
9.1K W
510KW
510KW 7.5KW
18V
18V 18V
The Circuit connected to transistor Fig. 2.30

i/p junction is.
+
510 ´ 510
Here RTh = 510 || 510 = 510KW
510 + 510 510KW V
Th
= 255 KW 18V
18V
FG 510 b18 + 18g IJ - 18 –
VTh =
H 510 + 510 K 18V
Fig. 2.31
= 0V
9.1KW
So the circuit becomes :-
By i/p KVL, C
B +
– 255 IB – 0.7 –7.5 (130 IB) + 18 = 0 V CE
255KW –
17.3 V BE E
Þ IB = = 0.01406 mA
1230 7.5KW
IC = bIB = 130 × 0.01406
@ 1.83 mA
VE = IC × 7.5 – 18 @ – 4.375V – 18V Fig. 2.32
By output KVL, 18 – 1.83 × 9.1 – VCE – 1.83 × 7.5 + 18 = 0
Þ VCE @ 5.62 V
Example-2.11 Find IE, VC & VCE
–8V
2.2KW
1.8KW
Solution :
The Circuit can be redrawn as - 10V
Fig. 2.33
By input KVL,
10V
–VBE – 2.2 × bIB + 8 = 0
7.3 1.8KW
Þ IB =
220 C
B +
7.3
IE ~ bIB =
2.2
= 3.31 mA + V CE b=100
V BE – –
VC = 10 – 3.31 × 1.8 ~ 4V
2.2KW
By output KVL,
10 – 1.8 × 3.31 – VCE – 2.2 × 3.31 + 8 =0
–8V Fig. 2.34
Þ VCE @ 18 – 13.2 = 4.8 V
Example-2.12
Determine VCE for the voltage-divider –18 V
bias configuration of Fig. 2.35
2.4 kW
47 kW 10 mF
v0
10 mF B
C
+
vi VCE b = 120
Solution
E –
Testing the condition
10 kW
bRE > 10R2 1.1 kW
results in (120)(1.1kW) > 10(10 kW)

132 k > 100 kW (satisfied) Fig. 2.35
Solving for VB, we have
R 2 VCC (10kW)( -18V)
VB = = = -316
. V
R1 + R 2 47 kW + 10kW
Applying Kirchhoff’s voltage law around the base-emitter loop yields

+VB – VBE – VE = 0
VE = VB – VBE
and VBE = – 0.7V for PNP transistor
Substituting values, we obtain
VE = – 3.16 V – ( 0.7 V)
= – 3.16 V + 0.7 V
= – 2.46 V
The current
VE 2.46 V
IE = = = 2.24 mA
. kW
R E 11
For the collector-emitter loop :
–IERE + VCE – ICRC + VCC = 0
Substituting IE @ IC and gathering terms, we have
VCE = – VCC + IC (RC + RE)
Substituting values gives
V CE = – 18 V + (2.24 mA) (2.4 kW + 1.1 kW)
= – 18 V + 7.84 V
= – 10.16 V
Example 2.13
Determine VC and VB for the
network of Fig. 2.36 RC 1.2 kW
C2
v0
10 mF
C1
Vi b = 45
10 mF
RB 100 kW
Solution : –VEE= –9V
Fig. 2.36
Applying Kirchhoff’s voltage law in the clockwise
direction for the base-emitter loop will result in
- I B R B - VBE + VEE = 0
VEE - VBE
and IB =
RB
Substitution yields
9 V - 0.7 V
IB =
100 kW
8.3 V
=
100 kW
= 83 mA
IC = bIB
= (45) (83 mA)
= 3.735 mA
VC= ICRC
= – (3.735 mA)(1.2 kW)
= – 4.48 V
VB = –IBRB
= – (83 mA) (100 kW)
= – 8.3 V
Example-2.14
Determine VCE Q and IE for the network of

Fig. 2.37.
C1
vi b = 90
10mF C2
RB 240 kW v0
10 mF
Solution : RE 2 kW
Applying Krichhoff’s voltage law to the
input circuit will result in –VEE –20 V Fig. 2.37
- I B R B - VBE - I E R E + VEE = 0
but I E = (b + 1) I B
and V EE – VBE – (b + 1) IBRE – IBRB = 0
VEE - VBE
IB =
with b g
RB + b + 1 RE
Substituting values yields
20V - 0.7 V
IB =
240kW + (91)(2 kW)
19.3 V 19.3V
= =
240 kW + 182 kW 422 kW
= 45.73 mA
IC = bIB
= (90) (45.73 mA)
= 4.12 mA
Applying Kirchoff’s voltage law to the output circuit, we have
– VEE + IERE + VCE = 0
but IE = (b + 1)IB
and VCE Q = VEE - (b + 1) I B R E
= 20 V – (91)(45.73 mA)(2 kW)
= 11.68 V
IE = 4.16 mA
Example-2.15 VCC = +20V
Determine VC and VB for the
network of Fig. 2.38
RC 2.7 kW
R1 8.2kW
C C2
C1 v0
10mF
vi
10 mF
E
R2 2.2 kW RE 1.8 kW
Solution :
The Thevenin resistance and voltage are
–VEE = – 20V
determined for the network to the left of the
base terminal as shown in Figs. 2.39 and 2.40. Fig. 2.38
R1 8.2 kW
B B
8.2 kW +
R2 2.2 kW R2 22.kW
VCC ETh
20 V
RTh VEE 20 V –
Fig. 2.39 Determining RTh. Fig. 2.40 Determining E Th

RTh :
RTh = 8.2 kW || 2.2 kW = 1.73 kW
ETh :
VCC + VEE 20V + 20V 40V

I= = =
R1 + R 2 8.2 kW + 2.2 kW 10.4 kW
= 3.85 mA
ETh = IR2 – VEE
= (3.85 mA)(2.2 kW) – 20 V
= – 11.53 V
RTh – VB
+
The network can then be redrawn as shown b = 120
in Fig. 2.41, where the application of 1.73 kW +
IB VBE
Kirchhoff’s voltage law will result in – E
ETh 11.53 V +
– ETh – IBRTh – VBE – IERE + VEE = 0 RE 1.8 kW
–
Fig. 2.41 VEE = – 20V
Substituting IE = (b + 1) IB gives
VEE – ETh – VBE – (b + 1) IBRE – IBRTh = 0
VEE - E Th - VBE
and IB =
R Th + ( b + 1) R E
20V - 1153
. V - 0.7 V
=
. kW + (121)(18
173 . kW)
7.77 V
=
219.53 W
= 35.39 mA
IC = bIB
= (120)(35.39mA)
= 4.25 mA
VC = VCC – ICRC
= 20 V – (4.25 mA)(2.7 Wk)
= 8.53 V
VB = –ETh – IBRTh
= – (11.53 V) – (36.39mA)(1.73 Wk)
= – 11.59 V
2.5 BIAS STABILIZATION

Only the fixing of a suitable operating point is not sufficient but it is also to be ensured
that the operating point remains stable i.e. it does not shift due to change in temperature or
due to variations in transistor parameters (due to replacement of transistor). Unfortunately
it is not possible in practice unless special efforts are made to achieve it.
The maintenance of the operating point stable (independent of temperature variations
or variations in transistor parameters) is known as stabilization.
2.6 NEED FOR BIAS STABILIZATION
The stabilization of operating point is essential because of
(i) Temperature dependence of collector current IC
(ii) Individual variations and
(iii) Thermal runaway.
(i) Temperature Dependence of Collector Current IC. The instability of collector current
IC, being equal to b IB + (1 + b) ICO, due to variations in temperature, is caused because of
the three following main factors.
(a) Reverse saturation current (leakage current), ICO, which doubles for every 10° C
rise in temperature.
(b) Transistor current gain ‘b’, which increases with the increase in temperature.
(c) Base-emitter voltage VBE, which decreases by 2.5 m V per0 C.
Any or all of the above factors can cause the bias point to shift from the values
originally fixed by the circuit because of a change in temperature.
Though with the change in temperature collector-emitter voltage V CE also changes
but the change is very small and collector current IC is not affected.
(ii) Individual Variations. The value of ‘b’ and ‘V’BE are not exactly the same for any
two transistors even of the same type. For an example BC 147 is a silicon transistor with
b varying from 100 to 600 (for one transistor b may be 100 and for the other it may be
600). The major reason for these variations is that transistor is a new device and
manufacturing techniques have not too much advanced. For an instance, it has not been
possible to control the base width and it may vary, although slightly, from one transistor to
another one of the same type. Such little variations result in a large change in the transistor
parameters such as b, VBE etc.
Thus when a transistor is replaced by another of the same type, the operating point
may shift. Such problems do not arise in case of vacuum tube circuits because it is possible
to manufacture vacuum tubes with identical characteristics.
(iii) Thermal Runaway. The collector current IC, being equal to b IB + (1 + b) ICO, increases
with the increase in temperature. This leads to increased power dissipation with further
increase in temperature. Being a cumulative process it can lead to thermal runaway
resulting in burn-out of the transistor. The self destruction of an unstabilized transistor is
called the thermal runaway.
However, if by some modification, IB is made to fall with increase in temperature
automatically, then decrease in the term b IB can be made to neutralize the increase in the
term (1 + b) ICO, thereby keeping IC almost constant. This will achieve thermal stability
resulting in bias stability.
2.7 STABILITY FACTOR
It is the ratio of change in collector current with change in any transistor constants.
It is of three types :-
S I CO = DI C DI CO VBE & b = Cons tan t
S VBE = DI C DVBE I CO & b = Cons tan t
Sb = DI C Db I
CO & VBE = Cons tan t
Ø Higher is the stability factor, the more sensitive the network variations in that
parameter i.e. the circuit exhibits thermal instability.
Ø To be stable & relatively insensitive to temperature variation, the circuit should have
low value of stability factor.
2.7.1 General Expression for SI CO
IC = bIB + (b+1) ICO
Now differentiating expression w.r.t IC, considering b constant,
dI C
dI C
dI
b g
dI
= b B + b + 1 CO
dI C dI C
dI B b + 1
Þ 1 = b dI + S
C I CO
dI B b + 1 b +1
Þ 1 = b dI + S Þ SI CO =
dI
1- b B
C I CO
dI C
2.7.2 General Expression for Sb
IC = bIB + (b+1) ICO
Differentiating the expression w.r.t IC considering ICO Constant ;
1= b
FG dI B
+ IB
db IJ
+ I CO
db
H di C dI C K dI C
I + IB
Þ 1- b
dI B
dI C
b
= I B + I CO
1
Sb
g
Þ Sb = CO
dI
1- b B
dI C
2.7.3 Stability factors in different Bias Circuit

In Fixed bias :
VCC - VBE
IB =
RB
¶IB
Þ =0
¶IC
So SI CO = b + 1
Sb = I CO + I B
Now I C = bI B = b
FG V - VBE IJ
H K
CC
RB
¶I C -b
Þ =
¶VBE R B
-b
Þ SVBE =
RB
As stability factors are dependent on b . So this circuit is least stable.
In Self / Emitter- Stabilized Circuit :
VCC - I B R B - VBE - I E R E = 0
Þ VCC – IBRB – VBE – (IC + IB) RE = 0 ....(1)
Differentiating w.r.t to IC, considering VBE Constant,
¶I B ¶I
0 - RB - 0 - RE - RE B = 0
¶I C ¶I C
¶I B -R E
Þ =
¶I C R B + R E
b +1
So SI CO =
RE
1+ b
RB + RE
FG1 + R IJ
H RK
B
Þ SI CO = bb + 1g E
bb + 1g + RR B
E
I CO + I B
and Sb =
RE
1+ b
RB + RE
It is also given as
æ R ö
IC1 ç1 + B ÷
Sb = è RE ø
æ R ö
b1 ç1 + b2 + B ÷
è RE ø
IC1 & b1 are the values under one network condition but b 2 is the new value due to tem-
perature change.
Here I C = bI B = b
FG V - VBE IJ
HR K
CC
B + bR E
¶I C -b
Þ =
¶VBE R B + bR E
-b
Þ S VBE =
R B + bR E
In voltage divider bias circuit :
In self bias expressions, VCC is replaced by VTh & RB is replaced by RTh.
R Th
1+
So SI CO b g
= b +1
RE
b g
R
b + 1 Th
RE
R Th
1+
b
Sb = I CO + I B g RE
b g R ,
b + 1 Th
RE
It is also given as
æ R ö
IC1 ç1 + Th ÷
Sb = è RE ø
æ R ö
b1 ç1 + b2 + Th ÷
è RE ø
IC1 & b1 are the values under one network condition but b 2 is the new value due to tem-
perature change.
-b
S VBE =
R Th + bR E
R Th
Here as < <b + 1
RE
So SI CO ~ 1 i.e. independent of b.
So it is most stable.
In dc feedback bias circuit :
The input KVL is
b g
VCC - I C + I B R C - I B R B - VBE - I C + I B R E = 0 b g
Differentiating w.r.t to IC with constant b & VBE,
0 - 1+
FG IJ
dI B dI dI
RC - B RB - 1+ B RE = 0
FG IJ
H dI CK dI C dI C H K
Þ
dI B F R +R
= -G
IJ
HR +R +R K
C E
dI C B C E
b +1
S I CO =
So
1+ b
FG
RC + RE IJ
H
RB + RC + RE K
RB
1+
RC + R E
SI CO b g
= b +1
b +1 b g
RB
RC + RE
RB
1+
RC + RE
& b
Sb = I CO + I B g
b g
b +1
RB
RC + R E
æ R ö
IC1 ç1 + B ÷
or Sb = è RE ø
æ R ö
b1 ç1 + b2 + B ÷
è RE ø
Example 2.16
VCC = 12V
Fig 2.42 shows the circuit of fixed bias using
a silicon transistor with b = 100. Determine IB IC
(i) base current, (ii) collector current (iii) VC,
1,130 k RC = 4kW
V B and V CB (iv) operating point and
(v) stability factor S.
B
Solution : IE
VCC - VBE Fig. 2.42

Base current, IB= RB
Here VCC= 12 V, RB = 1, 130 × 103 W
VBE for silicon transistor = 0.7 V
12 - 0.7
(i) IB = - 10m A Ans.
1,130 ´ 103
(ii) Collector current, IC = bIB = 100 × 10 × 10–6 = 1 m A Ans.
(iii) Collector-emitter voltage,V CE = VCC – IC RC
= 12 – 1 × 10–3 × 4 × 103 = 8 V
Collector voltage, VC = VCE = 8 V Ans.
because VE = 0
Base voltage, VB = Base-emitter voltage, VBE = 0.7 V Ans
Collector-base voltage, V CB = VC – VB = 8 – 0.7 = 7.3 V Ans.
(iv) Operating point, Q = (VCE, IC) = (8 V, 1 m A) Ans.
(v) For fixed bias stability factor, S = b + 1 = 100 + 1 = 101 Ans.
Example 2.17
In a fixed bias circuit using transistor with a = 0.97, the temperature changes from 300C to
600C producing change in IC from 2.2 mA to 3.8 m A. Assume reverse saturation current
changes 1.7 mA/oC. What is stability factor ?
Solution :
Change in collector current, DIC = 3.8 – 2.2 = 1.6 m A or 1.6 × 10–3A
Change in temperature, Dt = 60 – 30 = 30oC
Change in reverse saturation current for Dt of 30oC
DICO = 30 × 1.7 × 10–6 = 51 × 10–6 A
DI C 1.6 ´ 10 -3
Stability factor, S = = = 31.37 Ans.
DI CO 51 ´ 10 -6
2.8 DESIGN GUIDELINES OF TRANSISTORS BIASING CIRCUITS

In practice, for low powered transistors, the following guidelines are used as tips for designing
biasing circuits :
1. For better stabilisation, the value of RE should be kept high, but it produces larger
voltage drop across it. This leaves a smaller voltage drop across the collector load
resistor RC . Consequently, the output decreases. Therefore, a compromise has to be
made while selecting the value of RE . In common practice the value of RE is selected
between 500 to 1000 W.
2. The zero signal current IC is chosen so that the operating point lies in the centre of the
dc load line. For most of the amplifiers IC is selected as 1 mA. This value of IC is
considered to be most suitable because of the following reasons :
(i) At 1 mA, the output impedance of a transistor is very high. This increases the
voltage gain.
(ii) The collector junction is not overheated at this value of IC.
3. Usually, emitter voltage is maintained one-tenth of the supply voltage, i.e.,
VE=V2 = 0.1 VCC
To locate the Q point at the middle of the dc load line, the voltage across collector-
emitter terminals should be 0.5 VCC. The remaining voltage 0.4 VCC appears across the
collector resistor, therefore,
RC = 4 RE
4. The values of resistors R1 and R2 are so selected that the current flowing through them
I1 should be at least 10 times the base current IB i.e., I1 > 10 IB . This condition provides
for better stabilisation.
Example-2.18
A potential divider biasing circuit of an
npn germanium transistor is shown in
Fig.2.43. To fix the operating point at
IC = 2.5 mA, VCE = 3 V, find the values of
R1, R2 and RE.
Assuming the other circuit component and
transistor parameters to be VCC = 12 V, RC
= 3kW , b = 50 and I1 = 10 IB .
Solution :
Here,
VCC = 12 V, RC = 3 kW, b = 50, IC = 2.5 mA,
Fig. 2.43
VCE = 3 V and I1 = 10
VBE = 0.3 V (for Ge transistor)
IC 2.5
Base current, IB = = = 0.05 mA
b 50
Since IB is very small as compared to I1 , for reasonable accuracy it may be assumed
that same current I1 flows through R1 and R2
I1 = 10IB = 10 × 0.05 = 0.5 mA
VCC
Now, I1 =
R1 + R 2
VCC 12
\ R1 + R 2 = = = 24 kW
I1 0.5 mA
Writing loop equation for the collector-emitter (output) circuit, we get,
or VCC = IC R C + VCE + IC R E
or 12 = 2.5 mA × 3 kW + 3 + 2.5 mA × RE
12 - 7.5 - 3 1.5 V
\ RE = = = 600 W (Ans.)
2.5 mA 2.5mA
Voltage across R2, V2 = VBE + ICRE = 0.3 + 2.5 mA × 600 W = 0.3 + 1.5 = 1.8 V
V2 1.8
Resistance, R2 = = = 3.6 kW (Ans).
I1 0.5mA
Resistance, R1 = 24 – 3.6 = 20.4 kW (Ans.)
Example-2.19
An npn silicon transistor amplifier circuit is shown in Fig. 2.44. The values of
various components and transistor parameters are as under.
a = 0.985, VCC = 18V, RE = 2W
Calculate the value of R1, R2 and RC to set Q point at IC = 2 mA, VCE = 6 V.
Fig. 2.44
Solution :
Here, a = 0.985, VCC = 18 V, RE = 2 kW, IC = 2mA, VCE = 6 V,
VBE = 0.7 V (for Si transistor)
a 0.985
Now, b= = = 65.66
1 - a 1 - 0.985
IC 2 mA
Base current, IB = = = 0.33 mA
b 65.66
For design, considering I1 to be 10 times of IB;
I1 = 10 IB = 10 × 0.03 = 0.3 mA
Since IB is quite small to I1, we assume that same current I1 flows through R2 also.
VCC
\ I1 =
R1 + R 2
VCC 18
or, R1 + R 2 = = = 60kW
I1 0.3mA
Writing loop equation for the collector side, we get,
or, VCC = IC R C + VCE + I C R E (QI C ; I E )
or 18 = 2 mA × RC + 6 + 2 mA × 2 kW
18 - 6 - 4
or RC = = 4 kW (Ans.)
2 mA
Writing loop equation for the base emitter circuit, we get,
V2 = VBE + IERE (QI C ; I E )
or, I1R2 = V2 = VBE + IERE
or 0.3 mA × R2 = 0.7 + 2 mA × 2kW
0.7 + 4
or R2 = = 15.67 kW (Ans.)
0.3 mA
Now, R1 + R2 = 60W
or R1 = 60 – R1 = 60 – 15.67 = 44.33 kW (Ans.)
Q.1 What is bias stabilization ?

Ans : The maintenance of the operating or quiescent point stable (independent of temperature
variations or variations in transistor parameters) is known as bias stabilization.
Q.2 What is meant by mid-point biasing ?
Ans. When an amplifier circuit is so designed that the operating point, Q lies at the centre of the
dc load line, the amplifier is said to be midpoint biased.
Q.3 What is stability factor ?
Ans. Stability factor is defined as the rate of change of collector current Ic w.r.t. any one factor
of reverse saturation current Ico, VBE or b when other factors are constant.
Q.4 Why a fixed bias circuit is not commonly used ?
Ans. Rise in temperature causes increase in leakage current Ico, increase in current amplification
factor b and decrease in base-emitter voltage VBE, so operating point is not stabilized. This
is the reason that fixed bias circuit is not commonly used.
Q.5 Explain why collector-to/base bias circuit is seldom used?
Ans. The base resistor RB not only provides a dc feedback for the stabilization of the operating
point, but it also causes an ac feedback in a collector-to-base bias circuit. This is the reason
that this circuit is not much used.
Q.6 What is an amplifier ?
Ans. The device that amplifies the amplitude of the input signal is called the amplifier. An amplifier
may be defined as a device that increases the current, voltage or power of an input signal
with the help of a transistor by furnishing the additional power from a separate source of
supply.
Q.7 What is meant by small signal amplifier ?
Ans. When the input signal is quite weak and produces small fluctuations in the output current
in comparison to its quiescent value, the amplifier is called the small signal or voltage
amplifier.
Q.8 Explain how a BJT can be used as a switch.
Ans. A transistor can operate as a switch if it is simultaneously driven in saturation (closed
switch) and in cut-off (open switch) regions.
EXERCISE
1. In a fixed bias circuit using transistor with a = 0·97, the temperature changes from 30°C to
60°C producing change in IC from 2·2 mA to 3·8 mA. Assume reverse saturation current
changes1·7 mA/°C. What is the stability factor?
[Ans. 31·37]
3. A transistor uses potential divider method of biasing. R1 = 50 KW, R2 = 10 KW
and RE = 1 KW. If VCC = 12 V, find
(i) the value of IC ; given VBE = 0·1 V
(ii) the value of IC ; given VBE = 0·4 V. Comment on the result.
[Ans. (i) 1-9 mA, (ii) 1·7 mA (IC is independent of transistor param-
eters because Ic changes only by 10% while VBE varies by 300%)]
4. In a common emitter amplifier, R1 = 100 KW, R2 = 10 KW, RE = 1 KW and a = 0·98.
According to manufacturer’s data, collector reverse saturation current varies from 5 to 25
mA over the working temperature range. Find the variation in collector current IC when
(i) amplifier is unstabilized and (ii) stabilizing resistor RE is used.
[Ans. (i) 1 mA, (ii) 170·8 mA]
5. In a self biased CE amplifier , RL = 5 KW, R2 = 9 KW, R1 = 81 KW b = 50 and RE = 810
W. Compute the stability factor S.
[Ans. S = 9·2]
6. A silicon transistor having b = 52, VBE = 2·6 V, VCC = 24 V and RL = 5 KW is used in CE
amplifier. The operating point is required to be established at VCE = 12 V and IC = 2 mA
with stability factor not exceeding 4. Find suitable values of RE, R1 and R2.
[Ans. RE = 1 KW, R1 = 28·13 KW and R2 = 3·648 KW]
7. Find the quiescent current and the collector to emitter voltage for a silicon transistor with
b = 50 in the self-biasing arrangement. The circuit component values are VCC = 20 V,
RE = 2 KW, RL = 100 KW, R1 = 100 W and R2 = 5 KW.
[Ans. 1·26 mA,17·35 V]
8. An NPN transistor amplifier circuit uses self-biased arrangement and has a = 0·985 and
VBE = 0·3 V. If VCC = 16 V. Calculate R1 and RL to place Q point at IC = 2mA, VCE = 6 volt.
[Ans. 54·4 KW, 3KW]
9. A silicon NPN transistor amplifier circuit uses self-biased arrangement with following
parameters :
R1 = 10KW, R2 = 5KW, RL = 1KW, RE = 2KW, VCC = 15V and b =100.
Calculate exact value of emitter current.
[Ans. 2·11 mA]
ppp
Field Effect Transistors & Biasing

3.1 INTRODUCTION
So far we have discussed the circuit applications of ordinary transistors which are
also called bipolar junction transistor (BJT). These transistors are called bipolar junction
transistors because their operation relies on two types of charges i.e. holes and electrons.
The bipolar transistors are the backbone of linear electronics and are applied in most of the
linear applications. As bipolar transistors have low input impedance and considerable noise
level, therefore, in some of the applications unipolar transistors are better suited. The
operation of unipolar transistors depends upon only one type of charge i.e. either holes or
electrons.
There are two types of field-effect transistors namely the junction field effect
transistors (abbreviated as JFET or simply FET) and the insulated-gate field effect
transistors (IGFET) more commonly called the metal-oxide-semiconductor transistor
(abbreviated MOST or MOSFET). In this chapter, we shall focus our. attention on the
construction, working and circuit applications of these transistors.
3.2 DIFFERENCE BETWEEN BJT & FET
FET BJT
1) Voltage Controlled current source 1) Current controlled current source.
2) Unipolar device 2) Bipolar device
3) Requires less constructional area 3) Relatively larger area is required.
4) High input impedance 4) Low input impedance.
5) There is no offset voltage 5) It suffers from offset voltage problem.
6) Early effect and thermal run away problems 6) Early effect & thermal run away problems
are not observed are present.
7) Less noisy 7) more noisy.
8) Gain and width product is small 8) Gain bandwidth product is relatively more.
9) Less sensitive to the change in input signal 9) Highly sensitive to change in input signal.
10) More temperature stability. 10) Less Temperature stability.
11) Low power rating 11) High power rating.
Field Effect Transistors & Biasing 57
3.3 CLASSIFICATION OF FETs

FET
JFET MOSFET
n-channel DMOSFET EMOSFET

p-channel
D D
G G n-channel p-channel n-channel p-channel
S S D D D D
G ss G ss G ss G ss
S S S S
Here S ® Source, G ® Gate, D® Drain, SS ® Substrate.
3.4 JUNCTION FIELD EFFECT TRANSISTOR (JFET)
As shown in Fig. 3.1, it can be fabricated with either an N-channel or P-channel
though N-channel is generally preferred. For fabricating an N-channel JFET, first a narrow
bar of N-type semiconductor material is taken and then two P-type junctions are diffused
on opposite sides of its middle part [Fig. 3.1 (a)]. These junctions form two P-N diodes or
gates and the area between these gates is called channel. The two P-regions are internally
connected and a single lead is brought out which is called gate terminal. Ohmic contacts
(direct electrical connections) are made at the two ends of the bar-one lead is called
source terminal S and the other drain terminal D. When potential difference is established
between the two P-regions. The current consists of only majority carriers which, in the
present case, are electrons. P-channel JFET is similar in construction except that it uses
P-type bar and two N-type junctions. The majority carriers are holes which flow through
the channel located between the two N-regions or gates.
G Gate
D
Drain N G Gate
N D
P
Channel Drain P
(a) Source N
P
D S Channel Source
N D D S
G G
P P P D
G G
N N
S
S
N-Channel S S
(b) (c) P-Channel
N-channel JFET P-channel JFET Fig. 3.1
3.4.1 Standard notations
Worthnoting FET notations are as follows :
1. Source. The terminal through which the majority carriers enter the channel, is called
the source terminal S and the conventional current entering the channel at S is designated
as Ig.
2. Drain. The terminal, through which the majority carriers leave the channel, is called
the drain terminal D and the conventional current leaving the channel at D is designated
as ID.
The drain-to-source voltage is called VDS, and is positive if D is more positive than S.
3. Gate. There are two internally connected heavily doped impurity regions formed by
alloying, by diffusion, or by any other method available to create two P-N junctions.
These impurity regions are called the gate G. A voltage VGS is applied between the
gate and source in the direction to reverse-bias the P-N junction. Conventional current
entering the channel at G is designated as IG.
4. Channel. The region between the source and drain, sandwiched between-the two
gates is called the channel and the majority carriers move from source to drain through
this channel.
3.4.2 Operations of JFET
Ø For n-channel JFET, VDS is +v while VGS is +ve.
Ø For p-channel JFET, VDS is –ve while VGS is –ve.
Let us consider an N-channel JFET for discussing its operation.
(i) When neither any bias is applied to the gate (i.e. when VGS = 0) nor any voltage to the
drain w.r.t. source (i.e. when VDS = 0), the depletion regions around the P-N junctions
are of equal thickness and symmetrical.
D +VDD D +VDD
ID ID
... ..... N
.. ..... . ... ..... N
..... ...
........ .. .....
..... ... .
........
.. . . ........
... . .
.
... .. . .
........... . .... ...... .
.. . .
........... .
.. . . . . .
.. . . . . . .. . . . . .
G P ......... P
.. . . . . .
.........
........
G P ......... P
.........
........
.... ........
........
. .... .
..... .... ....
.... .
.........
.. .... –
. ..... ....
.........
N
.. .... .. ....
.. ....
N
+
S S
Fig. 3.2 : JFET with No Bias Fig. 3.3 : JFET with Small
Voltage Negative Gate Source Bias
(ii) When positive voltage is applied to the drain terminal D w.r.t. source terminal S without
connecting gate terminal G to supply, as illustrated in fig. 3.2, the electrons (which are
the majority carriers) flow from terminal S to terminal D whereas conventional drain
current ID flows through the channel from D to S. Due to flow of this current, there is
a uniform voltage drop across the channel resistance as we move from terminal D to
terminal S. This voltage drop reverse biases the diode. The gate is more negative with
respect to those points in the channel which are nearer to D than to S. Hence, depletion
layers penetrate more deeply into the channel at points lying closer to D than to S.
Thus wedge-shaped depletion regions are formed, as shown in fig. 3.2, when VDS is
applied. The size of the depletion layer formed determines the width of the channel
and hence the magnitude of current ID flowing through the channel.
To see how the width of the channel varies with the variation in gate voltage, let us
consider the situation when the gate is biased negative with respect to the source while the
drain is applied with positive bias with respect to the source, as illustrated in fig. 3.3. Now
the P-N junctions are reverse biased and depletion regions are formed. P-regions are
heavily doped compared to the N-channel, so the depletion regions penetrate deeply into
the channel. Since a depletion region is a region depleted of the charge carriers, it behaves
as an insulator. The result is that the channel is narrowed, the resistance is increased and
drain current ID is reduced. If the negative voltage at the gate is further increased, depletion
layers meet at the centre and the drain current ID is cut-off completely. On the other hand,
if the negative bias to the gate is reduced, the width of the depletion layers gets reduced
causing decrease in resistance and, therefore, increase in drain current ID. The gate-
source voltage VGS at which drain current ID is cut-off completely (pinched off), is called
the pinch-off voltage VP. It is also to be noted that
1. The amount of reverse bias is not the same throughout the length of the P-N junction.
When the drain current flows through the channel, there is a voltage drop along its
length. The result is that the reverse bias at the drain end is more than that at the
source end making the width of depletion layer more at the drain end than that at the
source end. Thus the channel becomes narrower at the drain end in comparison to
that at source end, as shown in fig 3.3.
2. The channel is not completely closed at the drain end. Because in that case there will
be no drain current, so there will be no voltage drop along the channel length and
amount of reverse bias will become uniform and the wedge shaped depletion region
will become rectangular one. The channel will open and the drain current will flow.
However, at pinch-off voltage, the channel width is reduced to a constant minimum
value to allow the flow of drain current.
3. The N-channel JFET behaves as a vacuum tube triode. The drain and source perform
the same functions as the plate and cathode, respectively and, like the grid of a triode,
the JFET gate controls the drain current. As is also the case with a grid, gate current
is to be avoided, so the gate-channel junctions are normally never forward biased.
The device is called the field-effect transistor (FET) because the drain current (output
current) is controlled by the effect of the extension of the field associated with the depletion
region developed by the reverse bias at the gate.
P-channel JFET operates in the same manner as an N-channel JFET except that
channel current carriers will be the holes in place of electrons and the polarities of V GS and
VDS are reversed.
3.5 JFET PARAMETERS
JFET has certain parameters which determine the performance. Such parameters
are (i) ac drain resistance, (ii) transconductance, (iii) amplification factor, and (iv) dc drain
resistance, as explained below :
1. AC Drain Resistance. It is defined as the ratio of change in drain-source voltage to
change in drain current at constant gate-source voltage and is denoted by rd .
D VDS
i.e. AC drain resistance, rd = D I at constant VGS
D
It is also called the dynamic drain resistance.

It is clear that in the active region the change in drain current, ID is very small for
change in drain-source voltage, VDS because the characteristic curves are almost flat.
Hence ac drain resistance of a JFET is very large ranging from 10 kW to 1 MW.
2. Transconductance. The control that the gate-source voltage has over the drain current,
ID is measured by transconductance. It is denoted by gm. It may be defined as the ratio of
change in drain current to the change in gate-source voltage at constant drain-source
voltage.
D ID
i.e. Transconductance, gm = at constant VDS
D VGS
It is also called the forward transconductance (gfs ) or forward transadmittance
(Yfs ). It is measured in mA/volt or micro-siemens.
The transconductance measured at IDSS is denoted by gmo
Mathematical Expression For Transconductance.
Differentiating both sides of Shockley equation I D = I DSS

FG1 - V IJ 2
H VK
GS
, we get
P
FG V IJ FG - 1 IJ d V
d I D = 2 I DSS 1 -
H V KH V K
GS
GS
P P
d ID F V IJ FG - 1 IJ
= 2 I G1 -
H V KH V K
GS
or d VGS
DSS
P P
=-
2I FG1 - V IJ
V H V K
DSS GS
or gm
P P
Substituting VGS = 0 in above expression, we get

2 I DSS
g mo = -
VP
So we have
FG
g m = g mo 1 -
VGS IJ
H VP K
3. Amplification Factor. It is defined as the ratio of change in drain-source voltage to the
change in gate-source voltage at constant drain current and is denoted by m.
D VDS
i.e. Amplification factor, m = D V at constant ID
GS
Amplification factor of a JFET indicates how much more control the gate-source
voltage has over drain current in comparison to the drain-source voltage.
D VDS D VDS D I D
Amplification factor, m = D V = D I ´ D V
GS D GS
Þ m = rd ´ g m = ac drain resistance × transconductance

Amplification factor m of a FET may be as high as 100.
4. DC Drain Resistance. It is also called the static or ohmic resistance of the channel and
is defined as ratio of drain-source voltage and drain current. It is denoted by RDS
VDS
i.e., R D S = I
D
3.6 JFET BIASING

The input junction of JFET is reverse biased, so the input impedance is very high
b g
Þ input or gate current I G @ 0 Amp .
So as compared to BJT, here is absence of feedback biasing but other three types of
biasings are present.
V DD
- Fixed biasing
- Self / source stabilized biasing RD
- Voltage divider biasing VO
3.6.1 Fixed biasing :- (Rs = 0) CO
V1
Ci RG |V
I DSS
given
V GG VP
|W
Fig. 3.4
During biasing analysis, the capacitors are
open circuited, in Fig. 3.4.
So the circuit becomes as Fig. 3.5
By input KVL,
- VGG - VGS = 0
V DD
Þ VGS = - VGG
This equation is known as transfer line equation or load line equation. RD

The value of ID can be determined
D
by shockley’s equation :- IG ~ 0A +
I D = I DSS
FG1 - V IJ 2
RG +
V DS
H V K
GS
V GS – –
P
V GG
S
= I DSS
FG1 - V IJ 2
H V K
GG
P Fig. 3.5
The Value of ID can also determined from graph by the intersection of transfer
characteristic curve and transfer line.
The transfer characteristic can be plotted by following table :-
b g
VGs Volt b g
I D mA
0 I DSS
0.3VP I DSS / 2 ID (mA)
0.5VP I DSS / 4 IDSS
Device
VP 0
Network
The transfer line can be plotted using transfer Q-point

line equation,
I DQ
VGS = –VGG
VP VGSQ = - VGG 0 VGS

Fig. 3.6 : Finding the solution for the
fixed-bias configuration
By output KVL :
VDD – IDRD – VDS = 0
Þ VDS = VDD – IDRD
Here VS = 0
VD = VDS + VS = VDD – IDRD
VG = VGS + VS = –VGG V DD
3.6.2 Self / Source Stabilized biasing

RD
Here RS is present. Even if not any
external biasing supply at input junction D
then also it is reverse biased. So it is VO
CO
self biasing. V
i
Ci G
RG S
RS
Fig. 3.7
VD
Biasing analysis circuit is - RD
ID
+
+ V DS
V GS –
By input KVL, IG ~ 0A – ID
RG
VGS = – IDRS RS
It is the transfer line/Load line equation.
Fig. 3.8
Analytical method :
The value of I D Q & VGSQ can be determined by putting value of VGS in shockley’ss
equation.
2
æ I R ö
I D = IDSS ç1 + D S ÷
è VP ø
Þ I 2D + K1ID + K2 = 0
Then by solving this equation, the value of ID Þ Value of VGS can be determined.
Graphical method :
Here transfer characteristic graph is first plotted by the table :-
b g
VGs Volt b g
I D mA
0 I DSS ID
0.3VP I DSS / 2 IDSS
0.5VP I DSS / 4
VP 0
Then transfer line is plotted by
transfer line VGS = –IDRS I DSS
2
Q-point
VGS ( V) I D ( mA )
0
0 0
- I DSS R S / 2 I DSS / 2
Vp VGSQ 0 VGS
I D SS R S
VG S = -
2
Fig. 3.9 : Sketching the self-bias line.

By Output KVL
VDD – IDRD –VDS –IDRS = 0

Þ VDS = VDD –ID (RD + RS) V DD
Here VS = IDRS
VG = 0
RD
VD = VDS + VS = VDD –IDRD R1
VO
3.6.3 Voltage divider biasing : CO
Vi
Ø The capacitors Ci, Co and Cs
Ci
are open-circuited in biasing
analysis.
R2
Ø It is called voltage divider RS CS
biasing, because the voltage
appeared across R 2 is the
voltage to the input of circuit. Fig. 3.10
Ø The biasing circuit becomes ® VD
V DD
RD
RD
– R 2 VDD
IG ~ 0A RTh VTh =
R1 + R 2
R1 V DS
V CC R2 Þ +
R Th = R 1 | | R 2
RS V GS
–
VTh RS +
Fig. 3.11 Fig. 3.12
By input KVL :
VTh –VGS –IDRS = 0
Þ VGS = VTh –IDRS
Transfer line equation
VGS ( V) I D ( mA ) ID
VTh 0 IDSS
0 VTh / R S
The transfer characteristic

graph is plotted by the table- VGS=0V, ID=VG/RS
Q-Point
VGS ( V) I D ( mA ) VGS=VG–IDRS
0 I DSS
0.3Vp I D SS 2
ID=0mA, VGS=VG
0.5Vp I DSS 4
Vp 0 0
VP +VG VGS
Fig. 3.13 : Sketching the network equation for the volt-

age-divider configuration.
From intersection point, I D Q & VGSQ are determined.

By output KVL
VDD – IDRD – VDS – IDRS = 0
Þ VDS = VDD – ID (RD + RS)
Here VS = IDR S
VG = VGS + VS or VG = VTh – IGRS =VTh
VD = VDS + VS = VDD – IDRD
Example-3.1
Determine the following for the network of Fig. 3.14
(a) VGSQ
16 V
(b) I D Q
2kW
(c) V DS
(d) VD D
(e) VG G I DSS = 10mA
(f) VS + VP = 8A
VGS
1MW – S
–
2V
+
Figure 3.14
Solution :
Mathematical Approach :
(a) VGSQ = - VGG = -2 V
FG1 - V IJ 2
FG -2 V IJ 2
(b) I DQ = I DSS
H VK H
= 10 mA 1 -
K
GS
P -8 V
= 10 mA (1– 0.25)2 = 10 mA (0.75)2 = 10 mA (0.5625)

= 5.625 mA
(c) VDS = VDD – IDRD = 16V – (5.625 mA)(2 kW)
= 16 V – 11.25 V = 4.75 V
(d) VD = VDS = 4.75 V
(e) VG = VGS = – 2 V
(f) VS = 0 V
Graphical Approach
The resulting Shockley curve and the vertical line at VGS = – 2V are provided in Fig 3.15.
It is certainly difficult to read beyond the second place without significantly.
ID (mA)
IDSS =10 mA
9
8
7
6
Q-point ID = 5.6 mA
5 Q
4
3 I DSS
= 2.5 mA
2 4
1
–8 –7 –6 –5 –4 –3 –2 –1 VGS
Vp=–8V Vp
= -4 V V GS Q = - VGG = -2 V
2
Fig. 3.15 : Graphical solution for the network of Fig. 3.14

increasing the size of the figure, but a solution of 5.6 mA from the graph of Fig. 3.15 is
quite acceptable. Therefore
VGSQ = - VGG = -2 V
(b) I D Q = 5.6 mA
(c) VDS = VDD – IDRD = 16 V – (5.6 mA)(2 kW)
= 16 V – 11.2 V = 4.8 V
(d) VD = VDS = 4.8 V
(e) VG = VGS = – 2 V
(f) VS = 0V
The results clearly confirm the fact that the mathematical and graphical approaches
generate solutions that are quite close.
Example-3.2
(a) VGSQ 20 V
(b) I D Q
ID
(c)V DS 3.3 kW
(d)V S
(e)V G D
(f) V D G
IDSS= 8 mA
+ Vp = – 6 V
VGS
– S
1 MW
RS 1kW
Fig.3.16
(a) The gate-to-source voltage is determined by

VGS = – IDRS = – ID · 1 = – ID
ID(mA)
VGS (V) ID (mA)
0 0
8
-4 4
7
The transfer characteristics curve 6
can be plotted by following table. 5
4
VGS (V) I D (mA)
3
0 8 Q-point IDQ =26
. mA
2
0.3 VP = -1.8 4
1
0.5 VP = -3 2
VP = -6 0 –6 –5 –4 –3 –2 –1 VGS(V)
VGSQ = -2.6 V
Fig. 3.17 : Determining the Q-point for the
network for Fig. 3.16
(b) At the quiescent point :

I D Q = 2.6 mA
(c) V DS = VDD – ID (RS + RD)

= 20 V – (2.6 mA) (1kW + 3.3 kW)
= 20 V – 11.18 V
= 8.82 V
(d) VS = IDRS
= (2.6 mA) (1kW)
= 2.6 V
(e) VG =0V
(f) VD = VDS + VS = 8.82 V + 2.6 V = 11.42 V
or VD = VDD – IDRD = 20 V – (2.6 mA)(3.3 kW) = 11.42 V
Example-3.3
Determine the following for the common-gate configuration of Fig. 3.18
12V
(a) VGSQ .
(b) I D Q .
(c) V D. 1.5W
(d) VG.
(e) V S. D VD
(f) V DS . G I DSS = 12 mA
VP = -6 V
12 V
S VS ID
680W 1.5 kW
D
Fig. 3.18
Solution : G
+
(a) The transfer characteristics and load VGS
– S
line of Fig.3.19 appear in Fig. 3.20.
+
The load line can be determined from input KVL, VRS 680W
–VGS –IDRS = 0 Þ VGS = –IDRS = – 0.68ID –
Fig. 3.19
VGS ID
0 0
-4 6
The characteristic line can be drawn from shockley’s equation.
VGS (V) ID
0 12
0.3 VP = -1.8 6
0.5 VP = -3 3
VP = -6 0
ID(mA)
12 IDSS
11
10
9
8
7
6
5
Q-point
4 I D Q @ 3.8 mA
3
2
1
–6 –5 –4 –3 –2 –1 0
VGSQ @ -2.6 V
Fig. 3.20 : Determining the Q-point for the network of Fig. 3.18
From Fig.3.20, it is found VGS = – 2.6V
Q
(b) From Fig. 3.20.
I D Q @ 38
. mA
(c) VD = VDD – IDRD

= 12 V – (3.8 mA)(1.5 kW) = 12 V – 5.7 V
= 6.3 V
(d) VG =0V
(e) VS = IDRS = (3.8 mA)(680W)
= 2.58 V
(f) V DS = VD – VS
= 6.3 V – 2.58 V
= 3.72 V
Example-3.4
(a)IDQ and VGS .
Q
(b)V D . +16 V
(c)V S.
2.1MW 2.4 kW
(d)V DS . 10 mF
(e)VDG. V0
Vi
5mF
270 kW
1.5 kW 20 mF

(a) For the transfer characteristics, if ID = IDSS/4 = 8 mA/4 = 2mA, then VGS = VP/2
= –4 V/2 = – 2V. The resulting curve representing shockley’s equation appears in
Fig. 3.22. The network equation in defined by
R 2 VDD ID (mA)
VG = 8 (IDSS)
R1 + R 2
7
(270 kW)(16 V) 6
=
2.1MW + 0.27 MW 5
= 1.82 V 4
and VGS = VG - I D R S 3
IDQ = 2.4 mA
= 1.82 V – ID (1.5 kW) Q-point 2
ID = 1.21 mA (VGS = 0V)
1
–4 –3 –2 –1 0 1 2 3
(VP) VGSQ=–1.8 V VG=1.82 V
(ID= 0 mA)
Fig. 3.22 : Determining the Q-point for the network of Fig. 3.21
When ID = 0 mA :
VGS = + 1.82 V
When VGS = 0 V;
182
. V
ID = = 121
. mA
. kW
15
The resulting bias line appears of Fig. 3.22 with quiescent values of
ID = 2.4 mA
Q
VGS = – 1.8 V
Q
and
(b) VD = VDD – 1DRD
= 16 V – (2.4 mA)(2.4 kW)
= 10.24 V
(c) V S = IDRS = (2.4mA)(1.5 kW)
= 3.6 V
(d) VDS= VDD – ID (RD + RS)
= 16 V – (2.4 mA)(2.4 kW + 1.5 kW)
= 6.64 V
or VDS = VD – VS = 10.24 V – 3.6 V
= 6.64 V
(e) Although seldom requested, the voltage VDG can easily be determined using
VDG = VD – VG
= 10.24 V – 1.82 V
= 8.42 V
Example-3.5 VDD=20V
Determine the following for ID
the network of Fig. 3.23. RD = 1.8 kW
(a) ID and VGS .
Q Q
(b) V DS .
IDSS = 9 mA
(c) V D .
VP = – 3V
(d) V S.
RS = 1.5 k
VSS = –10 V
Fig. 3.23
Solution :
(a) An equation for VGS in terms of ID is obtained by applying Kirchhoff’s voltage law
to the input section of the network as redrawn in Fig. 3.24.
– VGS – ISRS + VSS = 0
or VGS = VSS – ISRS
but IS = ID G
+ IS
and VGS = VSS - I D R S VGS
–
Here VGS = 10 V – ID (1.5 kW) +
RS = 1.5 k W
For ID = 0 mA
–
VGS = VSS = 10 V –
VSS = 10 V
For VGS = 0 V +
0 = 10 V – ID (1.5 kW) Fig.3.24 : Determining the network equation
for the configuration of Fig. 3.23.
10V
and ID = = 6.67 mA
. kW
15
The resulting plot points are identified on Fig. 3.25.
ID (mA)
9 (IDSS)
8
Q-point 7 ID = 6.9 mA
Q
6
5
4
3
2
1
VGS
–3 –2 –1 0 1 2 3 4 5 6 7 8 9 10
(VP) VGS = – 0.35 V VSS = 10V
Fig. 3.25
The transfer characteristics are sketched using the plot point established by V GS = VP/2 =
– 3 V/2 = – 1.5 V and ID = IDSS/4 = 9 mA/4 = 2.25 mA, as also appearing on Fig. 3.25. The
resulting operating point establishes the following quiescent levels.
ID = 6.9 mA
Q
VGSQ = – 0.35 V
(b)Applying Kirchhoff’s voltage law to the output side of Fig. 3.23 will result in
–VSS + ISRS + VDS + IDRD – VDD = 0
Substituting IS = ID and rearranging gives.
VDS = VDD + VSS - I D ( R D + R S )
In this case,
VDS = 20 V + 10 V – (6.9 mA)(1.8 kW + 1.5 kW)
= 30 V – 22.77 V
= 7.23 V
(c) VD = VDD – IDRD
= 20 V – (6.9 mA)(1.8 kW) = 20 V – 1.242 V
= 7.58 V
(d) VDS = VD – VS
or VS = VD – VDS
= 7.58 V – 7.23
= 0.35 V
Example-3.6
Determine IDQ, VGS , and VDS for he p-channel JFET of Fig. 3.26.
Q
–20 V
ID
68 k W 2.7 k W
D
+
G
IDSS = 9mA
VDS
+ VP = 4V
VGS –
–
S
20 k W
1.8 k W
– IS
+
Fig.3.26
Solution :
20kW( -20V)
VG = = -4.55 V
20kW + 68 kW
Applying Kirchhoff’s voltage law gives
VG – VGS + IDRS = 0
and VGS = VG + IDRS
Choosing ID = 0mA yields
VGS = VG = – 4.55 V
as appearing in Fig. 3.27 ID (mA)
Choosing VGS = 0 V, we obtain 8
7
V -4.55V
ID = G = - = 2.53 mA 6
RS . kW
18 5
4
as also appearing in Fig. 3.27.
ID =3.4 mA 3
Q Q-point
The resulting quiescent point
2
from Fig. 3.27 :
1
IDQ = 3.4 mA
VGSQ = 1.4 V –5 –4 –3 –2 –1 0 1 2 3 4 VGS
VP
VGSQ=1.4 V
Fig. 3.27
For VDS, Kirchhoff’s voltage law will result in
– IDRS + VDS– IDRD + VDD = 0
and VDS = – VDD + ID (RD + RS) 20V
= –20V + (3.4 mA)(2.7 kW +1.8 kW)
= – 20 V + 15.3 V 2.2KW
= – 4.7 V
D
Example-3.7
G IDSS = 4.5 mA
1) Find ID, VDS, VD & VS, in this Fig. 3.28 VP = –5V
S
0.68 KW
Fig. 3.28
Solution : VGS = VG – VS = 0
(Because of short circuit)
FG1 - V IJ 2
H VK
GS
So ID = IDSS
P
= 4.5 (1 –0)
Þ ID = 4.5 mA
VD = 20 – 2.2 × 4.5 = 10.1 V
VS = 0.68 × 2.5 = 3.06V
Example-3.8 Define IDSS & VP ?

Solution :
IDSS is the maximum drain to source saturation current flows when gate to source
voltage is zero.
VP (Pinch-off voltage) is the value of gate to source voltage when drain current
becomes zero.
VP = +ve For p - channel FET
VP = –ve For n-channel FET
Example-3.9 Find ID, VS, VG, VP in Fig.3.29 18V
91 2KW
Solution : Here VTh = ´ 18 750KW
91 + 750 D 9V
= 1.95 V G
IDSS = 8mA
VG = VTh (Q IG ~ 0 A)
S
Þ VG = 1.95V
91KW 0.68 KW
VD = 18 – 2ID
Þ 9 = 18 – 2ID Þ ID = 4.5 mA
VS = 0.68 × 4.5
= 3.06 V Fig. 3.29
I D = I DSS
FG1 - V IJ 2
Þ 1-
VGS
=
ID
H VK
GS
P
VP I DSS
18V
ID 4.5
Þ VGS VP = 1 + = 1+ = 1236
.
I DSS 8 2KW
D
V - VS 1.95 - 3.06 IG ~ 0A 9V
Þ V P = VG S VP = G =
VP 1.236
RTh G
= -0.9 Volt
VTh S
0.68kW
Fig. 3.30
3.7 MOSFET
Ø This is a type of FET, where gate is made up of SiO2 layer and metal is used to have
contacts. So it is named as metal oxide semi conductor FET (MOSFET).
Ø In MOSFET there are 4 terminals :
(a) Source (S) (b) Gate (G) (c) Drain (D) (d) Substrate (SS)
Substate is a large block semiconductor on which source, gate & drain are created.
Ø It can be used as four terminal device or as three terminal device.
When used as three terminal device, then source is shorted with substrate.
Ø Between source to drain, there is presence of channel. The channel may be n-type or
p-type.
In n - channel MOSFET :-
SS ® p - type
S&D ® n - type
In p-channel MOSFET :-
SS ® n-type
S&D ® p - type
Ø The channel may be initially present or may be later to be created by suitable supply.
If channel is initially present, then it is DMOSFET.
If channel is initially absent, then it is EMOSFET.
Ø Here also input junction is reverse biased, so input current (IG) = 0A.
3.8 D-MOSFET (Depletion MOSFET)
Ø In this type of MOSFET, the channel is initially present.
Construction
Ø A large block of semiconductor known as substrate, (n-type in p-mos & p-type in
n-mos) is taken.
Ø On the substrate, source and drain are formed.
Ø Source and drain are n-type in n-mos & p-type in p-mos.
Ø A silicon dioxide (SiO2) layer forms the gate region.
Ø The metal contacts are taken from each terminal.
Ø A channel (of n-type in n-mos or of p-type in p-mos) is formed between source to
drain.
(Drain)
D
SiO2
n-channel
n
Metal contacts
Substrate
(Gate) SS
p
G
n substrate
S n-doped
(Source) regions
Operation : Fig. 3.31
Let us consider n-channel DMOSFET.
Substrate is shorted to source to use as three terminal device.
D
n
+
+
e SS
G e VDS
n
e p
VGS= 0 V e –
e
S – e
n
ID = IS = IDSS
Fig. 3.32
Case-I (VGS = 0, VDS > 0)

Ø Under this condition, –ve terminal of VDS connected to source will repel the electrons,
while +ve terminal connected to drain attracts the electrons.
Ø Due to presence of channel, current flow occurs.
Ø As VDS is increased then current increases to a certain value, after that saturates.
The maximum current of ID attained when VGS = 0V, is known as drain to source
saturation current (IDSS).
Ø This case is similar to JFET.
Case-II (VGS < 0, VDS > 0)
Ø When VDS is set at a +ve value, then maximum current is flowing for VGS = 0V.
Ø Now if VGS = –ve, then –ve terminal of VGS is connected to gate. It will repel electron
from channel, so channel width decreases.
Ø Due to decrease in channel, drain current decreases. At a particular value of V GS, ID
becomes zero, known as Pinch-off voltage.
Ø Here as channel gradually decreasing, it is known as depletion mode of operation
of DMOSFET which is same as that of JFET.
Case-III (VGS > 0 with VDS > 0)
Ø In this condition, the +ve terminal is connected to gate that will attract the electrons
and accumulate at channel by which channel width increase Þ ID increases.
Ø This is known as enhancement mode of operation
Ø It is violating the name so this mode is not used.
ID(mA)
Depletion 10.9 VGS= + 1V

Enhacement
mode
mode
8 IDSS VGS= + 0 V
4
I DSS
VGS= – 1 V
2
2 I DSS VGS= – 2 V
4 VGS= VP/2=– 3 V
–4 V
–5 V
–6 –5 –4 –3 –2 –1 0 VGS 0 VDS
VP VP VGS= VP= – 6 V
2 0.3VP
Fig. 3.33 : Drain and transfer characteristics for an n-channel depletion-type MOSFET.
for VP= –6 V and IDSS = 8 mA
NOTE :
So depletion mode DMOSFET @ JFET.
It also satisfied shockley’s equation :-
F1 - V I 2
I D = I DSS GH V JK
GS
NOTE :
Ø In n-channel DMOS, VGS = –ve
Ø In p-channel DMOS, VGS = +ve
3.9 E-MOSFET (ENHANCEMENT - MOSFET)
In this type of MOSFET, the channel is initially absent (shown in Fig.3.34(a)) and it can be
created by giving suitable input supply, shown in Fig.3.34(b).
Construction
Ø A large block of D SiO2
semiconductor known as n-doped
substrate, (n-type in p-mos regions
& p-type in n-mos) is
taken.
n
Ø On the substrate, source Metal
and drain are formed. contacts
Ø Source and drain are G p-type

n-type in n-mos & p-type substrate Substrate
in p-mos. SS
Ø A silicon dioxide (SiO2)
layer forms the gate n
region.
Ø The metal contacts are
taken from each terminal.
n-doped
Ø The channel is initially S
region
absent and later will be Fig. 3.34(a)
created by suitable supply.
Operation
Let us consider n-channel EMOSFET.
Case -I : (VGS = 0, VDS > 0)
Ø Although, –ve terminal connected to source repels electrons & +ve terminal connected
to drain attracts electrons, due to absence of channel, no current will flow.
Ø To make the current flow, first the channel is to be created.
CASE - II : (VGS < 0, VDS > 0)

Ø The channel as is of n-type, channel can be created when electrons are deposited
near gate.
Ø Now by giving –ve supply to VGS, the electrons are repelled, not accumulated near
gate.
Ø So there can’t be current flow.
CASE-III : (VGS > 0, VDS > 0)
The +ve supply at gate accumulates electrons near gate, so channel will start to create.
Ø The channel is completely created at a particular value of V GS after which current
flow starts.
This voltage is known as threshold voltage.
Ø So out of total VGS supply, VTh amount is used to create the channel, rest is used to
drive the current.
So here equation is D SiO2
n-doped
regions
n-channel
n
Metal
contacts
G p-type
substrate Substrate
SS
n-doped region
S
Fig. 3.34(b)
b
I D = k VGS - VTh g 2
K = constant, cant be determined from given ID(ON) and as “ON” condition.
eV j
2
Þ k = I D ( ON ) GS ( ON ) - VTh
Ø Here upto VTh, no current flow occurs.

Ø Here VDG = VDS – VGS
& VDS = VGS – VTh
ID (mA)
ID(mA)
10 10 VGS= +8 V
9 9
8 8
7 7 VGS = + 7V
6 6
5 5 VGS = +6 V
4 4
3 3
VGS = + 5 V
2 2
VGS = +4 V
1 1 VGS = +3 V
0 1 2 3 4 5 6 7 8 VGS 0 5 10 15 20 25 VDS
VT VGS=VT=2 V
Fig. 3.35
NOTE :
Ø In n-channel EMOS, VGS = +ve
Ø In p-channel EMOS, VGS = –ve
Example-3.10
For the n-channel depletion-type MOSFET of Fig. 3.36, determine :
(a) ID and VGS . 18V
Q Q
(b) V DS .
1.8 kW
110 MW
V0
I DSS = 6 mA
Vi
VP = -3V
10 MW 750 W
Fig. 3.36
Solution :
(a) Transfer characteristic plot can be VGS (V) ID (mA)
drawn by using following table, that
satisfy Shockley’s equation 0 6
- 0.9 3
-1.5 1.5
-3 0
From the Fig.3.36 the threshold (VG) can be given as
10MW(18V)
VG = = 1.5V
10MW + 110MW
Here from input KVL, VGS = VG - I D R S = 1.5V - I D (0.75KW)
It can be the transfer line equation can be plotted by following points.
VGS (V) I D (mA)

1.5
0 =2 ID (mA)
0.75
1.5 0 11
10
The graph of transfer line equation can 9
be plotted by using the equation
8
7
6 ID (mA)
5
4
Q-point 3 IDQ = 3.1 mA
2
1
–3 –2 –1 0 1 2
VGS
VGSQ = – 0.8 V
Fig. 3.37 Determining the Q-point for the network of Fig. 3.36
The characteristic graph and resulting bias line appear in Fig. 3.37. The resulting operating
point :
IDQ = 3.1 mA
VGSQ = – 0.8 V
(b) Now : VDS = VDS – ID (RD + RS)
= 18 V – (3.1 mA)(1.8 kW) + 750 W)
@ 10.1 V
Example-3.11
(a) ID and VGSQ.
Q
(b) V D .
20 V
6.2 kW
V0
IDSS = 8 mA
Vi VP = – 8V
1M W
2.4 kW
Fig. 3.38
Solution :
(a) The self-bias configuration results in
VGS = – IDRS
The graph for transfer line equation can be obtained by following points, that satisfy
VGS = – IDRS
VGS ( V) I D ( mA )
0 0
ID(mA)
-4 2
The transfer characteristic graph can 12
be plotted by using following points 11
that satisfy Shockley’s equation. 10
9
VGS ( V) I D ( mA ) 8
7
0 8
6
-2.4 4 5
-4 2 4
-8 0 3
2 ID = 1.7 mA
Q
1
The resulting Q-point :
IDQ = 1.7 mA –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 VGS
VGSQ = – 4.3 V VP V = – 4.3 V
GSQ
(b) VD = VDD – IDRD

Fig.3.39 : Determining the Q-point for the
= 20 V – (1.7 mA) (6.2 kW)
network of Fig. 3.38
= 9.46 V
Example-3.12
Determine IDQ and VDSQ for the enhancement-type MOSFET of Fig. 3.40
12 V
2 kW
V0
1 mF
10 MW
ID(on) = 6 mA
VGS(on) = 8 V
Vi
VGS(Th) = 3 V
1 mF
Fig. 3.40
Solution :
Plotting the Transfer Curve :
Two points are defined immediately as shown in Fig. 3.41 Solving for k :
I D ( on )
k=
( VGS( on ) - VGS( Th ) ) 2
6 mA 6 ´ 10 -3
= = A / V2 ID VGS = 10 V, ID = 11.76 mA
b
8V - 3V g 2
25
12
= 0.24 × 10–3 A/V2 11
10
For VGS = 6 V
9
ID = 0.24 × 10–3 (6 V – 3 V)2 8
= 0.24 × 10–3(9) 7
ID(on) 6
= 2.16 mA 5
For VGS = 10 V 4
3
ID = 0.24 × 10–3 (10 V – 3 V)2
2
= 0.24 × 10–3(49) 1
= 11.76 mA
0 1 2 3 4 5 6 7 8 9 10
as also appearing on Fig. 3.41. The
VGS(Th) VGS(on)
four points are sufficient to plot the
full curve for the range of interest as Fig. 3.41 Plotting the transfer curve
shown in Fig. 3.41. for the MOSFET of Fig. 3.40
For the Network Bias Line :
VGS = VDD – IDRD ID = mA
= 12 V – ID (2 kW)
12
VGS = VGS = VDD = 12 V |I D = 0 mA 11
10
9
VDD 12 V
ID = R = 2 kW = 6 mA|VGS = 0 V
8
D VDD 7
6
RD 5
The resulting bias line appears
4
in Fig. 3.42. IDQ = 2.75 mA 3
At the operating point : 2
1 Q-Point
I D Q = 2.75 mA 0 1 2 3 4 5 6 7 8 9 10 11 12 VGS
VGSQ = 6.4 V
and VGS Q = 6.4 V
Fig. 3.42 : Determining the Q-point
with VDSQ = G GSQ = 6.4 V for the network of Fig. 3.40
Example-3.13
40 V
Determine ID , VGSQ, and
Q
VDS for the network of Fig. 3.43. 3 kW
22 MW ID Q
D
G VDS VGS(Th) = 5 V
+ ID(on) =3 mA
VGSQ – at VGS(on) = 10 V
18 MW
0.82kW
Solution :
Network :
R 2 VDD (18 MW)(40 V)
VG = = = 18 V Fig. 3.43
R1 + R 2 22 MW + 18 MW
VGS = VG – IDRS = 18 V – ID(0.82 k W)
When ID = 0 mA
VGS = 18 V – (0 mA)(0.82 kW) = 18 V
as appearing on Fig. 3.44.
When VGS = 0 V,
VGS = 18 V – ID (0.82 kW)
0 = 18 V – ID (0.82 kW) ID(mA)
18 V
ID = = 21. 95 mA
0.82 kW 30
20
10 Q-point
IDQ @ 6.7 mA
0 5 10 15 20 25 VGS
VGS(Th) VGSQ=12.5 V VG = 18 V
Fig. 3.44 : Determining the Q-point for

the network of Example 3.13
Device :
VGS(Th) = 5 V, ID(on) = 3 mA with VGS(on) = 10 V
I D( on )
k=
dV
GS ( on ) - VGS( Th ) h 2
3 mA
= . ´ 10 -3 A V 2
= 012
b10 V - 5 Vg 2
and ID = kd V - V
GS h GS ( Th )
2
= 0.12 × 10–3 (VGS – 5)2

which is plotted on the same graph.
From Fig. 3.44.
I D Q @ 6.7 mA
V GS Q = 12.5 V
V DS = VDD – ID (RS + RD)
= 40 V – (6.7 mA) (0.82 kW + 3.0kW)
= 40 V – 25.6 V
= 14.4 V
3.10 CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor)
* This is a special type of MOSFET in which both P-channel MOSFET & n-channel
MOSFET are developed in a single substrate.
* It consists of a PMOS stacked on top on a NMOS, but they need to be fabricated on
a single wafter.
* It is named so because when one type of MOSFET is ‘ON’, other type is OFF and
Vice-Versa. It is only possible in enhancement type of MOSFET.
* It has extensive application in digital logic design because of relatively high input
impedance, fast switching speeds and lower operating power levels.
3.10.1 CMOS Construction Vi
V0
VSS
G2 G1
S2 D2 D1 S1
SiO2
n+ p+ p p+ n+ n n+ p+
When “on” When “on”

p
p-channel MOSFET n-channel MOSFET
n-type substrate
Fig. 3.45
3.10.2 CMOS Inverter Layout
Substrate contact PMOS transistors v0
VDD
v1
2/1
n-well
boundary
p+
v1 v0
VDD Ground
Polysilicon gate Metal
2/1
Ground n+ NMOS transistor
Substrate contact Contact
Fig. 3.46
3.10.3 CMOS Inverter

VDD= 5V VDD= 5V
VDD= 5V
R on p R on p
S
Mp
G v1 = VDD v1 = 0
D vO = 0 vO = V DD
v1 v0
D
G
MN Ron n R on n
S
VSS
(a) (b) (c)
Fig.3.47 : (a) Circuit schematic for a CMOS inverter (b) Simplified operation model
with a high input applied (c) Simplified operation model with a low input applied
3.10.4 CMOS Inverter Operation
• When vI is pulled high (VDD), the PMOS inverter is turned off, while the NMOS is
turned on pulling the output down to VSS.
• When vI is pulled low (VSS), the NMOS inverter is turned off, while the PMOS is
turned on pulling the output up to VDD.
Static Characteristics of the CMOS Inverter
VDD= 5V VDD= 5V
S Ron p
Mp “Off”
vI = 5V vO = 0
“1”
MN “On” C
Ron N C
S
VSS
(a) (b)
VDD= 5V VDD= 5V
S Ron p
Mp “On”
vI = 0 vO = VDD
“0”
MN “Off” C
Ron N C
S
VSS
(c) (d)
Fig.3.48
• The figure-3.48 shows the two modes of static operation with the circuit and simplified
models.
• Notice that VH = 5V and VL = 0V, and that ID = 0mA which means that there is no
static power dissipation.
3.10.5 CMOS Voltage Transfer Characteristics
5.0 V
VIL
VOH 1 2
4.0 V MN saturted
MN off
MP linear
vO = vI + 1
Output voltage
3.0 V MN and MP saturated
3
2.0 V
MP saturated
1.0 V MN linear
VIH
VOL 5
vO = vO – 1
0V 4 MP off
0V 1.0 V 2.0 V 3.0 V 4.0 V 5.0 V

vI
Fig.3.49
• The VTC shown is for a CMOS Inverter that is symmetrical (KP = KN)
• Region 1: vO = VH
vI < VTN
• Region 2: |vDS| < |vGS – VTP|
• Region 4: vDS > vGS – VTN
6.0 V
• Region 5: vO = VL VDD= 5V
vI > VDD – |VTP|
VDD= 4 V
4.0 V
Output voltage
VDD= 3 V
vO = vI
VDD= 2 V
2.0 V
0V
0V 1.0 V 2.0 V 3.0 V 4.0 V 5.0 V 6.0 V

vI
Fig.3.50
Simulation result shows the varying VTC of the inverter as VDD is changed.
• Minimum voltage supply:2VT·ln(2)
6.0 V
• The simulation result
shows the varying VTC of
vO = vI
the inverter as KR = 5
4.0 V
KN/KP = KR is changed.
Output voltage
• For K R > 1 the NMOS

current drive is greater and KR = 1
2.0 V
it forces vI < VDD/2
• For K R < 1 the PMOS
current drive is greater and KR = 0.2
it forces vI > VDD/2 0V
0V 1.0 V 2.0 V 3.0 V 4.0 V 5.0 V

vI
Fig.3.51
Q.1 Why are field-effect transistors called unipolar transistors ?

Ans. In field-effect transistors current conduction is by only one type of majority carriers (either
by electrons or by holes) and, therefore, these are called unipolar transistors.
Q.2 Why the channel of a JFET is never completely closed at the drain end ?
Ans. If the channel is completely closed in JFET, then there will be no drain current, so there will
be no voltage drop along the channel length and amount of reverse bias will become uniform
and wedge-shaped depletion region will become rectangular one.
Q.3 How is drain current controlled in a JFET ?
Ans. In a JFET drain current is controlled by controlling the reverse bias given to its gate (i.e.
V GS).
Q.4 What is meant by drain characteristic of FETs ?
Ans. The curve drawn between drain current and drain-source voltage with gate-to-source voltage
as the parameter is called the drain characteristic.
Q.5 What is meant by transfer characteristic of FETs ?
Ans. The curve drawn between drain current and gate-source voltage for a given value of drain-
source voltage is called the transfer characteristic.
Q.6 No current flows through the channel of a JFET when VGS = 0 and VDS = 0, though channel
is fully-open. Why ?
Ans. When drain-source voltage is zero, there is no attracting potential at the drain, so no current
flows inspite of the fact that the channel is fully open.
Q.7 Define pinch-off voltage for a JFET
Ans. The value of drain-source voltage at which channel is pinched-off (i.e. all the free charges
from the channel get removed) is called the pinch-off voltage.
Q.8 What are the parameters that control the pinch-off voltage of JFET ?
Ans. Parameters that control the pinch-off voltage of JFET are electron charge, donor/acceptor
concentration density, permittivity of channel material and half width of channel bar.
Q.9 Why FET is called a voltage controlled device ?
Ans. In a FET, drain current is controlled by the effect of the extension of the field associated
with the depletion region developed by the reverse bias on the gate, so it is called a voltage
controlled device.
Q.10 How does the FET behave (i) for small values of |VDS| and (ii) for large values of |VDS| ?
Ans. (i) FET behaves us an ordinary resistor for small value of |VDS| i.e. in ohmic region.
(ii) FET behaves as a constant current source for large values of |V DS| till breakdown
occurs.
Q.12. How does the current vary with the gate voltage in the saturation region ?
Ans. Drain current decreases with the increase in gate-source bias |V DS|. When VGS = 0; drain
current ID = IDSS, drain-source saturation current and when VGS = Vp; drain current ID = 0.
Q.13. How does the transconductance vary with drain current ?
Ans. Transconductance gm of a FET varies with the drain current ID as given by the following
equation.
2
gm = I DS.I DSS
| VP |
Q.14. What is meant by gate-source cut-off voltage ?
Ans. The gate-source bias voltage required to reduce the drain current to zero is designated
the gate-source cut-off voltage VGS (OFF) . It is equal to pinch-off voltage Vp.
Q.15 What is meant by saturation region ?
Ans. The region of drain characteristic of a FET in which, drain current remains fairly constant
is called the saturation or pinch-off region.
Q.16 What is dynamic resistance of a JFET ?
Ans. The ratio of change in drain-source voltage to change in drain current at a given gate-
source voltage is known as ac drain resistance or dynamic resistance rd
D VDS
i. e. rd =
D I D at constant VGS.
Q.17 What is meant by transconductance with reference to JFET ?
Ans. The control that gate-source voltage has over the drain current is measured by the
transconductance of a JFET. It may be defined as the ratio of change in drain current to the
change in gate-source voltage for a given value of drain-source voltage i.e.
D ID
gm =
D VGS at constant VDS.
EXERCISE
1. Explain the basic construction of an enhancement type N-channel MOSFET. Draw and
explain its static characteristics. How is the threshold voltage of MOS-transistor adjusted?
2. Explain the operation of an N-channel enhancement type MOSFET with the help of its
(ID – VDS) and (ID – VGS) characteristics.
3. Draw the equivalent circuit of a MOSFET operating in enhancement mode.
4. Describe the steps followed in fabrication of a P-channel enhancement type MOSFET.
Explain why P-channel enhancement FET is a popular in MOS systems?
5. Describe the construction and characteristics of a N-channel enhancement MOSFET,
also define its threshold voltage.
6. The following readings were obtained experimentally from a FET
V GS 0V 0V – 0·3V
V DS 7V 14·5 V 14·5 V
ID 10mA 10·25 mA 9·2 mA
Determine rd , gm and m. [Ans. 30 kW, 3500 m mhos, 105]
7. For a N-channel JFET, IDSS = 8 mA, VP = – 4 V, VGS = –1 V. Determine ID , gmo and gm.
[Ans. 4·5 mA, 4 mA/V, 3 mA/V]
8. Determine the value of transconductance of a FET when the drain current changes from
1 mA to 1·5 mA with a change in gate voltage from – 2·125 V to – 2 V.
[Ans. 4000 n mhos]
9. For a particular N-channel JFET, VGS (off) = – 4 V. What would be the value of ID when VGS
= – 6 V? [Ans. zero]
10. When a reverse gate voltage of 18 V is applied to a FET, the gate current is 0·9 × 10–3 mA.
Determine the resistance between gate and source. [Ans. 20,000 W]
ppp
95
Small Signal Operation of BJT

4.1 INTRODUCTION
One of the important aspect of ac signal analysis of BJT is the magnitude of input
signal. It will determine whether small signal or large signal techniques should be applied.
The large signal operation can be best studied graphically because of involvement of certain
non-linear operation in it.
But for small signal operation, the BJT can be replaced by its equivalent model. There
are two models commonly used in small signal analysis of BJT networks.
i) hybrid model
ii) re model.
4.2 TWO-PORT DEVICES AND THE HYBRID MODEL
A box representing a two-port network is illustrated in fig. 4.1. The terminal behaviour of
a two-port device may be specified by two voltages and two currents (voltage v1, and
current il at the input port and voltage v2 and current i2 at the output port. The conventional
positive polarities of voltages v1 and v2 and currents i1 and i2 are shown in the figure. Out
of four quantities (v1, v2, i1 and i2), any two may be selected as independent variables and
the remaining two be expressed in terms of the selected independent variables. This leads
to various two-port parameters, out of which following three are more important.
Fig.4.1 : Conventional Positive Polarities of Voltages and

Currents in a Two-Port Network
1. Open-circuit impedance parameters or Z-parameters Z11, Z12, Z21 and Z22
2. Short-circuit admittance parameters or Y-parameters Y11, Y12, Y21 and Y22
3. Hybrid parameters or the h-parameters.
In transistor amplifier analysis, Z- and Y-parameters were used earlier. But now hybrid or
the h-parameters alone are used in a transistor circuit analysis and, therefore, only the
h-parameters will be taken here for discussion.
4.2.1 Hybrid Parameters or h-parameters
For the two-port network illustrated .in fig. 4.1, if input current i1 and the output voltage v2
are taken as independent variables and the two-port shown in the figure is linear, we may
write
v1 = h11 i1 + h12 v2 ...(4.1)
i2 = h21 i1 + h22 v2 ...(4.2)
In the above equations, the hs are fixed for a given circuit and are called the hybrid or h-
parameters. Because these four parameters have mixed dimensions (h11 has dimension of
ohm, h12 and h21 are dimensionless, and h22 has dimension of mho or siemen) so they are
called hybrid or h-parameters.
1. Meaning of h-parameters. By assuming that the given two-port network has no
reactive element and by applying open-circuit (i1 = 0) or short-circuit (v2 = 0) conditions to
equations (4.1) and (4.2), the h-parameters can be defined as below :
If the output terminals are short-circuited, (fig. 4.2) output voltage v2 becomes zero
and equations (4.1) and (4.2) become
v1 = h11 i1 + h12 × 0 = h11 i1
and i2 = h21 i1 + h22 × 0 = h21 i1
v1 i2
or, h11 = and h 21 =
i1 v2 =0
i1 v2 =0
Since h11 is the ratio of input voltage and input current with output terminals short-circuited,
it is called the input impedance with output short-circuited. The subscript 11 of h11
defines the fact that the parameter is determined by the ratio of quantities measured at the
input terminals. Its unit is ohm.
Fig. 4.2
Fig. 4.3
Small Signal Operation of BJT 97
Similarly h21 is the ratio of output and input currents (i.e. i2/i1) with output terminals
short-circuited, so it is called the forward transfer current gain with output short-
circuited. Obviously it is dimensionless quantity.
If the input terminals are open-circuited and we drive the output terminals with voltage
v2, as shown in fig. 4.3, input current i1 becomes zero and equations (4.1) and (4.2) become
v1 = h11 × 0 + h12 v2 = h12 v2
and i2 = h21 × 0 + h22 v2 = h22 v2
v1 i2
or h12 = and h 22 =
v2 i1 = 0
v2 i1 = 0
Thus the parameter h12 is the ratio of input voltage to the output voltage with zero input
current (i.e. i1 = 0). It is dimensionless quantity and is called the open-circuit reverse
transfer voltage ratio, the subscript 12 of h12 reveals that the parameter is a transfer
quantity determined by the ratio of input to output measurements.
Similarly h22 is the ratio of output current to the output voltage with zero input current
(i.e. i1 = 0). It is called the open-circuit output admittance and is measured in Siemens,
the subscript 22 in h22 indicates that it is determined by a ratio of output quantities.
2. Notations. The convenient alternative subscript notations recommended by the IEEE
Standards are given below :
i = 11 = input o = 22 = output
f = 21 = forward transfer r = 12 = reverse transfer
In case of transistors, another subscript (b,e, or c) is added to designate the type of
configuration. For example hie = h11e = input resistance in common emitter figuration.
Notations used in transistor amplifier for the three configurations are tabulated below.
TABLE 4.1
S.No. h -parameter Common Base Common Emitter Common Collector
Configuration Configuration Configuration
1. h 11 h ib h ie h ic
2. h 12 hrb h re h rc
3. h 21 hfb hfe hfc
4. h 22 h ob h oe h oc
Since the two-port network (or the device) described by equations (4.1) and (4.2) is assumed
to have no reactive elements, the four parameters h11 , h12, h21 and h22 are real numbers
and voltages and currents v1, v2, and i1, i2 are function of time. However, if the reactive
elements had been included in the device, the excitation would be considered to be sinusoidal,
the h-parameters would in general be functions of frequency, and the voltages and currents
would be represented by phasors V1, V2, and I1, I2.
4.2.2 Hybrid Model
The hybrid circuit for any two-port network characterized by equations (4.1) and (4.2)
is shown in fig. 4.4. If Kirchhoff s voltage law and Kirchhoff s current law are applied to
the input and output ports, equations (4.1) and (4.2) respectively will be obtained. Thus
model given in fig. 4.4 truly satisfies equations (4.1) and (4.2).
Fig. 4.4 Hybrid Model For The Two Port Network Shown in Fig. 4.1
The input circuit derived from equation (4.1) appears as a resistance h11 in series with
a voltage generator h12 v2. The output circuit, derived from equation (4.2) consists of a
current generator h21 i1 and shunt resistance h22. This circuit is called hybrid equivalent
because its input portion is a Thevenin’s equivalent (or a voltage generator in series with a
resistance) while the output portion is a Norton’s equivalent (or a current generator with
shunt resistance). Thus it is a mixture or hybrid. The symbol ‘h’ is simply the abbreviation
of the word hybrid (hybrid means “mixed”).
The hybrid equivalent circuit (or model) given in fig. 4.4 is an extremely important one
in the area of electronics today. It will appear over and over again in the analysis to follow.
There are two main reasons of popularity of hybrid model. First, it isolates the input and
output circuits, their interaction being accounted for by the two controlled voltage an current
sources—the effect of output upon input is represented by the equivalent voltage generator
h12 v2 and the effect of input upon output is represented by the current generator h2l i1. The
value of the former depends upon the output voltage v2 while the value for the latter
depends upon the input current i1. Secondly, the two portions of the circuit are in a form
which makes it simple to take into account the source and the load circuits.
4.3 TRANSISTOR HYBRID MODEL
The basic assumption in arriving at a transistor linear model or equivalent circuit is that
the variations about the operating or quiescent point are small and, therefore, the transistor
parameters can be considered constant over the small range of operation.
Many transistor models have been proposed, each one having its particular merits and
demerits. The transistor model presented here, is given in terms of the h-parameters,
which are real numbers at audio-frequencies, are easy to measure, can also be obtained
from the static characteristics of a transistor, and are particularly convenient to use in
analysis and design of circuit. Furthermore, a set of h-parameters is specified for many
transistors by the manufacturers.
To derive a hybrid model for a transistor, let us consider the basic CE amplifier circuit
given in fig. 4.5. The variables iB, iC, vB and vC represent the total instantaneous values of
currents and voltages. We may select the input current iB and output voltage vC as
independent variables. Since input voltage vB is some function f1 of iB and vC and output
current iC is another function f2 of iB and vC, we may write
VB = f1 (iB , vC) ...(4.3)
iC = f2 (iB , vC) ...(4.4)
Fig. 4.5 : Basic CE Configuration

Making a Taylor’s series expansion of equations (4.3) and (4.4) about the zero signal
operating point (IB, VC) and neglecting higher order terms we have
df1 df1
Dv B = Di B + DvC ...(4.5)
di B VC
dvC IB
df 2 df 2
Di C = Di B + Dv C ...(4.6)
di B VC
dvC IB
df 2 df 2
where partial derivatives di and di are taken keeping collector voltage VC constant
B B
df1 df 2
while partial derivates dv and di are taken keeping base current IB constant.
C B
The quantities Dv B , Dv C , Di B and DiC represent the small-signal (incremental) base

and collector voltages and currents and may be represented as vb, vc. ib, and ic respectively
as per standard notations. We may now write equations (4.5) and (4.6) as below
vb = hie ib + hre vc ...(4.7)
ic = hfe ib + hoe vc ...(4.8)
df1 dv B vb
where h ie = = = ...(4.9 a)
di B VC
di B VC
ib VC = 0
df 2 di C ic
h fe = = = ...(4.9 b)
di B VC
di B VC
ib VC = 0
df1 dv B vb
h re = = = ...(4.9 c)
dvC IB
dvC IB
vc IB =0
df 2 di C ic
h oe = = = ...(4.9 d)
dv C IB
dv C IB
vc IB =0
The partial derivatives of equations (4.9) define the h-parameters for the transistor in
common-emitter (CE) configuration.
Equations (4.7) and (4.8) are found to be of exactly the same form as equations (4.1)
and (4.2) hence, the model shown in fig. 4.4 can be used to represent a transistor.
The common-emitter (CE) common-base (CB), and common-collector (CC)
configurations, their hybrid models and their terminal volt-ampere equations are summarized
in Table 4.2.
TABLE 4.2
Configuration Circuit Schematic Hybrid Model v-i Equations
Common v b = h ie i b + h re v c
Emitter, CE i c = f fe i b + h oe vc
Common v e = h ib i e + h rb v c
Base, CB i c = h fb i e + h ob v c
Common v b = h ic i b + h rc ve
Collector i e = h fc i b + h oc v e
CC
The circuits and equations in above Table 4.2 are valid for either an N-P-N or P-N-P
transistor and are independent of the type of load or biasing method.
4.4 DETERMINATION OF h-PARAMETERS FROM STATIC CHARACTERISTICS
Functional relationships for the CE configuration of total instantaneous collector .current
and base voltage in terms of two variables (base current and collector voltage) are given
by equations (4.4) and (4.3) respectively. Such functional relationships are represented by
families of characteristic curves

of transistors, Two families of
curves are usually specified for
transistors. The output
characteristic curves depict the
relationship between the output
current and voltage, with input
current as the parameter. The
input characteristic curves give
the relation between input
voltage and input current with
output voltage as parameter. h-
parameters can be determined
graphically from the input and
output characteristics of a
transistor for a particular
configuration. Fig. 4.6 : Output Characteristics For Common
Emitter N-P-N Transistor
4.4.1 Determination of Hybrid Parameters hfe and hoe.
For a common-emitter configuration, the output characteristic curves given in fig.4.6.
In this fig. let us consider the curve for iB = IB = 60 mA. At a point Q on this curve, the
quiescent collector current and collector voltage are Ic and Vc respectively. If a vertical
straight line is drawn through point Q intersecting curves for i B1 = 40 mA and i B2 = 80 mA
at points Q1 and Q2 respectively, the corresponding collector currents will be i C1 and iC2
respectively,
Now from equations [4.9 (b) and 4.9 (d)] we have
diC DiC iC2 - iC1
h fe = = = ...(4.10)
di B Di B VC
i B2 - i B1
di C Di
and h oe = = C = Slope of the output characteristic curve at the point
dv C Dv C IB
AC
= ...(4.11)
BC
Thus the value of hoe at point Q is given by the slope of the output characteristic curve
at that point. Thus slope can be determined by drawing a line tangential to the characteristic
curve at the point Q. The slope can also be determined by drawing an incremental triangle
ABC about point Q and noting the values of AC and BC.
The parameter hfe is the most important transistor small signal parameter. This common-
emitter current transfer ratio, or CE alpha, is also written ae or b', and called the small-
signal beta of the transistor.

4.4.2 Determination of Hybrid Parameters hre and hie.
For a common-emitter configuration, the input characteristics are shown in fig. 4.7. In this
figureletusconsiderthecurveforvC = VC. At a point Q on this curve, the quiescent base
voltage and base current are VB and IB respectively. If a vertical straight line is drawn
through this point Q intersecting curves for v C1 and v C 2 at points Q1 and Q2 respectively,,
the corresponding values of base voltages will be v B1 and v B2 respectively,,
Now from equations 4.9 (c) and 4.9 (a) we have
dv B Dv B v B2 - v B1
h re = = = ...(4.12)
dv C DvC IB
v C2 - vC1
dv B Dv B
h ie = =
di B Di B VC
Fig 4.7 : Input Characteristics For Common.

Emitter N-P-N Transistor
AC
= Slope of the input characteristic curve at the point = ...(4.13)
BC
Since hre is of the order of 10–4 so Dv B << Dv C and hence the above method is not
accurate in practice, though it is correct in principle.
Slope of the input characteristic curve giving the value of hie can be determined by
either drawing a straight tangential line to the input characteristic curve at point Q or by
drawing an incremental triangle ABC about point Q and noting the values of AC and BC.
The above procedure explained for the determination of the common-emitter
h-parameters can also be used for determination of the common-base and common-collector
h-parameters from the appropriate input and output characteristics.
4.5 TYPICAL VALUES OF h-PARAMETERS FOR A TRANSISTOR
Typical values of h-parameters of a transistor for CE, CB and CC configurations at
IE = 1.3 mA are given below in Table 4.3.
TABLE 4.3
Configuration Com mon -Emitter CE Common-Base CB Common-Collector CC
Parameter CE CB CC
hi 1.1 kW 21.6 W 1.1 kW
hr 2.5 × 10–4 2.9 × 10–4 ~1
hf 50 – 0.98 – 51
ho 25 W S (m A/V) 0.49 m S (m A/V) 25 m S (m A/V)
I/h o 40 kW 2.04 M W 40 kW
4.6 CONVERSION OF HYBRID PARAMETERS IN TRANSISTOR

THREE CONFIGURATIONS
Some transistor manufacturers provide only the four CE hybrid parameters while others
provide CB h-parameters. Sometimes, for a specific purpose, it becomes necessary to
convert one set of h-parameters in one configuration to another set in another configuration.
The conversion formulas can be obtained using the definitions of the parameters involved
and Kirchhoff s laws.
(a) Common Base Hybrid Model (b) Circuit of Fig (a) Redrawn in
Fig. 4.8 CE Configuration
For example let us convert common emitter h-parameters to the common-base h-
parameters. For this purpose first the CB hybrid model is drawn as shown in fig. 4.8 (a)
and then it is redrawn in CE configuration, as shown in fig. 4.8 (b). The latter corresponds
in every detail to the former except that the emitter terminal E is made common to the
input and output ports.
Vbe Vbc + Vce Vbc

By definitions h re = = =1+
Vce Ib = 0
Vce Ib = 0
Vce Ib =0
If Ib = 0, then Ic = - Ie , and the current I in hob in fig. 4.8 (b) is I = (1 + hfb) Ie

= hobVbc
Applying Kirchhoff s voltage law to the output mesh of fig. 4.8 (b) we have
h ib Ie + h rb Vcb + Vbc + Vce = 0
Combining the above two equations we have
h ib h ob Vbc -(1 + h fb )
Vbc - h rb Vbc + Vbc + Vce = 0 or =
1 + h fb Vce h ib h ob + (1 - h rb )(1 + h fb )
Vbc h ib h ob - (1 + h fb )h rb
Thus h re = 1 + = ...(4.14)
Vce h ib h ob + (1 - h rb )(1 + h fb )
This is an exact expression. The simpler approximate formula is obtained by noting
that, for typical values given in Table 4.3 hrb << 1 and hob hib << (1 + hfb)
h ib h ob
So h re = - h rb ...(4.15)
1 + h fb
Vbe
By definition h ie =
Ib Vce = 0
If terminals C and E are connected

together in fig. 4.8 (b), we have circuit shown
in fig. 4.9. From fig. 4.9, we see that
Fig. 4.9
Vcb = - Vbc = - Vbe
Applying Kirchhoff s voltage law to the left hand mesh, we have
Vbe + h ib I e + h rb Vcb = 0
Combining the above two equations we have
1 - h rb
Ie = - Vbe
h ib
Applying Kirchhoff s current law to node B in fig. 4.9 we have
I b + Ie + h fb Ie - h ob Vbe = 0
1 - h rb
or, I b = (1 + h fb ) Vbe + h ob Vbe
h ib
Vbe h ib
Thus h ie = = ...(4.16)
Ib h ib h ob + (1 - h rb )(1 + h fb )
This is an exact expression. Since hrb << 1 and hob hib << (1 + hfb), so the above equation
h ib
is reduced to h ie ; ...(4.17)
1 + h fb
Approximate conversion formulas for transistor parameters are given below in Table 4.4
TABLE- 4.4
Configuration Common-Emitter, Common-Base, Common-collector, Equivalent

CE CB CC T-Circuit
Parameter
h ib re
h ie 1.1 k W h ic * rb +
1 + h fb 1+ a
h ib h ob re
h re 2.5×10-4 - h rb 1 - h rc *
1 + h fb rc (1 - a)
-
h fb a
h fe 50 -(1 + h fc ) * =b
1 + h fb 1- a
h ob 1
h oe 25 m S(m A / V) h oc *
1 + h fb rc (1 - a)
h ie
h ib 21.6W - h ic / h fe re + (1 - a )rb
1 + h fe
h ie h oe h ic h oc
h rb - h re 2.9 × 10-4 h re - -1 rb / rc
1 + h fe h fc
- h fe 1 + f fc
h fb -0.98 - -a
1 + h fe h fc
h oe - h oc
h ob 0.49 m S (m A / V) 1/ rc
1 + h fe h fc
h ib re
h ic h ie * 1.1 kW rb +
1 + h fb 1- a
re
h rc 1 - h re ; 1* 1 1 1-
rc (1 - a)
-1 1
h fe -(1 + h fe ) * -51 -
1 + h fb 1- a
h ob 25 m S (m A / V) 1
h oc h oe *
1 + h fb rc (1 - a)
h fe 1 + h fc
a - h fb 0.98
1 + h fe h fc
1 + h fe * 1 - h fc * 2.04 MW
rc
h oe h ob h oc
h re * h rb 1 + h rc *
re h ib - (1 + h fb ) * 10W
h oe h ob h oc
h re h rb * h fc 590 W
rb h ie - (1 + h fe ) * h ic + (1 - h rc ) *
h oe h ob h oc
Example-4.1
hfe = 50, hie = 0.83 kW, find out the current gain (hfb) and input impedance (hib) for a
transistor in CB configuration
-h fe -50
Solution : h fb = = = -0.98 Ans.
1 + h fe 1 + 50
- h ie 0.83 ´ 103
h ib = = = 16.27 W Ans .
1 + h fe 1 + 50
Example-4.2
The h-parameters for a CE configuration are hie = 2,600 W, hfe = 100, and hre = 0.02 × 102
and hoe = 5 × 10–6 S. Find h-parameters for CC configuration.
Solution : hic = hie = 2,600 W Ans.
hfc = – (1 + hfe) = – (1 + 100) = – 101 Ans.
hrc = 1 – hre ~ 1 Ans.
hoc = hoe = 5 × 10–6 S Ans.
4.7 TRANSISTOR AMPLIFIER CIRCUIT PERFORMANCE IN h-PARAMETERS
A transistor amplifier can be formed simply by connecting a signal source to the input
and an external load to the output terminals of a transistor, as shown in fig. 4.10 and giving
proper bias to it. All transistor amplifiers, connected in any one of the three possible
configurations, are basically two-port devices, as shown in fig. 4.10, that is, there are a pair
of input terminals and a pair of output terminals. In fig. 4.11, the transistor has been replaced
with its small-signal hybrid model without specifying the configuration. The circuit shown
in fig. 4.11 is valid for any type of load whether it be a pure resistance, an impedance or
another transistor. This is true because the transistor hybrid model was derived without
any regard to the external circuit in which the transistor is incorporated. For an amplifier
there are six quantities of great interest (input impedance, output impedance, current gain,
voltage gain, power gain and phase relationship), each of which will be discussed in detail
here.
Fig. 4.10 : Basic Amplifier Circuit

Fig. 4.11 : Small Signal Hybrid Model of Transistor

Amplifier Circuit Shown in Fig. 4.10
For the resulting equations to be useful, however, the quiescent point must be established
and the resulting h-parameters must be known :
1. Input Impedance. The input impedance Zin is defined as the ratio of input voltage to
the input current i.e.
V1
Zin = ... (4.18)
I1
From the input circuit shown in fig. 4.11 we have
V1 = h i I1 + h r V2 ... (4.19)
Substituting V1 = hi I1 + hr V2 in equation (4.18) we have
h i I1 + h r V2 V
Zin = = hi + hr 2 ... (4.20)
I1 I1
From the output circuit shown in fig. 4.11 we have
-V2
I 2 = h f I1 + h o V2 = ... (4.21)
ZL
The minus sign is used here because the actual current flows in the direction opposite to
that of I2.
V2 -h f
So = ... (4.22)
I1 h + 1
o
ZL
V2
Substituting value of I from equation (4.22) in equation (4.20) we have
1
hr hf
Input impedance Zin = h i - 1 ... (4.23)
ho +
ZL
~ hi ... if hr or ZL is very small.
It is seen that Zin depends on ZL i.e. ac resistance of the load across the output termi-
nals of the transistors.
2. Current Gain. The current gain is denoted by Ai and is defined as the ratio of output
current to input current.
IL -I2
i.e. Ai = = ... (4.24)
I1 I1
Applying Kirchhoffs current law to node A in the output circuit
I2=hf I1 + h0 V2
Substituting V2 = – I2 ZL from equation (4.21) we have
I2 = hf I1 – h0 I2 ZL
-I 2 -h f
or Current gain Ai = = ...(4.25)
I1 1 + h o ZL
~ – hf if ZL is zero or h0 ZL<< 1
Current Gain Taking Rs into Account. The source current is not the transistor input
current because it partly flows through Rs and partly through Zin. So the voltage source Vs
with series source resistance Rs is replaced by the Norton’s equivalent source, shown in
fig. 4.12, consisting of current source Is with source resistance Rs in shunt. The overall
current gain Ais is given as
- I2 -I2 I1 I
A is = = . = Ai 1 ...(4.26)
Is I1 Is Is
I1 Rs
From fig. 4.12, I = Z + R
s in s
Ai R s
So Ais = Z + R ...(4.27)
in s
Norton’s “Equivalent For The Source

Fig. 4.12
Note that if Rs = ¥ then Ais = Ai. Hence Ai is the current gain for an ideal current
source (one with infinite source resistance).
3. Voltage Gain. The voltage gain is denoted by Av and is defined as the ratio of output
voltage to the input voltage i.e.
V V -h f
Av = 2 = 2 = ... (4.28)
V1 I1Zin æ 1 ö
ç 0
h + ÷ in
Z
è ZL ø
V2 -h f
Q from equation (4.22) =
I1 h + 1
o
ZL
Voltage Gain Taking Rs into Account. Overall voltage gain Avs is given as
V2 V2 V1 V
A vs = = . = Av 1 ... (4.29)
Vs V1 Vs Vs
From the equivalent input circuit of the amplifier given in fig. 4.13, we have
V1 Zin
=
Vs Zin + R s
Zin
So A vs = A v ... (4.30)
Zin + R s
Note that if Rs = 0 the Avs = Av. Hence Av is
the voltage gain for an ideal voltage source
(one with zero internal resistance). In
practice, the quantity Avs is more meaningful
than Av since usually, the source resistance
has significant effect on the overall voltage
amplification.
Independent of the transistor
characteristics, the voltage and current gains
taking source impedance into account, is Fig. 4.13 : Thevenin’s Equivalent
related as provided that the current and For The Source
voltage generators have the same source resistance Rs
4. Output Admittance. The output admittance Yout is defined as the ratio of the output
current to output voltage with Vs = 0 i.e.
I
Yout = 2 with Vs = 0
V2 ...(4.31)
I1
= hf + ho ...(4.32)
V2
Q from equation (4.21), I2 = hf I1 + h0 V2
Now from input circuit shown in fig. 4.11 we have

R s I1 + h i I1 + h r V2 = 0 ...(4.33) taking Vs = 0
I1 hr
or =- ...(4.34)
V2 hi + Rs
I1 -h r
Substituting V = h + R from equation (4.34) in equation (4.32) we have
2 i s
hf hr
Yout = h o - ...(4.35)
hi + R s
It is be noted that output admittance is a function of source resistance Rs. If the
source impedance is purely resistive, as it has been assumed, then Y0 is real (purely
conductance).
In the above definition of Yout, the load ZL has been considered external to the amplifier.
If the output impedance of the amplifier stage with ZL included is required, the load
impedance can be determined as the parallel combination of ZL and Zout (i.e., ZL || Zout).
5. Power Gain. The average power delivered to the load shown in fig. 4.10, P2 equals
| V2 | IL | cos f where f is the phase angle between V2 and IL. For situation under
discussion power delivered, P2 = – V2 I2 cos f. The minus sign arises for the same reason
discussed in the derivation of input impedance. It indicates that the load is absorbing power
and not supplying to the amplifier circuit. For purely resistive load, cos f = 1 and P2 = –V2
I2. The input power is V1 I1 So power gain
P2 -V2 I 2
Ap = = . = -A v Ai ...(4.36)
P1 V1 I1
As V2 = – I2 RL and I2 = Ai I1
V2 - Ai I1R L -Ai R L - Ai R L
\ Av = = = =
V1 V1 V1 / I1 Zin
æ -Ai R L ö Ai2 R L
So power gain, A p = -A v Ai = - ç ÷ i
A = ...(4.37)
è Zin ø Zin
Example-4.3
A junction transistor has the following h-parameters:
hie = 2,000 W; hre = 1.6 × 10–4, hfe = 49, hoe = 50 m A/V
Determine the current gain, voltage gain, input resistance and output resistance of the CE
amplifier if the load resistance is 30 k W and the source resistance is 600 W.
- h fe -49
Solution : Current gain, A i = = = -19.6
1 + h oe R L 1 + 50 + 10-6 ´ 30 ´ 103
-4
h oe h fe 1.6 ´ 10 ´ 49
Input resistance, R in = h ie - = 2, 000 - = 1, 906 W Ans.
1 -6 1
h oe + 50 ´ 10 +
RO 30 ´ 103
- h fe - h fe R L AR -19.6 ´ 30 ´ 103
Voltage gain, A v = = = i L = = -308.5
æ 1 ö (1 + h oe R L )R in R in 1.906
ç h oe + ÷ R in
è RL ø
R in 1,906
Overall voltage gain, A vs = A v = -308.5 ´ = -235 Ans.
R in + R s 1,906 + 600
Rs 600
Overall current gain, A is = Ai = -19.6 ´ = -4.7 Ans.
R in + R s 1,906 + 600
h fe h re 49 ´ 1.6 ´ 10-4
Output conductance, G out = h oe - = 50 ´ 10-6 - = 46.985 ´ 10-6 S
h ie + R s 2,000 + 600
1 1
Output resistance, Rout = = = 21, 283 W or 21,293 kW Ans.
G out 46,985 ´ 10-6
Example-4.4
A BJT has hie = 2 k W, hfe = 100, hre = 2.5 × 10–4 and hoe - 25 m A/V as parameters in CE
configuration. It is used as an emitter follower amplifier with Rs = 1 k W and RL = 500 W.
Determine for the amplifier the voltage gain AVs = V0/VS, the current gain Ais = I0/IS, the
input resistance Ru and output resistance R0.
Solution:
For emitter follower (common-collector) amplifier, transistor parameters are :
hic = hie = 2 kW
hfc = – (1 + hfe) = – (l + 100) = – 101
hre = 1 – hre = 1 – 2.5 × 10–4 = 0.99975 ~ 1
hoc = hoe = 25 × 10–6 S
-h fc -(-101)
Current gain Ai = = = 99.75
1 + h oc R L 1 + 25 ´ 10-6 ´ 500
h re h fe 1 ´ ( -101)
Input resistance, Rin = hic - = 2 ´ 103 - = 51.876 kW Ans.
1 -5 1
h oc + 25 ´ 10 +
RL 500
-h fc -(1 - 101)
Voltage gain, Av = = = 0.9614
æ 1 ö æ -6 1 ö
ç 25 ´ 10 + ´ ´ 3
ç h oc + ÷ R in 500 ÷ø
51.876 10
è R L ø è
R in 51.876
Overall voltage gain, Aus = Av = 0.9614 ´ = 0.9432 Ans.
R in + R s 51.876 + 1
Rs 1
Overall current gain, Ais = Ai = 99.75 ´ = 1.886 Ans.
Ri + Rs 51.876 + 1
h fc ´ h rc (-101 ´ 1)
Output conductance, G0 = hoc - = 25 ´ 10-6 - = 33.69 ´ 10-3 S
h ic + R s 2 ´ 10 + 1 ´ 10
3 3
1 1
Output resistance, R0 = = = 29.68 W Ans.
G o 33.69 ´ 10-3
4.8 LIMITATIONS OF h-PARAMETERS
Input impedance, output impedance, current gain, voltage gain and power gain of a
transistor amplifier can be determined accurately by using h-parameters of the circuit.
However, there are two major limitations in the use of these parameters, as mentioned
below.
1. By using h-parameters correct answers can be had for small ac signals only because
a transistor behaves as a linear device for small signals only.
2. It is very difficult to get the exact values of h-parameters for a particular transistor. It
is due to the fact that h-parameters are subject to considerable variations action due to
change in operating point.
While predicting performance of an amplifier, care is required to be taken that
h-parameter values used are correct for the operating point under consideration.
4.9 STEPS FOR DRAWING SMALL SIGNAL MODEL
1) Setting all dc sources to zero and replacing them by a short-circuit equivalent

2) Replacing all capacitors by a short-circuit equivalent.
3) Removing all elements bypassed by the short-circuit equivalents introduced by steps
1 and 2.
4) Redrawing the network in a more convenient and logical form.
4.10 STEPS FOR ANALYSIS OF TRANSISTOR CIRCUIT
1) Draw the actual wiring diagram of the circuit neatly.
2) Mark the points B (base), C (collector), and E (emitter) on this circuit diagram. Locate
these points as the start of the equivalent circuit. Maintain the same relative positions
as in the original circuit.
3) Replace each transistor by its h-parameter model.
4) Transfer all circuit elements from the actual circuit to the equivalent circuit of the
amplifier.
5) Replace each independent dc source by its internal resistance. The ideal voltage source
is replaced by a short circuit, and the ideal current source by an open circuit.
6) Solve the resultant linear circuit for mesh or branch currents and node voltages by
applying Kirchhoff’s current and voltage laws (KCL and KVL).
4.11 re - TRANSISTOR MODEL
26mv
For any configuration re =
IE
4.11.1 Common base configuration
c Ic c
e e Ie
IC=aIe
b b
Fig. 4.14 Fig. 4.15
The diode equivalent circuit consists of VT, re and an ideal diode.

For ac analysis dc source VT is made short circuited and as the diode is forward biased so
ideal diode is ON.
So the re model is,
e c
Ie IC
re aIe
(For n-p-n Transistor)

b
Fig. 4.16
e c
Ie IC
re
aIe
(For p-n-p Transistor)
b
Fig. 4.17
4.11.2 Common emitter configuration

c c
Ic
c b Ib b Ib
b b b
Ib Ie
e re
e e
Fig. 4.18
Here Vbe = Iere = (b+ 1) Ibre
Zi =
Vbe
Ib
b g
= b + 1 re
~ bre
And Zo = ro (let)
So the re-model is :-
b c
Ib IC
bre
bI b ro
Ie (For n-p-n Transistor)

e
Fig. 4.19
b c (For p-n-p Transistor)

Ib Ic
bre bIb r0
Ie
e
Fig. 4.20
4.12 COMPARISON BETWEEN HYBRID MODEL & re - MODEL
h - parameter model re-model

I) It is the actual model I) It is the approximate model
II) It is identical for all types II) It is different for different
of configurations configurations.
III) Analysis is little bit complex III) It’s analysis is comparatively easier.
IV) It is useful at lower frequencies IV) It is useful for all frequencies.
4.13 BJT SMALL-SIGNAL ANALYSIS

Common-Emitter Fixed-Bias Configuration
VCC
RC C Vo
Io Ii Io
RB
Vo B
Ii Vi
B C2 RC
Vi Zo
C1 Zo RB
Zi E
Zi
E
Fig. 4.21 Fig 4.22
Ii Ib IC
+ Z C +
i Io
Vi
RB bre b Ib ro RC Vo
– –
Zo
Fig 4.23
Zi : Figure 4.23 clearly reveals that
Z i = R B ||bre ohms
For the majority of situations RB is greater than bre by more than a factor of 10, it becomes
Zi @ bre ohms
R B ³10bre
Zo
ro RC
Fig. 4.24
Z0: The output impedance of any system is defined as the impedance Z0 determined when
Vi = 0. For Fig 4.23, when Vi = 0, Ii = Ib = 0, resulting in an open-circuit equivalence for the
current source. The result is the configuration of Fig. 4.24
Z o = R C || ro ohms
If r0 > 10 RC, the approximation RC || ro @ RC is frequently applied and
Zo @ R C
ro ³10 R C
AV :The resistors r0 and RC are in parallel,

and V0 = – bIb (RC || r0)
Vi
but Ib =
brC
V0 = -b
FG V IJ bR || r g
H br K
i
so that C 0
e
and AV =
V
=-
0 bR || r g C 0
Vi re
RC
If r0 > 10RC, AV = -
re r0 ³10 R C
Ai : The current gain is determined in the following manner :

Applying the current-divider rule to the input and output circuits,
I0 =
br gbbI g
0 b
and
I0
=
r0b
r0 + R C I b r0 + R C
with Ib =
bR gbI g
B i
or
Ib
=
RB
R B + bre I i R B + bre
Ai =
Io I
= o
FG IJ FG I IJ = FG r b IJ FG R IJ
H K H I K H r + R K H R + br K
b o B
The result is Ii Ib i o C B e
Io bR B ro
Ai = =
and Ii b gb
ro + R C R B + bre g
If r0 > 10RC and RB > 10bre,
I0 bR B r0
Ai = @
I i ( r0 )( R B )
and Ai @b
r0 ³10 R C , R B ³10bre
Zi
and also Ai = AV
RC
Phase Relationship : The negative sign in the resulting equation for AV reveals that a
1800 phase shift occurs between the input and output signals, as shown in Fig. 7.25.
VCC
V0
RC
Vi RB
V0 0 t
0
t Vi
Fig.4.25 : Demonstrating the 1800 phase shift between input and output waveforms
Example-4.5 For the network given below :
Fig. 4.26
(a) Calculate IB, IC and re.

(b) Determine Zi and Z0 .
(c) Calculate Av and Ai .
(d) Determine the effect of r0 = 40 kW on Av and Ai
Solution : (a) Applying KVL to the loop containing RB = 390 kW
10V - 0.7V
IB = = 23.85 mA
390kW
Since IC = b I B
Þ I C = 100 ´ 23.85 = 2.38 mA
Also I E = (b + 1) I B = 101 ´ 0.02385 mA = 2.409 mA
26 mV
Hence re =
IE
26 mV
Þ re = = 10.79 W
2.409 mA
(b) Now Zi = bre
or Zi = 100 ´ 10.79 W = 1.079 kW = 1.08 kW
and Zo = R C = 4.3 kW
RC 4.3kW
(c) Av = - =- = -398.52
re 10.79 W
and current gain A i = b since condition R B > 10b re . i.e. 390 kW > 10.79 kW is fulfilled.
Hence A i = b = 100
(d) Including the effect of ro = 40 kW
ro || R C 3.883 kW
Av = - =- = -359.83
re 10.79 W
Thus, magnitude of Av is reduced.
bR B ro
Now Ai =
(ro + R C )(R B + bre )
(100) ´ (390kW) ´ (40 kW)

= = 90.044
(44.3kW) ´ (391.08kW)
Hence, the effect of ro on Ai is to reduce it by (100 – 90) = 10.
Example-4.6
VCC
For the network shown, determine VCC for a
voltage gain of Av = 200. 4.7 kW
1M W
V0
Vi b = 90
Solution : Given Av = – 200

Fig. 4.27
Since nothing is said about ro so, we will neglect its effect.
-R C
Now Av =
re (for fixed-bais configuration)
4.7 kW
Þ -200 = -
re
4.7 kW 4700
Þ re = = = 23.5 W
200 200
26 mV
Since re =
IE
26mV 26
Þ 23.5 = Þ IE = mA = 1.106 mA
IE 23.5
Now I E = (b + 1)I B
IE 1.106 mA
or IB = = = 0.012mA = 12.16 mA
(b + 1) 91
From d.c analysis
VCC - VBE
IB =
RB
VCC - 0.7V
Þ 12.16 ´ 10-6 =
1 ´ 106
Þ (VCC - 0.7) = 12.16 ´ 10-6 ´ 1 ´ 106 = 12.16
or VCC = 12.16 + 0.7 = 12.86 V
4.14 VOLTAGE-DIVIDER BIAS

VCC
I0
R1 RC
Ii V0
B C C2
Vi
C1 Z0
E
Zi R2
RE CE
Fig. 4.28 : Voltage-divider bias configuration

Substituting the re equivalent circuit will result in the network of Fig. 4.29. Note the
absence of RE due to the low-impedance shorting effect of the bypass capacitor, CE. That
is, at the frequency (or frequencies) of operation, the reactance of the capacitor is so small
compared to RE that it is treated as a short circuit across RE. When
Ii
b Ib c
+ +
I0
Zi
Vi R1 R2 bre b Ib r0 RC V0
– e e Z0 –
R’
Fig. 4.29 : Substituting the re equivalent circuit into the ac equivalent network of Fig. 4.28
VCC is set to zero, it places one end of R1 and RC at ground potential as shown in Fig. 4.29.
In addition, note that R1 and R2 remain part of the input circuit while RC is part of the output
circuit. The parallel combination of R1 and R2 is defined by
R 1R 2
R ¢ = R1 || R 2 =
R1 + R 2
Zi : From Fig. 4.29,
Z i = R ¢||bre
Z0 : From Fig. 4.29 with Vi set to 0 V resulting in Ib = 0 mA and bIb = 0 mA,

Z 0 = R C || r0
If r0 > 10RC,
Z0 @ R C
r0 ³10 R C
AV : Since RC and r0 are in parallel,

b gb
V0 = - bI b R C || r0 g
Vi
and Ib =
bre
V0 = -b
FG V IJ bR || r g
H br K
i
so that C 0
e
V0 - R C || r0
and AV = =
Vi re
which is an exact duplicate of the equation obtained for the fixed-bias configuration.
For ro > 100RC.
V0 R C
AV = @
Vi re
Ai : Here
R ¢ = R 1 || R 2 = R B , the equation for the current gain will be
I0 bR ¢r0
Ai = =
Ii b
r0 + R C R ¢ + bre gb g
For ro > 10RC.
I0 bR ¢r0
Ai = @
b
I i r0 R ¢ + bre g
I0 bR ¢r0
and Ai = @
I i R ¢ + bre r0 ³10 R C
And if R ¢ ³ 10bre
I 0 bR ¢
Ai = =
Ii R¢
I0
and Ai = @b
Ii r0 ³10 R C , R ¢³10bre
Again,
Zi
A i = -A v
RC
Phase relationship : The negative sign reveals a 1800 phase shift between V0 and Vi.
Example-4.7
For the network shown below :
(a) Determine re (b) Calculate Zi and Zo
(c) Find Av and Ai (d) Repeat part (b) and with ro = 50 kW
Fig. 4.30
Solution : The above configuration can be equivalently drawn as shown in the figure.
R 1R 2 (39 kW) ´ (4.7 kW)
R ¢ = R1 || R 2 = =
R1 + R 2 43.7 kW
Þ R ¢ = 4.194 kW
Fig. 4.30 (a)

(a) d.c testing
b R E > 10 R 2
Þ (100) ´ (1.2 kW) > 10(4.7 kW)
120 kW > 47 kW satisfied
Using the approximate approach

R2 (4.7 kW)
VB = VCC . = (16 V). = 1.72 V
R1 + R 2 39 kW + 4.7 kW)
VE = VB - VBE = 1.72 V - 0.7 V = 1.02 V
VE 1.02V
IE = = = 0.850 mA
R E 1.2 kW
26mV 26 mV
\ re = = = 30.56 W
IE 0.850 mA
(b) Zi = R ¢ || b re
Now b re = 100 ´ 14.789 W = 1.479 kW
(4.194 kW) ´ (1.479 kW)
\ Zi = (4.194 W) || (1.479 kW) =
4.673 kW
Þ Zi = 1.093 kW, Zo = R C = 3.9 kW
RC 3.9 kW
(c) Voltage gain Av = - =-
re 14.789 ´ 10-3 kW
Þ Av = – 263.71
For voltage divider bias
R ¢b (4.194 kW) ´ (100)
Ai = = = 73.93
R ¢ + bre 4.194 kW + 1.479 kW
(d) Now given ro = 50 kW
Zi will not depend on ro and
Hence Zi = 1.093 W
Zo = R e || ro = (3.9 kW) || (50 kW )
(3.9 kW) ´ (50 kW)
= = 3.618 kW
53.9 kW
R C || ro 3.618 kW
Av = - =- = -244.64
re 14.789 ´ 10-3 kW
R¢ rb
Current gain A i = · o
R ¢ + bre ro + R C
4.194 kW (50 kW) ´ (100)

Þ Ai = ´ = 68.58.
5.673 kW 53.9 kW
Example-4.8
(a) Determine re
(b) Calculate VB and VC.
Vo
(c) Determine Zi and A v =
Vi
Solution : d.c. testing is

b R E > 10 R 2
Fig. 4.31
Þ (180) × (2.2 kW) > 10 × 56 kW
Þ 396 kW > 560 kW, which is not true
Hence, we will proceed in a general way.
Drawing the base-emitter portion of the network.
Fig. 4.31 (a)

R th = R1 || R 2 = 220 kW || 50 kW = 44.638 kW
R 2 .VCC
E th = VR 2 = = 4.058V
R1 + R 2
Fig. 4.31 (b)

E th - VBE 4.058V - 0.7 V

Hence IB = =
R th + (b + 1)R E 44.638 kW + 398.2 kW
= 7.583 mA
Hence I E = (b + 1)IB = 1.372 mA
26 mV
(a) Thus rd = = 18.943 W
IE
(b) Now, from diagram, it is very clear that
VB = E th - I B ´ R th
Þ VB = 4.058 V - 7.583 ´ 106 ´ 44.638 ´ 103 V = 3.719 V
Also Q IC = b IB
Þ IC = 180 ´ 7.583 ´ 10-6 A = 1.365 mA
Now, from the original diagram, we find
VC = VCC - I C ´ R C
= 20 - 1.365 ´ 10-3 ´ 6.8 ´ 103 = 10.718 V
(c) Zi = R ¢ || b re where R ¢ = R th
R th ´ bre (44.638kW) ´ (3.41kW)
or Zi = =
R th + bre 48.048 kW
or Zi = 3.168 kW
Vo
Voltage gain Av =
Vi
R C 6.8 ´ 103
But Av = - = = -358.97
re 18.943
4.15 CE EMITTER-BIAS CONFIGURATION
The networks examined in this section include an emitter resistor that may or may not
be bypassed in the ac domain. We will first consider the unbypassed situation and then
modify the resulting equations for the bypassed configuration.
Unbypassed
The most fundamental of unbypassed configurations appears in Fig. 4.32. The re equiv-
alent model is substituted in Fig. 4.33, but note the absence of the resistance r0. The effect
of r0 is to make the analysis a great deal more complicated, and considering the fact that in
most situations its effect can be ignored, it will not be included in the current analysis.
However, the effect of r0 will be discussed later in. this section.
Applying Kirchhoff ‘s voltage law to the input side of Fig. 4.33 will result in
Vi = I bb re + I e R E
or Vi = I bb re + (b + 1)I b R E
and the input impedance looking into the network to the right of RB is
Vi
Zb = = bre + (b + 1)R E
Ib
Fig.4.32 : CE emitter-bias Fig.4.33 : Substituting the re equivalent circuit into

configuration. the ac equivalent network of Fig. 4.32.
The result as displayed in Fig. 4.34 reveals that the input impedance of a transistor with an
unbypassed resistor RE is determined by
Z b = bre + (b + 1)R E
Since b is normally much greater than 1, the approximate equation is the following:
Z b @ b re + bR E
and Zb @ b(re + R E )
Since RE is often much greater than re ,
Zb @ bR E
Zi :
Zi = R B || Zb
Fig. 4.34 Defining the input impedance of a

transistor with an unbypassed emitter resistor.
Z0 : With Vi set to zero, Ib = 0 and bIb can be replaced by an open-circuit equivalent. The
result is
Zo = R C
Vi
Av : Ib =
Zb
and Vo = - Io R C = -b Ib R C
æV ö
= -b ç i ÷ R C
è Zb ø
Vo bR
with Av = =- C
Vi Zb
Substituting Zb = b(re + RE) gives
Vo RC
Av = =-
Vi re + R E
and for the approximation Zb @ b R E ,
Vo R
Av = @- C
Vi RE
Ai : The magnitude of RB is often too close to Zb to permit the approximation I b = Ii .

Applying the current-divider rule to the input circuit will result in
R B Ii
Ib =
R B + Zb
Ib RB
and =
Ii R B + Z b
In addition, Io = bIb
Io
and =b
Ib
I o Io I b
so that Ai = =
Ii I b Ii
RB
=b
R B + Zb
Io bR B
and Ai = =
Ii R B + Z b
Zi
or A i = -A v
RC
Phase relationship: The negative sign reveals a 180° phase shift between Vo and Vi.
Effect of r0 : The equations appearing below will clearly reveal the additional complexity
resulting from including r0 in the analysis. Note in each case, however, that when certain
conditions are met, the equations return to the form just derived. The derivation of each
equation is beyond the needs of this text and is left as an exercise for the reader. Each
equation can be derived through careful application of the basic laws of circuit analysis
such as Kirchhoff’s voltage and current laws, source conversions, Thevenin’s theorem,
and so on. The equations were included to remove the nagging question of the effect of r0
on the important parameters of a transistor configuration.
Zi:
é (b + 1) + R C / ro ù
Z b = b re + ê ú RE
ë 1 + (R C + R E ) / ro û
Since the ratio Rc/r0 is always much less than (b + 1),
(b + 1)R E
Zb @ bre +
1 + (R C + R E ) / ro
For ra > 10(RC + RE),
Zb @ bre + (b + 1) R E
In other words, if r0 > 10(RC + RE), all the equations derived earlier will result. Since
b + 1 @ b , the following equation is an excellent one for most applications:
Zb @ b(re + R E )
ro ³10(R C + R E )
Zo :
é ù
ê b(ro + re ) ú
Zo = R C || ê ro + ú
ê bre ú
1+
êë R E úû
However, r0 >> re, and

é ù
ê b ú
Zo @ R C || ro ê1 - ú
ê 1 + bre ú
êë RE úû
which can be written as
é ù
ê 1 ú
Zo @ R C || ro ê1 + ú
ê 1 + re ú
êë b R E úû
Typically 1/b and re/RE are less than one with a sum usually less than one. The result
is a multiplying factor for r0 greater than one. For b = 100, re = 10W, and RE = 1 kW:
1 1 1
= = = 50
1 re 1 10 W 0.02
+ +
b RE 100 1000 W
and
which is certainly simply RC. Therefore,
Zo = R C
Any level of ro
which was obtained earlier.

Av :
b R C é re ù R C
- ê1 + ú +
Vo Zb ë ro û ro
Av = =
Vi R
1+ C
ro
re
The ratio r << 1
o
bR C R C
- +
V Zb ro
and Av = o @
Vi R
1+ C
ro
For r0 > 10RC ,
Vo bR C
Av = @
Vi Zb
ro ³10R C
as obtained earlier.
Ai: The determination of Ai will be left to the equation
Zi
Ai = A v
RC
using the above equations.

Bypassed
If RE of Fig. 4.32 is bypassed by an emitter capacitor CE, the complete re equivalent
model can be substituted resulting in the same equivalent network as in Fixed bias circuit.
Example-4.9
For the network shown :
(a) Determine re (b) Find Zi and Zo
(c) Calculate Av and Ai (d) Repeat parts (b) and with ro = 50 kW
(Assume ro = ¥ W for parts (b) and (c) unless otherwise stated)
Fig. 4.35
Solution :
Substituting the re equivalent circuit into the a.c. equivalent network of above figure, we get
(a) From d.c. analysis, we get
VCC - VBE 20V - 0.7V
IB = =
R B + (b + 1)R E 390 kW + (141)1.2 kW
Þ I B = 34.51 mA
I E = (b + 1) I B = 141 ´ (34.51 mA) = 4.866 mA
26mV 26mV
and re = = = 5.343 W
IE 4.866 mA
Fig. 4.35 (a)

(b) From equivalent diagram
Z b = b re + (b + 1) R E
= (140) (5.343 W) + (141) (1.2 kW)
= 169.95 kW » 170 kW
Now Zi = R B || Zb = 390 kW || 169.95 kW
Þ Zi = 118.37 kW
Zo = R C = 2.2 kW
bR C (140)(2.2 kW)
(c) Voltage gain Av = - =- = -1.812
Zb 169.95 kW
bR B (140) ´ 390 kW
Ai = =
R B + Z b 390 kW + 169.95kW
Þ A i = 97.5
(d) The placement of ro for this particular configuration is such that for typical parameter
values, the effect of ro on the output impedance and voltage gain can be ignored.
i.e. there will be no change by including ro = 50 kW and the results are all same as
calculated before.
Example-4.10
For the network configuration
given below, determine RE and
RB, if Av = 10 and Ie = 3.8 W.
Assume that Zb = bRE.
Fig. 4.36
Solution : Given AV = – 10
v
b RC
We know that Av = -
Zb
bRC R
or Av = - =- C (as given in the problem)
b RE RE
8.2 kW
Þ -10 = -
RE
8.2 kW
or RE = = 0.82 kW = 820 W
10
Now, given re = 3.8 W
26 mV , we get I = 26 mV
From re = E
IE re
26 mV
IE = = 6.842 mA
3.8 W
Also, since I E = (b + 1) I B
IE 6.842mA
Therefore IB = = = 56.546 mA
(b + 1) 121
But, d.c. analysis suggests that
VCC - VBE
IB =
R B + (b + 1)R E
20V - 0.7V
or 56.546 ´ 10-6 =
R B + (121)(820 W)
19.3 ´ 106
Þ R B + 99.22 kW = = 341.315 kW
56.546
or R B = 341.315 kW - 99.22 kW = 242.1 kW
Example-4.11
For the network of Fig. 4.37, determine (using appropriate approximations):
(a) r e.
(b) Z i
(c) Z 0.
(d) Av.
(e) A i
Fig. 4.37
Solution
(a) Testing bRE > 10R2
(210)(0.68 kW) > 10(10 kW)
142.8 kW > 100 kW (satisfied)
R2 10 kW
VB = VCC = (16 V) = 1.6V
R1 + R 2 90kW + 10 kW
VE = VB - VBE = 1.6V - 0.7V = 0.9V
VE 0.9 V
IE = = = 1.324 mA
R E 0.68kW
26 mV 26 mV
re = = = 19.64 W
IE 1.324 mA
(b) The ac equivalent circuit is provided in Fig. 4.38.
Now R B = R ¢ = R 1 || R 2 = 9 kW
Fig.4.38 : The ac equivalent circuit of Fig. 4.37.

The testing conditions of r0 ³ 10(R C + R E ) and r0 ³ 10R C are both satisfied. Using the
appropriate approximations yields
Z b @ b R E = 142.8 kW
Zi = R B || Z b = 9kW ||142.8 kW
= 8.47 kW
(c) Z0 = Rc = 2.2 kW
RC 2.2 kW
(d) A v = - R = - 0.68 kW = -3.24
E
Zi æ 8.47 kW ö
(e) A i = -A v R = -(-3.24) ç 2.2 kW ÷
C è ø
= 12.47
Example-4.12
Repeat Example 4.11 with CE in place.
Solution
(a) The dc analysis is the same, and re = 19.64 W.
(b) Zb = bre = (210)(19.64 W) @ 4.12 kW
Zi = RB||Zb = 9kW||4.12kW
= 2.83 kW
(c) Z0 = Rc = 2.2 kW
RC 2.2kW
(d) A v = - =- = -112.02 (a significant increase)
re 19.64W
Zi æ 2.83 kW ö
(e) Ai = -A v = -(-112.02) ç ÷
RL è 2.2 kW ø
= 144.1
Another variation of an emitter-
bias configuration appears in Fig. 4.39.
For the dc analysis, the emitter
resistance is R E1 + R E 2 , while for the
ac analysis, the resistor R E in the
equations above is simply R E1 with
R E 2 bypassed by CE.
Fig. 4.39 : An emitter-bias configuration with a portion
of the emitter-bias resistance bypassed in the ac domain.
4.16 EMITTER-FOLLOWER CONFIGURATION

When the output is taken from the emitter terminal of the transistor as shown in
Fig.4.40, the network is referred to as an emitter-follower. The output voltage is always
slightly, less than the input signal due to the drop from base to emitter, but the approximation
Av @ 1 is usually a good one. Unlike the collector voltage, the emitter voltage is in phase
with the signal Vi. That is, both V0 and Vi will attain their positive and negative peak values
at the same time. The fact that V0 “follows” the magnitude of Vi with an in-phase relationship
accounts for the terminology emitter-follower.
The most common emitter-follower configuration appears in Fig. 4.40. In fact, because
the collector is grounded for ac analysis, it is actually a common-collector configuration.
Other variations of Fig. 4.40 that draw the output off the emitter with V0 @ Vi will appear
later.
The emitter-follower configuration is
frequently used for impedance-matching
purposes. It presents a high impedance at
the input and a low impedance at the output,
which is the direct opposite of the standard
fixed-bias configuration. The resulting effect
is much the same as that obtained with a
transformer, where a load is matched to the
source impedance for maximum power
transfer through the system.
Substituting the re equivalent circuit into
the network of Fig. 4.40 will result in the Fig. 4.40 : Emitter-follower configuration.
network of Fig. 4.41.
Fig. 4.41 Substituting the re equivalent circuit into the ac equivalent network of Fig. 4.40.
Zi : Zi = R B || Zb
with Z b = bre + (b + 1)R E
or Zb @ b(re + R E )
and Zb @ bR E
Z0 : The output impedance is best described by first writing the equation for the current Ib:
Vi
Ib =
Zb
and then multiplying by (b + 1) to establish Ie. That is,
Vi
Ie = (b + 1)I b = (b + 1)
Zb
Substituting for Zb gives
(b + 1)Vi
Ie =
b re + (b + 1)R E
Vi
or Ie =
[bre /(b + 1)] + R E
but (b + 1) @ b
b re br
and @ e = re
b +1 b
Vi
so that Ie @
re + R E
The Figure that represents the above equation is given as :
Fig. 4.42 : Defining the output impedance for the emitter-follower configuration.
To determine Z0, Vi is set to zero and
Z0 = R E || re
Since RE is typically much greater than re, the following approximation is often applied:
Z0 @ re
Av: Figure 4.42 can be utilized to determine the voltage gain through an application of the
voltage-divider rule:
R E Vi
Vo =
R E + re
Vo RE
and Av = =
Vi R E + re
Since RE is usually much greater than re, RE + re = RE and
Vo
Av = @1
Vi
Ai : From Fig. 4.41
R B Ii
Ib =
R B + Zb
Ib RB
or =
Ii R B + Z b
and Io = - Ie = -(b + 1)I b
Io
or, = -(b + 1)
Ib
Io I o I b RB
so that Ai = = = -(b + 1)
Ii I b Ii R B + Zb
and since (b + 1) @ b
bR B
Ai @ -
R B + Zb
Zi
or A i = -A v
RE
Phase relationship: V0 and Vi are in phase for the emitter-follower configuration.
Effect of r0:
Zi:
(b + 1)R E
Zb = bre +
R
1+ E
r0
If the condition r0 > 10RE is satisfied,

Z b = bre + (b + 1)R E
Zb @ b(re + R E )
r0 ³10R E
Z0:
bre
Zo = ro || R E ||
(b + 1)
Using b + 1 @ b,
Zo = ro || R E || re
and since ro ? re ,
Zo @ R E || re
Any r0
Av:
(b + 1)R E / Zb
Av =
R
1+ E
r0
If the condition r0 > 10RE is satisfied and we use the approximation b + 1 @ b

bR E
Av @
Zb
But Zb @ b(re + R E )
bR E
so that Av @
b(re + R E )
RE
Av @
and re + R E
re ³10R E
Example-4.13
For the network of following configuration :
(a) Determine re and b re
(b) Find Zi and Zo
(c) Calculate Av and Ai
Fig. 4.43
Solution :
(a) Substituting the re equivalent circuit into the a.c. equivalent network of given figure.
This emitter follower type configuration.
Fig. 4.44 (a)

VCC - VBE
\ IB =
R B + (b + 1) R E
16 V - 0.7 V
= = 26.86 mA
270 kW + (111)(2.7 k W)
Thus I E = (b + 1)I B = (111)(26.86 mA) = 2.981 mA
26 mV 26 mV
re = = = 8.722 W
IE 2.981 mA
and b re = (110)(8.722 W) = 959.42 W

(b) Z b = b re + (b + 1) R E
= 110 ´ (8.722 W) + 111 ´ (2.7 kW)
= 300.66 kW » b R E
Thus Zi = R B || Zb = (270 kW)|| (300.66 kW)
270 ´ 300.66
= kW = 142.25 kW
570.66
For output impedance, the portion of network appears as
Fig. 4.44 (b)

Therefore Zo = R E || re = (2.7 kW) || (8.722 W)
(2.7 kW) ´ (8.722 W)

= = 8.694 = re
2.7 kW + 8.722 W
Vo RE
(c) Voltage gain Av = =
Vi R E + re
2.7 kW
Þ Av = = 0.977 » 1
2.7 kW + 8.722 W
b RB (110) ´ 270 kW)

Current gain Ai - =-
R B + Zb 270kW + 300.66 kW
Þ Ai = – 52.045
Ai can also be calculated with the help of following relation.
Zi 142.25 kW
Ai = -A v = -(0.997) ´ = 52.52
RE 2.7 kW
Example-4.14
For the network of given figure :
(a) Determine Zi and Zo
(b) Find Av
(c) Calculate Vo if Vi = 1 mV
Fig. 4.45
Solution :
This is the configuration of emitter following type.
(a) From KVL applying in the loop containing RB and RE
8V - 0.7 V
We get IB =
390 kW + (120 + 1)5.6kW
7.3 V
= = 6.84 mA
1067.6 kW
Hence I E = (b + 1)I B = 0.83 mA
26 mV 26 mV
Therefore re = = = 31.325 W
IE 0.83 mA
and b re = 120 ´ 31.325W = 3759.04 W = 3.76 kW
Now, as we shown in the re equivalent circuit of last problem.
Z b = b re + (b + 1) R E = 3.76 kW + 121 ´ 5.6 kW
= 681.36 kW
Thus Zi = R B || Zb = (681.36 kW) ||(390 kW)
681.36 ´ 390
= kW = 248 kW
681.36 + 390
Calculate Zo, drawing the portion of the network is below :
Fig. 4.45 (a)

Therefore Zo = R E || re
(5.6 kW) ´ (31.325 W)

or Zo = = 31.15 W = re
(5.6kW) + (31.325 W)
(b) For voltage gain, we utilize the above figure voltage drop across R E = Vo + 8V.
æ Vi + 8 ö
But that drop also equals ç ÷ ´ RE
è re + R E ø
Vi + 8
or ´ 5.6 = Vo + 8
5.631
or (Vi + 8) ´ 0.994 = (Vo + 8)
or A v = 0.994
Alternatively we can also calculate by simple voltage division rule
R E Vi
Vo =
re + R E
Vo 5.6 kW
or Av = = = 0.994
Vi 31.325 W + 5.6 kW
Vo
(c) We have A v = 0.994 or = 0.994
Vi
Given Vi = 1mV
Hence Vo = 0.994 ´ Vi
or, Vo = 0.994 ´ 1mV = 0.994 mV.
4.17 APPROXIMATE HYBRID EQUIVALENT CIRCUIT
The analysis using the
approximate hybrid equivalent
circuit of Fig. 4.46 for the
common-emitter configuration
and of Fig. 4.47 for the
common-base configuration is
very similar to that just
performed using the re model.
Although time and priorities do
not permit a detailed analysis of Fig. 4.46 : Approximate common-emitter hybrid
all the configurations discussed equivalent circuit.
thus far, a brief overview of
some of the most important will
be included in this section to
demonstrate the similarities in
approach and the resulting
equations.
Fig. 4.47 : Approximate common-base hybrid

equivalent circuit.
Since the various parameters of the hybrid model are specified by a data sheet or
experimental analysis, the dc analysis associated with use of the re model is not an integral
partofthe use ofthe hybrid param eters.hie = bre, hfe = b, hoe = 1/r0, hfb = – a, and hib =
re
4.17.1 Fixed-Bias Configuration
For the fixed-bias
configuration of Fig. 4.48, the
small-signal ac equivalent
network will appear as shown
in Fig. 4.49 using the
approximate common-emitter
hybrid equivalent model.
Fig. 4.48 : Fixed-bias configuration.
Fig. 4.49 : Substituting the approximate hybrid equivalent circuit into the
ac equivalent network of Fig.4.48.
Zi : From Fig. 4.49,
Zi = R B || h ie
Zo : From Fig. 4.49,
Z0 = R C ||1/ h oe
Av : Using R ¢ = 1/ h oe || R C ,
Vo = - Io R ¢ = - IC R ¢
= - h fe I b R ¢
Vi
and Ib =
h ie
Vi
with Vo = -h fe R¢
h ie
Vo h (R ||1/ h oe )
so that Av = = - fe C
Vi h ie
Av : Assuming that R B >> h ie and 1/ h oe ³ 10R C , then I b @ Ii and I o = IC = h fe I b = h fe Ii

with
Io
Ai = @ h fe
Ii
Example-4.15
For the network of Fig. 4.50, determine :
(a) Z i .
(b) Z o .
(c) Av.
(d) A i .
(a) Zi = R B || h ie = 330 kW ||1.175 kW
@ h ie = 1.171 kW
1 21
(b) ro = = = 50 kW
h oe 20 mA / V
1
Zo = || R C = 50 kW || 2.7 kW = 2.56 kW @ R C
h oe
h fe (R C ||1/ h oe ) (120)(2.7 kW || 50 kW)

(c) A v = - h ie
=-
1.171kW
= -262.34
(d) A i @ h fe = 120
4.17.2 Voltage-Divider Configuration
For the voltage-divider bias configuration of Fig. 4.51, the resulting small-signal ac
equivalent network will have the same appearance as Fig. 4.49, with RB replaced by
R ¢ = R 1 || R 2 .
Fig. 4.51 : Voltage-divider bias configuration.

Zi : From Fig. 4.49 with RB = R',
Zi = R ¢ || h ie
Z0 : From Fig. 4.49,
Zo @ R C
Av :
h fe (R C ||1/ h oe )
Av = -
h ie
Ai :
h fe R ¢
Ai = -
R ¢ + h ie
4.17.3 Unbypassed Emitter-Bias Configuration

For the CE unbypassed emitter-bias
configuration of Fig. 4.52, the small-
signal ac model will be the same as re
model, with bre replaced by h ie and
b I b by h fe I b . The analysis will
proceed in the same manner.
Fig. 4.52 : CE unbypassed emitter-bias

configuration.
Zi :
Zb @ h fe R E
and Zi = R B || Zb
Z0 : Z0 = R C
h fe R C h R
Av : Av = - @ - fe C
Zb h fe R E
RC
and Av @ -
RE
h fe R B
Ai : Ai =
R B + Zb
Zi
or A i = -A v
RC
Emitter-Follower Configuration
For the emitter-follower of Fig. 4.53, the small-signal ac model will match be as re model
with b re = h ie and b = h fe .
Zi :
Zb @ h fe R E
Zi = R B || Zb
Fig. 4.53 : Emitter-follower configuration.

Z0 : For Z0,the output network defined by the resulting equations will appear as shown in
Fig. 4.54.
h ie
Z0 = R E ||
1 + h fe
or since 1 + h fe @ h fe ,
h ie
Z0 @ R E ||
h fe
Fig. 4.54 : Defining Z0, for the emitter-follower configuration.

Av : For the voltage gain, the voltage-divider rule can be applied to Fig. 4.54 as follows :
R E (Vi )
V0 =
R E + h ie /(1 + h fe )
but since 1 + h fe @ h fe ,
V0 RE
Av = @
+
Vi R E h ie / h fe
Ai :
h fe R B
Ai =
R B + Zb
Zi
or A i = -A v
RE
Common-Base Configuration
The last configuration to be
examined with the approximate
hybrid equivalent circuit will be
the common-base amplifier of
Fig. 4.55. Substituting the
approximate common-base
hybrid equivalent model will
result in the network of Fig.
Fig. 4.55 Common-base configuration.
4.56.
Fig. 4.56 : Substituting the approximate hybrid equivalent circuit into the ac
equivalent network of Fig. 4.55
From Fig. 4.56,
Zi : Zi = R E || h ib
Zo : Zo = R C
Av : Vo = - Io R C = -(h fb Ie )R C
Vi Vi
with Ie = and Vo = -h fb RC
h ib h ib
so that
V0 h R
Av = = - fb C
Vi h ib
Ai :
Io
Ai = = h fb @ -1
Ii
Example-4.16
For the common base network of figure given below :
(a) Determine Zi and Zo
(b) Calculate Av and Ai
(c) Determine a and b
h fb = -0.992
h ib = 9.45 W
h ob = 1mA / V
Fig. 4.57
Solution :
Substituting the approximate hybrid equivalent circuit :
Fig. 4.57 (a)

(a) Zi = R E || h ib
Given VEE = 4 V, VCC = 12 V, R C = 2.7 kW, R E = 1.2 kW
\ Zi = R E || h ib = (1.2 kW)||(9.45 W )
(1.2 kW) ´ (9.45 W)

Þ Zi = = 9.376 W = 9.38 W
1.20945 kW
Output impedance Zo = R C
or Zo = 2.7 kW
Vo h R
(b) Voltage gain Av = = - fb C
Vi h ib
(-0.992) ´ 2.7 kW
or Av = - = 283.43
9.45 W
and current gain A i = h fb = -0.992 » -1
(c) To determine a and b .
For common base configuration
Current gain is hfb is also called a
\ magnitude of a = 0.992
a
Also since b =
1- a
0.992 0.992
or b= = = 124
1 - 0.992 8 ´ 10-3
Example-4.17
For the fixed bias configuration of given figure :
(a) Determine AVNL, Zi and Zo.
(b) Sketch the two-port model with the parameters determined in part (a) in place.
(c) Calculate the gain Av using the model of part (b).
(d) Determine the current gain Ai.
(e) Determine Av, and Ai using the re model and compare the results above.
Fig. 4.58
Solution :
(a) D.C. analysis :
VCC - VBE 18 - 0.7
IB = = = 25.44 mA
RB 680 K
I E = (b + 1)I B = 101 ´ (25.44 mA) = 2.569 mA
26mV 26 mV
re = = = 10.12 W
IE 2.569 mA
RC 3.3 kW
A VNL = - =- = -326.087
re 10.12 W
Zi = R B || b re = 680 kW ||1.012 kW = 1.0105 kW
Zo = R C = 3.3 kW.
(b) Using the information above, the two-port equivalent can be drawn as follow :
Fig. 4.59
(c) From the above model :
RL
Vo = (A VNL ´ Vi ) ´
RL + Ro
RL 4.7 kW
Þ A v = R + R A VNL = 4.7 kW + 3.3 k W (-326.087) = -191.6
L o
Zi
(d) Ai = -A v
RL
1.0105 kW
A i = -(-191.6) ´ = 41.19
4.7 kW
(e) Substituting the re model will result in the network shown :
Note here that RL || RC
i.e. R ¢L = R L || R C = 4.7 kW || 3.3 kW
(4.7 k W) ´ (3.3 kW)

or R ¢L = = 1.9387 kW
8.0k W
Fig. 4.60
The output voltage

Vo = -b I B R ¢L
Vi V
with Ib = , and Vo = -b i ´ R ¢L
b re bre
Vo R¢ R || R L
So that Av = =- L =- C
Vi re re
Substituting values, we get
1.9387 kW
Av = - = -191.58 = -191.6
10.12 W
as obtained above,
For the current gain, by the current division rule
(680 kW) Ii (680 kW) ´ Ii
Ib = =
(680 kW) + 1.012 kW (681.012 kW)
or I b = 0.9985 Ii @ Ii ... (1)
3.3kW (b I b ) (3.3 kW)bI b
and Io = =
3.3 kW + 4.7 kW 8.0 kW
3.3
or Io = b I b = 0.4125 b Ib
8
Io 0.4125 b Ib 0.4125 b Ii
Now Ai = = = (from 1)
Ii Ii Ii
or Ai = 0.4125 (100)
= 41.25
The result matches with the value solved in part (d).
Example-4.18
For the voltage-divider configuration of Fig.4.61.
(a) Determine AVNL, Zi and Zo.
(b) Sketch the two-port model with
the parameters Determined in part
(a) in place.
(c) Calculate the gain Av using the
model of part (b).
Fig. 4.61
Solution :
(68 kW) ´ (16 kW)
R ¢ = R1 || R 2 = (68 kW) || (16 kW) =
84 kW
or R ¢ = 12.95 kW or R th = R ¢ = 12.95 kW
Vo R
A VNL = =- C
Vi re
The calculate re
R 2 VCC 16 kW ´ VCC 16 kW
E th = = = ´ 16 V = 3.048 V
R1 + R 2 68 kW + 16 kW 84 kW
E th - VBE 3.048 V - 0.7 V

Now IB = =
R th + (b + 1)R E 12.95 kW + 101 ´ 0.75 kW
or I B = 26.47 mA
Therefore I E = (b + 1)I B = 101(26.47 mA) = 2.67 mA
26mV 26 mV
Now re = = = 9.725 W
IE 2.67 mA
RC 2.2 kW
Now A VNL = - =- = -226.23
re 9.725 W
Input impedance Zi = R ¢ || b re = (12.95 kW)||(0.9725 kW)
or Zi = 0.904 kW @ b re
¥ Zi = 904.55 W
Output impedance Zo = R C = 2.2 kW
(b) The two-port model is shown below :
Fig. 4.62
(c) In the small-signal a.c. model RC and RL will be in parallel and thus, voltage gain :
R C || R L
Av =
re
R CR L 1 RL æ RC ö
or AV = - ´ = ç- ÷
R C + R L re R C + R L è re ø
RL 5.6 kW
or Av = A VNL = (-226.23)
RC + RL 2.2 kW + 5.6 kW
or A v = (0.718) (–226.23) = – 162.42
As was solved in the last problem, the values can be obtained by substituting the re
model as well.
This is an example of the circuit having only load resistance with voltage divider bias.
Q.1 What is the effect of source resistance on voltage gain of a common base transistor amplifier ?
Ans. The voltage gain of a CB transistor amplifier will decrease if source resistance is considered
because in such a case there will be a voltage drop across the source resistance and output
voltage will decrease.
Q.2 Explain what will happen to the voltage gain of an amplifier if the bypass capacitor is open-
circuited.
Ans. Removal of bypass capacitor causes excessive degeneration in the amplifier circuit i.e.
there is a voltage drop across RE and so the output is reduced. It means voltage gain will
reduce.
Q.3 Why common-collector circuit is known as an emitter follower ?
Ans. The CC circuit amplifier is culled an emitter follower because in this circuit the output
voltage at the emitter terminal follows the input signal applied to the base terminal.
Q.4 What are the main purposes for which a common-collector amplifier may be used ?
Ans. For a common collector amplifier, current gain is as high as for CE amplifier, voltage gain is
less than unity, input resistance is the highest and the output resistance is the lowest of all the
three (CE, CC and CB) configurations. This circuit finds wide application as a buffer
amplifier between a high impedance source and a low impedance load.
Q.5 What is an ac emitter resistance ?
Ans : The dynamic resistance of the emitter-base junction diode is called the ac emitter resistance.
26 mV
It is given as IE when IE is the dc emitter current at Q-point.
Q.6 What is the effect of removal of emitter bypass capacitor in a CE amplifier circuit ?
Ans : Removal of bypass capacitor in a CE amplifier circuit causes excessive degeneration in the
amplifier circuit and therefore reduction in voltage gain.
EXERCISE
1. The following test results were obtained in a CE amplifier circuit while measuring
h-parameters experimentally:
(i) W ith ac outputshorted Ib = 25 mA, Ic = 1.2 mA, Vbe - 30 mV and Vce = 0
(ii) With ac input open-circuited Ib = 0, Ie = 32 mA, Vbe = 0.3 mV and Vce = 1.2 V
Determine hybrid parameters of the given transistor.
[Ans. hie = 1.2 kW; hfe = 48; hre = 2.5 × 10–4; hoe = 25 mS]
2. Ifhie = 2 kW, hfe = 80, hre = 10–4 and hoe = l0–5 mho, RS = RL = 1 kW. Calculate (i) Ai (int),
(ii) Ai (ext), (iii) Av (int), (iv) Av (ext) and (v) Ri.
[Ans. (i) – 79.2, (ii) 26.5, (iii) 39.76, (iv) 26.47, (v) 1,992 W]
3. A BJT has the following h-parameters :
hie = 2,000 W; hre = 16 × 10–5; hfe = 49 and hoe = 50 mA/V.
amplifier if the load resistance is 30 kW. Neglect source resistance.
[Ans. Ai = – 19.6, Av = - 308.5; Zin = 1,906 W; Zout = 21.7 kW]
4. A BJT having hie = 1,500 W, hfe = 100, hre= 2 × 10–5 and hoe = 25 × 10–6 A/V is used as an
emitter follower amplifier with RS = 1,000 W and RL = 500 W. Determine for the amplifier
Vout V I
, A vs = o , Ais = o , R in and R out .
Vin Vs Is
[Ans. Av = 0.97, Avs, = 0.952, Ais = 1.9, Rin = 51.376 kW, Rout = 24.74 W]
5. A junction transistor has the following h-parameters:
hie = 2,000 W; hre = 1.6 × 10–4, hfe = 49, hoe = 50 mAV
amplifier if the load resistance is 30 kW and the source resistance is 600 W.
[Ans. –4.7, –235, 1906 W, 21.283 kW]
6. For the circuit shown, taking b = 200 and VBE = 0.6 V
(i) Find ICQ and VCEQ
(ii) Redraw the circuit in small signal form
using common emitter h-parameters
and assuming that the capacitance ac
short-circuits.
(iii) If hie = 11.4 kW; hre = 1.0 × 10–4 ;
hfe = 200 and hoe = 14.7 × 10 S, calculate
the voltage gain Av in the frequency
range where the capacitors are Fig. 4.63
assumed to be ac short-circuits.
ppp [Ans. 0.8 mA; 4.39 V; 98]
Small Signal Analysis of FET

5.1 INTRODUCTION
For small signal operation of FET, it is replaced by its equivalent model. It helps to calculate
the gain of the amplifier. FET has very high input impedance and comparatively low voltage
gain as compared to BJT. In case of FET, power consumption is very less. But in case of
FET, the current gain is infinite as input current = 0 Amp.
5.2 FET SMALL SIGNAL MODEL
In a FET, instantaneous drain current iD is a function of the instantaneous gate-source
voltage VGS and instantaneous drain-source voltage VDS and is therefore, expressed as
iD = f (vGS , VDS )
If both the gate and drain voltages are varied, the change in drain current is given
approximately by the first two terms in the Taylor’s series expansion,
d iD d iD
D iD = · D v GS + ·D v DS
d v GS VDS
d v DS VGS
Using the conventional small signal notations, DiD, DVGS and D vDS may be replaced
respectively by time varying components id , vgs and vds. Now,
1
i d = g m v gs + v ds
rd
d iD D iD id
where g m = ~ =
dv GS VDS
D v GS VDS
v gs
VDS
Small Signal Analysis of FET 157
Parameter gm is the mutual conductance, or transconductance
1 d iD D iD id
and r = dv ~
D v GS
=
v gs
d GS VDS VDS VDS
The reciprocal of rd is the drain conductance gd .

Circuit shown in fig. 5.1 shows drain current id in form of gm , rd , vgs and vds . This circuit
forms the low frequency small signal model for FET: This model consists of one dependent
current generator whose current gm vgs is proportional to the time varying gate source
voltage vgs and proportionality constant is the transconductance gm. Small signal model for
sinusoidal input voltage of rms value Vgs may be drawn, as shown in fig. 5.2 where vgs , id
, vds have been replaced respectively by rms values Vgs, Id and Vds.
GATE, G DRAIN Id
+D G
+D
id
rd v ds gmVgs rd Vds
Vgs Vgs
g mv gs
S
S
SOURCE, S S
Fig. 5.1 : Low Frequency Small Signal Fig. 5.2 : Low Frequency Small Signal Model
Model For FET For Sinusoidal Input of FET
5.3 COMPARISON OF LOW FREQUENCY MODELS OF FET AND BJT
1. Both FET and BJT models have a dependent current generator in the output circuit.
2. In FET models, the generator current is proportional to the input voltage Vgs while in
BJT models, the generator current is proportional to the input current.
3. In FET models input impedance is very high (theoretically infinite at low frequencies)
while in common emitter BJT model the input impedance is of the order of 800 W.
4. In FET, there is no feedback from output (drain) to the input (source) while in BJT
models it is. Thus it can be safely said that at low frequencies, FET forms a more ideal
amplifier than BJT amplifier.
5.4 JFET FIXED-BIAS CONFIGURATION
The fixed-bias configuration of
Fig. 5.3 includes the coupling
capacitors C1 and C2 that isolate the
dc biasing arrangement from the
applied signal and load; they act as
short-circuit equivalents for the ac
analysis.
Once the level of gm and rd are
determined from the dc biasing
Fig. 5.3 : JFET fixed-bias configuration.
arrangement, specification sheet, or characteristics, the ac equivalent model can be

substituted between the appropriate terminals as shown in Fig. 5.4. Note that both capacitors
have the short-circuit equivalent because the reactance XC = l/(2pfC) is sufficiently small
compared to other impedance levels of the network, and the dc batteries V GC and VDD are
set to zero volts by a short-circuit equivalent.
Fig. 5.4 : Substituting the JFET ac equivalent circuit unit into the network of Fig. 5.3.
Zi : Figure 5.5 clearly reveals that
Zi = R G
because of the open-circuit equivalence at the input terminals of the JFET.
Fig. 5.5 : Redrawn network of Fig. 5.4.

Z0: Setting V, = 0 V as required by the definition of Z0 will establish Vgs as 0 V also. The
result is gmVgs = 0 mA, and the current source can be replaced by an open-circuit equiva-
lent as shown in Fig. 5.6. The output impedance is
Zo = R D || rd
If the resistance rd is sufficiently large (at least 10:1) compared to RD, the approximation
rd||RD @ RD can often be applied and
Zo @ R D
rd ³10R D
Fig. 5.6 : Determining Z0.

Ai : Solving for V0 in Fig. 5.5, we find
but Vo = -g m Vgs (rd || R D )
and Vgs = Vi
so that Vo = -g m Vi (rd || R D )
Vo
Av = = -g m (rd || R D )
Vi
If rd > 10RD :
Vo
Av = = -g m R D
Vi
Phase Relationship: The negative sign in the resulting equation for Av clearly reveals a
phase shift of 180° between input and output voltages.
5.5 JFET SELF-BIAS CONFIGURATION
Bypassed Rs
The fixed-bias configuration has
the distinct disadvantage of requiring
two dc voltage sources. The self-bias
configuration of Fig. 5.7 requires only
one dc supply to establish the desired
operating point.
The capacitor C S across the

source resistance assumes its short-
circuit equivalence for dc, allowing Rs
to define the operating point. Under
ac conditions, the capacitor assumes Fig.5.7 : Self-bias JFET configuration.
the short-circuit state and “short
circuits” the effects of RS. If left in the ac, gain will be reduced as will be shown in the
paragraphs to follow.
The JFET equivalent circuit is established in Fig. 5.8 and carefully redrawn in Fig.5.9.
Zi :
Zi = R G
Fig. 5.8 : Network of Fig.5.7 following the substitute of the JFET ac equivalent circuit.
Fig. 5.9 : Redrawn network of Fig. 5.8

Zo :
Zo = rd || R D
If rd > 10RD,
Zo @ R D
rd ³10R D
Av : A v = -g m (rd || R D )
Phase relationship : The negative sign in the solutions of Av again indicates a phase shift
of 1800 between Vi and Vo .
Unbypassed RS
If CS is removed from Fig. 5.7, the resistor RS will be part of the ac equivalent circuit as
shown in Fig. 5.10.
Fig. 5.10 : Self-bais JFET configuration including the efforts of RS with rd = ¥W .

Initially, the resistance rd will be left out of the analysis to form a basis for comparison.
Zi : Due to the open-circuit condition between the gate and output network, the input
remains the following :
Zi = R G
Zo : The output impedance is defined by
Vo
Zo =
Io Vi = 0
Setting Vi = 0 V in Fig. 5.10 will result in the gate terminal being at ground potential
(0 V). The voltage across RG is then 0 V, and RG has been effectively “Shorted out” of the
picture.
Applying Kirchoff’s current law will result in
Io + ID = g m Vgs
with Vgs = -(Io + ID )R S

so that Io + I D = -g m (Io + I D )R S = -g m Io R S - g m I D R S
or I o [1 + g m R S -] = - I D [1 + g m R S ]
and Io = -I D (the controlled current source g m Vgs = 0 A
for the applied conditions)
Since Vo = - I D R D
then Vo = -(- Io )R D = Io R D
Vo
Zo = = RD
and Io
rd =¥W
If rd is included in the network, the equivalent will appear as shown in Fig. 5.11.
Fig. 5.11 : Including the effects of rd in the self-bias JFET configuration.
Vo ID R D
Since Zo = =-
Io Vi = 0 V
Io
we should try to find an expression for Io in terms of ID.

Applying Kirchhoff’s current law :
Io = g m Vgs + I rd - Id
but Vrd = Vo + Vgs
Vo + Vgs
and Io = g m Vgs + - ID
rd
æ 1ö I R
or Io = ç g m + ÷ Vgs - D D - I D using Vo = - I D R D
è rd ø rd
Now, Vgs = -(I D + Io )R S
æ 1ö I R
so that Io = - ç g m + ÷ (ID + Io )R S - D D - ID
è rd ø rd
é R ù é R R ù
with the result that Io ê1 + g m R s + S ú = -I D ê1 + g m R S + S + D ú
ë rd û ë rd rd û
é R R ù
-I D ê1 + g m R S + S + D ú
Io = ë rd rd û
or,
R
1 + gm RS + S
rd
Vo -ID R D
and Zo = =
Io æ R R ö
- ID ç1 + g m R S + S + D ÷
è rd rd ø
R
1 + gm RS + S
rd
é RS ù
ê1 + g m R S + ú
Zo = ë rd û
RD
and finally,
é RS R D ù
ê1 + g m R S + + ú
ë rd rd û
æ R ö R R R
For rd ³ 10R D , ç1 + g m R s + S ÷ >> D and 1 + g m R S + S + D
è rd ø rd rd rd
RS
@ 1 + gm RS + and
rd
Zo = R D
rd ³10R D
Av : For the network of Fig. 5.11, an application of Kirchhoff’s voltage law on the input
circuit will result in
Vi - Vgs - VR s = 0
Vgs = Vi - ID R S
The voltage across rd using Kirchoff’s voltage law is
Vo - VR S
Vo - VR S
and I¢ =
rd
so that an application of Krichhoff’s current law will result in
Vo - VRS
I D = g m Vgs +
rd
Substituting for Vgs from above and substituting for Vo and VR S we have
(-I D R D ) - (ID R S )
I D = g m [ Vi - ID R S ] +
rd
é R + RS ù
so that I D ê1 + g m R S + D ú = g m Vi
ë rd û
g m Vi
or ID =
R + RS
1 + gm R S + D
rd
The output voltage is then
g m R D Vi
Vo = - ID R D = -
R + RS
1 + gmRS + D
rd
Vo gm R D
Av = =-
Vi R + RS
and 1 + gm R S + D
rd
Again if rd ³ 10(R D + R S ),
Vo g R
Av = =- m D
Vi 1 + gm RS
rd ³10(R D + R S )
Phase Relationship : The negative sign reveals that a 1800 phase shift will exist between
Vi and Vo.
5.6 JFET VOLTAGE-DIVIDER CONFIGURATION
Fig.5.12 : JFET voltage-divider configuration.

Substituting the ac equivalent model for the JFET will result in the configuration of
Fig.5.13.Replacingthedcsupply V DD by a short-circuit equivalent has grounded one end
of R1 and RD. Since each network has a common ground, R1 can be brought down in
parallel with R2 as shown in Fig.5.14. RD can also be brought down to ground but in the
output circuit across rd. The resulting ac equivalent network now has the basic format of
some of the networks already analyzed.
Fig.5.13 : Network of Fig. 5.12 Fig.5.14 : Redrawn network

under ac conditions. of Fig. 5.13.
Zi : R1 and R2 are in parallel with the open-circuit equivalence of the JFET resulting in
Zi = R1 || R 2
Zo : Setting Vi = 0 V will set Vgs and gmVgs to zero and
Zo = rd || R D
For rd > 10RD,
zo @ R D
rd ³10R D
Av : Vgs = Vi
and Vo = -g m Vgs (rd || R D )
Vo -g m Vgs (rd || R D )
so that Av = =
Vi Vgs
Vo
and Av = = -g m (rd || R D )
Vi
If rd ³ 10R D ,
Vo
Av = @ -g m R D
Vi
rd ³10R D
5.7 JFET SOURCE-FOLLOWER (COMMON-DRAIN) CONFIGURATION

The output is taken off the source terminal and, when the dc supply is replaced by its short-
circuit equivalent, the drain is grounded (hence, the terminology common-drain).
Fig. 5.15 : JFET source-follower configuration.
G D
Substituting the JFET equivalent circuit
+
will result in the configuration of
Fig. 5.16. The controlled source and
internal output impedance of the JFET
_
are tied to ground at one end and RS on
S
the other, with Vo across RS. Since
gmVgs, rd, and RS are connected to the
same terminal and ground, they can all
be placed in parallel as shown in Fig.
5.17. The current source reversed
direction but Vgs is still defined between Fig. 5.16 : Network of Fig. 5.15
the gate and source terminals. following the substitution of the JFET ac
equivalent model.
Fig. 5.17 : Network of Fig. 5.16 redrawn.

Zi : Figure 5.17 clearly reveals that Zi is defined by
Zi = R G
Zo : Setting Vi = 0 V will result in the gate terminal being connected directly to ground as
shown in Fig. 5.18.
Fig. 5.18 : Determining Zo for the network of Fig.5.15

The fact that Vgs and Vo are across the same parallel network results in Vo = – Vgs.
Applying Kirchhoff’s current law at node S,
Io + g m Vgs = I rd + IR S
Vo Vo
= +
rd R S
é1 1 ù
The result is Io = Vo ê + ú - g m Vgs
ë rd R S û
é1 1 ù
= Vo ê + ú - g m [ - Vo ]
ë rd R S û
é1 1 ù
= Vo ê + + gm ú
ë rd R S û
Vo Vo 1 1
and Zo = = = =
Io é1 1 ù 1
+
1
+ gm
1
+
1
+
1
Vo ê + + gm ú
rd R S rd R S 1/ g m
ë rd R S û
which has the same format as the total resistance of three parallel resistors. Therefore,
Zo = rd || R S ||1/ g m
For rd ³ 10R S ,
Zo @ R S ||1/ g m
rd ³10R S
Av : The output voltage Vo is determined by

and applying Kirchhoff’s voltage law around the perimeter of the network of Fig. 5.17 will
result in
Vi = Vgs + Vo
and Vgs = Vi - Vo
so that Vo = g m (Vi - Vo )(rd || R S )
or Vo = g m Vi (rd || R S ) - g m Vo (rd || R S )
and Vo [1 + g m (rd || R S )] = g m Vi (rd || R S )
Vo g (r || R S )
so that Av = = m d
Vi 1 + g m (rd || R S )
In the absence of rd or if rd > 10 RS,
Vo g R
Av = @ m S
Vi 1 + g m R S
rd ³10R S
Phase Relationship : Since Av is a positive quantity, Vo and Vi are in phase for the JFET
source-follower configuration.
5.8 JFET COMMON-GATE CONFIGURATION
Substituting the JFET equivalent circuit will result in Fig. 5.20. Note the continuing
requirement that the controlled source gmVgs be connected from drain to source with rd in
parallel. The isolation between input and output circuits has obviously been lost since the
gate terminal is now connected to the common ground of the network. In addition, the
resistor connected between input terminals is no longer RG but the resistor RS connected
from source to ground.
Fig. 5.19 : JFET common-gate configuration
Fig. 5.20 : Network of Fig. 5.19 following substitution of JFET ac equivalent model.
Zi : The resistor RS is directly across the terminals defining Zi. Let us therefore find the
impedance Z¢i of Fig. 5.19, which will simply be in parallel with RS when Zi is defined.
The network ofinterestis redrawn as Fig.5.21.The voltage V ' = – Vgs. Applying
Kirchhoff’s voltage law around the output perimeter of the network will result in
V¢ - Vrd - VR D = 0
and Vrd = V¢ - VR D = V¢ - I¢R D
Fig. 5.21 : Determining Z¢i for the network of Fig. 5.19

Applying Kirchhoff’s current law at node a result in
I¢ + g m Vgs = Ird
(V¢ - I¢R D )
and I¢ = Ird - g m Vgs = - g m Vgs
rd
V¢ I¢R D
or I¢ = - - g m [ - V¢ ]
rd rd
é R ù é1 ù
so that I¢ ê1 + D ú = V¢ ê + g m ú
ë rd û ë rd û
é RD ù
ê1 + ú
V¢ ë rd û
Z¢i = =
and I¢ é 1ù
êg m + ú
ë rd û
V¢ rd + R D
or Z¢i = =
I¢ 1 + g m rd
and Zi = R S || Z¢i
é r + RD ù
result in Zi = R S || ê d ú
ë 1 + g m rd û
If rd > 10RD, then RD/rd << 1 and 1/rd << gm :
é RD ù
ê1 + ú
Z¢i = ë
rd û 1
@
é 1 ù gm
êg m + ú
ë rd û
and Zi @ R S ||1/ g m
rd ³10R D
Zo : Substituting Vi = 0 V in Fig 5.20 will “short-out” the effects of RS and set Vgs to 0 V.
The result is gmVgs = 0, and rd will be in parallel with RD. Therefore,
Zo = R D || rd
For rd > 10RD,
Zo @ R D
rd ³10R D
Av : Figure 5.20 reveals that

Vi = – Vgs
and Vo = IDRD
the voltage across rd is
Vrd = Vo - Vi
Vo - Vi
and I rd =
rd
Applying Kirchhoff’s current law at node b in Fig. 5.20 Results is
I rd + ID + g m Vgs = 0
and I D = -I rd - g m Vgs
é V - Vi ù
= -ê o ú - g m [ -Vi ]
ë rd û
Vi - Vo
ID = + g m Vi
rd
é V - Vo ù
so that Vo = ID R D = ê i + g m Vi ú R D
ë rd û
Vi R D Vo R D
= = + gm
rd rd
é R ù éR ù
and Vo ê1 + D ú = Vi ê D + g m R D ú
ë rd û ë rd û
é RD ù
êg m R D + ú
Av = o = ë
V rd û
with Vi é RD ù
ê1 + ú
ë rd û
For rd ³ 10R D , the factor RD/rd can be dropped as a good approximation and
Av = gmR D
rd ³10R D
Phase Relationship : The fact that Av is a positive number will result in an inphase
relationship between Vo and Vi for the common-gate configuration.
5.9 DEPLETION-TYPE MOSFETs
The fact that Shockley’s equation is also applicable to depletion-type MOSFETs results
in the same equation for gm. In fact, the ac equivalent model for D-MOSFETs is exactly
the same as that employed for JFETs as shown in Fig. 5.22.
The only difference offered by D-MOSFETs is that VGSQ can be positive for n-
channel devices and negative for p-channel units. The result is that gm can be greater than
gm0 as demonstrated by the example to follow. The range of rd is very similar to that
encountered for JFETs.
Fig. 5.22 : D-MOSFET ac equivalent model.

5.10 ENHANCEMENT-TYPE MOSFETS
The enhancement-type MOSFET can be either an n-channel (nMOS) or p-channel (pMOS)
device, as shown in Fig. 5.23. The ac small-signal equivalent circuit of either device is
shown in Fig. 5.23, revealing an open-circuit between gate and drain-source channel and a
current source from drain to source having a magnitude dependent on the gate-to-source
voltage. There is an output impedance from drain to source rd, which is usually provided on
specification sheets as an admittance yos. The device transconductance, gm, is provided on
specification sheets as the forward transfer admittance, yfs.
In our analysis of JFETs, an equation for gm was derived from Shockeley’s equation.
Fig. 5.23 : Enhancement MOSFET ac small-signal model.

For E-MOSFETs, the relationship between output current and controlling voltage is defined
by
I D = k(VGS - VGS(Tb) ) 2
Since gm is still defined by
DI D
gm =
DVGS
we can take the derivative of the transfer equation to determine gm as an operating point.
That is,
dID d d
gm = = k(VGS - VGS(Th) )2 = k (VGS - VGS(Th) )2
dVGS dVGS dVGS
d
= 2k(VGS - VGS(Th) ) (VGS - VGS(Th) ) = 2k(VGS - VGS(Th) )(1 - 0)
dVGS
and g m = 2k(VGS - VGS(Th) )
Example-5.1
Determine Z i , Z o , A v for the
unbypassed source resistance shown
in figure yfs = 3 ms, fos = ms :
Fig. 5.24
Solution : The a.c. equivalent diagram is drawn below :

1 1
rd = = = 20 kW
yos 50 ´ 10-6
g m = yfs = 3ms = 3 ´ 10-3 s
Fig. 5.24(a)
The input impedance of the self-bias, JFET configuration is given
Z i = 10 MW
The output impedance of the configuration
é Rs ù
ê1 + g m R s + ú
Zo = ë rd û
´ RD
é RS R D ù
ê1 + g m R s + + ú
ë rd rd û
Here g m = 3 ´ 10-3 s, R s = 1.1 kW

R D = 3.3 kW, rd = 20 kW
é
( -3
)1.1 ù
êë1 + 3 ´ 10 ´ 1.1 ´ 10 + 20 úû ´ 3.3K
3
Zo =
é -3 1.1 3.3 ù
êë1 + (3 ´ 10 ´ 1.1 ´ 10 ) + 20 + 20 úû
3
Zo =
[1 + 3.3 + 0.055] ´ 3.3 K
Þ
[1 + 3.3 + 0.55 + 0.165]
4.355
Þ Zw = ´ 3.3K Þ Zo = 3.179 kW
4.52
We get, the formula of output impedance is given by appearing Kirchoff’s law

Io = g m Vgs + I rd - I D
Vrd = Vo + Vgs
Vo + Vgs
Þ Io = g m Vgs + - ID
rd
Now Vgs = -(I D + Io )R S
æ 1ö I R
Io = - ç g m + ÷ (ID + Io )R S - D D - ID
è rd ø rd
é R R ù
-I D ê1 + g m R S + S + D ú
Io = ë rd rd û
æ RS ö
ç1 + g m R S + ÷
è rd ø
Vo -I D R D
Now Zo = =
Io Io
Put the values of the desired component, get the output impedance, Zo. The voltage gain is
given by
VO -g m R D
Þ Av = =
V1 1 + g R + R D + R S
m s
rd
3 ´ 10-3 ´ 3.3 ´ 103

Þ Av = -
(3.3 + 1.1)K
1 + (3 ´ 10-3 ´ 1.1 ´ 103 ) +
20K
-9.9 -9.9
= = = 2.19
æ 4.4 ö 4.3 + 0.22
1 + 3.3 + ç ÷
è 20 ø
Example-5.2
Determine Zi, Zo and V o for the
network shown in Fig. 5.25, if
Vi = 20 mV.
IDSS = 12 mA, VP = –3 V, rd = 100 kW,

VGSQ = 0.925 V
Fig.5.25
Solution : The a.c. equivalence of the above network is drawn below :
Fig. 5.25 (a)

The input impedance, Zi is given as
82 ´ 11
Zi = (82 MW)||(|| MW) = MW
82 + 11
= 9.699 MW = 9.7 MW
The output impedance Zo = (100 kW)|| (2 kW)
100 ´ 2
Þ Zo = Þ Zo = 1.96 kW
100 + 2
Vo -g m Vgs ´ Zo -g m Zo Vi
Voltage gain Av = = =
Vi Vi Vi
Þ A v = -g m Zo
2 IDSS 2 ´ 12
Now g mo = = = 8ms
VP 3
æ V ö æ 1 - (-0.9525) ö
g m = g mo ç1 - GSQ ÷ = 8 ´ 10-3 ç ÷
è VP ø è (-3) ø
= 5.46 ms
The voltage gain A v = -g m Zo = -5.46 ´ 10-3 ´ 1.96 ´ 103 = -10.701
Therefore, output voltage
Vo = A v ´ Vi = -10.701 ´ 20 = -214.03 mV
Example-5.3
For a JFET voltage divider configuration determine Zo, Zi and Vo, if Vi = 20 mV and
rd = 20 kW, IDSS = 12 mA, VP = –3 V, VGSQ = – 0.9525 V.
Fig. 5.26
Solution :
The a.c. equivalent of the JFET voltage divider configuration is drawn below :
Fig. 5.26 (a)

The input impedance
Zi = (82 MW)||(11 MW)
82 ´ 11
= = 9.7 MW
82 + 11
The output impedance
20 ´ 2
Zo = (20 kW) || (2 kW) = kW
22
= 1.818kW = 1.82 kW
Vo -g m Vgs (rd || R D )
Voltage gain Av = =
Vi Vgs
Þ A v = -g m Zo
Þ A v = -g m ´ 1.82 ´ 103
Now, to calculate gm, we have

2 IDSS 2 ´ 12
g mo = = = 8 ms
Vp 3
æ V ö
So g m = g mo ç1 - GSQ ÷
è VP ø
æ ( -0.9525) ö
= 8 ´ 10-3 ç 1 - ÷ = 5.46 ms
è (-3) ø
The voltage gain A v = -g m ´ 1.82 ´ 103

= -5.46 ´ 10-3 ´ 1.82 ´ 103 = -9.937
Therefore Vo = A v ´ Vi = -9.937 ´ 20 ´ 10-3 = -198.74 mV.
Example-5.4
For a JFET source follower configuration calculate Zi, Zo and Av :
Given IDSS = 9 mA VP = –4.5 V
rd = 40 kW VGQ = –2.818 V
Fig. 5.27
Solution :
For the JFET source followers configuration the small signal model is drawn below by
having capacitors short-circuit equivalent. The JFET source follower is a common drain
configuration from the figure, we have the input impedance.
Zi = 10 MW
The output impedance is given by
Zo = rd || 2.2 kW ||(1/ g m )
Fig. 5. 27 (a)
Now rd = 40 kW
2I DSS 2 ´ 9 ´ 10-3
g mo = = = 4ms
Vp 4.5
æ V ö æ (2.818) ö
Now g m = g mo ç1 - GSQ ÷ = 4 ´ 10-3 ç1 - ÷
è VP ø è (-4.5) ø
= 4 ´ 10-3 (1 - 0.6262) = 1.459 ´ 10-3 s = 1.495 ms

Zo = 40 kW || 2.2 kW || 668.8 W
Þ Zo-1 = (40 ´ 103 ) -1 + (2200) -1 + (668.8-1 )
Þ Zo-1 = 1.9747 ms
1
Þ Zo = = 0.506 kW = 506 W
1.9747
Thus, the output impedance
Zo = 506 W
The voltage gain is given by
Vo g (r || R s )
Av = = m d
Vi 1 + g m (rd || R s )
Now rd || R s = 40 kW || 2.2 kW = 2.085 kW
Vo 1.495 ´ 10-3 ´ 2.085 ´ 103

Av = =
Vi 1 + (1.495 ´ 10-3 ´ 2.085 ´ 103 )
3.0075 3.1175
= = = 0.7571
1 + 3.1175 4.1175
Example-5.5
Determine Zi, Zo and Av for the network
JFET. Fixed biased configuration, if
IDSS = 12 mA, VP = –6 V and yos = 40 ms :
Fig. 5.28
Solution :
The small signal model of the above configurations is drawn below :
Fig. 5.28 (a)

From the figure, we have
Input impedance Zi = 1 MW
2 IDSS 2 ´ 12 ´ 10-3
g mo = = = 4ms
Vp 6
æ V ö
Now g m = g mo = ç1 - GSQ ÷ (Here, VGSQ = –1.5 from figure)
è VP ø
æ (-1.5) ö
Þ g m = 4 ´ 10-3 ç 1 - ÷
è (-6) ø
æ 1ö
Þ g m = 4 ´ 10-3 ç1 - ÷
è 4ø
Þ gm = 3 ms
The output impedance Zo = rd || R D
Þ Zo = 40 kW ||1.8 kW
1 1
Here rd = = = 40 kW
y os 24 ms
40 ´ 1.8
Þ Zo =
40 + 1.8
Þ Zo = 1.722 kW
The output voltage = Vo = -(rd || R D )g m Vgs
Vo
Þ = -(rd || R d )g m
Vgs
Vo
Þ Av = = - Zo g m
Vgs
Hence, the voltage gain
Av = –Zogm
Þ A v = -1.722 ´ 103 ´ 3 ´ 10-3
Þ Av = –5.1675
Thus, we have Zi = 1 mW, Zo = 1.722 kW
Av = –5.168
Example-5.6
For the network of JFET common gate configuration determine : (a) input impedance
Zi, (b) output impedance Zo, (c) output voltage Vo
If Vi = 10–4V rd = 25 kW
IDSS = 8 mA, VP = –2.8 V, VgsQ = – 1.75 V
Fig. 5.29
Solution : rd = 25 kW
2 I DSS 2 ´ 8 ´ 10-3
g mo = =
VP 2.8
Þ g mo = 5.71 ms
æ V ö
g m = g mo ç1 - GSQ ÷
è VP ø
æ (-1.75) ö
= 5.71 ´ 10-3 ç1 - ÷
è (-2.8) ø
= 2.14 ´ 10-3 = 2.14 ms

The small signal model configuration is drawn below :
Fig. 5.29(a)
æ r + RD ö
The input impedance Zi = R s || ç d ÷
è 1 + g m rd ø
rd + R D (35 + 3.3) kW
Now =
1 + g m rd 1 + 2.14 ´ 10-3 ´ 25 ´ 103
28.3
= kW = 0.5192 kW
54.3
Now Zi = 1.5 kW || 0.5192 kW
1.5 ´ 0.5192
= kW = 0.38569 kW = 385.7 W
1.5 + 0.5192
25 ´ 3.3
The output impedance Zo = rd || R D = 25 || 3.3 = kW = 2.915kW
28.3
é RD ù
êg m R D + ú
Av = ë
rd û
The voltage gain
é RD ù
ê1 + r ú
ë d û
é -3 3.3 ù
êë 2.14 ´ 10 ´ 3.3 ´ 10 + 25 úû
3
Av =
Þ é 3.3 ù
êë1 + 25 úû
Av =
[7.062 + 0.132] = 6.355
Þ [1 + 0.132]
Vo
The voltage gain Av =
Vi
The output voltage
Vo = A v ´ Vi = 6.355 ´ 10.1 ´ 10-3 = 0.6355mV
Thus, we have Zi = 385.7 W
Zo = 2.915 kW
Vo = 0.6355 mV
Example-5.7
For the depletion type MOSFET, determine the output voltage, if yos = 20 ms:
Fig. 5.30
IDSS = 8 mA, VP = –3 V, Vgs = +1 mV
Solution :
1 1 1000 ´ 103
rd = = = = 50kW
yos 20 ´ 10-6 20
2 I DSS 2 ´ 8 ´ 10-3
g mo = = = 5.33 ms
VP 3
Vgs 0.001
g m = g mo 1 - = 5.33 ´ 10-31 -
VP -3
= 5.33 ´ 10-3 (1.000333) = 5.3318 ms

The input impedance Zo = 10 MW.
Fig. 5.30(a)
The input impedance
Zo = rd || R D = 50 kW || 1.1 kW
50 ´ 1.1
= kW = 1.076 kW
51.1
The voltage gain A v = -g m (rd || R D )
Vo
Þ = - g m Zo
Vi
Þ Vo = -g m Zo Vi
Þ Vo = -5.33 ´ 10-3 ´ 1.076 ´ 103 ´ 2 ´ 10-3
Þ Vo = –11.473 mV
Another method of approximation can be used since
rd = 10R d ³ 50 kW > 1.1´ 10 kW
50 kW > 11 kW
A v = -g m R D
= -5.33 ´ 10-3 ´ 1.1 ´ 103 = -5.863
Output voltage Vo = A v ´ Vi = -5.863 ´ 2 ´ 10-3 = -11.726 mV
Example-5.8
Choose the values of RD and Rs for the network shown in Fig. 5.31, that will result in
1
a gain of 8 using relatively high of gm for this device defined at VGS = VP .
4
IDSS = 10 mA VP = 4V
yos = 20 ms gmo = 5 ms
Fig. 5.31
Solution :
2I DSS 2 ´ 10
g mo = = = 5 ms
VP 4
1 1 1000 ´ 103
rd = = = = 50 kW
y os 20 ´ 10-6 20
2
æ V ö
I D = IDSS ç 1 - GSQ ÷
è VP ø
2
æ 1ö 9
= 10 ´ 10-3 ç 1 - ÷ = ´ 10 ´ 10-3 = 5.625 mA
è 4 ø 16
æ V ö æ 1ö
g m = g mo ç1 - GSQ ÷ = 5ms ç1 - ÷
è VP ø è 4ø
The magnitude of A v = g m (R D || rd )
Þ 8 = 3.75 × 10–3 (RD || rd)
Þ R D || rd = 2.13 kW
Þ R D || 50 kW = 2.13 kW
R D || 40 kW = 2.13kW
1 1
Þ RD = VGSQ = VP
-(50) + (2.13)-1
-1
4
1
Þ R D = 2.2 kW (´4) = -1V
4
The value of Rs is determined by the d.c. operating condition as follows :

VGSQ = -I D R s
Þ –1 = (5.625 mA) Rs
Þ R s = 177.8 W
The closest standard value of R s = 180 W.
EXERCISE
1. Write shockley’s equation. How is it used to design d.c. biasing of JFET ?

2. Write shockley’s equation applied to JFET device. Using it derive an expression for gm .
3. Draw the transfer characteristics of an n-channel enhancement type MOSFET. For a self
bias arrangement show how to determine the Q-point graphically.
4. Draw the low frequency small-signal FET model with proper Labels. How this model
differs from its high frequency counterpart ?
5. Calculate g m for a JFET having device parameters IDSS = 10mA and VP = -6V.
0
6. Calculate gm for a JFET (IDSS = 15mA, VP = –5V) at a bias point of VGS = –2V .
7. For a JFET having gm = 3.36ms at VGSQ = – 25V, what is the value of IDSS if VP = –4V ?
8. Draw JFET self bias configurations and find Zi, Z0, AV in
(i) Bypassed RS and (ii) Unbypassed RS
9. Sketch properly the JFET common gate configuration and hence find Zi, ZO, AV and the
phase relationship between the output voltage and input voltage
10. In JFET voltage divider bias configuration, given VDD = 20V, R1 = 80MW, R2 = 10MW
RD = 2KW, Rs=510kW, IDSS = 10mA, VP = –4V, rd= 50kW. Find (i) Zi (ii) z0 (iii) AV (iv) V0
if Vi = 25mV
11. In JFET source follower VDD = 20V, RG = 1 MW RS = 2.2kW, IDSS = 9mA , VP = –4V,
rd =40kW. Determine Zi, Z0 and AV .
ppp
System Approach, Effect of RS & RL

6.1 TWO-PORT SYSTEMS
The description to follow can be applied to any two-port system—not only those
containing BJTs and FETs—although the emphasis in this chapter is on these active devices.
The emphasis in previous chapters on determining the two-port parameters for various
configurations will be quite helpful in the analysis to follow. In fact, many of the results
obtained in the last two chapters are utilized in the analysis to follow.
In Fig. 6.1, the important parameters of a two-port system have been identified. Note
in particular the absence of a load and a source resistance. The impact of these important
elements is considered in detail in a later section. For the moment recognize that the
impedance levels and the gains of Fig. 6.1 are determined for no-load (absence of RL) and
no-source resistance (Rs) conditions.
If we take a “Thevenin look” at the output terminals we find with Vi set to zero that
ZTh = Zo = R o
Fig. 6.1 : Two-port system.

ETh is the open-circuit voltage between the output terminals identified as V0. However,
Vo
A VNL =
Vi
System Approach, Effect of RS & RL 187
and Vo = A v NL Vi
so that E Th = A vNL Vi
Note the use of the additional subscript notation “NL” to identify a no-load voltage gain.
Substituting the Thivenin equivalent circuit between the output terminals will result in
the output configuration of Fig. 6.2. For the input circuit the parameters Vi and Ii are
related by Zi = Ri, permitting the use of Ri to represent the input circuit. Since our present
interest is in BJT and FET amplifiers, both Z0 and Zi can be represented by resistive
elements.
Fig. 6.2 : Substituting the internal elements for the two-port system of Fig. 6.1.
6.2 EFFECT OF A LOAD IMPEDANCE (RL)
In this section, the effect of an applied load is investigated using the two-port model of
Fig. 6.2. The model can be applied to any current- or voltage-controlled amplifier. A v NL is,
as defined earlier, the gain of the system without an applied load. Ri and R0 are the input
and output impedances of the amplifier as defined by the configuration. Ideally, all the
parameters of the model are unaffected by changing loads or source resistances
Applying a load to the two-port system of Fig. 6.2 will result in the configuration of
Fig. 6.3. Applying the voltage-divider rule to the output circuit will result in
R L A v NL Vi
Vo =
RL + Ro
Vo RL
and Av = = Av
Vi R L + R o NL
Fig. 6.3 : Applying a load to the two-port system of Fig. 6.2.

Since the ratio RL/(RL + R0) will always be less than 1:

The loaded voltage gain of an amplifier is always less than the no-load level.
Note also that the formula for the voltage gain does not include the input impedance or
current gain.
Although the level of R, may change with the configuration, the applied voltage and
input current will always be related by
Vi Vi
Ii = =
Zi R i
Defining the output current as the current through the load will result in
Vo
Io =
RL
with the minus sign occurring due to the defined direction for I0 in Fig. 6.3. The current
gain is then determined by
Io -Vo / R L V Z
Ai = = =- o i
Ii Vi / Zi Vi R L
Zi
and A i = -A v
RL
Example-6.1
In Fig. 6.4, a load has been applied to the fixed-bias transistor amplifier.
(a) Determine the voltage and current gain using the two-port systems approach.
(b) Determine the voltage and current gain using the re model and compare results.
Fig. 6.4 : Example 6.1

Solution : (a) Here Zi = 1.071 kW (with re = 10.71W and b = 100)
Z0 = 3 kW
A v NL = -280.11
RL
Av = Av
R L + R o NL
2.2 kW
= (-280.11)
2.2 kW + 3kW
= (0.423)(–280.11)
= –118.5
For the current gain,
Zi
Ai = -A v
RL
In this case, Z, is unaffected by the applied load and
1.071kW
Ai = -( -118.5) = 57.69
2.2 kW
(b) Substituting the re model will result in the network of Fig. 6.5. Note in particular that
the applied load is in parallel with the collector resistor RC defining a net parallel
resistance
R ¢L = R C || R L = 3kW || 2.2 kW = 1.269 kW
The output voltage
Vo = -bI B R ¢L
Fig. 6.5 : Substituting the re model in the ac equivalent network of Fig. 6.4.
Vi
with Ib =
bre
Vi
and Vo = -b R ¢L
bre
Vo R¢ R || R L
so that Av = =- L =- C
Vi re re
Substituting values gives

1.269 kW
Av = - = – 118.5
10.71 W
as obtained above. For the current gain, by the current-divider rule,
(470 kW)Ii
Ib = = 0.9977Ii @ Ii
470 kW + 1.071kW
3kW(bIb )
and Io =
3kW + 2.2 kW
= 0.5769bIb
Io 0.5769 bIb 0.5769bIi
so that Ai = = =
Ii Ii Ii
= 0.5769(100) = 57.69
For a particular design, the smaller the level of RL, the lower the level of ac voltage gain.
6.3 EFFECT OF THE SOURCE IMPEDANCE (Rs)
In Fig. 6.6, a source with an internal resistance has been applied to the basic two-port
system .ThedefinitionsofZi and A v NL are such that:
The parameters Zi and A v NL of a two-port system are unaffected by the internal

resistance of the applied source.
Fig. 6.6 : Including the effects of the source resistance Rs.

However:
The output impedance may be affected by the magnitude of Rs.
The fraction of the applied signal reaching the input terminals of the amplifier of
Fig.6.6 is determined by the voltage-divider rule. That is,
R i Vs
Vi =
Ri + Rs
It clearly shows that the larger the magnitude of Rs, the less the voltage at the input
terminals of the amplifier. In general, therefore:
For a particular amplifier, the larger the internal resistance of a signal source
the less the overall gain of the system.
For the two-port system of Fig. 6.6,
Vo = A v NL Vi
R i Vs
and Vi =
Ri + Rs
Ri
so that Vo = A v NL Vi = Vs
Ri + Rs
Vo Ri
and A vs = = Av
Vs R i + R s NL
If Rs = 0 W (ideal voltage source), A vs = A v NL , which is the maximum possible value.

The source current:
Vs
I s = Ii =
Rs + Ri
Example-6.2
In Fig. 6.7, a source with an internal resistance has been applied to the fixed-bias
transistor amplifier
(a) Determine the voltage gain A vs = V0/Vs. What percent of the applied signal
appears at the input terminals of the amplifier?
(b) Determine the voltage gain A vs = V0/Vs using the re model.
Fig. 6.7 : Example 6.2.

Solution : (a) The two-port equivalent for the network appears in Fig. 6.8.
Fig. 6.8 : Substituting the two-port equivalent network for the fixed-bias
transistor amplifier of Fig. 6.7.
Vo Ri 1.071 kW
A vs = = A v NL = ( -280.11)
Vs R i + R s 1.071kW + 0.5kW
= (0.6817)(–280.11)
= –190.96
R i Vs (1.071kW)Vs
Vi = = = 0.6817 Vs
R i + R s 1.071kW + 0.5kW
or 68.2% of the available signal reached the amplifier and 31.8% was lost across the
internal resistance of the source.
(b) Substituting the re model will result in the equivalent circuit of Fig. 6.9. Solving for V0
gives
Vo = -(100I b )3kW
Vs Vs
with Zi @ bre and Ib @ Ii = =
R s + bre 1.571 kW
æ Vs ö
and Vo = -100 ç ÷ 3kW
è 1.571 kW ø
Vo (100)(3 kW)
so that A vs = =-
Vs 1.57 kW
as above.
Fig. 6.9 : Substituting the re equivalent circuit for the fixed-bias transistor amplifier of Fig. 6.7.
6.4 COMBINED EFFECT OF Rs AND RL

In Fig. 6.10, a source with an internal resistance Rs and a load RL have been applied to
atwo-portsystem forwhich theparam eters Zi , A v NL , and Z0 have been specified. For the
moment, let us assume that Zi and Z0 are unaffected by RL and Rs, respectively.
Fig. 6.10 : Considering the effects of Rs and RL on the gain of an amplifier.

At the input side we find
R i Vs
Vi =
Ri + Rs
Vi Ri
or =
Vs R i + R s
and at the output side,

R L A v NL Vi
Vo =
RL + Ro
Vo R L A vNL
or Av = =
Vi R L + R o
For the total gain A vs = Vo / Vs , the following mathematical steps can be performed:
Vo Vo Vi
A vs = =
Vs Vi Vs
Vo Vo
and substituting V & V ,
i s
R L A v NLRi
A vs =
RL + Ro Ri + Rs
Vo Ri RL
and A vs = = Av
Vs R i + R s R L + R o NL
Since Ii = Vi / R i , as before,
Ri
A i = -A v
RL
or using Is = Vs /(R s + R i ) ,
Rs + Ri
A is = - A vs
RL
The larger the source resistance and/or smaller the load resistance, the less the
overall gain of an amplifier.
Example-6.3
For the single-stage amplifier of Fig. 6.11, with RL = 4.7 kW and Rs = 0.3 kW, determine:
(a) A vs .
(b) Av = Vo/Vi
(c) A i .
The two-port parameters for the fixed-bias configuration are Zi = 1.071 kW, Zo = 3 kW,
and A v NL = – 280.11.

Solution :
Vo Ri RL
(a) A vs = = Av
Vs R i + R s R L + R o NL
æ 1.071 kW öæ 4.7 kW ö
=ç ÷ç ÷ (-280.11)
è 1.071kW + 0.3 kW øè 4.7 kW + 3kW ø
= (0.7812)(0.6104)(–280.11)
= (0.4768)(–280.11)
= –133.57
Vo R L A v NL (4.7 kW)(-280.11)
(b) A v = = =
Vi R L + R o 4.7 kW + 3kW
= (0.6104)(–280.11) = – 170.98
Ri æ 1.071 kW ö
(c) Ai = -A v = -(-170.98) ç ÷
RL è 4.7 kW ø
= 38.96
Rs + Ri æ 0.3 kW + 1.071 kW ö
or, A is = - A vs = -(-133.57) ç ÷
RL è 4.7 kW ø
= 38.96
6.5 BJT CE NETWORKS
Fixed Bias
For the fixed-bias configuration the system model with a load and source resistance will
appear as shown in Fig. 6.12.
RL
Vo = A v Vi
R L + R o NL
Fig.6.12 : Fixed-bias configuration with Rs and RL.

A v NL = - R C / re and R o = R C
R L (-R C / re )Vi
Vo = -
R L + RC
Vo R R 1
and Av = =- L C
Vi R L + R C re
RLRC
but R L || R C =
R L + RC
R L || R C
and Av = -
re
If the re model were substituted for the transistor in the fixed-bias configuration, the network
of Fig. 6.13 would result, clearly revealing that RC and RL are in parallel.
Fig. 6.13 : Fixed-bias configuration with the substitution of the re model.

For the voltage gain A vs of Fig. 6.12,
Zi Vs
Vi =
Zi + R s
Vi Zi
and =
Vs Zi + R s
Vo Vi Vo
with A vs = =
Vs Vs Vi
Zi
so that A vs = Av
Zi + R s
Since the load is connected to the collector terminal of the common-emitter configuration,
Zi = bre
and Zo = R C
as obtained earlier.
Voltage-Divider Bias
For the loaded voltage-divider bias configuration of Fig. 6.14, the load is again connected
to the collector terminal and Zi remains
Zi @ R ¢ || b re (R ¢ = R1 || R 2 )
and for the system’s output impedance
Zo = R C
Fig. 6.14 : Voltage-divider bias configuration with Rs and RL.

In the small-signal ac model, RC and RL will again be in parallel and
R C || R L
Av = -
re
Zi
with A vs = Av
Zi + R s
Fig. 6.15 : CE unbypassed emitter-bias configuration with Rs and RL.

For the output impedance,
Zo = R C
For the voltage gain, the resistance RC will again drop down in parallel with RL and
Vo R || R L
Av = =- C
Vi RE
Vo Zi
with A vs = = Av
Vs Zi + R s
Io Z
and Ai = = -A v i
Ii RL
but keep in mind that Ii = Is = Vs/(Rs + Zi) = Vi/Zi.
Collector Feedback
This circuit is shown in Fig. 6.16.
Fig. 6.16 : Collector feedback configuration with Rs and RL.

R C || R L
Av = -
re
Zi
with A vs = Av
Zi + R s
The output impedance
Zo @ R C || R F
RF
and Zi = b re ||
AV
Example-6.4
The collector feedback amplifier of Fig. 6.17 has the following no-load system
parameters:A VNL = –238.94, Zo = RC||RF = 2.66 kW, and Zi = 0.553 kW, with re = 11.3 W,
and b = 200. Using the systems approach, determine:
(a) Av.
(b) A vs .
(c) Ai,

Solution :
(a) For the two-port system:
R C || R L 2.7 kW || 3.3kW
Av = - =-
re 11.3 W
1.485 kW
=- = –131.42
11.3 W
RF 180 kW
with Zi = bre || = (200)(11.3 W) ||
Av 131.42
= 2.26kW || 1.37kW = 0.853 kW
= 0.853 kW
The system approach will result in the configuration of Fig. 6.18 with the value of Zi
as controlled by RL and the voltage gain.
R L A v NL (3.3kW)(-238.94)
Av = = = –132.3
RL + Ro 3.3kW + 2.66 kW
Fig. 6.18 : The ac equivalent circuit for the network of Fig. 6.17.
Zi 0.853 kW
(b) A vs = Z + R A v = 0.853kW + 0.6kW (-132.3)
i s
= –77.67
Zi æ 0.853 kW ö (132.3)(0.853 kW)
(c) Ai = -A v R = -(-132.3) ç 3.3 kW ÷ = 3.3 kW
L è ø
= 34.2
Zi + R s æ 0.853 kW + 06.kW ö
or A i = - A vs = -(-77.67) ç ÷
RL è 3.3 kW ø
= 34.2
6.6 BJT EMITTER-FOLLOWER NETWORKS
The input and output impedance parameters of the two-port model for the emitter-
follower network are sensitive to the applied load and source resistance. For the emitter-
follower configuration of Fig. 6.19, the small-signal ac model would appear as shown in
Fig. 6.20.
Fig. 6.19 : Emitter-follower configuration with Rs and RL.
Fig. 6.20 : Emitter-follower configuration of Fig. 6.19 following the substitution

of the re equivalent circuit.
The i/p section can be represented by Fig. 6.21
Fig. 6.21 : Determining the Thevenin equivalent circuit for the input circuit of Fig. 6.19.
Applying Kirchhoff’s voltage law to the input circuit of Fig. 6.20 will result in
Vs - I b R s - Ibb re - (b + 1)I b R ¢E = 0
and Vs - I b (R s + bre + (b + 1)R ¢s ) = 0
Vs
so that Ib =
R s + bre + (b + 1)R ¢E
Establishing Ie, we have
(b + 1)Vs
Ie = (b + 1)I b =
R s + bre + (b + 1)R ¢E
Vs
Ie =
and
[(R s + bre ) /(b + 1)] + R ¢E
Using b + 1 @ b yields
Vs
Ie =
(R s / b + re ) + R ¢E
Drawing the network to “fit” this equation will result in the configuration of Fig. 6.22a. In
Fig. 6.22b, Re and the load resistance RL have been separated to permit a definition of Z0
and Io .
(a) (b)
Fig. 6.22 : Networks resulting from the application of Kirchhoff’s voltage law to
the input circuit of Fig. 6.20.
The voltage gain can then be obtained directly from Fig. 6.22a using the voltage divider
rule:
Vo R E || R L
and A vs = =
Vs R E || R L + R s / b + re
Setting Vs = 0 and solving for Z0 will result in
æR ö
Zo = R E || ç s + re ÷
è b ø
For the input impedance,
Zb = b(re + R ¢E )
and Zi = R B || Zb
or Zi = R B || b(re + R E || R L )
For no-load conditions, the gain equation is
RE
A vNL @
R E + re
while for loaded conditions,
Vo R E || R L
Av @ =
Vi R E || R L + re
Example-6.5
For the loaded emitter-follower configuration of Fig. 6.23 with a source resistance
and theno-load two-portparam etersofZi = 155.83kW, Z0 = 21.6 W, and AVNL = 0.993 with
re = 21.74 W and b = 65, determine:
(a) The new values of Zi and Z0 as determined by the load and Rs, respectively.
(b) Av using the systems approach.
(c) A vs using the systems approach.
(d) A i = I o / Ii

Solution
Zi = R B || b(re + R E || R L )
= 560 kW || 65(21.74 W + 3.3kW || 2.2 kW)
1442443
1.32 kW
= 560 kW|| 87.21 kW

= 75.46 kW
versus 155.83 kW (no-load).
æR ö
Zo = R E || ç s + re ÷
è b ø
æ 0.56 kW ö
= 3.3kW || ç + 21.74 W ÷
è 65 ø
= 3.3kW || 30.36 W
= 30.08 W
versus 21.6 W (no Rs).
(b) Substituting the two-part equivalent network will result in the small-signal ac equivalent
R L A v NL Vi (2.2 kW)(0.993)Vi
Vo = =
RL + Ro 2.2 kW + 30.08 W
@ 0.98Vi
with
Fig. 6.24 : Small-signal ac equivalent circuit for the network of Fig. 6.23
(c)
so that
(d)
= –33.61
6.7 FET NETWORKS
Already discussed that the isolation present between gate and drain or source of an
FET amplifier ensures that changes in RL do not affect the level of Zi and changes in Rsig
do not affect R0. In essence, therefore:
The no-load two-port model of Fig. 6.2 for an FET amplifier is unaffected by an
applied load or source resistance.
Bypassed Source Resistance
For the FET amplifier of Fig. 6.25, the applied load will appear in parallel with RD in
the small-signal model, resulting in the following equation for the loaded gain :
Fig.6.25 : JFET amplifier with Rsig and RL.

The impedance levels remain at
Unbypassed Source Resistance

For the FET amplifier of Fig. 6.26, the load will again appear in parallel with RD and the
loaded gain becomes
with
and
Fig. 6.26 : JFET amplifier with unbypassed RS.

Example-6.6
For the FET amplifier of Fig. 6.27, the no-load two-port parameters are
= – 3.18, Zi = R1||R2 = 239 kW, and Z0 = 2.4 kW, with gm = 2.2 mS.
(a) Using the two-port parameters above, determine Av and

(b) Calculate the loaded gain and compare to the result of part (a).

Solution :
(a) The small-signal ac equivalent network appears in Fig. 6.28, and
= – 2.105
= – 2.096
Fig. 6.28 : Small-signal ac equivalent circuit for the network of Fig. 6.27
(b)
= – 2.105.
Source Follower
For the source-follower configuration of
Fig. 6.29. The value of Zi can be determined
as
Fig. 6.29 : Source-follower configuration

with Rsig and PL .
The loaded voltage gain has the same format as the unloaded gain with RS replaced by the
parallel combination of RS and RL.
The output impedance is determined as,
Common Gate
Even though the common-gate configuration of Fig. 6.30 is somewhat different from
those described above with regard to the placement of RL and Rsig, the input and output
circuits remain isolated and
The loaded voltage gain is given by
Fig. 6.30 : Common-gate configuration with Rsig and RL.

EXERCISE
1. What are the parameters generally used in two port system ?
2. If we will consider the internal resistance Rs at the input of the two port system, does it
affectthe Zi , A V and Z0 ?
NL
3. Combined effect RS and RL results the increase or decrease of the overall gain of an
amplifier. Explain.
4. Draw the emitter-follower configuration of BJT with RS and RL (small-signal ac model)
and hence find the voltage gain for no-load conditions and loaded conditions.
5. For the emitter stabilized network of Fig. 6.31
(i) Determine A VNL , Zi and Z0.
(ii) Sketch two port model of Fig. 6.2 with the values determined in (i)
(iii) Determine AV and A VS .
(iv) Change RS to 1.2kW. What is the effect on A VNL , Zi and Z0 ?
(v) Change RS to 1.2kW and determine AV and A VS . What is the effect of increasing
levels of RS on AV and A VS ?
Fig. 6.31
6. The JFET amplifier circuit of Fig. 6.32 has VP = –4V and IDSS = 12 mA , and at ID =
12mA, the output resistance r0 = 25kW
(i) Determine Vg, VD and Kgs
(ii) Determine the values of gm and r0.
(iii) Replace the JFET with its small signal model, thus obtaining the small signal equivalent
circuit of the amplifier.
(iv) Use the equivalent circuit in (iii) to determine Rin and Vg / Vin .
(v) Use the equivalent circuit to determine V0 / Vg .

(vi) Find the overall gain V0 /Vin
Fig. 6.32
ppp
Frequency Response of Amplifiers

7.1 INTRODUCTION
Normally during analysis of amplifier circuits, we are ignoring the effect of capacitive
elements. WE are only analysing the resistive elements. Now we will deserve the frequency
effects introduced by larger capacitive elements of lower frequencies and smaller capacitive
elements at higher frequencies. Since we will analyse the response of an amplifier over a
wide range of frequencies, logarithmic scale is need to be use for analysis. In some cases
it is also called as decibel scale.
Decibels :
Bel is a logarithmic ratio, defined by the equation to relate power levels P1 & P2 is
P2
G = log10 bel.
P1
1 bel = 10 decibel
P2
So G = 10log10 decibel.(dB)
P1
Now decibel in terms of voltage is described as follows :
P2
G = 10log10 dB
P1
V2 2
= 10log10 R dB
V1 2
R
Frequency Response of Amplifiers 211
2
æV ö
= 10log10 ç 2 ÷ dB
è V1 ø
V2
Þ G = 20log10 dB
V1
7.2 AMPLIFIER FREQUENCY RESPONSE

It is a graphical representation of the relationship between amplifier gain and operating
frequency.
The response may be between voltage gain and frequency or between power gain
and frequency.
Fig. 7.1 : Frequency response of a RC coupled amplifier

The figure shows the frequency response of a RC coupled amplifier. From the graph it is
clear that
l There are three bands of frequencies, Lower band, middle band and upper band.
l The gain is approximately constant in middle band of frequencies. This band of
frequencies is referred as Bandwidth of the amplifier.
l As operating frequency decreases from the midband area of the curve, a point is
reached where voltage gain becomes 1 2 times of the midband value or power gain
becomes 1 2 times of the midband value. This frequency is called lower cutoff
Frequency (f1).
This occurs due to input coupling, output coupling and bypass capacitors of the amplifier
circuits.
l As operating frequency increases from the midband area of the graph, a point is
reached where voltage gain becomes 1 2 times of midband value. This point is called
upper cutoff frequency (f2).
This occurs due to wiring capacitors and junction / parasitic capacitors.
The Bandwidth, BW = f 2 - f1
The cutoff frequency is also called as half power frequency because of following.
P a V2
1
At cutoff frequencies voltage gain drops to 2 times of midband value then power
2
æ 1 ö =1
gain drops to ç ÷ times of midband value.
è 2ø 2
The geometric center frequency (f0) of an amplifier is the geometric average of the
cut-off frequencies.
It is given by f 0 = f1f 2
Þ f 02 = f1 .f 2
f0 f2
Þ f =f
1 2
At geometric centre frequency the power gain and voltage gain are maximum.
Measuring the Cutoff Frequencies
The cutoff frequencies of an amplifier can be measured with an oscilloscope using the
following procedure :
1. Set up the amplifier for the maximum undistorted output signal.
2. Establish that you are operating in the midband frequency range by varying the
frequency of the input signal several kilohertz in both directions. If you are in the
midband range, slight variations in operating frequency will not cause any significant
changes in the output amplitude of the circuit.
3. If you are not midband, adjust input frequency until you are.
4. Adjust the volts/division calibration control on the osciloscope until the amplifier output
waveform fills exactly seven major divisions (peak-to-peak).
5. To measure the value of f1 decrease the operating frequency until the amplifier output
waveform fills only five major divisions. At this frequency, the amplitude of the amplifier
has dropped to 0.707 of its maximum value. This indicates that we are operating at the
lower cutoff frequency.
6. To measure the value of f2 increase the operating frequency until the same thing
happens on the high-frequency end. The frequency at which this occurs is f2.
7.3 TRANSISTOR CUT-OFF FREQUENCIES
Even if no external stray capacitances were present, the device internal capacitances
and the transit time of charge carriers across the transistor junctions and through the
semiconductor material limit the circuitry frequency response. This limitation is expressed
in terms of cut-off frequencies, called the alpha and beta cut-off frequencies.
7.3.1 Alpha Cut-off Frequency
The alpha cut-off frequency (fa or – fhfb) is defined as the frequency at which the
1
current gain a falls to = or 0.707 of its low frequency value a0, corresponding to a
2
3 db loss. Thus, at the alpha cut-off frequency (fa or – fhfb) a = 0.707 a0 where a0 is the
low frequency value of a listed in the transistor manuals.
Alpha cut-off frequency is found to be (i) inversely proportional to the square of
the base width and (ii) directly proportional to the minority carrier mobility.
7.3.2 Beta Cut-off Frequency
The beta cut-off frequency (fb) is defined as the frequency at which the current gain
é a ù 1
b êi.e. ú decreases to = or 0.707 of its low frequency value, Thus at fb
ë 1- a û 2
0.707 a 0
b=
1 - a0
The alpha and beta cut-off frequencies are related by the approximate expression
fb ; (1 - a 0 ) f a
Since a0 is close to unity, the beta cut-off frequency fb is much lower than the alpha
cut-off frequency fa usually listed in the manufacturer’s data sheets.
In fact fa @ b fa
The phase angle (lag) is close to 60° at the alpha cut-off frequency. The magnitude
of a at some other frequency f, other than cut-off can be estimated from the following
approximate relation
a0
a;
2
æ f ö
1+ ç ÷
è fa ø
7.3.3 The fT Parameter of a Transistor
It is another high frequency characteristic of a transistor and is defined as the frequency
at which the short-circuit common emitter current gain, b falls to unity.
It is related to fb as fT = b fb where b refers to its low frequency value.
Obviously fT is much larger than fb. However, it is smaller than fa and is related
with fa by the following relation.
f a @ 1.2 f T
7.3.4 Gain-Bandwidth Product
For any amplifier, gain-bandwidth product is constant and is equal to fT. For example if
b = 1 at a frequency of 6 MHz, then fT = 6 MHz i.e. gain-bandwidth product = 6 MHz
Thus, for a given fT in an amplifier, gain can be increased only at the expense of its
bandwidth.
Example-7.1
For the 2N525 transistor, alpha (–hfb) = 0.978 and fa = 2.5 MHz. Determine fb and b at
this frequency.
Solution:
Beta cut-off frequency, fb = (1 – a0) fa = (1 – 0.978) × 2.5 = 0.055 MHz Ans.
0.707 a 0 0.707 ´ 0.978
and b at 0.055 MHz = = = 31.43 Ans.
1 - a0 1 - 0.978
Example-7.2
A transistor with alpha cut-off frequency = 5 MHz and hfe or b = 50 is used in a
common emitter configuration. When connected as an amplifier, it has stray capacitance
of 80 pF at the output terminals. Determine the upper 3-db frequency when (a) RL = 10
kW and (b) RL = 100 k W.
Solution :
fa = 5 MHz, b = 50
f a 5MHz fa
\ fb = = = 100 kHz Q from equation (12.77) fb =
b 50 b
Stray capacitance Cs would reduce the amplifier gain by 3-db when
1
= RL
2pf s Cs
2 2
(a) or fs = = = 200 kHz
2pCS R L 2p ´ 80 ´ 10-12 ´ 10 ´ 103
Obviously, before attaining this value, cut-off would have occurred at fb = 100 kHz,
so f 2 = 100 kHz Ans.
2
(b) fs = -12
= 20 kHz
2p ´ 80 ´ 10 ´ 100 ´ 103
Since fs < fb so f 2 = f s = 20 kHz Ans.
7.4 BODE PLOT
The frequency response of an amplifier or any linear network is indicated by plotting
two curves
1) The magnitude of transfer gain with change in frequency. and
2) The phase lead angle as a function of frequency.
These characteristics are called bode plots.
7.5 LOW-FREQUENCY ANALYSIS

In the low-frequency region of the
single-stage BJT or FET amplifier, it is the
R-C combinations formed by the network
capacitors CC, CE, and CS and the network
resistive parameters that determine the
cutoff frequencies. In fact, an R-C
network similar to Fig. 7.2 can be Fig. 7.2 R-C combination that will
established for each capacitive element define a low cutoff frequency.
and the frequency at which the output
voltage drops to 0.707 of its maximum value determined. Once the cutoff frequencies
due to each capacitor are determined, they can be compared to establish which will
determine the low-cutoff frequency for the system.
At very high frequencies,
1
XC = @0W
2pfC
and the short-circuit equivalent can be
substituted for the capacitor as shown in
Fig. 7.3. The result is that V0 @ Vi at high
frequencies. At f = 0 Hz,
Fig. 7.3 R-C circuit of Figure 7.2 at
1 1 very high frequencies.
XC = = = ¥W
2pfC 2p(0)C
and the open-circuit approximation can be

applied as shown in Fig.7.4, with the result
that V0 = 0 V.
Fig. 7.4 R-C circuit of Figure

11.9 at f = 0 Hz.
As the frequency increases, the capacitive reactance decreases and more of the
input voltage appears across the output terminals.
Fig. 7.5 : Low frequency response for the R-C circuit of Figure 7.2.
The output and input voltages are related by the voltage-divider rule in the following
manner:
RVi
Vo =
R - jXC
with the magnitude of V0 determined by
RVi
Vo =
R 2 + XC2
For the special case where XC = R,
RVi RVi RVi RVi 1
Vo = = = = = Vi
R 2 + XC2 R2 + R2 2R 2 2R 2
Vo 1
and Av = = = 0.707 |XC = R
Vi 2
In other words, at the frequency of which XC = R, the output will be 70.7% of the
input for the network of Fig. 7.3. The frequency at which this occurs is determined from
1
XC = =R
2pf1C
1
and f1 =
2pRC
In terms of logs,
1
G v = 20 log10 A v = 20log10 = = -3dB
2
while at Av = V0/Vi = 1 or V0 = V, (the maximum value),
Gv = 20 logl0 1 = 20(0) = 0 dB
There is a 3-dB drop in gain from the midband level when f = f1.
Vo R 1 1 1
Again, A v = = = = =
Vi R - jX C 1 - j(X C / R) 1 - j(1 / wCR) 1 - j(1 / 2pfCR)
and using the frequency defined above,
1
Av =
1 - j( f1 / f )
In the magnitude and phase form,

Vo 1 -1
Av = Ð tan ( f1 / f )
Vi 1 + ( f1 / f ) 14 4244
2 3
14 4244 3 phase R by which
Vo leads Vi
magnitude of A v
For the magnitude when f = f1,

1 1
Av = = = 0.707 ® -3 dB
1 + (1) 2 2
In the logarithmic form, the gain in dB is
1
A v(dB) = 20log10
1 + ( f1 / f )
2
1/ 2
é æ f ö2 ù
A v(dB) = -20log10 ê1 + ç 1 ÷ ú
êë è f ø úû
é æ f ö2 ù
= - ( 12 ) (20) log10 ê1 + ç 1 ÷ ú
êë è f ø úû
é æ f ö2 ù
= -10 log10 ê1 + ç 1 ÷ ú
êë è f ø úû
For frequencies where f << f1 or (f1/f)2 >> 1, the equation above can be approximated by
2
æ f ö
A v(dB) = -10 log10 ç 1 ÷
è f ø
and finally,
f1
A v(dB) = -20 log10
f f << f1
f1
At f = f1 : = 1 and - 20 log10 1 = 0 dB
f
f1
At f = 12 f1 : = 2 and - 20 log10 2 @ -6 dB
f
f1
At f = 1
4
f1 : = 4 and - 20 log10 2 @ -12 dB
f
f1
At f = 101 f1 : = 10 and - 20 log10 10 @ -20 dB
f
A plot of these points is indicated in Fig. 7.6 from 0. 1 f1 to f1. This results in a
straight line when plotted against a log scale. In the same figure, a straight line is also
drawn for the condition of 0 dB for f >> f1. As stated earlier, the straight-line segments
(asymptotes) are only accurate for 0 dB when f >> f1 and the sloped line when f1 >> f.
We know, however, that when f = f1, there is a 3-dB drop from the mid-band level.
Employing this information in association with the straight-line segments permits a fairly
accurate plot of the frequency response as indicated in the same figure. The piecewise
linear plot of the asymptotes and associated breakpoints is called a Bode plot of the
magnitude versus frequency.
Fig. 7.6 : Bode plot for the low-frequency region.

The calculations above and the curve itself demonstrate clearly that:
A change in frequency by a factor of 2, equivalent to 1 octave, results in a 6-dB
change in the ratio as noted by the change in gain from f1/2 to f1.
As noted by the change in gain from f1/2 to f1:
For a 10:1 change in frequency, equivalent to 1 decade, there is a 20-dB change
in the ratio as demonstrated between the frequencies of f1/10 and f1.
The phase angle q is determined from
f1
q = tan -1
f
For frequencies f << f1,
f1
q = tan -1 ® 90°
f
For instance, if f1 = 100f,
f1
q = tan -1 = tan -1 (100) = 89.4°
f
For f = f1,
f1
q = tan -1 = tan -1 1 = 45°
f
For f >> f1
f1
q = tan -1 ® 0°
f
For instance, if f = 100f1,
f1
q = tan -1 = tan -1 0.01 = 0.573°
f
A plot of q = tan–1(f1,/f) is provided in Fig. 7.7. If we add the additional 180° phase shift
introduced by an amplifier, the phase plot will be obtained.
Fig. 7.7 Phase response for the R-C circuit

7.6 LOW-FREQUENCY RESPONSE-BIT AMPLIFIER
For the network of Fig. 7.8, the capacitors CS, CC, and CE will determine the low-
frequency response. We will now examine the impact of each independently in the
order listed.
Fig. 7.8 Loaded BJT amplifier with capacitors that affect the low-frequency response.
Effect of CS :
Since CS is normally connected
between the applied source and the active
device, the general form of the R-C
configuration is established by the network
of Fig. 7.9. The total resistance is now RS
+ Ri, and the cutoff frequency is given as,
Fig,7.9 : Determining the effect of CS
on the low frequency response.
1
f Ls =
2p(R s + R i )Cs
At mid or high frequencies, the reactance of the capacitor will be sufficiently small
to permit a short-circuit approximation for the element. The voltage Vi will then be
related to Vs by
R i Vs
Vi |mid =
Ri + Rs
At f Ls , the voltage Vi will be 70.7%

of the value, assuming that CS is the only
capacitive element controlling the low-
frequency response.
The Fig. 7.10 shows the input section.
Fig.7.10 : Localized ac equivalent for CS.
The value of Ri for Eq. (11.27) is determined by
R i = R1 || R 2 || bre
The voltage Vi applied to the input of the active device can be calculated using the
voltage-divider rule:
R i Vs
Vi =
R s + R i - jXCs
Effect of CC :
Since the coupling capacitor is normally connected between the output of the active
device and the applied load, the R-C configuration that determines the low cutoff frequency
due to Cc appears in Fig. 7.11. From Fig. 7.11, the total series resistance is now R0 + RL
and the cutoff frequency due to Cc is determined by
1
f LC =
2p(R o + R L )CC
Fig. 7.11 : Determining the effect of CC on the low-frequency response.

Ignoring the effects of CS and CE, the output voltage V0 will be 70.7% of its midband
value at f LC , The output section is given in Fig. 7.12. The voltage R0 is given as,
R o = R C || ro
Fig. 7.12 : Localized ac equivalent for Cc with V, = 0 V.

CE
Effect of CE :
To determine f LE , the network
“seen” by CE must be determined as
shown in Fig.7.13. Once the level of Re is
established, the cutoff frequency due to
CE can be determined using the following
equation:
1 Fig.7.13: Determining the effect of

f LE =
2pR e CE CE on the low-frequency response.
For the network of Fig. 7.8, the ac

equivalent as “seen” by CE appears in
Fig.7.14. The value of Re is therefore
determined by
æ R¢ ö
R e = R E || ç s + re ÷
è b ø
where R ¢s = R s || R 1 || R 2 Fig.7.14 : Localized ac equivalent of CF.
The effect of CE on the gain is best

described in a quantitative manner by
recalling that the gain for the configuration
of Fig. 7.15 is given by
-R C
Av =
re + R E
Fig. 7.15 Network employed to describe
the effect of CE on the amplifier gain.
The maximum gain is obviously available where RE is zero ohms. At low frequencies,
with the bypass capacitor CE in its “open-circuit” equivalent state, all of RE appears in
the gain equation above, resulting in the minimum gain. As the frequency increases, the
reactance of the capacitor CE will decrease, reducing the parallel impedance of RE and
C£ until the resistor RE is effectively “shorted out” by CE. The result is a maximum or
midband gain determined by Av = – RC/re. At f LE the gain will be 3 dB below the
midband value determined with RE “shorted out.”
7.7 LOW-FREQUENCY RESPONSE- FET AMPLIFIER
There are again three capacitors of primary concern as appearing in the network
of Fig. 7.16 CG, CC, and CS.
Fig.7.16 : Capacitive elements that affect the low-frequency

response of a JFET amplifier.
For the coupling capacitor between the source and the active device, the ac equivalent
network will appear as shown in Fig. 7.17. The cutoff frequency determined by CG will
then be
1
f LG =
2p(R sig + R i )CG
For the network of Fig. 7.16,
Ri = RG
Typically, RG >> Rsig, and the lower
cutoff frequency will be determined
primarily by RG and CG. The fact that RG
is so large permits a relatively low level of
C G while maintaining a low cutoff
Fig.7.17 : Determining the effect of
frequency level for f LG . CG on the low-frequency response.
Effect of CC :
For the coupling capacitor between the active device and the load the network of Fig.7.18
will result. The resulting cutoff frequency is
1
f LC =
2p(R o + R L )CC
For the network of Fig. 7.16,
R o = R D || rd
Fig.7.18:Determining the effect of
CC on the low-frequency response.
Effect of CS :
For the source capacitor CS, the resistance
level of importance is defined by Fig. 7.19.
The cutoff frequency will be defined by
1
f Ls =
2pR eq CS
Fig.7.19 : Determining the effect of
CS on the low-frequency response.
For Fig. 7.16, the resulting value of Req is
RS
R eq =
1 + R S (1 + g m rd ) /(rd + R D || R L )
which for rd @ ¥W becomes.
1
R eq = R S ||
gm
7.8 MILLER EFFECT CAPACITANCE

In the high-frequency region, the capacitive elements of importance are the inter-
electrode (between terminals) capacitances internal to the active device and the wiring
capacitance between leads of the network. The large capacitors of the network that
controlled the low-frequency response have all been replaced by their short-circuit
equivalent due to their very low reactance levels.
For inverting amplifiers (phase shift of 180° between input and output resulting in
a negative value for Av), the input and output capacitance is increased by a capacitance
level sensitive to the inter-electrode capacitance between the input and output terminals
of the device and the gain of the amplifier. In Fig. 7.20, this “feedback” capacitance is
defined by Cf .
Fig. 7.20 Network employed in the derivation of an equation for the

Miller input capacitance.
Applying Kirchhoff’s current law gives
Ii = I1 + I2
Using Ohm’s law yields
Vi V
Ii = , I1 = i
Zi Ri
Vi - Vo Vi - A v Vi (1 - A v )Vi
and I2 = = =
XC f XC f XC f
Substituting, we obtain
Vi Vi (1 - A v )Vi
= +
Zi R i XC f
1 1 1
= +
and Zi R i XC f /(1 - A v )
XC f 1
= = X CM
1 - Av w(1 - A v )C f
but 14 4244 3
CM
1 1 1
and = +
Zi R i X C M
establishing the equivalent network of

Fig.7.21.
Fig. 7.21 Demonstrating the impact of

the Miller effect capacitance.
In general, therefore, the Miller effect input capacitance is defined by
CMi = (1 - A v )C f
This shows us that:

For any inverting amplifier, the input capacitance will be increased by a Miller
effect capacitance sensitive to the gain of the amplifier and the inter-electrode
(parasitic) capacitance between the input and output terminals of the active device.
The Miller effect will also increase the level of output capacitance, which must
also be considered when the high-frequency cutoff is determined. In Fig. 7.22, the
parameters of importance to determine the output Miller effect are in place. Applying
Kirchhoff’s current law will result in
Io = I1 + I 2
Vo Vo - Vi
with I1 = and I 2 =
Ro XC f
The resistance R0 is usually sufficiently large to permit ignoring the first term of the
equation compared to the second term and assuming that
Vo - Vi
Io @
XC f
Substituting Vi = V0/Av from Av = Vo/Vi will result in

Vo - Vo / A v Vo (1 - 1/ A v )
Io = =
XC f XC f
Fig.7.22 : Network employed in the derivation of an equation for

the Miller output capacitance.
Io 1 - 1/ A v
and =
Vo XC f
Vo XC f 1 1
or = = =
Io 1 - 1/ 4 v wC f (1 - 1/ A v ) wC Mo
resulting in the following equation for the Miller output capacitance:
æ 1 ö
CM o = ç 1 - ÷C f
è Av ø
For the usual situation where Av >> 1.
CMo @ C f
A v >>1
7.9 HIGH-FREQUENCY RESPONSE

At the high-frequency end, there are two factors that will define the -3-dB point: the
network capacitance (parasitic and introduced) and the frequency dependence of hfe(b).
In the high-frequency region, the RC network of concern has the configuration
appearing in Fig. 7.23. At increasing frequencies, the reactance XC will decrease in
magnitude, resulting in a shorting effect across the output and a decrease in gain. The
derivation leading to the corner frequency for this RC configuration follows along similar
lines to that encountered for the low-frequency region. The most significant difference
is in the general form of Av appearing below:
1
Av =
1 + j( f / f 2 )
which results in a magnitude plot such as shown in Fig. 7.24 that drops off at 6 dB/
octave with increasing frequency.
Fig. 7.23 : R-C combination that will define a high cutoff frequency.
Fig. 7.24 : Asymptotic plot

The analysis is same as low frequency analysis.
7.10 BJT HIGH FREQUENCY RESPONSE
In Fig. 7.25, the various parasitic capacitances (Cbe, Cbc, Cce) of the transistor have
been included with the wiring capacitances ( CWi ,CWo ) introduced during construction.
The high-frequency equivalent model for the network of Fig. 7.25 appears in Fig. 7.26.
Fig. 7.25 BJT amplifier with the capacitors

that affect the high-frequency response.
Fig. 7.26 High-frequency ac equivalent model for the network of Fig. 7.25.
Note the absence of the capacitors Cs, Cc, and CE, which are all assumed to be in the
short-circuit state at these frequencies. The capacitance Ci includes the input wiring
capacitance C Wi , the transition capacitance Cbe, and the Miller capacitance C Mi . The
capacitance Co includes the output wiring capacitance CWo , the parasitic capacitance
Cce, and the output Miller capacitance C Mo . In general, the capacitance Cbe is the largest
of the parasitic capacitances, with Cce the smallest. In fact, most specification sheets
simply provide the levels of Cbe and Cbc and do not include Cce unless it will affect the
response of a particular type of transistor in a specific area of application.
Determining the Thivenin equivalent circuit for the input and output networks of
Fig. 7.26 will result in the configurations of Fig. 7.27. For the input network, the -3-dB
frequency is defined by
1
f Hi =
2pR Thi Ci
(a) (b)
Fig. 7.27 Thevenin circuits for the input and output networks of the
with R Thi = R s || R1 || R 2 || R i
and Ci = CWi + Cbe + CMi = C Wi + Cbe + (1 - A v )Cbe
At very high frequencies, the effect of Ci is to reduce the total impedance of the
parallel combination of R1, R2, Rf, and Ci in Fig. 7.26. The result is a reduced level of
voltage across C,, a reduction in Ib, and a gain for the system.
For the output network,
1
f Ho =
2pR Tho Co
with R Tho = R C || R L || ro
and Co = CWo + Cce + CMo

At very high frequencies, the capacitive reactance of C0 will decrease and
consequently reduce the total impedance of the output parallel branches of Fig. 7.26.
The net result is that V0 will also decline toward zero as the reactance XC becomes
smaller. However, the decrease in hfe (or b) with frequency must also be considered as
to whether its break frequency is lower than f H i or f Ho .
hfe (or b) Variation
The variation of hfe (or b) with frequency will approach, with some degree of accuracy,
the following relationship:
h femid
h fe =
1+ j( f/fb )
The use of hfe rather than b in some of this descriptive material is due primarily to
the fact that manufacturers typically use the hybrid parameters when covering this
issue in their specification sheets, and so on.
The only undefined quantity, fb , is determined by a set of parameters employed in
the hybrid p or Giacoletto model frequently applied to best represent the transistor in
the high-frequency region. It appears in Fig. 7.28. The various parameters warrant a
moment of explanation. The resistance rbb includes the base contact, base bulk, and
base spreading resistance. The first is due to the actual connection to the base. The
second includes the resistance from the external terminal to the active region of
Fig. 7.28 Giacoletto (or hybrid ir) high-frequency transistor

small-signal ac equivalent circuit.
the transistors, while the last is the actual resistance within the active base region. The
resistances rb'e, rce, and rb'c are the resistances between the indicated terminals when
the device is in the active region. The same is true for the capacitances Cb'c and Cb'e,
although the former is a transition capacitance while the latter is a diffusion capacitance.
In terms of these parameters,
g b¢e
fb (sometimes appearing as f h fe ) =
2p(Cb¢e + Cb¢e )
or since the hybrid parameter hfe is related to gb'e through gm = h femid g b¢e ,
1 gm
fb -
h femid 2p(Cb¢e + Cb¢c )
1 h fe b 1
Now g m = h femid g b¢e = h femid @ mid = mid =
rb¢e hie bmid re re
and using the approximations,
Cb¢e @ C be and Cb¢c @ C bc
will result in the following form
1
fb @
2pbmid re (Cbe + Cbc )
It reveals that since re is a function of the network design: fb is a function of the

bids conditions.
The following equation permits a direct conversion for determining fb if fa and a
are specified.
fb = f a (1 - a )
A quantity called the gain-bandwidth product is defined for the transistor by the
condition
h femid
=1
1 + j( f / fb )
h fe : Current gain in CE configuration ü

ý of BJT
h fb : Current gain in CB configuration þ
Fig. 7.29 hfe and hfb versus frequency in the high-frequency region.
h femid
so that h fe = 20 log10 = 20log10 1 = 0 dB
dB 1 + j( f / fb )
The frequency at which h fe = 0 dB is clearly indicated by fT in Fig. 7.29. The

dB
magnitude of hfe at the defined condition point (fT >> fb) is given by
h femid h femid
@ =1
1 + j( f / fb ) 2 fT / fb
so that fT @ h femid · fb
(gain-bandwidth product)
or fT @ b mid fb {Q f b @ BW}
fT
with fb =
b mid
1
So, fT @ b mid
2pb mid re (C be + C bc )
1
and fT @
2pre (Cbe + Cbc )
7.11 HIGH-FREQUENCY RESPONSE-FET AMPLIFIER

As shown in Fig. 7.30, there are inter-electrode and wiring capacitances that will
determine the high-frequency characteristics of the amplifier. The capacitors Cgs and
Cgd typically vary from 1 to 10 pF, while the capacitance Cds is usually quite a bit smaller,
ranging from 0.1 to IpF.
Since the network of Fig. 7.30 is an inverting amplifier, a Miller effect capacitance
will appear in the high-frequency ac equivalent network appearing in Fig. 7.31. At high
frequencies, Ci will approach a short-circuit equivalent and Vgs will drop in value and
reduce the overall gain. At frequencies where C0 approaches its short-circuit equivalent,
the parallel output voltage V0 will drop in magnitude.
The cutoff frequencies defined by the input and output circuits can be obtained by
first finding the Thevenin equivalent circuits for each section as shown in Fig. 7.32. For
the input circuit,
Fig. 7.30 Capacitive elements that affect the high-frequency

response of a JFET amplifier.
Fig. 7.31 High-frequency ac equivalent circuit for Fig. 7.30.

1
f Hi =
2pR Thi Ci
and R Thi = R sig || R G
with Ci = CWi + Cgs + CMi

and CMi = (1 - A v )Cgd

for the output circuit,
1
f Ho =
2pR Tho Co
Fig.7.32 : The Thevenin equivalent circuits for the

(a) input circuit and (b) output circuit.
with R Tho = R D || R L || rd
and Co = CWo + Cds + CMo
æ 1 ö
and C Mo = ç1 - ÷ Cgd
è Av ø
Example-7.3
Determine the lower cut-off frequency for the network shown below using the following
parameters
CS = 10 mF, CE = 20 mF, CC = 1 mF, RS = 1 kW, R1 = 40 kW, R2 = 10 kW, RE = 2 kW,
RE = 2 kW, RC = 4 kW, RL = 2.2 kW, b = 100, VCC = 20 V, and ro = 40 kW.
Also find Av mid.
Fig. 7.33
Solution : From d.c. analysis, we have

b R E = (100) (2kW) = 200 kW >> 10 R 2 = 100 kW
R2 (20V)10 kW
The result is Vth = VB = Vcc ´ R + R = 10 kW + 40 kW
1 2
200
or VB = V=4V
50
Now VE = VB - VBE = 4 V - 0.7 V = 3.3 V
VE 3.3V
Hence IE = = = 1.65 mA
R E 2kW
26 mV 26 mV
or re = = = 15.76 W
IE 1.65mA
and b re = 100(15.76 W) = 1576 W = 1.576 kW
Effect of CS : Lower cut-off frequency
1
f LS =
2p (R s + R i )Cs
Where R i = R 1 ||R 2 || bre
or R i = (40 kW)|| (10 kW)||1.576 kW = 1.32 kW
1 1
hence f LS = =
2p(R s + R i )Cs 2p (1kW + 1.32 kW)(10mF)
1 100
= -6
= = 6.86Hz.
2p ´ 2.32K ´ 10 ´ 10 2p ´ 2.32
4 ´ 40
Effect of Cc : R o = R c || ro = (4 kW)||(40 kW) = kW = 3.64 kW
44
Lower cut-off frequency
1
f LC =
2p(R o + R L )Cc
1
or f LC =
2p(3.64 kW + 2.2 kW)(1m F)
1 1000
= =
6.28 ´ 5.84 ´ 103 ´ 10-6 6.28 ´ 5.84
Þ f LC = 27.27 Hz.
Effect of CE : R ¢s = R s || R 1 || R 2 ||= (1kW) || (40 kW) || (10 kW)

@ 0.889k W
æ R¢ ö æ 0.889 kW ö
and R e = R E || ç s + re ÷ = (2 kW) || ç + 15.76 W ÷
è b ø è 100 ø
= (2kW)||(8.89 W + 15.76W) = (2kW)|| (24.56 W)
@ 24.35 W
1 1
Hence f LE = =
2p R e CE 6.28 ´ 24.35 ´ 20 ´ 10-6
105
= @ 327 Hz
6.28 ´ 24.35 ´ 2
Midband gain
Vo R || r || R L
A v mid = =- c o
Vi re
(4 kW) || (40 kW) || (2.2 kW) 1370.72 W

or A v mid = - =- = -87
15.76 W 15.76 W
Example-7.4
For the network shown in Fig. 7.34
Fig. 7.34
Vo
(a) Determ ine re (b) Find A v mid =
Vi
Vo
(c) Calculate Zi (d) Find A vs mid =
Vs
(e) Determ ine fLS , fLC ,and fLE (f) Determine the low cut-off frequency.
Solution : From d.c. analysis b R E > 10 R 2

Þ 120 ´ 1.2kW > 10 ´ 10kW
Þ 144 kW > 100 kW satisfied.
So, we can apply the approximate analysis as
R2 (10 kW) 140
(a) Vth = ´ Vcc = ´ 14 V = V
R1 + R 2 78kW 78
or Vth = 1.795 V = VB
and R th = R 1 || R 2 = (68 kW)||(10 kW) = 8.72 kW
Now VE = VB - VBE = 1.795 V - 0.7 V = 1.095 V
VE 1.095 V
and IE = = = 0.9125mA
R E 1.2 kW
26 mV 26mV
Hence re = IE
=
0.9125mA
= 28.49 W
or re = 28.49 W
Vo R || R L (5.6 kW) || (3.3kW)
(b) A v mid = =- C =-
Vi re 28.49 W
2076.4
= = -72.88
28.49
(c) The input impedance
Zi = R 1 || R 2 || b re
or Zi = (68kW ) || (10 kW) || (120 ´ 28.49 W)
= 68kW ||10kW ||3.42 kW
or R i = Zi = 2.456 kW
Vo Vo Vi
(d) A vs mid - = .
Vs Vi Vs
Ri
Also Vi = Vs ´
R i + R s (voltage division rule)
Vi Ri
or =
Vs R i + R s
Ri 2.456
or A vs mid = A v mid ´ = (-72.88) ´
Ri + Rs 2.456 + 0.82
= (–72.88) × 0.75 = –54.66
1
(e) f LS = , given Cs = 0.47 mF
2p(R s + R i )Cs
1
or f LS = ¹±
6.28(0.82 kW + 2.450 kW)0.47 mF
108
=
6.28 ´ 3.276 ´ 103 ´ 47
105
= Hz = 103.42 Hz
6.28 ´ 3.276 ´ 47
1
f LC = , R o = R c = 5.6 kW, Cc = 0.47 mF
2p(R o + R L )Cc
1
f LC =
6.28(5.6 kW + 3.3kW)(0.47 mF)
1
=
6.28 ´ 8.9 ´ 10-5 ´ 47
105
= Hz = 38.07 Hz
6.28 ´ 8.9 ´ 47
1
Now f LE = ,CE = 20 mF
2pR c CE
æ R¢ ö
R e = R E || ç S + re ÷ , where R ¢S = R1 || R 2 || R S
è b ø
Now R S¢ = (68 kW) || (10 kW) || (0.82 kW ) = 0.75 kW
æ 0.75kW ö
R e = (1.2 kW) || ç + 28.49 W ÷
è 120 ø
= (1.2 kW) || (6.246 W + 28.49W)
1200 ´ 34.736
= = 33.76 W
1234.736
1
and f LE =
2p´ 33.76 ´ 20 ´ 10-6
105
= Hz = 235.83 Hz
6.28 ´ 33.76 ´ 2
(f) Since f LE is the largest of the three cut-off frequencies, it defines the low cut-off
frequency.
f L = f LE = 235.83 Hz
Example-7.5
Figure 7.35 for the emitter stabilized network :
Fig. 7.35
Vo
(a) Determine re (b) Find A v mid = V
i
Vo
(c) Calculate Zi (d) Find A vs mid = V
S
(e) Determine fLS, fLC and fLE

(f) Determine the low cut-off frequency.
Solution : From d.c. analysis, we have
VCC - VBE 20 V - 0.7 V
(a) IB = =
R B + (b + 1) R E 470 kW + 111 ´ 0.91kW
19.3 V
= = 33.8 mA
571.01kW
and hence I E = (b + 1) I B = 111 ´ 33.8 mA = 3.75mA
26 mV 26 mV
Now re = = = 6.93 W
IE 3.75 mA
Vo R || R L
(b) A v mid = =- C
Vi re
3 ´ 4.7
R e || R L = (3kW) || (4.7 kW) = kW = 1.1831 kW
7.7
1.8312 kW
or A v mid = - = -264.24
6.93 W
(c) Input impedance
Zi = R B || bre = (470 kW) || (110 ´ 6.93 W) = 761W
Vo Vo Vi Ri
(d) A vs mid = = ·
VS Vi VS or A vs mid = A v mid ´ R + R
i S
716 W
= ( -264.26) ´ = -147.76
(0.761 + 0.6)kW
1 1
(e) f Ls = =
2p(R i + R S )CS 2p ´ 1361 ´ 10-6
106
= Hz @ 117 Hz
6.28 ´ 1361
1 1
f LC = =
2p(R C + R L )CC 2p(3 + 4.7) ´ 103 ´ 10-6
1000
= Hz = 20.68 Hz
6.28 ´ 7.7
1
f LE =
2pR e CE
Now R ¢S = R S || R B = (0.6 kW) || (470 kW) = 359 W
R ¢S 359 W
+ re = + 6.93 W = 10,194 W
b 110
æ R¢ ö
Now R e = R E || ç S + re ÷ = (0.91 kW) || (10.194 W)
è b ø
910 ´ 10.194
= W = 10.08 W
920.194
1 106
Hence f LE = =
2p ´ 10.08 ´ 6.8 ´ 10-6 6.28 ´ 10.08 ´ 6.8
= 2322.8 Hz = 2.323 kHz
(f) Since fLE is the largest out of the three frequencies, hence resultant lower cut-off
frequency.
fL = fLE = 2.323 kHz
Example-7.6
Fig. 7.36
Given I DSS = 6 mA and VP = -6 Vl rd = ¥W.
(a) Determine VGS-Q and ID-Q.
(b) Find gmo and gm.
Vo
(c) Calculate the midband gain of A v = .
Vi
(d) Determine Zi.
Vo
(e) Calculate A vs = V .
S
(f) Determ ine fLG , fLC and fLS.

(g) Determine the low cut-off frequency.
Solution :
(a) As we know for FET that no current flows through RG, i.e. IG = 0 unlike BJT.
Hence, applying KVL to the Gate-source loop, we get
VGS = –1.2 ID ... (1)
From Shokley’s equation, we have
2
æ V ö
I D = I DSS ç 1 = GS ÷
è VP ø
2 2
æ V ö æ V ö
or I D = 6 ç 1 - GS ÷ = 6 ç 1 + GS ÷
è -6 ø è 6 ø
(6 + VGS )2 1
=6 = (6 + VGS ) 2
36 6
Þ 6I D = (5 + VGS ) 2 = 36 + VGS
2
+ 12VGS ... (2)
Putting value of ID from (1) into (2), we get
6
- VGS = 36 + VGS
2
+ 12 VGS
1.2
or 2
VGS + 12 VGS + 36 + 5 VGS = 0
Þ 2
VGS + 17 VGS + 36 = 0
-17 ± 17 2 - 4 ´ 36 -17 ± 12.04

or VGS = =
2 2
= –2.48 V, –14.52 V (rejected)
Hence VGS-Q = -2.48 V
VGS- Q 2.48
From (1), ID-Q = - = mA = 2.07 mA
1.2 1.2
2 I DSS 2 ´ 6 mA
(b) We know that gmo = = = 3 ms
VP 6
æ V - ö
and g m = g mo ç1 - GS Q ÷
è VP ø
æ æ -2.48 ö ö æ 2.48 ö
= 2 ç1 - ç ÷ ÷ = 2 ç1 - ÷ ms
è è -6 ø ø è 6 ø
Þ gm = 2 × 0.59 = 1.18 ms
(c) Midband gain Av for an FET is given by
A v = -g m (R D || R L )
Given R D = 3kW and R L = 3.9 kW
3 ´ 3.9
\ R D || R L = (3 kW)||(3.9 kW) = kW = 1.6956 kW
6.9
Þ A v = -1.18 ´ 10-3 ´ 1.6966 ´ 103 = -2
(d) Input impedance for an FET is
Zi = R G = 1 M W
Vo Vo Vi V
(e) A vs = = ´ = Av ´ i
Vs Vi Vs Vs
RG 1MW
Now Vi = Vs ´ = Vs ´
R G + R sig 1MW + 1kW
Vi 1MW
or = = 0.999 » 1
Vs 1.001MW
and A vs @ A v = -2
1 1
(f) Now f LG = =
2p(R sig + R i )CG 2p(1kW + 1MW) ´ 0.1mF
1
Þ f LG = = 1.59 Hz
6.28 ´ 1.001 ´ 106 ´ 0.1 ´ 10-6
1
f LC = Here, C c = 4.7 mF
2p(R o + R L )Cc
R o = R D || rd Qrd = ¥
Ro = RD
(R D + R L ) = 3kW + 3.9 kW = 6.9 kW
1
Þ f LC =
2p ´ 6.9 kW ´ 4.7 ´ 10-6
1000
= Hz = 4.91Hz
6.28 ´ 6.9 ´ 4.7
1
f LC = , R sig = 1 kW, CS = 10 mF
2p Req.CS
1 1
Re q. = R si g || = (1kW) || = (1kW) || (0.847 kW)
gm 1.18 ms
or, Req. = 458.7 W
1
Hence f LS =
2p ´ (458.7 W) ´ (10 mF)
1
=
2p ´ 458.7 ´ 10 ´ 10-6
105
Þ f LS = = 34.71 Hz
6.28 ´ 458.7
(g) Since out of the three frequencies f LS is highest, therefore

Lower cut-off frequency = f LS = 34.71 Hz. .
Example-7.7
Fig. 7.37
(a) Determine VGSQ and IDQ.
(b) Find gmo and gm.
Vo
(c) Calculate the midband gain of A v =
Vi
(d) Determine Zi.
Vo
(e) Calculate A vs = V .
s
(f) Determine fLG, fLC, and fLS .

(g) Determine the low cut-off frequency. Given IDSS = 10 mA, VP = –6V.
What effect did the voltage divider configuration have on the input impedance and the
gain Avs compared to the biasing arrangement shown in Example 10.6.
Solution :
R2
(a) VG = Vth = VDD ´
R1 + R 2
68kW
or VG = (20 V) ´
220kW + 68kW
68
= 20 ´ = 4.722 V
288
Now, applying kirchhoff’s voltage law in the Gate source loop, we get
VG - VGS - VRS = 0, VRS = I D R S (Q IG = 0)
Þ VG - VGS - I D - R S = 0
Þ VGS = VG - I D R S = 4.722 V - ID ´ 2.2, ID is in mA.

or VGS = 4.722 - 2.2 ID
4.722 - VGS
ID = ... (1)
2.2
Now from Shockley’s equation
2
æ V ö
2
æ V ö
I D = I DSS ç 1 - GS ÷ = 10 ç 1 - GS ÷
è VP ø è -6 ø
2
æ V ö 10
= 10 ç 1 + GS ÷ , or I D = (6 + VGS ) 2
è 6 ø 36
Þ 3.6 I D = VGS
2
+ 12 VGS + 36 ... (2)
From (1) and (2)
æ 4.722 - VGS ö
÷ = VGS + 12VGS + 36
2
3.6 ç
è 2.2 ø
Þ 7.727 - 1.636 VGS = VGS
2
+ 12 VGS + 36
Þ 2
VGS + 13.636 VGS + 28.27 = 0
-13.636 ± (13.636) 2 - 4 ´ 28.27

Þ VGS =
2
-13.636 ± 8.536
Þ VGS =
2
= –2.55 V, – 11.086 (rejected)
Hence VGS-Q = -2.55V
From equation (1)
4.722 - VGS- Q 4.722 + 2.55
ID-Q = = = 3.305 mA
2.2 2.2
2 I DSS 2 ´ 10 mA
(b) g mo = = = 3.33ms
VP 6
æ V ö
and g m = g mo ç1 GS ÷
è VP ø
æ (-2.55) ö
= (3.33ms) ç 1 - ÷ = 1.916 ms.
è (-6) ø
(c) Midband voltage gain
A v = -g m (R D || R L )
Þ A v mid = -(1.916ms) (3.9kW ||5.6kW)
= -(1.916ms)(2.299 kW) = -4.4
(d) Input impedance
Zi = R G = R 1 || R 2
220 ´ 68
Þ Zi = (220 kW) || (68kW) = kW = 51.945kW
288
Vo Vo Vi V
(e) A vs = = ´ = A v mid ´ i
VS Vi VS VS
From voltage division rule
Ri V ´ 51.945kW
Vi = VS ´ = S = VS ´ 0.972
R i + R sig (51.945 + 1.5) kW
Vi
Þ = 0.972
VS
and A vs = -4.4 ´ 0.972 = -4.276
we see that the effect of this configuration is to reduce Zi from 1 MW (from Example
7.6) to 51.945 kW and to raise the magnitude of Avs from 2 to 4.276 as is compared from
the results of example 7.6.
1
(f) f LG =
2p(R sig + R i )CG
1
=
2p(1.5kW + 51.945kW) ´ 10-6
1
=
6.28 ´ 53.445 ´ 103 ´ 10-6
1000
= = 2.98Hz
6.28 ´ 53.445
1
f LC =
2p(R o + R L ) CC
1
= (Q R o = R D )
2p(3.9 kW + 5.6 kW)6.8 mF
1 1000
= -6
=
6.28 ´ 9.5 ´ 10 ´ 6.8 ´ 10
3
6.28 ´ 9.5 ´ 6.8
Þ f LC = 2.465 Hz.
1
and f LS = , where Req. = R sig ||
1
2p Req.CS gm
1
Re q. = (1.5 kW) || = (1.5 kW) || (0.522 kW) = 387.2 W
1.916 mS
1
Hence f LS =
2p ´ 387.2 ´ 10mF
1 105
Þ f LS = -5
= Hz
6.28 ´ 387.2 ´ 10 6.28 ´ 387.2
Þ f LS = 41.125 Hz
(g) Outofthe three frequencies,fLS is the largest one, hence
Lower cut-off frequency @ f LS
Þ fL = 41.125 Hz
Example-7.8
For the network of Fig. 7.38 shown in Example 7.4 the high frequency parameters are
given below :
Fig. 7.38
Cwi = 5PF,Cwo = 8PF, Cbc = 12PF,Cbe = 40 PF, Cce = 8PF
(a) Determ ine fHi and fHo
(b) Assuming the Cb¢e = Cbe and C b¢c = C bc ,find fb and f T .
Solution :
1
(a) f Hi =
2p R th1Ci
Where R th1 = R S || R 1 || R 2 || R i
R i = bre , from solution of Example 7.4
R i = 120 ´ 28.49 W = 3.42 kW, and A v mid = -72.88
Þ R th1 = (0.82 kW)||(68kW)|| (19 kW) || (3.42 kW)
= (0.82 kW)||(2.456kW)
= (0.6147 kW = 614.75 W
and Ci = C wi + C be + C Mi CMi = Miller input capacitance
= Cwi + C be + (1 - A v ) C bc CMo = Miller output capacitance
= 5 + 40 + (1 – (–72.88)) × 12
= 45 PF + 12 × 73.88 PF = 931.56 PF
1
Hence f Hi =
2p R th1Ci
1
Þ f Hi = Hz
2p ´ 614.75 ´ 931.56 ´ 10-12
1012
= Hz = 278.055kHz
6.28 ´ 614.75 ´ 931.56
1
f Ho =
2p R th 2 Co
R th 2 = R C || R L = (5.6 kW) || (3.3kW)
5.6 ´ 3.3
= kW = 2076.4 W
8.9
æ 1 ö
and Co = Cwo + CCe + CMo = Cwo + CCe + ç1 - ÷ Cbc
è Av ø
æ 1 ö
= 8PF + 8PF + ç 1 - ÷12PF
è -72.88 ø
= 16 PF + 12.165 PF = 28.165 PF
1
Hence f Ho =
2p ´ 2076.4 ´ 28.165PF
1
Þ f Ho =
2p ´ 2076.4 ´ 28.165 ´ 10-12
1012
= = 2.723 MHz
6.28 ´ 2076.4 ´ 28.165
1
(b) fb =
1
=
2p ´ 120 ´ 28.49(40PF + 12 PF)
1012
=
2p ´ 120 ´ 28.49 ´ 52
1012
Þ fb = = 0.896 MHz
6.28 ´ 120 ´ 28.49 ´ 52
f T = bmid fb = (120)(0.896) MHz
Þ f T = 107.484 MHz
Example-7.9
(a) Determine fHi and fHo
(b) Find fb and fT
Given C wi = 7 PF, C wo = 11 PF, C bc = 6 PF, C be = 20 PF, and C Ce = 10 PF

Solution : As calculated in Example 7.5
re = 6.93 W and b re = (110)(6.93 W) = 762.3 W
and A v mid = -264.24
1
(a) f Hi = , R th 1 = R S || R B || b re
2p R th1Ci
= (0.6kW) || (470 kW) || (0.7623kW)
= 0.3355 kW = 335.5 W
Ci = C wi + C be + C Mi = C wi + C be + (1 - A v )C bc
or Ci = 7 PF + 20PF + (1 - (1 - 264.24))(6 PF)
= 27 PF + 1591.44 PF = 1618.44 PF
1
Therefore f Hi =
2p´ 335.5 ´ 1618.44 ´ 10-12
1012
Þ f Hi = Hz = 293.25kHz
6.28 ´ 335.5 ´ 1618.44
1
and f Ho = , where
2pR th 2 Co
R th 2 = R C || R L = (3kW ) || (4.7 kW )
3 ´ 4.7
= kW = 1831.17 W
7.7
and C o = C wo + C Ce + C Mo
æ 1 ö
= Cwo + CCe + ç1 - ÷ Cbc
è Av ø
æ 1 ö
or Co = 11PF + 10PF + ç 1 - ÷ 6 PF
è -264.24 ø
= 21 PF + 6.023 PF = 27.023 PF
1 1
\ f Ho = =
2pR th 2 Co 2p ´ 1831.17 ´ 27.023PF
1
=
6.28 ´ 1831.17 ´ 27.023 ´ 10-12
1012
= Hz = 3.218 MHz.
6.28 ´ 1831.17 ´ 27.023
1
(b) fb =
1
Þ fb =
2p ´ 110 ´ 6.93 ´ (20PF + 6PF)
1
=
2p ´ 110 ´ 6.93 ´ 20PF
1012
= Hz = 8.034 MHz
6.28 ´ 110 ´ 6.93 ´ 26
f T = bmid fb = (110) (8.034) MHz
Þ f T = 883.7 MHz
7.12 MULTISTAGE FREQUENCY EFFECTS

For a second transistor stage connected directly to the output of a first stage, there
will be a significant change in the overall frequency response. In the high-frequency
region, the output capacitance C0 must now include the wiring capacitance (Cw ), parasitic
1
capacitance (Cbe), and Miller capacitance (CM ) of the following stage. Further, there
1
will be additional low-frequency cutoff levels due to the second stage that will further
reduce the overall gain of the system in this region. For each additional stage, the upper
cutoff frequency will be determined primarily by that stage having the lowest cutoff
frequency. The low-frequency cutoff is primarily determined by that stage having the
highest low-frequency cutoff frequency. Obviously, therefore, one poorly designed stage
can offset an otherwise well-designed cascaded system.
The effect of increasing the number of identical stages can be clearly demonstrated
by considering the situations indicated in Fig. 7.39. In each case, the upper and lower
cutoff frequencies of each of the cascaded stages are identical. For a single stage, the
cutoff frequencies are f1 and f2 as indicated. For two identical stages in cascade, the
drop-off rate in the high- and low-frequency regions has increased to -12 dB/octave or
—40 dB/decade. At f1 and f2, therefore, the decibel drop is now -6 dB rather than the
defined band frequency gain level of —3 dB. The —3-dB point has shifted to f1¢ and
f 2¢ as indicated, with a resulting drop in the bandwidth. A -18-dB/octave or – 60-dB/
decade slope will result for a three-stage system of identical stages with the indicated
reduction in bandwidth ( f1¢¢ and f 2¢¢ ).
Assuming identical stages, an equation for each band frequency as a function of
the number of stages (n) can be determined in the following manner: For the low-
frequency region,
A vlow , (overall ) = A v1 A v2 A v3 ...A vn
low low low low
Fig. 7.39 : Effect of an increased number of stages on the cutoff

frequencies and the bandwidth.
but since each stage is identical, A v1low = A v2low = etc. and
A v1 = (A v1 )n
low ,(overall ) low
n
Av æ Av ö 1
or low
(overall) = ç low ÷ =
A vmid ç Av ÷ (1 - jf1 / f )n
è mid ø
Setting the magnitude of this result equal to 1/ 2 (–3 dB level) results in
1 1
=
[1 + ( f1 / f1¢) ] 2 n 2
n 1
ìé 1
2ü ì 2 nü 2
ï ê æ f1 ö ú ï ï éêæ f1 ö ùú ï
ù
2-
or í 1+ ç ÷ ý =í ç ÷ ý = (2)1/ 2
ï êë è f1¢ ø úû ï ï êëè f1¢ ø úû ï
î þ î þ
n
é æ f ö2 ù
so that ê1 + ç 1 ÷ ú = 2
ê è f1¢ ø ú
ë û
2
æ f ö 1
and 1+ ç 1 ÷ = 2 n
è f1¢ ø
f1
with the result that f1¢ =
2 1/ n
-1
In a similar manner, it can be shown that for the high-frequency region,
f1¢ = ( 21/ n - 1) f 2
7.13 SQUARE-WAVE TESTING
The frequency response of an amplifier can be determined experimentally by applying
a square-wave signal to the amplifier and noting the output response. The shape of the
output waveform will reveal whether the high or low frequencies are being properly
amplified. The use of square-wave testing is significantly less time-consuming than
applying a series of sinusoidal signals at different frequencies and magnitudes to test the
frequency response of the amplifier.
The reason for choosing a square-wave signal for the testing process is best
described by examining the Fourier series expansion of a square wave composed of a
series of sinusoidal components of different magnitudes and frequencies. The summation
of the terms of the series will result in the original waveform. In other words, even
though a waveform may not be sinusoidal, it can be reproduced by a series of sinusoidal
terms of different frequencies and magnitudes.
The Fourier series expansion for the square wave of Fig. 7.39 is
4 æ 1 1 1
v= Vm ç sin 2p fs t + sin 2p(3 fs )t + sin 2p(5 fs )t + sin 2p(7 fs )t
p è 3 5 7
1 1 ö
+ sin 2p(9 fs )t + ... + sin 2p (nfs )t ÷
9 n ø
The first term of the series is called the fundamental term and in this case has the
same frequency, fs, as the square wave. The next term has a frequency equal to three
times the fundamental and is referred to as the third harmonic. Its magnitude is one-
third the magnitude of the fundamental term. The frequencies of the succeeding terms
are odd multiples of the fundamental term, and the magnitude decreases with each
higher harmonic. Figure 7.41 demonstrates how the summation of terms of a Fourier
series can result in a nonsinusoidal waveform. The generation of the square wave of
Fig. 7 .40 would require an infinite number of terms. However, the summation of just the
fundamental term and the third harmonic in Fig. 7.40a clearly results in a waveform that
is beginning to take on the appearance of a square wave. Including the fifth and seventh
harmonics as in Fig. 7.41b takes us a step closer to the waveform of Fig. 7.40.
Fig. 7.40 Square wave.

Since the ninth harmonic has a magnitude greater than 10% of the fundamental
term [ 19 (100%) = 11.1 %], the fundamental term through the ninth harmonic are the
major contributors to the Fourier series expansion of the square-wave function. It is
therefore reasonable to assume that if the application of a square wave of a particular
frequency results in a nice clean square wave at the output, then the fundamental through
the ninth harmonic are being amplified without visual distortion by the amplifier.
Fig. 7.41 : Harmonic content of a square wave.

If the response of an amplifier to an applied square wave is an undistorted replica
of the input, the frequency response (or BW) of the amplifier is obviously sufficient for
the applied frequency. If the response is as shown in Fig. 7.42a and b, the low frequencies
are not being amplified properly and the low cutoff frequency has to be investigated. If
the waveform has the appearance of Fig. 7.42c, the high-frequency components are not
receiving sufficient amplification and the high cutoff frequency (or BW) has to be
reviewed.
Fig. 7.42 : (a) Poor low frequency response; (b) very poor low-frequency response;
(c) poor high-frequency response; (d) very poor high-frequency response.
The actual high cutoff frequency (or BW) can be determined from the output
waveform by carefully measuring the rise time defined between 10% and 90% of the
peak value, as shown in Fig.7.43. Substituting into the following equation will provide the
uppercutofffrequency,and sinceBW = f Hi - f Lo @ f Hi , the equation also provides an
indication of the BW of the amplifier.
Fig. 7.43 : Defining the rise time and tilt of a square wave response.
0.35
BW @ f Hi =
tr
The low cutoff frequency can be determined from the output response by carefully
measuring the tilt of Fig. 7.43 and substituting into one of the following equations:
V - V¢
% tilt = P% = ´ 100%
V
V - V¢
tilt = P = (decimal form)
V
The low cutoff frequency is then determined from
P
f Lo = fs
p
Example-7.10
The application of a 1-mV, 5-kHz square wave to an amplifier resulted in the output
waveform of Fig. 7.44.
(a) Write the Fourier series expansion for the square wave through the ninth harmonic.
(b) Determine the bandwidth of the amplifier.
(c) Calculate the low cutoff frequency.
Solution
4mV æ 1 1
(a) vi = ç sin 2p(5 ´ 103 )t + sin 2p(15 ´ 103 )t + sin 2p(25 ´ 103 )t
p è 3 5
1 1 ö
+ sin 2p(35 ´ 103 )t + sin 2p(45 + 103 )t ÷
7 9 ø
(b) t r = 18 ms - 2ms = 16 ms
0.35 0.35
BW = =
tr 16 ms = 21,875 Hz s @ 4.4fs
V - V¢ 50mV - 40mV
(c) P= = = 0.2
V 50mV
P æ 0.2 ö
f Lo = fs = ç ÷ (5kHz) = 318.31 Hz
p è p ø
Fig.7.44 : Example 7.10

Q.1 What is meant by frequency response of an amplifier ?

Ans : The frequency response is the graph of voltage gain versus input frequency.
Q.2 What is midband range ?
Ans : The midband range is the region where coupling and bypass capacitors act as short-circuits,
and stray and transistor capacitances act as open circuits. In this region, the voltage gain is
almost a constant.
Q.3 What is meant by – 3 dB frequency ?
Ans : – 3 dB frequency, f–3 dB, is one at which the power is reduced to one-half of the maximum
magnitude.
Q.4 Define the term bandwidth of an amplifier.
Ans : The bandwidth (BW) of an amplifier is defined as the difference between the half-power
points or –3 dB frequencies.
Q.5 What is decibel power gain ?
Ans : Decibel power gain is defined as 10 times the common logarithm of the power gain i.e.,
A p (dB) = 10 log10 A p
Q.6 What is decibel voltage gain ?

Ans : Decibel voltage gain is defined as 20 times the common logarithm of the voltage gain i.e.,
Av (dB) = 20 log10 Av
Q.7 Why sometimes, in frequency response plot, it becomes necessary to plot frequency on
logarithmic scale ?
Ans : The frequency plot on logarithmic scale, in case of frequency response plot, becomes
necessary so as to accommodate large frequency ranges. On a linear graph it would be
impossible to plot any large range of frequencies (for example 1 Hz to 1 MHz) on a single
graph. So the horizontal axis on frequency response plots is normally scaled logarithmically.
Q.8 Define alpha cutoff frequency and beta cutoff frequency and how these are related to
each other.
Ans. The alpha cutoff frequency fa or fhfb is defined as the frequency at which the common
1
base current gain a. (or hfo) falls to or 0.707 of its low-frequency value a() corre-
2
sponding to a 3 dB loss.
The beta cutoff frequency fb or fhfe or foe is defined as the frequency at which common
1
emitter current gain b (or hfe) falls to or 0.707 of its low-frequency value.
2
fb and fa are related as

fb = (1 – a0) fa
Q.9 Define fT of a BJT.
Ans : The fT of a BJT is defined as the frequency at which the short-circuit common emitter
current gain b falls to unity. It is equal to bfb.
Q.10 If fT = 500 MHz and hfe = 100 for a BJT, what is its fb ?
Ans : 5 MHz.
Q.11 What is Miller’s theorem ? ‘
Ans : A feedback impedance from the output to the input of an inverting amplifier is equivalent to
two impedances — one impedance across the input terminals and the other across the
output terminals. This statement is Miller’s theorem.
Q.12 Why do you cascade the amplifiers ?
Ans : The voltage/power gain or frequency response obtainable from a single stage amplifier is
usually not sufficient to meet the needs of either a composite electronic circuit or load
device, so cascading of amplifiers is required to provide greater voltage or current
amplification or both.
Q.13 What is a multistage amplifier circuit ?
Ans : A transistor circuit containing two or more stages of amplification is known as a multistage
amplifier.
Q.14 Which one of the transistor configurations is most suitable for cascading of amplifiers ?
Ans : Common emitter configuration is most widely used configuration in cascading of amplifiers,
because of its high voltage gain.
Q.15 Why R-C coupling is the most widely used coupling between the two stages of a cascaded
amplifier ?
Ans : R-C coupling is the most commonly used coupling between the two stages of a cascaded
or multistage amplifier because it is cheaper in cost, very compact circuit and provides
excellent frequency response.
Q.16 Why the overall gain of a multistage amplifier is less than the product of gains of individual
stages ?
Ans : The overall gain of a multistage amplifier is less than the product of gains of individual
stages because of the loading effects of the following stages.
Q.17 Why coupling capacitor provided in a self biased CE R-C coupled amplifier is also called
the blocking capacitor ?
Ans : In a self biased R-C coupled CE amplifier, coupling capacitor transmits ac signal but blocks
the dc voltage of the first stage from reaching the base of the next stage, so it is also called
the blocking capacitor.
Q.18 Why does R-C coupling give constant gain over mid frequency range ?
Ans : In mid-frequency range, the voltage gain of an R-C coupled amplifier remains almost
constant. This is because in mid-frequency range, with the increase in frequency, the
reactance of the coupling capacitor decreases thereby increasing the gain but at the same
time lower capacitive reactance causes higher loading resulting in lower voltage gain.
Thus the two effects neutralize each other and uniform gain is obtained in mid-frequency
range. What is meant by bandwidth ?
Q.19 The difference between the upper cutoff frequency f2 and lower cutoff frequency f1 is
called the bandwidth.
EXERCISE
1. An amplifier has an input signal of 20 V peak-to-peak and an input impedance of 400 kW.
It gives an output of 10 V peak-to-peak across a load resistance of 5 W. Calculate the
power gain in dB. [Ans. 43 dB]
2. Given that the 40397 transistor has fT = 80 MHz and hfe = 224 at 1 kHz. Calculate the a
and b cutoff frequencies for the 40397. [Ans. 96 MHz; 357 kHz]
3. The output power of an amplifier is 100 mW when the signal frequency is 5 kHz. When
the frequency is increased to 25 kHz, the output falls to 50 mW. Calculate the dB change
in power. [Ans. - 3 dB]
4. For the two-stage R-C coupled low level audio amplifier shown in Fig. 1, compute the
following :
Fig.7.45
(i) ri , (ii) Av1 , (iii) Av2 , (iv) Av in dB. Neglect VBE and take re = 25 mV/IE
[Ans. (i) 1.247 kW (ii) 80 (iii) 320 (iv) 88 dB]
5. An R-C coupled amplifier has a voltage gain of 200 in the frequency range of 200 Hz and
20 kHz. On either side of these frequencies, the gain falls to 141.5 at 25 Hz and 40 kHz.
Determine the bandwidth. [Ans. 25 Hz to 40 kHz]
ppp
259
Compound Configurations
8.1 INTRODUCTION
The configuration in which more than one devices (FET, BJT, MOSFET) are connected
together is called compound configuration. There are different types of configurations :
cascade, cascode, darlington etc.
Here also we will discuss current mirror and differential amplifier circuits.
8.2 CASCADE CONNECTION
A popular connection of amplifier stages is the cascade connection. Basically, a cascade
connection is a series connection with the output of one stage then applied as input to the
second stage. Figure 8.1 shows a cascade connection of two FET amplifier stages. The
cascade connection provides a multiplication of the gain of each stage for a larger overall
gain.
The gain of the overall cascade amplifier is the product of stage gains A v1 and A v 2 ,
A v = A v1 A v2 = (-g m1 R D1 )(-g m 2 R D2 )
Fig. 8.1 : Cascaded FET amplifier.

The small signal model is given by the following.
Fig. 8.2 : Small signal model of cascade FET amplifier

The input impedance of the cascade amplifier is that of stage 1,
Zi = R G i
while the output impedance is-that of stage 2,
Zo = R D 2
The main function of cascading stages is the larger overall gain achieved.
Example-8.1
Calculate the dc bias, voltage gain, input impedance, output impedance, and the resulting
output voltage for the cascade amplifier shown in Fig. 8.3. Calculate the load voltage if a
10-kW load is connected across the output.
Fig 8.3 Cascade amplifier circuit for Example 8.1.

Solution
Both amplifier stages have the same dc bias. Using dc bias techniques,
VGSQ = -1.9 V, I DQ = 2.8 mA
Both transistors have
2I DSS 2(10mA)
g m0 = = = 5mS
VP -4 V
Compound Configurations 261
and at the dc bias point,
æ VGSQ ö æ -1.9V ö
g m = g m0 ç1 - ÷÷ = (5mS) ç1 -
ç
è VP ø è -4V ÷ø = 2.6 mS
The voltage gain of each stage is
A v1 = A v 2 = -g m R D = -(2.6mS)(2.4 kW) = -6.2
The cascade amplifier voltage gain is
A v = A v1 A v2 = (-6.2)(-6.2) = 38.4
Vo = A v Vi = (38.4)(10 mV) = 384 mV
The cascade amplifier input impedance is
Zi = ZG = 3.3 MW
The cascade amplifier output impedance (assuming that rd = ¥ ) is
Z0 = RD = 2.4 kW
The output voltage across a 10-kQ load would then be
RL 10 kW
VL = Vo = (384 mV) = 310 mV
Zo + R L 2.4 kW + 10 kW
BJT Cascade Amplifier
An RC-coupled cascade amplifier built using BJTs is shown in Fig. 8.4. The advantage of
cascading stages is the large overall voltages gain. The value of r e is obtained using DC
biasing.
Fig. 8.4 : Cascaded BJT amplifier (RC-coupled)

The small signal model is given as follows.
Fig. 8.5 : re-model of cascasde BJT amplifier

The voltage gain of each stage is
-R C || R L
Av =
re
The amplifier input impedance is that of stage 1,
Zi = R1 || R 2 || b re
and the output impedance of the amplifier is that of stage 2,
Zo = R C || ro
Example-8.2
Repeat example 8.1 for following figure.
Fig. 8.6 RC-coupled BJT amplifier

Solution
DC bias analysis results in
VB = 4.7 V, VE = 4.0V, VC = 11V, IE = 4.0 mA
At the bias point,
26 26
re = = = 6.5 W
I E 4.0
The voltage gain of stage 1 is then
R C || (R1 || R 2 || bre )
A v1 = -
re
(2.2 kW) || [15 k W || 4.7 kW || (200)(6.5 W)]

=-
6.5 W
665.2 W
=- = -102.3
6.5 W
while the voltage Gain of stage 2 is
RC 2.2 kW
A v2 = =- = -338.46
re 6.5 W
for an overall voltage gain of
A v = A v1 A v2 = (-102.3)(-338.46) = 34,624
The output Voltage is then
Vo = A v Vi = (34,624)(25mV) = 0.866 V
The amplifier input impedance is
Zi = R 1 || R 2 || b re = 4.7 kW ||15 kW || (200)(6.5W )
= 953.6 W
while the amplifier output impedance is
Zo = R C = 2.2 kW
If a 10-kW load is connected to the amplifier output, the resulting voltage across the load is
RL 10 kW
VL = Vo = (0.866 V) = 0.71 V
Zo + R L 2.2 kW + 10 kW
Example-8.3
For the cascade amplifier of Fig. 8.7, calculate input impedance, output impedance, voltage
gain, and the resulting output voltage.
Fig. 8.7 : Cascaded JFET-BJT amplifier for Example 8.3

Solution
Since Ri (stage 2) = 15 kW || 4.7 kW || 200 (6.5 W) = 953.6 W, the gain of stage 1 (when
loaded by stage 2) is
A vi = -g m [ R D || R i (stage 2) ]
= – 2.6 mS(2.4 kW || 953.6 W) = –1.77
From Example 8.2, the voltage gain of stage 2 is A v 2 = –338.46. The overall voltage gain
is then
A v = A v1 A v2 = ( -1.77)(-338.46) = 599.1
V0 = AVVi = (599.1)(1 mV) » 0.6 V
The input impedance of the amplifier is that of stage 1,
Zi = 3.3 MW
while the output impedance is that of stage 2,
Z0 = RD = 2.2 kW
8.3 CASCODE CONNECTION
A cascode connection has one transistor on top of (in series with) another. Figure 8.8
shows a cascode configuration with a common-emitter (CE) stage feeding a common-
base (CB) stage. This arrangement is designed to provide a high input impedance with low
voltage gain to ensure that the input Miller capacitance is at a minimum with the CB stage
providing good high-frequency operation.
Fig. 8.8 : Cascode configuration.

The practical cascode amplifier circuit is given in Fig. 8.9
Fig. 8.9 : Practical cascode circuit

Example-8.4
Calculate the voltage gain for the cascode amplifier of Fig. 8.9.
Solution
DC bias analysis using procedures of Chapter 4 result in
VB1 = 4.9 V, VB2 = 10.8V, IC1 » IC2 = 3.8 mA
The dynamic resistance of each transistor is then

26 26
re = = - 6.8 W
I E 3.8
The voltage gain of stage 1 (common-emitter) is approximately
RC r
A v1 = - = - e = -1
re re
The voltage gain of stage 2 (common-base) is
R C 1.8 kW
A v2 = = = 265
re 6.8 W
resulting in an overall cascode amplifier gain of
A v = A v1 A v2 = (-1)(265) = –265
8.4 DARLINGTON CONNECTION
A very popular connection of two bipolar junction transistors for operation as one
“superbeta” transistor is the Darlington connection shown in Fig. 8.10. The main feature
of the Darlington connection is that the composite transistor acts as a single unit with a
current gain that is the product of the current gains of the individual transistors. If the
connection is made using two separate transistors having current gains of b1 and b2 , the
Darlington connection provides a current gain of
bD = b1b 2
Fig. 8.10 : Makeup of Darlington transistor.

If the two transistors are matched so that b1 = b2 = b , the Darlington connection provides
a current gain of
bD = b2
A Darlington transistor connection provides a transistor having a very large current
gain, typically a few thousand.
Fig. 8.11 : Basic Darlington bias circuit.

DC Bias of Darlington Circuit
A basic Darlington circuit is shown in Fig. 8.11. A Darlington transistor having very high
current gain, bD i is used. The base current may be calculated from
VCC - VBE
IB =
R B + bD R E
I E = (bD + 1)I B » bD I B
Dc voltages are
VE = I E R E
VB = VE + VBE
AC Equivalent Circuit
A Darlington emitter-follower
circuit is shown in Fig. 8.12. The ac
input signal is applied to the base of
the Darlington transistor through
capacitor C1, with the ac output, V0,
obtained from the emitter through
capacitor C2. An ac equivalent circuit
is drawn in Fig. 8.13. The Darlington
transistor is replaced by an ac
equivalent circuit comprised of an input
resistance, ri , and an output current
source, b D I b . Fig. 8.12: Darlington emitter-follower circuit.
Fig. 8.13 AC equivalent circuit of Darlington emitter-follower.

AC INPUT IMPEDANCE
The ac base current through ri is
Vi - Vo
Ib =
ri
Since Vo = (I b + b D I b )R E
using above two equations,
I b ri = Vi - Vo = Vi - Ib (1 + bD )R E
Solving for Vi ,
Vi = Ib [ ri + (1 + bD )R E ] » Ib (ri + bD R E )
The ac input impedance looking into the transistor base is then
Vi
= ri + bD R E
Ib
and that looking into the circuit is
Zi = R B || (ri + bD R E )
AC OUTPUT IMPEDANCE
The ac output impedance can be determined for the ac circuit shown in Fig. 8.14a.
The output impedance seen by load RL is determined by applying a voltage V0 and measuring
the current I0 (with input Vs set to zero). Figure 8.14b shows this situation. Solving for I0
yields
Vo Vo V V æV ö
Io = + - bD I b = o + o - bD ç o ÷
RE ri RE ri è ri ø
æ 1 1 b ö
=ç + + D ÷ Vo
è R E ri ri ø
Solving for Z0 gives
Vo 1
Zo = =
Io 1/ R E + 1/ ri + bD / ri
ri r
= R E || ri || » i
bD bD
Fig. 8.14 : AC equivalent circuit to determine Z0.

Example-8.5
For the circuit shown in Fig. 8.15, calculate the d.c. bias voltage, VE2 and emitter current
IE2 .
Fig. 8.15
Solution : The base current

VCC - VBE
IB =
R B + BD R E
This is a circuit of Darlington pair
16V - 1.6 V 14.4 V
\ IB = =
2.4 MW + 6000(510 W) 5.46 MW
or I B = 2.637 mA » 2.64 mA
The emitter current I E = (b + 1) I B » 6000 ´ 2.64 mA
or I E = 15840 mA = 15.84 mA
The emitter d.c. voltage is
VE 2 = VE = I E ´ R E
or VE 2 = (15.84 mA) ´ (510 W) = 8.0784 V » 8.08V
The base voltage is VB = VE + VBE
or VB = 8.08V + 1.6 V = 9.68 V
The emitter current I E 2 = IE = 15.84 mA.
Example-8.6
Calculate the input impedance of the circuit of Fig. 8.12 if ri = 5 kW
Solution
Zi = 3.3 MW||[5 kW + (8000)(390 W)] = 1.6 MW
AC CURRENT GAIN
The ac output current through RE is (see Fig. 8.13)
Io = I b + bD I b = (b D + 1)Ib » b D Ib
The transistor current gain is then
Io
= bD
Ib
The ac current gain of the circuit is
I o Io I b
Ai = =
Ii I b Ii
We can use the current-divider rule to express I b / Ii :
RB RB
Ib = Ii » Ii
(ri + bD R E ) + R B R B + bD R E
so that the ac circuit current gain is
RB bD R B
A i = bD =
R B + bD R E R B + bD R E
Example-8.7
Calculate the output impedance of the circuit in Fig. 8.12
Solution
5kW 5 kW
Zo = 390 W || 5kW || = = 0.625 W
8000 8000
AC VOLTAGE GAIN
The ac voltage gain for the circuit of Fig. 8.12 can be determined using the ac equivalent
circuit of Fig. 8.16. Since
Vo = (I b + bD Ib )R E = I b (R E + bD R E )
and Vi = I b ri + (I b + b D I b )R E
From which we obtain
Vi = I b (ri + R E + b D R E )
Vi
so that Vo = (R E + bD R E )
ri + (R E + bD R E )
Vo R E + bD R E
Av = = =1
Vi ri + (R E + bD R E )
Fig.8.16 : AC equivalent circuit to determine Av.

8.5 CURRENT MIRROR CIRCUITS
A current mirror circuit (see Fig.8.17) provides a constant current and is used primarily in
integrated circuits. The constant current is obtained from an output current, which is the
reflection or mirror of a constant current developed on one side of the circuit. The circuit
Fig. 8.17 : Current mirror circuit.

is particularly suited to IC manufacture since the circuit requires that the transistors used
have identical base-emitter voltage drops and identical values of beta—results best achieved
when transistors are formed at the same time in IC manufacture. In Fig. 8.17, the current
Ix, set by transistor Q1 and resistor Rx, is mirrored in the current I through transistor Q2.
The currents Ix and I can be obtained using the circuit currents listed in Fig. 8.18. We
assume that the emitter current (IE) for both transistors is the same. The two transistor
base currents are then approximately
IE I
IB = » E
b +1 b
The collector current of each transistor is then
IC » I E
Finally, the current through resistor Rx, Ix, is
2I E b IE 2I E b + 2
IX = IE = = + = IE » I E
b b b b
In summary, the constant current provided at the collector of Q2 mirrors that of Q1.
Since
VCC - VBE
IX =
RX
the current Ix set by VCC and Rx is mirrored in the current into the collector of Q2. Transistor
Q1 is referred to as a diode-connected transistor because the base and collector are shorted
together.
Fig. 8.18 : Circuit currents for current-mirror circuit.

Example-8.8
Calculate the mirrored current / is the circuit
of Fig. 8.19
Fig. 8.19
Solution :
The constant current provided at the collector
of Q2 mirror is that of Q1 .
VCC - VBE
Since Ix =
Rx
The current Ix set by VCC and Rx is mirrored

is the current into the collector of Q2.
VCC + VBE Fig. 8.19 (a)
There I = Ix =
Rx
18V - 0.7 V 17.3 V

or I= = = 8.65 mA
2 kW 2 kW
Example-8.9
Calculate the current I, through each of the
transistors Q2 and Q3 in the following circuit.

In current mirror circuits, we assume that the emitter current IE for all the transistors are
the same (Q1, Q2 and Q3 being fabricated near each other on the same chip).
The three base currents are approximately
IE I
IB = » E
b +1 b
The collector current of each transistor is then
IC » I E
finally, the current through resistor Rx
Ix is Ix = IE + 3 IB
IE b + 3
or Ix = IE + 3 = IE » IE
b b
VCC - VBE
Therefore I = Ix =
Rx
8V - 0.7 V 7.3V
or I= =
2.5 2.5kW
Figure 8.21 shows another form of current mirror to provide higher output impedance
than that of Fig. 8.17. The current through RX is
VCC - 2VBE I b +1
IX = » IE + E = IE » IE
RX b b
Assuming that Q1 and Q2 are well matched, the output current, I, is held constant at
I » IE = IX
Again we see that the output current I is a mirrored value of the current set by the fixed
current through RX.
Figure 8.22 shows still another form of current mirror. The JFET provides a constant
currentsetatthe valueofIDSS. This current is mirrored, resulting in a current through Q2
of the same value:
I = IDSS
Fig. 8.21 : Current mirror Fig. 8.22: Current mirror circuit

connection with higher output impedance.
8.6 DIFFERENTIAL AMPLIFIER CIRCUIT
The differential amplifier circuit is an extremely popular connection used in 1C units.
This connection can be described by considering the basic differential amplifier shown in
Fig. 8.23. The circuit has two separate inputs, two separate outputs, and that the emitters
are connected together. The circuit can also operate using a single supply.
A number of input signal combinations are possible:
If an input signal is applied to either input with the other input connected to ground,
the operation is referred to as “single-ended.”
If two opposite polarity input signals are applied, the operation is referred to as
“double-ended.”
If the same input is applied to both inputs, the operation is called “common-mode.”
Fig. 8.23 : Basic differential amplifier circuit.

In single-ended operation, a single input signal is applied. However, due to the common-
emitter connection, the input signal operates both transistors, resulting in output from both
collectors.
In double-ended operation, two input signals are applied, the difference of the inputs
resulting in outputs from both collectors due to the difference of the signals applied to both
inputs.
In common-mode operation, the common input signal results in opposite signals at
each collector, these signals canceling so that the resulting output signal is zero. As a
practical matter, the opposite signals do not completely cancel and a small signal results.
The main feature of the differential amplifier is the very large gain when opposite
signals are applied to the inputs as compared to the very small gain resulting from common
inputs. The ratio of this difference gain to the common gain is called common-mode
rejection.
DC Bias
Fig. 8.24 DC bias of differential amplifier circuit.

VE = 0 V - VBE = -0.7 V
The emitter dc bias current is then
VE - (-VEE ) VEE - 0.7 V
IE = »
RE RE
Assuming that the transistors are well matched,
IE
IC1 = IC2 =
2
resulting in a collector voltage of
IE
VC1 = VC2 = VCC - IC R C = VCC - RC
2
Example-8.10
Calculate d.c. bias values of Ic and Vc for the watched transistor of figure given below :
Fig. 8.25
Solution
Fig. 8.25 (a)

Now VE = VB - VBE = 0 - 0.7 V
or VE = -0.7 V
The emitter d.c. bias current is then
VE - (-VEE ) VEE - 0.7 V
IE = »
RE RE
15 - 0.7 V 14.3 V
or IE = = = 3.0425 mA
4.7 kW 4.7 kW
The collector current is then
I E 3.0425 mA
IC = = = 1.521 mA
2 2
i.e I C1 = I C 2 = I C = 1.521 mA
Resulting in a collector voltage of
VC1 = VC2 = VC , which equals from diagram to
VC = VCC - IC R C = 15 V - (1.521 mA)(4.7 kW)
or VC = 15V - 7.15 V = 7.85 V
The common emitter voltage is thus – 0.7 V, while the collector bias voltage is 7.85 V for
both outputs.
AC Operation of Circuit
An ac connection of a differential
amplifier is shown in Fig. 8.26.
Separate input signals are applied as
Vi1 and Vi2 , with separate outputs
resulting as Vo1 and Vo2 . To carry

out ac analysis, the circuit is redrawn
in Fig. 8.27. Each transistor is replaced
by its ac equivalent.
Fig. 8.26 AC connection of differential amplifier.
Fig. 8.27 AC equivalent of differential amplifier circuit.

SINGLE-ENDED AC VOLTAGE GAIN

To calculate The single-ended ac voltage gain, Vo/Vi, apply signal to one input with the
other connected to ground, as shown in Fig. 8.28. The ac equivalent of this connection is
drawn in Fig. 8.29.
Fig. 8.28 Connection to calculate A v1 = Vo1 / Vi1
Fig. 8.29 AC equivalent of circuit in Fig. 8.28

1 input KVL equation. If one assumes that the two transistors are well matched, then
I b1 = I b2 = I b
ri1 = ri2 = ri
With RE very large (ideally infinite), the circuit for obtaining the KVL equation simplifies to
that of Fig. 8.30, from which we can write
Vi1 - Ib ri - I b ri = 0
Vi1
so that Ib =
2ri
If we also assume that
b1 = b2 = b
b Vi1
then IC = bIb = b
2ri
and the output voltage magnitude at either collector is
Vi1 bR C
Vo = IC R C = b RC = Vi
2r1 2b re
for which the single-ended voltage gain
magnitude at either collector is
Vo R C
Av = =
Vi1 2re
Fig. 8.30 Partial circuit to calculate I b .

Example-8.11
Calculate Vo in the circuit is shown in Fig. 8.31
Fig. 8.31
Solution :
This is the circuit incorporating a.c operation with single-ended a.c. voltage gain.
Given Vi1 = 2 mV and Vi2 = 0
The d.c. bias calculation provide
VEE - 0.7 V 12 V - 0.7 V
IE = =
RE 33kW
11.3 V
or IE = = 342.42 m A
33kW
The collector d.c. current is then
IE
IC = = 171.212 mA
2
Now, collector voltage
VC = VCC - I C R C = 12 V - (171.212 mA)(36 kW)
or VC = 12 V - 6.164 V = 5.836 V
26 mV IE
The value of re is re = (I / 2) , because, is the emitter current for each transistor..
E 2
26 mV
or re = = 151.86 W
0.1712 mA
The a.c. voltage gain magnitude can be calculated using the relation
Vo R C 36 kW
Av = = or Av = = 118.53
Vi1 2 re 2 ´ 151.36 W
Hence, output as voltage Vo = A v Vi1 = (118.53)(2 mV) = 237 mV
or required Vo = 237 mV = 0.237 V
Double-Ended AC Voltage Gain
A similar analysis could also be used to show that for the condition of signals applied to
both inputs, the differential voltage gain magnitude would be
Vo bR C
Ad = =
Vd 2ri
where Vd = Vi1 - Vi 2
Common-Mode Operation of Circuit
While a differential amplifier provides large amplification of the difference signal applied
to both inputs, it should also provide as small an amplification of the signal common to both
inputs. An ac connection showing common input to both transistors is shown in Fig. 8.32.
The ac equivalent circuit is then drawn in Fig. 8.33, from which we can write
Vi - 2(b + 1)I b R E
Ib =
ri
which can be rewritten as
Vi
Ib =
ri + 2(b + 1)R E
The output voltage magnitude is then
bVi R C
Vo = IC R C = bI b R C =
ri + 2(b + 1)R E
providing a voltage gain magnitude of
Vo bR C
Ac = =
Vi ri + 2(b + 1)R E
Fig. 8.32 Common-mode connection.
Fig. 8.33 AC circuit in common-mode connection.

Example-8.12
For the differential amplifier circuit shown in Fig. 8.34, calculate the differential gain, the
common mode gain and the CMRR.
Fig. 8.34
Given that T1 and T2 are identical with the h-parameters hie = 2 K, hre = 8 × 10–4, hfe = 100,
hoe is negligible.
Solution : Given VCC = + 12 V, VEE = – 12 V
Circuit shown is of emitter-coupled differential amplifier.
The circuit is bisected for two differential modes are shown:
Fig. 8.34 (a)

VS
For differential mode, VS becomes , and
2
For common mode, RE becomes 2 RE.
Substituting the hybrid model for differential mode
Fig. 8.34(b)
Here, hoe neglected.
Applying KVL to first loop yields.
VS1
= (2.1kW) Ib1 + 8 ´ 10-4 Vo ... (1)
2
and Vo = -(2 kW)100 Ib1 = -200 Ib1 ... (2)
Putting value of Vo from 92) in Eq. (1), we get
VS1
= 2.1 Ib1 - 8 ´ 10-4 ´ 200 Ib1 = 1.94 Ib1
2
Þ VS1 = 2 ´ 1.94 I b1 = 3.88 I b1 ... (3)
From equations (2) divided by (3), we get
Vo 200
=-
VS1 3.88
200
or differential gain A d = - = -51.55
3.88
Substituting the hybrid model for common mode
Fig. 8.34(c)
From KVL
VS2 = 2.1I1 + 8 ´ 10-4 Vo + (2kW)(101 I1 )
Þ VS2 = 204.1 I1 + 8 ´ 10-4 Vo ... (4)
Also Vo = -200 I1 ... (5)

Putting the value of Vo from Eqs (5) into (4) yields
VS2 = 204.1 I1 + 8 ´ 10-4 (-200 I1 )
Þ VS2 = 204.1 I1 - 0.16 I1 = 203.94 I1 ... (6)
From Eqs (S) divided by (6), we get
Vo -200 I1 200
= =-
VS2 203.94 I1 203.94
or Common mode gain
Vo 200
AC = =- = -0.981
VS2 203.94
Now, common mode rejection ratio is given by
Ad 51.5
CMRR = = = 52.5
A c 0.981
Example-8.13
For the cascaded amplifier shown, find
input impedance, output impedance,
current gain and voltage gain for
individual stage as well as for overall
amplifier.
Take R S = 1 kW, R C1 = R e2 = 2 kW,

and use standard values of the
h-parameters.
Solution :
The circuit shown is a CE – CC configuration Fig. 8.35
The h-parameters are :
CE CC
hi 1.1 kW 1.1 kW
–4
hr 2.5 × 10 1
hf 50 –51
ho 25 ms 25 ms
For second stage amplification (CC stage) :
-h fe 51
current gain A i2 = =
1 + h oe R e2 1 + 25 ´ 10-6 ´ 2 ´ 103
or A i2 = 48.57
Input impedance R i 2 = h ic + h rc A i2 R e2 = 1.1 + 1 ´ 48.57 ´ 2
= 98.24 kW
R e2
voltage gain A v2 = Ai 2 ´
R i2
48.57 ´ 2 kW
or A v2 = = 0.99 = 1
98.24 kW
For first stage (CE stage) :
R C1R i2 (2kW) ´ (98.24 kW)
Effective load R L1 = =
R C1 + R i2 100.24 kW
= 1.96 kW
-h fe -50
current gain A i1 = =
1 + h oe R L1 1 + 25 ´ 10-6 ´ 1.96 ´ 103
or A i1 = -47.66
input impedance
R i1 = h ie + h re A i1R L1
or R i1 = 1.1kW + 2.5 ´ 10-4 (-47.46)(1.96) = 1.08kW
R L1
voltage gain A v1 = A i1 ´
Ri1
1.96 kW
= (-47.46) ´ = -47.46 ´ 1.815
1.08kW
or A vi = -86.13
-1
æ h h ö
output Impedance R o1 = ç h oe fe re ÷
è h ie + R S ø
-1
æ -6 50 ´ 2.5 ´ 10-4 ö
or R = ç 25 ´ 10 - ÷
1100 + 100 ø
o1
è
= 68.59 kW
output impedance taking RC1 into account is
R ¢o1 = R C1 || R o1 = (69.59 kW) || (2 kW)
68.59 ´ 2
or R ¢o1 = - 1.94 kW
68.59 + 2
For overall cascade amplifier

Output impedance
-1
æ h h ö
R o = ç h oc - fe re ÷ , R ¢S2 = R ¢o1
è h ic + R ¢S2 ø
-1
æ 1 ´ (-51) ö
or R o = ç 25 ´ 10-4 - ÷ = 49.94 W
è 1100 + 1940 ø
Output impedance taking Re2 into account is
R ¢o = R o || R e2 = (49.94 W) || (2000 W)
49.94 ´ 2000
= = 48.72 W
2049.94
R C1
current gain A i = Ai1 A i2
R i2 + R e1
2
= (-47.66) (48.57) = -46.19
2 + 98.24
voltage gain A v = A v1 + A v 2 = (-86.13)(0.99)
= –85.27

Q.1 Why do you cascade the amplifiers ?
Ans. The voltage / power gain or frequency response obtainable from a single stage amplifier is
usually not sufficient to meet the needs of either a composite electronic circuit or load
device, so cascading of amplifiers is required to provide greater voltage or current
amplification or both.
Q.2 What is a multi-stage amplifier circuit?
Ans. A transistor circuit containing two or more stages of amplification is known as a multi-
stage amplifier.
Q.3 What are the various coupling schemes used in cascaded amplifiers ?
Ans. The various coupling schemes used in cascaded amplifiers are
(i) R-C coupling (ii) transformer coupling (iii) impedance coupling and (iv) direct coupling.
Q.4 Which one of the transistor configurations is most suitable for cascading of amplifiers?
Ans. Common emitter configuration is most widely used configuration in cascading of amplifiers,
because of its high voltage gain.
Q.5 Why R-C coupling is the most widely used coupling between the two stages of a cascaded
amplifier ?
Ans. R-C coupling is the most commonly used coupling between the two stages of a cascaded
or multistage amplifier because it is cheaper in cost, very compact circuit and provides
excellent frequency response.
Q.6 Why the overall gain of a multi-stage amplifier is less than the product of gains of individual
stages ?
Ans. The overall gain of a multi-stage amplifier is less than the product of gains of individual
stages because of the loading effects of the following stages.
Q.7 Why coupling capacitor provided in a self biased C E R-C coupled amplifier is also called
the blocking capacitor ?
Ans. In a self biased C E R-C coupled amplifier, coupling capacitor transmits ac signal but
blocks the dc voltage of the first stage from reaching the base of the next stage, so it is also
called the blocking capacitor.
Q.8 Why does R-C coupling give constant gain over mid frequency range ?
Ans. In mid frequency range, the voltage gain of an R-C coupled amplifier remains almost
constant. This is because in mid frequency range, with the increase in frequency, the
reactance of the coupling capacitor decreases thereby increasing the gain but at the same
time lower capacitive reactance causes higher loading resulting in lower voltage gain.
Thus the two effects neutralize each other and uniform gain is obtained in mid frequency
range.
Q.9 What is meant by bandwidth ? Ans. The difference between the upper cut-off frequency
f2 and lower cut-off frequency f1 is called the bandwidth.
Q.10 Why are R-C coupled amplifiers widely used as voltage amplifiers ?
Ans. R-C coupled amplifiers are widely used as voltage amplifiers because of their excellent
audio-fidelity over a wide range of frequency.
Q.11 How do you improve the gain of an R-C coupled amplifier at low frequencies ?
Ans. The voltage gain of an R-C coupled amplifier at low frequencies can be improved by
(i) selecting very large coupling and bypass capacitors so that their reactance is small
(ii)making (RS + RB) << (RC + RL) and (iii) selecting transistor with small hie.
Q.12 Why a bypass capacitor is used on the bottom of each secondary winding in a transformer-
coupled amplifier ?
Ans. In a transformer-coupled amplifier, bypass capacitor is used on the bottom of each
secondary winding to get an ac ground and to prevent the loss of signal power in the
biasing resistors
Q.13 Why coupling-capacitors are not required in a transformer-coupled amplifier?
Ans. No coupling capacitor is required in a transformer-coupled amplifier, because dc isolation
between the two stages is provided by the transformer itself ?
Q.14 What type of coupling would you use for amplification of a signal obtained from a thermo-
couple meant for measuring temperature of a furnace ?
Ans. Direct-coupling.
Q.15 Why direct-coupling is not suitable for amplification of high frequency signals ?
Ans. At high frequency, the gain of the direct-coupled amplifier falls off due to inter-electrode’
capacitance of the device and wiring capacitance, so it is not used for amplification of high
frequency signals.
Q.16 What is drift in dc amplifiers?
Ans. Drift in dc amplifier refers to the shift or change of the operating point.
Q.17 Name the drift compensation techniques used in the design of dc amplifiers.
Ans. The techniques that can be used for stabilizing the quiescent point are
(i) diode compensation (ii) thermistor compensation (iii) sensistor compensation
Q.18 Three identical cascaded amplifier stages has an overall upper 3 db cut-off frequency of
200 kHz. What is upper 3 db cut-off frequency of each stage?
f 2n 200 ´ 103
Ans. fe = = = 392.3 K Hz
21/ n - 1 21/ 3 - 1
Q.19 What are the main characteristics of a Darlington amplifier ?
Ans. The main characteristics of a Darlington amplifier are high input impedance, low output
impedance and high current gain.
Q.20 What are the main characteristics of cascode amplifier ?
Ans. The main characteristics of cascode amplifier are high input impedance, the same voltage,
gain as that of a CE amplifier but very low input capacitance so as to provide good high
frequency operation.
EXERCISE
1. Anam plifierhasan inputsignalof20V peak-to-peakand an inputimpedanceof400 kW.

It gives an output of 10 V peak-to-peak across a load resistance of 5 W. Calculate the
power gain in db. [Ans. 43 db]
2. The output power of an amplifier is 100 mW when the signal frequency is 5 k Hz. When
the frequency is increased to 25 kHz, the output falls to 50 mW. Calculate the db change
in power. [Ans. – 3 db]
3. An R-C coupled amplifier has a voltage gain of 200 in the frequency range of 200 Hz and
20 k Hz. On either side of these frequencies, the gain falls to 141.5 at 25 Hz and 40 k Hz.
Determine the bandwidth.
[Ans. 25 Hz to 40 kHz]
4. Determine the necessary transformer turn-ratio for transferring maximum power to a load
resistors of 8 W from a source of impedance 5 k W. [Ans. 25 : 1]
ppp
Feedback Amplifiers
9.1 INTRODUCTION
While studying the amplifiers, we have given due consideration on their characteristics
such as voltage gain, input impedance, output impedance and bandwidth. All these
parameters are almost constant for a given amplifier i.e., an amplifier has more or less
fixed value of these parameters and the designer does not have any control over these
parameters. However, in general practice, the values of these parameters are required to
be changed as per the need. This can be done by different ways such as gain could be
reduced by using voltage divider network in the input or in the output circuit of the amplifier;
the input and output impedances could be controlled by connecting resistors in series or in
parallel with the terminals concerned. But all these methods result in wastage of signal
power. Therefore, these techniques are rarely employed in practice. A much more powerful
technique available with us for modifying amplifier characteristics is feedback technique.
The amplifiers in which feedback is employed are known as feedback amplifiers.
The feedback circuits not only modify the characteristics of the amplifier but they also
improve stability in gain, reduce phase and frequency distortion and reduce the noise level
at the output. In this chapter, we shall discuss the effects and methods of providing negative
feedback in the transistor amplifiers.
9.2 THE FEEDBACK CONCEPT
The process by which a fraction of output energy of a device (amplifier) is injected
back to its input is known as feedback.
In a feed back network the main parts are -
i) signal source
ii) Basic amplifier
Feedback Amplifiers 291
iii) Sampler / sampling Network

iv) Feedback network
v) Mixer / mixing network
Fig. 9.1 Representation of any single-loop feedback connection around a basic

amplifier. The transfer gain A may represent Av, AI, GM or RM.
Signal Source :
This may be a voltage source or a current source, that supplies the signal to the basic
amplifier.
Basic amplifier :
This may be voltage amplifier, current amplifier, trans-conductance amplifier or a
trans-resistance amplifier. The ratio of output to the input of the basic amplifier is known
as gain (A).
Sampling network :
The output of the basic amplifier is given to the feedback network with the help of
sampling network or sampler. There are two types of sampling
i) Voltage or shunt or node sampling.
ii) Current or series or loop sampling.
Fig. 9.2 Feedback connections at the output of a basic amplifier, sampling the
output (a) voltage and (b) current
Feedback network :
This is the network that decides how much percentage of the output will be given as
feedback. The gain of the feedback network is given by b.
Mixer network :
This network does the mixing of the source signal with the feedback signal. There are
two types of mixing.
i) Shunt or current or node mixing.
ii) Series or voltage or loop mixing.
Fig. 9.3 Feedback connections at the input of a basic amplifier.

(a) Series comparison. (b) Shunt mixing.
9.3 TYPES OF FEEDBACK
i) Positive feedback or regenerative feedback :
When Feedback energy of a device (amplifier) is inphase with the input signal, it is
known as positive feedback.
The positive feedback is also known as regenerative or direct feedback.
- It increases the gain of the amplifier.
- It increases the noise, distortion.
- It decreases the stability.
- It is used in oscillator circuits.
ii) Negative or degenerative Feedback :
When feedback energy of the amplifier is 1800 out of phase with the input signal and
thus opposes it then it is known as negative feedback.
It is also known as degenerative feedback or reverse feedback.
- It decreases the gain of the amplifier.
- It decreases noise, distortion.
- It increases the stability.
- It is used in amplifier circuits.
9.4 PRINCIPLE OF FEEDBACK IN AMPLIFIERS

For an ordinary amplifier (i.e. one without feedback), the
voltage gain equals the ratio of output voltage and input
voltage, as illustrated in fig. 9.4. Fig. 9.4
i.e. Voltage gain, A = Vout
Vin
The gain is called the open-loop gain.
Let a fraction (say b) of the output voltage Vout be supplied back to the input and A be the
Vout
open-loop gain (i.e. A = V ). Now the input voltage becomes
in
Vin = Vs + Vf = Vs + b Vout in case of positive feedback

and Vin = Vs – Vf = Vs – b Vout in case of negative feedback
i.e. Vin = Vs ± bVout depending on whether the feedback voltage is in phase with or in
phase opposition to the input signal voltage.
Consider a negative feedback case. The actual input voltage to the amplifier is the
signal voltage Vs less feedback voltage Vf ( (bVout).
i.e. Actual input voltage to amplifier, Vin = Vs – b Vout
The output voltage Vout must be equal to the input voltage (Vs – b Vout) multiplied by
amplifier gain A. So
Output voltage, Vout = A (Vs – b Vout)
or (1 + b A) Vout = A Vs
Vout A
or =
Vs 1 + bA
Vout
But V is called the voltage gain of the amplifier with feedback, Af . This is also referred
s
to as closed-loop gain.
Vout A
Thus voltage gain with negative feedback, A f = V = 1 + bA
s
A
Similarly voltage gain with positive feedback, A f = 1 - b A
The term b A is called the feedback factor whereas b is known as the feedback
ratio and (1 ± b A) is known as loop gain.
In general both A and b are phasor quantities (having magnitude as well as phase).
Every amplifier stage introduces a phase shift of 180° (assuming CE configuration, as
usual). Thus for a 3-stage amplifier, total phase shift between the output and input will be
3 x 180° = 540° or 180°. b is usually arranged to have a phase value of 0° or 180° (i.e.
either inphase with input signal voltage or in phase opposition to it).
Since (1 – b A) is a complex quantity, it can be observed that
1. If (1 – b A) is less than unity, then for positive feedback, Af exceeds A. This condition
corresponds to positive feedback because voltage feedback adds to input signal voltage
and increases input voltage Vin. Positive feedback, though, increases the gain but it reduces
the stability and increases the distortion and so it is usually avoided.
2. If (1 – b A) is equal to zero then the gain Af becomes infinite. This is only possible
when input is zero. Thus the amplifier is then capable of giving output voltage even with
zero signal. Under such situation the circuit operates as an oscillator.
3. If (1 – b A) is greater than unity then Af is smaller than A. This means the feedback
voltage Vin becomes smaller than input signal voltage Vs. This corresponds to negative
feedback in an amplifier. Though negative feedback reduces the gain of the amplifier but
improves its performance in several aspects, given in the succeeding Articles. It may be
noted that negative voltage feedback does not affect the current of the circuit.
Note : The assumptions made in investigating the effect of negative feedback on the
amplifier characteristics are
1. Basic amplifier is unilateral from input to the output.
2. Passive feedback network is unilateral and transmits a signal from the output to the
input but not in the opposite direction.
3. Feedback network presents no loading on the output of the basic amplifier.
4. There is no forward transmission through the P feedback network.
Example-9.1
An amplifier with voltage gain of 60 db uses 1 20 of its output in negative feedback.

Calculate the gain with feedback in db.
Solution :
60
Open-loop voltage gain, A = 60 db or antilog = 1,000
20
1
Feedback ratio, b = = 0.05
20
A 1,000
Gain with feedback, A f = = = 19.6 or 20 log10 19.6 db = 25,85 db
1 + b A 1 + 0.05 ´ 1,000
Ans
Example-9.2
Voltage gain of an amplifier without feedback is 60 db. It decreases to 40 db with feedback.
Calculate the feedback factor.
Solution :
Voltage gain of amplifier without feedback, A = 60 db or 1,000
Voltage gain with feedback, Af = 40 db or 100 Q 20 log Af = 40 db or Af = 100
A
\ Gain with feedback, A f =
1 + bA
A 1,000
or Feedback factor, b A = -1 = -1 = 9 Ans.
Af 100
Example-9.3
A single stage transistor amplifier has a voltage gain of 600 without feedback, and 50 with
feedback. Calculate the %age of output which is feedback to the input.
Solution :
Voltage gain without feedback, A = 600
Voltage gain with feedback, Af = 50
A
QAf =
1 + bA
600
\ 50 =
1 + 600 b
or b = 0.01833
Percentage of output voltage that is feedback to the input
Vf
= ´ 100 = b ´ 100 = 0.01833 × 100 = 1.833% Ans.
Vout
Example-9.4
An amplifier with a negative feedback provides an output voltage of 5 V with an input
voltage of 0.2 V. On removal of feedback, it needs only 0.1 V input to give the same
output. Determine (i) gain without feedback (ii) gain with feedback and (iii) feedback
ratio.
Solution :
Output voltage 5
Gain without feedback, A = Input voltage without feedback = = 50 Ans.
0.1
Output voltage 5
Gain with feedback, A f = Input voltage with feedback = = 25 Ans.
0.2
A
Now since A f =
1 + bA
50
\ 25 =
1 + 50 b
50
-1
25
or Feedback ratio = = 0.02 Ans.
50
Example-9.5
A negative feedback of b = 0.002 is applied to an amplifier of gain 1,000. Calculate the
change in overall gain of the feedback amplifier if the internal amplifier is subjected to a
gain reduction of 15%.
Solution :
Voltage gain without feedback, A = 1,000
b = 0.002
A 1,000
Voltage gain with feedback, A f = = = 333.33
1 + b A 1 + 0.002 ´ 1,000
When open-loop gain is reduced by 15%
A' = (1 – 0.15) × 1,000 = 850
850
Voltage gain with feedback, A¢f = = 314.8
1 + 0.002 ´ 850
A f - A¢f 333.333 - 314.8
Percentage change in overall gain = ´ 100 = ´ 100 = = 5.6% Ans.
Af 333.333
9.5 ADVANTAGES OF NEGATIVE FEEDBACK
There are numerous advantages of negative feedback which outweigh its only drawback
of reduction in gain. Among the advantages are :
1. Gain Stability. The voltage gain of an amplifier with negative feedback is given as Af
= A / (1 + A b). If A b >> 1 then the expression becomes Af =
1
b
i.e. overall gain of
feedback amplifier Af is independent of internal gain and depends only on feedback
ratio b, and b in turn depends on the passive elements such as resistors. Resistors
remain fairly constant and so the gain is stabilised.
2. Reduced Non-linear Distortion. A large signal stage has non-linear distortion which
is reduced by a factor (1 + A b) when negative feedback is used.
3. Reduced Noise. There is always a noise voltage in the amplifier which is reduced by
a factor (1 + A b) when negative feedback is used.
4. Increased Bandwidth (or Improved Frequency Response). The bandwidth (BW)
of an amplifier without feedback is equal to the separation between 3-db frequencies
f1 and f2. If A is the gain then gain-bandwidth product is A × BW. With the negative
feedback the amplifier gain is reduced and since gain bandwidth product has to remain
constant in both cases, so obviously the bandwidth will increase to compensate for the
reduction in gain.
5. Increased Input Impedance. The input impedance of the amplifier with negative
feedback is increased by a factor (1 + A b).
6. Reduced Output Impedance. The output impedance of the amplifier with negative
feedback is reduced by a factor (1 + A b)
9.5.1 Stabilization of gain with negative feedback
The variations in temperature, supply voltages, ageing of components or variations in
transistor parameters with replacement are some of the factors that affect the gain of an
amplifier and cause it to change. However, the overall gain of the amplifier can be made
independent of these variations if negative feedback is used. This is an important advantage
of negative feedback.
the voltage gain with negative feedback is given as
A A 1
Af = ; ;
1 + b A bA b ... if A b is made much larger than unity
The gain is thus independent of internal gain of the amplifier and depends on the
passive elements such as resistors. The values of resistors remain fairly constant because
they can be chosen very precisely with almost zero temperature coefficient of resistance.
Thus the gain is stabilized.
Even if open-loop gain A is not very large, some improvement in gain stability can be
achieved.
Differentiating equation w.r.t. A we have
d Af (1 + b A) - A ´ b 1 dA
= = or d A f =
dA (1 + b A) 2
(1 + b A) 2
(1 + b A) 2
Dividing above equation by equation (15.4) we have
d Af d A 1+ b A 1 dA
= ´ =
Af A (1 + b A) 2
(1 + b A) A
In negative feedback (1 + b A) >> 1, the percentage change in gain with negative
feedback is less than the percentage change in gain without feedback. Thus negative
feedback improves the gain stability of the amplifier.
Example-9.6
It is desired to design a feedback amplifier with a closed-loop voltage gain of -100.
The closed loop- gain should not vary by more than 1% despite 10% variation in the open-
loop voltage gain. Determine the open-loop voltage gain and the feedback factor for the
amplifier.
dAf 1
Solution : Variation in closed-loop gain, A = 100 = 0.01
f
d A 10
Variation in open-loop gain, = = 0.1
A 100
dAf 1 dA
= .
Af (1 + b A) A
1
or 0.01 = ´ 0.1
1+ bA
0.1
or Feedback factor, b A = -1 = 9 Ans.
0.01
1
Af =
1+ b A
A
so 100 =
1+ 9
or Open-loop voltage gain, A = 100 × 10 = 1,000 Ans.
Example-9.7
An amplifier gain changes by ± 10 %. Using negative feedback, the amplifier is to be
modified to yield a gain of 100 with ± 0.1 % variation. Find the required open-loop gain of
the amplifier and the amount of negative feedback.
Solution:
d A 10
Variation in open-loop gain, = = 0.1
A 100
dAf 0.1
Variation in closed-loop gain, = = 0.001
Af 100
dAf 1 dA
= .
Af (1 + b A) A
1
or 0.001 = 1 + b A ´ 0.1
0.1
or Feedback factor, bA = – 1 = 99
0.001
A
Af =
1+ bA
or Open-loop voltage gain, A = A f (1 + b A) = 100 (1 + 99) = 10,000 Ans.
Af 100 1
Amount of negative feedback = = = Ans.
A 10,000 100
9.5.2 Reduction in Frequency Distortion with Negative Feedback
For a negative feedback amplifier having b A >> 1 the gain with feedback is given as
1
Af @ . It follows from this that if the feedback network is purely resistive, the gain with
b
feedback becomes independent of frequency even though the basic amplifier is frequency
dependent. Practically, the frequency distortion arising because of varying amplifier gain
with frequency is considerably reduced with negative feedback.
9.5.3 Reduction in Non-linear Distortion with Negative Feedback
Harmonic distortion occurs when a transistor or other device is driven beyond its
range of linear operation. Now negative feedback is used and the strength of the input
signal is increased by the same factor by which the gain is reduced. Thus the magnitude of
output signal remains unaltered and thus there is a reduction in harmonic or non-linear
distortion. It may be proved as below.
Let the amplifier with open-loop gain A produce a distortion D in the output signal
without feedback. Now when feedback is applied, output as well distortion is feedback to
the input. Let the gain with feedback be Af and distortion in the output Df. A part b Df of
this distortion is feedback to the input. It gets amplified by factor A and becomes b A Df.
Net distortion, Df = D – b A Df Q distorted output is inphase opposition
D
or Df = 1 + b A
Thus the distortion is reduced by the same factor as the gain.

However, it is to be noted that improvement in distortion is possible only when the
distortion is introduced by the amplifier itself, not when it is already present in the input
signal.
Example-9.8
An amplifier has an input of 10 mV and a gain of 200 without feedback. The distortion
produced at the output of the amplifier is 10%. It is desired to reduce the distortion to 1%
by using negative feedback. Calculate the gain, input voltage and output voltage with
feedback.
Solution: Distortion without feedback, D = 10% = 0.1

Distortion with feedback, Df = 1% = 0.01
Amplifier gain without feedback, A = 200
D
Df =
1+ bA
0.1
or 0.01 = 1 + 200 b
or b = æç ö
0.1
- 1÷ 200 = 0.045 or 4.5%
è 0.01 ø
A 200
Gain with feedback, A f = = = 20 Ans.
1 + b A 1 + 0.045 ´ 200
New output voltage, Vout = Af Vs = 20 × 10 m V = 200 mV or 0.2 V Ans.
New input voltage, Vin = 0.01 V + (– 0.045 × 0.2) = 0.001 V or 1 m V Ans.
Example-9.9
An amplifier with an open-loop voltage gain of 1,000 delivers 10 W of output power at
10% second harmonic distortion, when the input signal is 10 mV. If 40 db negative voltage-
series feedback is applied and the output power is to remain at 10 W, determine (i) the
required input signal (ii) percentage second harmonic distortion and (iii) closed loop voltage
gain.
Solution: Open-loop gain, A = 1,000
Distortion without feedback, D = 10% or 0.1
Input signal voltage, Vs = 10 mV
40
b A = 40 db or antilog = 100
20
1
Since with feedback the output is reduced by , so the input must be increased by a
1 + Ab
factor (1+ b A) so as to deliver the same output. Thus
(i) Input signal voltage V's = Vs × (1 + b A) = 10 mV × (1 + 100) = 1.01 V
Ans.
D 100
(ii) Percentage second harmonic distortion, Df = = % = 0.1% Ans.
1 + b A 1 + 100
A 1,000
(iii) Closed-loop voltage gain, A f = = =9.9 Ans.
1 + b A 1 + 100
9.5.4 Reduction in Noise with Negative Feedback

Noise in an amplifier is reduced in the same way as distortion. However, distortion is
usually introduced in the last stage of the amplifier and, therefore, is always within the
feedback loop whereas noise in an amplifier may be generated or introduced from outside
source at any stage that may not be within the feedback loop. The noise can be reduced by
negative feedback only if its source lies within the feedback loop after the first stage.
As non-linear distortion generated within the amplifier is reduced with negative feedback
by a factor (1 + b A), the noise introduced within amplifier also gets reduced by the same
factor (1 + b A) on using negative feedback and the performance of the amplifier is thus
much improved.
9.5.5 Effect of Negative Feedback on Input Impedance
High input impedance is always desirable in an amplifier as it will not load the preceding
stage or the input voltage source. Such a desirable characteristic can be had with the help
of negative feedback. The effect of negative feedback on the input impedance of an
amplifier is explained below.
A more detailed series feed back connection is shown in fig. 9.5. The input impedance
can be determined as follows :
Fig. 9.5 Voltage-Series Feedback Connection
Vin Vs - V f
Iin = =
Zin Zin
Vs - b Vout
= Q V f = b Vout
Zin
Vs - b A Vin
= Q Vout = A Vin
Zin
or Iin Zin = Vs - b A Vin

or Vs = Iin Zin + b A Vin = Iin Zin + b A Iin Zin
Vs
or I = Zin + b A Zin Q Vin = Iin Zin
in
Vs
and Zinf = I = Zin + (b A)Zin = Zin (1 + b A)
in
Thus, series voltage negative feedback increases the input impedance of an amplifier
by a factor (1+ b A). This is the same factor by which voltage gain is reduced.
9.5.6 Effect of Negative Feedback on Output Impedance
Just an high input impedance is advantageous to an amplifier, so is low output impedance.
With lower output impedance, the amplifier is better suited to drive a low impedance load.
Such a desirable characteristic can be had by employing negative feedback. The effect of
negative feedback on the output impedance of an amplifier is explained below.
The voltage-series feedback circuit given in fig. 9.5 provides sufficient circuit detail
for determining output impedance with feedback. The input terminals are short-circuited
so that — Vf is now the only input voltage to the amplifier. Now a voltage source Vout is
applied at the output terminals so that Iout current is drawn from the applied source.
Now Vout = IoutZout + A Vin = IoutZout – AVf
Q Vin = -V f
= IoutZout – (b Vout) Q V f = b Vout

or Vout+ A b Vout= IoutZout
Vout Zout
or Vout(l + b A)=IoutZout or =
Iout 1 + b A
Zout Zout
or Zout f = 1 + b A Q Output impedance with feedback Zout f
Iout
Thus, series voltage negative feedback reduces the output impedance of an amplifier by a
factor (1 + b A). This is the same factor by which voltage gain is reduced.
Example-9.10
An amplifier has an input impedance of 1 k W and output impedance of 10 kW and a
voltage gain of 10,000. If a negative feedback of b = 0.02 is applied to it, determine the
input and output impedances of the amplifier.
Solution : Open-loop gain of amplifier, A = 10,000
Feedback ratio, b = 0.02
Input impedance without feedback, Zin = 1 k W
Output impedance without feedback, Zout = 10 k W
Input impedance with feedback, Zin f = (1 + b A) Zin
= (1 + 0.02 × 10,000) × 1 k W = 201 kW Ans.
Zout 10 kW
Output impedance with feedback, Zout f = 1 + b A = 1 + 0.02 ´ 10,000 = 49.75 W Ans.
Example-9.11
An amplifier with a gain of 60 db has an output impedance of 10 k W. It is required to
modify its output impedance to 1 k W. What type of feedback has to be applied ? Calculate
the feedback factor. Also find the percentage change in the overall gain, for a 10 %
change in the open-loop gain of the amplifier.
60
Solution: Open-loop voltage gain, A = 60 db or antilog = 1,000
60
Zout
Output impedance with feedback, Zout f = 1 + b A
10 ´ 103
\ 1 x 103 = Q Zout f = 1 k W; Zout = 10k W; and A = 1,000
1 + b ´ 1,000
or b = 0.009
Feedback factor, b A = 0.009 × 1,000 = 9 Ans.
For 10 % decrease in open-loop gain, we have new open-loop gain
æ 10 ö
A¢ = ç 1 - ÷ A = 0.9 A = 0.9 × 1,000 = 900
è 100 ø
A¢ 900
New gain with feedback, A¢f = = = 98.9
1 + b A¢ 1 + 0.009 ´ 900
A f - A¢f 100 - 98.9

Percentage change in overall gain = ´ 100 = ´ 100 = 1.1% Ans
Af 100
A 1,000
QAf = = = 100
1 + bA 1 + 0.009 ´ 1,000
9.5.7 Effect of Negative Feedback on Bandwidth
Voltage gain with feedback is given as
Av 1
A vf = ;
1 + b A v b if b A v >> 1
and from the above result it may be concluded that the voltage gain may be made to
depend entirely on the feedback network. However, it is now important to consider the
fact that even if b is constant, the voltage gain Av is not, since it depends on frequency.
When negative feedback is applied in an amplifier, cut-off frequencies are also affected-
lower cut-off frequency is lowered by a factor of (1 + b A) while upper cut-off frequency
is raised by the same factor (1 + b A). This is explained below.
(i) Lower Cut-off Frequency f1 . The voltage gain at a frequency f in low frequency
range of R-C coupled amplifier is given as
A vm
A vl =
f
1- j 1 where f1 is lower cut-off frequency and j = -1 .
f
When negative feedback is applied
A vm
A vmf =
1+ bA vm
Avl
A vlf =
1+ bA vl
Substituting the value of Avl
A vm
1 - jf1 / f A vm A vm
A vlf = = =
A vm 1 - jf1 / f + b A vm 1 + b A vm - jf1 / f
1+ b
1 - jf1 / f
By dividing numerator and denominator by 1 + b Avm, this equation may be rewritten
A vmf
A vlf =
1 - jf1¢ / f
A vm f1
where A vmf = and f1¢ =
1 + b A vm 1 + b A vm
From above expressions we see that the midband amplification with feedback Avmf
equals the midband amplification without feedback divided by 1 + b Avm. Also the lower
cutoff frequency with feedback f1¢ equals the lower cut-off frequency without feedback
f1 divided by the same factor (1 + b Avm) i.e. lower cut-off frequency is reduced when
negative feedback is applied.
(ii) Upper Cut-off Frequency. The voltage gain at frequency f in the high frequency
range of R-C coupled amplifier is given as
A vm
A vh =
1 + j f / f2
When negative feedback is applied
A vh
A vhf =
1 + b A vh
Substituting the value of Avh we have
A vm
1 + jf / f 2 A vm
A vhf = =
A vm 1 + b A vm + j f / f 2
1+ b
1 + jf / f 2
By dividing the numerator and denominator by 1 + b Avm, the above equation may be re-
written as
A vmf
A vhf =
1 + jf / f 2¢
A vm
where Avmf = and f 2¢ = f 2 (1 + b A vm )
1 + b A vm
Thus we see that upper cutoff frequency with feedback equals the corresponding
cutoff frequency without feedback f2 multiplied by the factor (1 + b Avm) i.e. upper cut-off
frequency is raised when negative feedback is applied in an amplifier.
The effect of negative feedback on frequency response curve is shown in fig. 9.6.
Bandwidth. The bandwidth with negative feedback is given as
Fig. 9.6 Amplifier Frequency Response With and Without Negative Feedback
f1
B Wf = f 2¢ - f1¢ = f 2 (1 + b A vm ) -
1 + b A vm
Since f 2¢ > f 2 and f1¢ < f1 hence the bandwidth with negative feedback is increased.
Assuming f 2¢ >> f1¢ and f 2 >> f1 bandwidth may be re-written as
B Wf = f 2 (1 + b A vm ) = (1 + b A vm ) times bandwidth without feedback.

Thus we see that bandwidth of an amplifier with negative feedback is increased by

the same factor by which voltage gain is reduced and gain bandwidth product remains the
same. However, since the amplifier with feedback has lower gain, the net operation is to
trade bandwidth for gain.
Example-9.12
An R-C coupled amplifier has Am = 50,000, fH = 20 kHz; fL = 30 Hz. A resistive
voltage negative feedback is added such that b = 5 × 10–5. Find Amf, fHf and fLf. Derive the
relations to be used for the calculations.
Solution: Open-loop gain, Am = 50,000
Feedback ratio, b = 5 × 10–5
Am 50,000
A mf = = = 14, 285.7 Ans.
1 + b A m 1 + 5 ´ 10-5 ´ 50,000
Upper cut-off frequency with feedback,
f Hf = f H (1 + b A m ) = 20 ´ 103 (1 + 5 ´ 10-5 ´ 50, 000) = 70 kHz Ans.

Lower cut-off frequency with feedback,
fL 30
f Lf = = - 8.57 Hz Ans.
1 + b A m 1 + 5 ´ 10-5 ´ 50,000
Example-9.13
Derive an expression for the overall gain of a voltage series feedback amplifier. An
amplifier has the midband gain of 1,500 and a bandwidth of 4 MHz. The midband gain
reduces to 150 when a negative feedback is applied. Determine the value of feedback
factor and the bandwidth.
Solution: Midband gain Avm = 1,500
A vm
Midband gain with feedback, Avmf = 1 + b A
vm
Substituting the value of Avmf = 150 and Avm = 1,500 in above equation we have
1,500
150 =
1 + b A vm
1,500
or Feedback factor, B Avm = -1 = 9 Ans.
150
Bandwidth with feedback, B Wf = (1 + b A vm ) ´ Bandwidth without feedback
= (1 + 9) x 4 = 40 MHz Ans.
9.6 TYPES OF NEGATIVE FEEDBACK CONNECTIONS

Depending on types of sampling and mixing, there are four types of negative feedback
connections.
i) Voltage - series feedback
ii) Voltage - shunt feedback
iii) Current - series feedback
iv) Current - shunt feedback
In all connections the first word refers to the type of sampling and 2nd word refers to the
type of mixing.
Fig. 9.7 Feedback amplifier types : (a) Voltage-series feedback, Af / Vo /Vs;

(b) voltage-shunt feedback, Af = Vo/Is; (c) current-series feedback, Af = Io /Vs;
(d) current-shunt feedback, Af = Io /Is.
Table 9.1 Summary of Gain, Feedback, and Gain with Feedback from Fig. 9.2
Voltage-Series Voltage-Shunt Current-Series Current-Shunt
Vo Vo Io Io
Gain without feedback A Vi Ii Vi Ii
Vf If Vf If
Feedback b Vo Vo Io Io
Af Vo Vo Io Io
Gain with feedback
Vs Is Vs Is
9.6.1 Input resistance

We now discuss qualitatively the effect of the topology of a feedback amplifier upon the
input resistance. If the feedback signal is returned to the input in series with the applied
voltage, it increases the input resistance. Since the feedback voltage V f opposes Vs , the
input current Ii is less than it would be if Vf were absent. Hence the input resistance with
feedback Rif º Vs/Ii (Fig. 13.10) is greater than the input resistance without feedback Ri.
We show below that, for this topology, Rif = Ri(1 + bA) = RiD.
Negative feedback in which the feedback signal is returned to the input in shunt with
the applied signal (regardless of whether the feedback is obtained by sampling the output
Fig. 9.8 Voltage-series feedback circuit used to calculate input and output resistances.
current or voltage) decreases the input resistance. Since Is = Ii + If , then the current Ii (for
a fixed value of Is) is decreased from what it would be if there were no feedback current.
Hence Rif º Vi/Is = IiRi|Is is decreased because of the type of feedback. We show below
that, for this topology, Rif = Ri/(1 + bA) = Ri/D.
Table 9.2 summarizes the characteristics of the four types of negative-feedback
configurations : For series comparison, Rif > Ri, whereas for shunt mixing, Rif < Ri.
Table 9.2 Effect of negative feedback an amplifier characteristic
Type of feedback
Voltage-series Current-series Current-Shunt Voltage-Shunt
Reference………. Fig.9.7(a) Fig.9.7 (b) Fig. 9.7 (c) Fig. 9.7 (d)
Rof……………… Decrease Increase Increase Decrease
Rif…………........ Increase Increases Decreases Decreases
Improves Voltage Transconductance Current Transresistance
Characteristics of amplifier amplifier amplifier Amplifier
Desensitiizes…… Avƒ GMƒ AIƒ RMƒ
Bandwidth…….. Increase Increase Increase Increase
Nonlinear
distortion………. Decrease Decrease Decrease Decrease
Voltage-series Feedback
We now obtain Rif quantitatively. The topology of Fig. 9.7a is indicated in Fig.9.8, with the
amplifier replaced by its Thevenin’s model. In this circuit Av represents the open-circuit
voltage gain taking Rs into account.
From Fig. 9.8 the input impedance with feedback is Rif = Vs /Ii ,. Also
Vs = IiRi + Vf = IiRi + bVo
and
A v Vi R L
Vo = = A v Ii R i
Ro + RL
where
Vo AvR L
Av º =
Vi R o + R L
Vs
Þ R if = = R i (1 + b A v )
Ii
Whereas Av represents the open-circuit voltage gain without feedback.
Current-series Feedback
From Fig. 9.7(b), proceeding in similar manner
Rif = Ri (1 + bGM)
and
Io GmRo
GM = =
Vi R o + R L
Current-shunt Feedback
The topology of Fig. 9.7(c) is indicated in Fig. 9.9, with the amplifier replaced by its
Norton’s model. In this circuit
Fig. 9.9 Current-shunt feedback circuit used to calculate input and output resistances.
Ai represents the short-circuit current gain taking R, into account. From Fig. 9.9
Is = Ii + I f = Ii + bI o
A i R o Ii
and Io = = A I Ii
Ro + R L
Io Ai R o
where AI º =
Ii R o + R L
Is = Ii + If = Ii + b A I Ii = (1 + b A I )Ii
From Fig. 9.9, R if = Vi / Is and R i = Vi / Ii . We obtain
Vi Ri
R if = =
(1 + b A I )Ii 1 + b A I
Voltage-shunt Feedback
Proceeding in a similar manner for the topology of Fig. 9.7(d), we obtain
Ri
R if =
1 + bR M
where
Vo R R
RM º = m L
Ii Ro + R L
9.6.2 Output Resistance
In negative feedback topology if there is voltage sampling (or connection is shunt
type) then the output resistance decreases i.e. Rof < Ro . And if there is current sampling
(or connection is of series types then the output resistance increases i.e. Rof > Ro .
Voltage-series Feedback
We now obtain quantitatively the resistance with feedback Rof looking into the output
terminals but with RL disconnected. To find Rof we must remove the external signal
(set Vs = 0 or Is = 0), let RL = ¥ , impress a voltage V across the output terminals, and
calculate the current I delivered by V. Then Rof º V/I. From Fig. 9.8 we find (with V0
replaced by V)
V - A v Vi V + b Ao V
I= =
Ro Ro
because, with Vs = 0, Vi = – Vf = – bV. Hence
V Ro
R of º =
I 1 + b Av
The output resistance with feedback R ¢of which includes RL as part of the amplifier
is given by Rof in parallel with RL, or
R of R L R R 1 Ro RL
¢ =
R of = o L =
R of + R L 1 + b A v R o /(1 + bA v ) + R L R o + R L + bA v R L
R o R L /(R o + R L )
=
1 + b A v R L /(R o + R L )
Since R ¢o = R o || R L is the output resistance without feedback but with RL considered as

part of the amplifier, we obtain
R ¢o
R ¢of =
1 + b AV
Voltage-shunt Feedback
Proceeding as outlined above, we obtain for this topology
Ro R ¢o
R of = and R ¢of =
1 + bR m 1 + bR M
Current-shunt Feedback
From Fig. 9.9 we find (with Vo replaced by V)
Vo
I= - A i Ii
Ro
With Is = 0, Ii = - If = -b Io = +b I. Hence
V V
I= - b Ai I or I(1 + b Ai ) =
Ro Ro
V
R of = = R o (1 + bAi )
I
The output resistance R ¢of which includes RL as part of the amplifier is not given by
R ¢o (1 + b A I ) , as one might thoughtlessly expect, We shall now find the correct expression
for R ¢of
R of R L R o (1 + bA i )R L RoRL 1 + b Ai
R ¢of = = =
R of + R L R o (1 + b Ai ) + R L R o + R L 1 + bAi R o /(R o + R L )
with R ¢o = R o || R L , we obtain
1 + bAi
R ¢of = R ¢o
1 + bA I
For R L = ¥, A I = 0 and R ¢o = R o ,
So, R ¢of = R o (1 + b A i )
Current-series Feedback
Proceeding as outlined above, we obtain for this topology
1 + bGm
R of = R o (1 + b G m ) and R ¢of = R ¢o
1 + bG M
9.7 METHOD OF ANALYSIS OF A FEEDBACK AMPLIFIER

It is desirable to separate the feedback amplifier into two blocks, the basic amplifier A and
the feedback network b because with a knowledge of A and b, we can calculate the
important characteristics of the feedback system, namely, A f , R if , and R of . The basic
amplifier configuration without feedback but taking Hie loading of the b network into
account is obtained by applying the following rules :
To find the input circuit:
1. Set V0 = 0 for voltage sampling. In other words, short the output node.
2. Set I0 = 0 for current sampling. In other words, open the output loop.
To find the output circuit:
1. Set Vi = 0 for shunt comparison. In other words, short the input node.
2. Set Ii = 0 for series comparison. In other words, open the input loop.
These procedures ensure that the feedback is reduced to zero without altering the
loading on the basic amplifier.
The complete analysis of a feedback amplifier is obtained by carrying out the following
steps:
1. Identify the topology, (a) Is the feedback signal Xf a voltage or a current? In other
words, is Xf applied in series or in shunt with the external excitation? (b) Is the sampled
signal X0 a voltage or a current? In other words, is the sampled signal taken at the
output node or from the output loop?
2. Draw the basic amplifier circuit without feedback, following the rules listed above.
3. Use a Thivenin’s source if Xf is a voltage and a Norton’s source if Xf is a current.
4. Replace each active device by the proper model (for example, the hybrid-II model for
a transistor at high frequencies or the ^-parameter model at low frequencies).
5. Indicate Xf and X0 on the circuit obtained by carrying out steps 2, 3, and 4. Evaluate
b = Xf / X0.
6. Evaluate A by applying KVL and KCL to the equivalent circuit obtained after step 4.
7. From A and b, find D, Af , Rif , Rof , and R ¢of .
Table 9.3 summarizes the above procedure and should be referred to when carrying
out the analyses of the feedback circuits.
Table 9.3 : Feedback amplifier analysis
Topology
(1) (2) (3) (4)
Characteristic Voltage-series Current-series Current-shunt Voltage-shunt
Feedback signal Xf Voltage Voltage Current Current

Samploed signal Xo Voltage Current Current Voltage
To find input loop, set † Vo = 0 Io = 0 Io = 0 Vo = 0
To find output loop, set † Ii = 0 Ii = 0 Vi = 0 Vi = 0
Signal source Thevenin Thevenin Norton Norton
b = Xf/Xo Vf/Vo Vf/Io If/Io If/Vo
A=Xo/Xi Av = Vo/Vi GM = Io/Vi AI = Io/Ii RM = Vo/Ii
D = 1 + bA 1 + b AV 1 + b GM 1 + b AI 1 + b RM
Af AV/D GM/D AI/D RM/D
Rif RiD RiD Ri/D Ri/D
Ro Ro
Rof Ro(1 + b Gm) Ro(1 + b Ai)
1 + bA v 1 + bR m
R ¢o 1 + bG m 1 + bAi R ¢o
R ¢of = R of || R L R ¢o Ro
D D D D
9.8 VOLTAGE-SERIES FEEDBACK

Two examples of voltage-series Feedback topology are FET source follower & BJT common
collector amplifier (or emitter follower)
The FET Source Follower
The circuit is given in Fig. 9.10a. The feedback signal is the voltage Vf across R, and
the sampled signal is the output voltage Vo, across R. Hence this is the case of voltage-
series feedback.
Fig. 9.10 (a) The source-follower, (b) The amplifier without feedback and
(c) the FET replaced by its small-signal low-frequency model.
To find input circuit, set Vo = 0 and hence Vs will appear between G and S. To find the
output circuit, set Ii = 0 (i/p loop is opened & hence R will only appear in the output loop.
This topology stabilizes voltage gain. AV is calculated by inspection of Fig. 9.10c.
Since without feedback Vi = Vs, then
Vo g Vr R mR
Av = = m sd =
Vi (rd + R)Vs rd + R
where m = gmrd ,
mR r + (1 + m)R
D = 1 + bA v = 1 + = d
rd + R rd + R
AV mR
A vf = =
D rd + (1 + m)R
The input impedance of an FET is infinite, R i = ¥ , and hence R if = R i D = ¥ .
We are interested in finding the output resistance seen looking into the FET source S.
Hence R is considered as an external load RL. From Table 9.3
Ro r
R of = = d
1 + bA v 1 + m
because R0 = rd from Fig. 9.10c, b = 1, and Av = m . Also,
R ¢o Rrd rd + R Rrd
R ¢of = = =
D R + rd rd + (m + 1)R rd + (m + 1)R
The Emitter Follower
The circuit is given in Fig. 13.13a. The feedback signal is the voltage Vf across Re, and
the sampled signal is V0 across Re. Hence this is a case of voltage-series feedback.
Fig. 9.11 (a) An emitter follower, (b) The amplifier without feedback and (c) the transistor
replaced by its approximate low-frequency model.
We now draw the basic amplifier without feedback. To find the input circuit, set
V0 = 0, and hence Vs in series with Rs appears between B and E.
To find the output circuit, set Ii = Ib = 0 (the input loop is opened), and hence Re
appears only in the output loop. Following these rules, we obtain the circuit of
Fig. 9.11b. If the transistor is replaced by its low-frequency approximate model, the result
is Fig. 9.11c. From this figure V0 = Vf and b = Vf /V0 = 1.
This topology stabilizes the voltage gain. A v is calculated by inspection of
Fig. 9.11c. Since Re is considered as part of the amplifier, then Vi = Vs , and
Vo h fe Ib R e h R
Av = = = fe e
Vi Vs R s + h ie
h fe R e R + h ie + h fe R e
D = 1 + bA v = 1 + = s
R s + h ie R s + h ie
Av h fe R e
A vf = =
D R s + h ie + h fe R e
For h fe R e >> R s + h ie , A vf » 1 , as it should be for an emitter follower..
The input resistance without feedback is R i = R s + h ie from Fig. 9.11c.

Hence
R s + h ie + h fe R e
R if = R i D = (R s + h ie ) = R s + h ie + h fe R e
R s + h ie
We are interested in the resistance seen looking into the emitter. Hence R, is considered
as an external load.
Ro ¥
Now, R of = =
1 + bA v ¥
because, from Fig. 9.11c, we are looking into a current source R o = ¥ and Av= ¥ .
R ¢o R e (R s + h ie )
R ¢of = =
D R s + h ie + h fe R e
R s + h ie
and R of = lim R ¢of =
R o ®¥ h fe
Example-9.14
Calculate the amplifier gain of the circuit shown for an op-amp gain A = 105 and resistances
R 1 = 2kW and R 2 = 200W .
Fig. 9.12
Solution : Figure 9.12 is an example of voltage series feedback is an op-amp connection. The
feedback Factor :
R2 200 200
b= = = = 0.091
R1 + R 2 200 + 2000 2200
The gain of the amplifier with feedback
A 105
Af = =
1 + bA 1 + (0.091) ´ 105
105
Þ Af = = 10.999
9091.91
Note that since bA >> 1
1 1
Af @ = = 10.989
b 0.091
Example-9.15
For the two stage feedback amplifier shown Fig. 9.13 (a) identify the nature of feedback,
(b) draw the equivalent circuit without overall feedback. Obtain Av, Ri, and Ro, and (c)
determine D = 1 + Ab.
Fig. 9.13
Hence, write down Avf, Rif, Rof. Given hie = 1.1 K and hfe = 50.
Solution :
(a) The first stage has a local feedback due to RE = 100 ohm, which carries the collector
current and its voltage is in series opposition to the signal. It is voltage series feedback.
Overall, a fraction of the output Voltage Vo is fed in series opposition to the input.
0.1 1
b= = . It is voltage series feedback.
10.1 100
(b) In removing the overall feedback b
RE is modified to R ¢E = 0.1K parallel to 10 K
= RE approx.
The output is loaded by 10.1 K ohms due to the feedback network.
The bias resistors of 22 K and 220 K, give
22 ´ 220
RB = = 20 K
242
The circuit without feedback is as shown in Fig. 9.13(a)
Fig. 9.13 (a)

Considering the 1st stage which has local feedback due to RE
R i = h ie + (1 + h fe )R E
= 1.1 + 51 × 0.1 = 6.2 K ohms
I stage load = 22 K || 20 K || 1.1 K = 1 K ohm
- h fe ´ 1
A v1 = = -8
6.2
II stage R o = (4.6) || (10.1) = 3.3K
-h fe R o -50 ´ 3.3
A v2 = = = -150
h ie 1.1
The results are A v = -8 ´ -150 = +1200
R i = 6.2 K, R o = 3.3k
(c) Feedback factor D = 1 + Ab
1
A = 1200, b =
100
Hence D = 13
The effect of voltage series feedback is to make the amplifier a voltage controlled voltage
source (VVS). Hence, input resistance increases by factor D, output resistance decreases
1
by factor .
D
R if = 6.2 ´ 80.6 K ohms
3.3
R of = = 0.25K ohms
13
1200
A vf = = 92
13
V
Notes : (i) In calculating A v 2 note that i 2 = h and V is the output voltage of Ist stage.
i
(ii) For VVS in the ideal case R i = ¥, R o = 0

Hence, from R i , R o with no feedback.
R if = R i ´ D (increase)
Ro
R of = (decrease)
D
(iii) RB is across VS. Hence, the voltage across the input of the transistor Vi across Ri is
also VS. If there was a source resistance RS, then the input to the transistor is only a
fraction of VS. By Norton equivalent.
VS
Vi = ´R
RS
Where R = R S || R B || R i
9.9 CURRENT-SERIES FEEDBACK
Two examples of the current-series topology are considered. The common-emitter
transistor amplifier with a resistance Re in the emitter is analyzed first. Then the FET
common-source amplifier with a resistor R in the source lead is studied.
The Transistor Configuration
The circuit is given in Fig. 9.14a. The feedback signal is the voltage Vf across Re and
the sampled signal is the load current Io.
If the output signal is taken as the voltage Vo then
Vf -Io R e R
b= = =- e
Vo Io R L RL
The input circuit of the amplifier without feedback is obtained by opening the output
loop. Hence Re must appear in the input side. Similarly, the output circuit is obtained by
opening the input loop, and this places Re also in the output side. The resulting equivalent
circuit is given in Fig. 9.14b. And the circuit of Fig, 9.14b represents the basic amplifier
without feedback, but taking the loading of the b network into account.
ThistopologystabilizesthetransconductanceGM. In Fig. 9.14c the transistor is replaced
by its low-frequency approximate h-parameter model.
Fig. 9.14 (a) Amplifier with an unbypassed emitter resistance as an example of

current-series feedback, (b) The amplifier without feedback, but including the
loading of Re. (e) The /i-parameter model used for the transistor in (b).
Since the feedback voltage Vf appears across Re in the output circuit, then, from Fig. 9.14c
Vf -Io R e
b= = = -R e
Io Io
Since the input signal Vi without feedback is the Vs of Fig. 9.14c, then
Io -h fe I b -h fe
GM = = =
Vi Vs R s + h ie + R e
h fe R e R + h ie + (1 + h fe )R e
D = 1 + bG M = 1 + = s
R s + h ie + R e R s + h ie + R e
GM -h fe
G Mf = =
D R s + h ie + (1 + h fe )R e
Example-9.16
For the circuit shown with the given
informations calculate the circuit gain with
and without feedback
R B = 600 W, R E = 1.2 kW,
R C = 4.7 kW, b = 75 . Use VCC = 16 V.
Fig. 9.15
Solution : The configuration given in the question is BJT amplifier with current-Series feedback.
The gain without feedback is
-hf e -7.5
A= = = -0.0417
hie + R E 600 + 1200
Vf
The feedback factor b = = -R E = -1.2 = -1200
Io
The factor (1 + bA ) is then
(1 + bA) = 1 + (-1200)(-0.0417) = 1 + 50 = 51
Io A
The gain with feedback is then A f = =
Vs 1 + bA
-0.417
Þ Af = = -8.176 ´ 10-4
51
And the voltage gain with feedback A vf is
Vo
A vf = = A f R C = -8.176 ´ 4.7 ´ 103
Vs
Þ A vf = -3.843
Without feedback (RE = 0), the voltage gain is
- R C 04.7 ´ 103
Av = = = -303.2
re 15.5
The FET CS Stage with a Source Resistor
R The circuit of Fig. 9.16a is analogous to the transistor CE stage with an emitter resistor
Re. Proceeding as we did for the transistor amplifier, we obtain the circuit of Fig. 9.16b.
Replacing the FET by its low-frequency model results in Fig. 9.16c. Without feedback
Vi = Vs and
Io Io -g m rd -m
GM = = = =
Vi Vs rd + R L + R rd + R L + R
where m = rdgm
Vf
b= = -R
Io
mR r + R L + (m + 1)R
D = 1 + bG M = 1 + = d
rd + R L + R rd + R L + R
GM -m
G Mf = =
D rd + R L + (m + 1)R
Since R i = ¥ , then
Rif = RiD = ¥
If RL is considered to be an external load, then from Fig. 9.16c
R o = rd + R
rd + (m + 1)R
1 + bG m = lim D =
R L ®0 rd + R
rd + (m + 1)R
R of = R o (1 + bG m ) = (rd + R) = rd + (m + 1)R
rd + R
Fig. 9.16 (a) An FET amplifier with a source resistor R., (b) The amplifier without feedback, but
including the loading of R. (c) The FET replaced by its small-signal low-frequency model.
9.10 CURRENT-SHUNT FEEDBACK

Figure 9.17 shows two transistors in cascade with feedback from the second emitter to the
first base through the resistor R'. The voltage Vi2 is much larger than Vi1 because of the
voltage gain of Q1. Also, Vi2 is 180° out of phase with Vi1. Because of emitter-follower
action, Ve2 is only slightly smaller than Vi2, and these voltages are in phase. Hence Ve2 is
larger in magnitude than Vi1 and is 180° out of phase with Vi1. If the input signal increases
so that I¢s increases, If also increases, and Ii = I¢s - If is smaller than it would be if there
were no feedback. This action is characteristic of negative feedback.
The configuration of Fig. 9.17 approximates a current-shunt feedback pair. Since
Ve2 >> Vi1 , and neglecting the base current of Q2 compared with the collector current,
Vi1 - Ve2 V (I - I )R
If = » - e2 = o f e
R¢ R¢ R¢
R e Io
or If = = bIo
R¢ + Re
where b = R e /(R ¢ + R e ). Since the feedback current is proportional to the current, this
circuit is an example of a current-shunt feedback amplifier.
Io 1 R ¢ + R e
A If = » =
Is b Re
and hence we have verified that AIf is desensitized provided that R' and Re are stable
resistances. Note that Is º Vs / Rs.
The voltage gain with feedback is
Vo Io R c2 R ¢ + R e R c2 R e2
A Vf = = » =
Vs Is R s Re R s bR s
Fig. 9.17 Second-emitter to first-base feedback pair. (The input blocking

capacitor and the biasing resistors are not indicated.)
Fig. 9.18 The amplifier of Fig. 9.17 without feedback,

but including the loading of R'.
9.11 VOLTAGE-SHUNT FEEDBACK
Figure 9.19a shows a common-emitter stage with a resistor R' connected from the
output to the input.
In the circuit of Fig. 9.19a, the output voltage Vo is much greater than the input
voltage Vi and is 180° out of phase with Vi. Hence
Vi - Vo V
If = » - o = bVo
R¢ R¢
Fig. 9.19 (a) Voltage-shunt feedback, (b) The amplifier without feedback, but
including the loading of R'.
where b = – 1/R'. Since the feedback current is proportional to the output voltage, this
circuit is an example of a voltage-shunt feedback amplifier.
Vo 1
R Mf = » = -R ¢
Is b
Vo V 1 R¢
A Vf = = o » =-
Vs Is R s bR s Rs
Q.1 What is feedback in amplifiers ?

Ans. The process of combining a fraction of output energy back to the input is called the feedback.
Q.2 What is the difference between current and voltage feedback ?
Ans. Voltage feedback refers to connecting the output voltage as input to the feedback network
while current feedback refers to tapping off some output current through the feedback
network.
Q.3 How do series feedback and shunt feedback differ from each other?
Ans. Series feedback means connecting the feedback signal in series with the input signal voltage
while shunt feedback means connecting the feedback signal in parallel with an input current
source.
Q.4 Why voltage series feedback is most commonly used in cascaded amplifiers?
Ans. In cascaded amplifiers, high input impedance and low output impedance are usually the
main requirements and both of these requirements can be met by voltage series feedback,
so it is most commonly used in cascaded amplifiers.
Q.5 What is the effect of negative feedback on gain in an amplifier ?
Ans. The negative feedback in an amplifier decreases the voltage gain.
Q.6 What is the effect of a negative feedback on the input impedance of a voltage series
feedback amplifier?
Ans. Negative feedback increases the input impedance of a voltage series feed back amplifier
by a factor(1 + (b A) where b A is the feedback factor.
Q.7 Whether the input impedance of a voltage series feedback amplifier increases or decreases
with negative feedback?
Ans. Series voltage negative feedback increases the input impedance of an amplifier by a factor
(1 + b A), where b A is the feedback factor.
Q.8 What is the effect of negative feedback on the input and output impedances of a voltage
series feedback amplifier?
Ans. Series voltage negative feedback increases the input impedance and reduces the output
im pedance by a factor(1 + b A).
Q.9 What is the effect of negative feedback on the bandwidth of an amplifier ?
Ans. Bandwidth of an amplifier is increased, when negative feedback is introduced, by a factor
(1 + b A), by which its gain is reduced.
Q.10 What is effect of removing bypass capacitor across the emitter resistor in case of a CE
amplifier ?
Ans. Voltage gain is reduced, when the bypass capacitor across the emitter resistor in a CE
amplifier is removed.
Q.11 Why an emitter follower is called so ?
Ans. In an emitter follower, output and input voltages are approximately equal in magnitude and
also inphase i.e. emitter output voltage closely follows the input and that is why it is called
the emitter follower.
Q.12 Why an emitter follower is preferred over a transformer for impedance matching?
Ans. An emitter follower is preferred over a transformer for impedance matching because it is
not only more convenient than a transformer but it also provides better frequency response.
EXERCISE
1. What do you mean by feedback in amplifiers? Define negative and positive feedbacks.
2. Give the general theory of feedback.
3. Explain a feedback amplifier with the help of a block diagram.
4. Draw the block diagram of a negative feedback amplifier. Derive an expression for the
voltage gain of an amplifier of gain A when subjected to negative feedback with a feed-
back fraction b.
5. State the merits and demerits of negative feedback in amplifiers.
6. Explain how negative feedback in an amplifier helps in reducing the distortion and noise.
7. Discuss the effect of negative feedback on
(i) distortion, (ii) input impedance and (iii) output impedance.
8. Explain how the gain of an amplifier can be stabilized with the help of negative feedback.
9. Discuss the effects of negative feedback on amplifier characteristics.
10. If the response of an R-C coupled amplifier in the low frequency range is given by
(A v ) m
( A v )I =
1 - j(f1 / f )
where (Av)m is the mid-frequency gain and f1 is the lower cut-off frequency, derive an
expression for the lower cut-off frequency f' for a feedback amplifier.
11. Explain the nature of feedback in an emitter follower circuit. State the advantages of this
circuit and mention its use. Can this circuit be vised as a voltage amplifier?
12. Name a circuit in which a 100% negative feedback occurs. Discuss the working of an
emitter follower circuit. Derive the expressions for :
(i) input and output impedances
(ii) current and voltage gains.
13. Discuss Darlington Pair. What are its primary features ? Obtain expressions for Av, Ai and
Ri.
14. Discuss biasing problem in Darlington Pair. How it is solved ? Explain bootstrapping prin-
ciple and how effectively it is used in Darlington Pair ?
15. Write short note on
(i) Darlington emitter follower
(ii) Boot strapping
16. The total harmonic distortion of an amplifier is reduced from 15% to 3% when 4% negative
feedback is used. Find (i) the voltage gain without feedback and (ii) the voltage gain with
feedback.
[Ans. (i)100, (ii) 20]
17. The overall gain of a multistage amplifier is 140. When negative feedback is applied, the
gain is reduced to 17·5. Find the fraction of the output that is fed back to the input.
[Ans. 3 = 1/20 ]
18. An amplifier having a gain of 500 without feedback has an overall negative feedback
applied which reduces the gain to 100. Calculate the fraction of output voltage fed back. If
due to ageing of components, the gain without feedback falls by 20%, calculate the percentage
fall in gain with feedback.
[Ans. 4·7%]
ppp
327
Sinusoid Oscillators
10.1 INTRODUCTION
In many of the electronic applications, electrical energy at a specific high frequency
ranging from a few Hz to several MHz is required. The electrical energy at this frequency
(other than power frequency) is obtained with the help of an electronic device called an
oscillator. An oscillator is just an electronic circuit which converts dc energy into ac
energy of required frequency.
Oscillators find their extended use in electronic equipment. For instance, these are
used in radio and television receivers to generate high frequency (carrier frequency) waves
in the tuning stage. These are used to test the performance of a stereo amplifier, radio
receiver, TV etc. Generation of high frequencies (an oscillator) is also essential in all
communication systems, for example, in radio and television broadcasting where the
transmitters radiate the signals at very high carrier frequencies (550 kHz to 22 MHz-radio;
47 MHz to 230 MHz-television). In industry, the oscillators are used with induction and
dielectric heating where electrical energy at high frequency is required.
The above discussion shows, how important is for an electronic engineer to study
about an oscillator. Although oscillators can produce sinusoidal as well as non-sinusoidal
(such as square) waves. But in this chapter, we shall confine our attention to sinusoidal
oscillators.
10.2 SINUSOIDAL OSCILLATOR
A static electronic device that produces sinusoidal oscillations of desired frequency
is called a sinusoidal oscillator.
It is just an electronic circuit that receives d.c. energy and changes it into a.c. energy of
desired frequency. The frequency of oscillations depends upon the circuit parameters. It is
important to mention here that an alternator (a.c. generator) also produces sinusoidal
oscillations of 50 Hz, but it is not called an oscillator because of the following reasons.
(i) An alternator is a mechanical device having rotating parts whereas an oscillator is a

static electronic device.
(ii) An alternator converts mechanical energy into alternating electrical energy whereas
an oscillator converts d.c. energy into a.c. energy.
(iii) An alternator produces 50Hz frequency oscillations and cannot produce high frequency
oscillations (because of some mechanical constraints) whereas, an oscillator can
produce oscillations ranging from a few hertz to several MHz.
Although electrical oscillations can be produced by mechanical devices (like alternator),
but electronic oscillators are only used for generation of oscillations because of their following
merits :
(i) An electronic oscillator has no rotating part. Consequently, it has little wear and tear
and hence longer life.
(ii) The operation of an electronic oscillator is quite silent since it has no rotating part.
(iii) It operates at a very high efficiency since there is no wastage of energy due to friction
as it has no rotating part.
(iv) It can produce oscillations of frequency ranging from small values (< 20 Hz) to
extremely high values (100 MHz).
(v) The frequency of oscillations produced at the output can be changed easily as and
when desired.
(vi) It has much better frequency stability i.e., the frequency once set remains constant
for a considerable period of time.
10.3 TYPES OF ELECTRICAL OSCILLATIONS
The sinusoidal electrical oscillations are of two types viz damped oscillations and undamped
oscillations.
Damped oscillations
The electrical oscillations in which amplitude decreases with time are known as damped
oscillations. The wave form of the damped oscillations is shown in Fig. 10.1 (a). These
oscillations are produced by the system in which no means are provided to compensate for
losses. Therefore, due to loss of energy in the system producing oscillations, the amplitude
of oscillations goes on decreasing with time. It is important to note that the amplitude of
oscillations is decreasing but the frequency remains the same since it depends upon the
parameters of the circuits.
Fig. 10.1
Sinusoid Oscillators 329
Undamped oscillations
The electrical oscillations in which amplitude does not change with time are known as
undamped oscillations. The wave form of the undamped oscillations is shown in Fig.
10.1 (b). These oscillations are produced by the system in which some means are provided
to compensate for losses. In this case what so ever is the toss of energy after each
oscillation, the same amount of energy is supplied by some means. Consequently, the
amplitude of the wave remains constant. These are the oscillations which are used in
various electronic equipment.
10.4 OSCILLATORY CIRCUIT
Fig. 10.2
A circuit that produces electrical oscillations of a desired frequency is known as an
oscillatory circuit or tank circuit.
Figure 10.2 shows a simple oscillatory circuit which contains a capacitor C and an inductor
(or coil) L connected in parallel. The frequency of oscillations produced by this oscillatory
circuit is determined by the value of C and L. Let us examine how this oscillatory circuit
works :
The circuit arrangement to charge the capacitor of an oscillatory circuit is shown in
Fig. 10.2. When switch S is thrown to stud 1, the capacitor C is charged at the battery
potential in the direction shown. Now throw the switch to stud 2, the capacitor will discharge
through inductor L and sets up the electrical oscillations as explained below :
Fig. 10.3
When capacitor discharges through inductor L, the excess of electrons on plate B
travel through L and reach at plate A as shown in Fig. 10.3 (a). This flow of current sets up
magnetic field around the coil as shown in Fig. 10.3 (b). Due to inductive effect, the
current builds up slowly and attain its maximum value when the capacitor is fully discharged.
Thus, the electrostatic field energy at the capacitor is converted into magnetic field energy
around the coil.
Now, the magnetic field set-up around the coil begins to collapse and produces a
counter e.m.f. This counter e.m.f. will continue the flow of current (or electrons) in the
same direction as shown in Fig. 10.3 (c). The result is that the capacitor is now charged
with opposite polarity as shown in Fig. 10.3 (d).
Once the magnetic field is totally collapsed, the capacitor is fully charged. Then the
capacitor starts discharging and electrons start moving from plate A to B through inductor
L as shown in Fig. 10.3 (e). Again the magnetic field is set-up around the coil but in
opposite direction when the capacitor is fully discharged as shown in Fig. 10.3 (f). The
magnetic field collapses which keep the flow of electrons continuous in the same direction
[See Fig. 10.3 (g)]. When the magnetic field is completely collapsed, the capacitor C is
fully charged as shown in Fig. 10.3 (h) and regains its first position.
Thus, a sequence of charging and discharging of capacitor results in alternating motion
of electrons and produces oscillations Actually, in this L-C circuit, the energy stored in
electrostatic field of capacitor is supplied to inductor and is stored in magnetic field. Then
the energy stored in magnetic field is transferred to the capacitor and is stored in the
electrostatic field. Thus interchange of energy between capacitor (C) and inductor (L) is
repeated over and again resulting in the production of oscillations.
Wave form :
In the given L-C circuit, during each
cycle, there are resistive and radiation
losses in the capacitor. Therefore, the
amplitude of oscillating current
decreases
Fig. 10.4
gradually and eventually becomes zero. Thus, damped oscillations (See Fig. 10.4) are
produced by this circuit
Frequency of oscillations : The value of circuit constants L and C determine the
frequency of oscillations. The actual frequency of oscillations is the resonant frequency
(natural frequency) of the tank circuit and is given by the relation
1
fr = [At resonance I (2p/L) = I/2bfC]
2p LC
10.5 UNDAMPED OSCILLATIONS FROM AN L-C CIRCUIT
As discussed earlier, damped oscillations are produced by an L-C circuit. In order to
make these oscillations undamped, energy of correct magnitude (equal to losses) and proper
phase must be supplied to the circuit to overcome the losses that occur during each half
cycle, In other words, in order to make the osculations in the tank circuit undamped, as
shown in Fig. 10.5, the following conditions must be fulfilled,
(i) The amount of energy supplied should be such so as to meet the losses in the tank
circuit. However, when load is connected, it draws some energy from the tank,
therefore, equivalent additional energy has to be supplied to the tank.
Fig. 10.5
(ii) The applied energy should be in phase with the oscillations su-up in the tank circuit.
(iii) The frequency of the energy supplied to the tank should be the same as that of the
oscillations produced by it.
10.6 POSITIVE FEEDBACK AMPLIFIER AS AN OSCILLATOR
We have seen that negative feedback is employed in amplifiers for their stability.
Whereas, positive feedback is employed in oscillators for their operation. An oscillator is a
device that generates ac output signal without any input ac signal. A fraction of output is
fed back to the input; the feedback signal is the only input to the internal amplifier.
To understand how an oscillator produces an output signal without an external input
signal, consider a block diagram shown in Fig. 10.6. for the time being, assume that v is the
signal applied at the input terminals XY of the internal amplifier with voltage gain A. The
amplified signal available at the output is Av. A fraction of this signal mAv is fed back to the
input (say it reaches at point Z). It must be ensured by the feedback circuit that the feedback
signal mAv must be in phase with the input signal v.
Fig. 10.6 Fig. 10.7
Fig. 10.8 Fig. 10.9 Fig. 10.10

Now, assume that terminal Z is connected with X and input signal v is removed (See
Fig. 10.7). The only signal which is to drive the amplifier is feedback (i.e., mAv). If mA is
less than unity, mAv is less than v and the output signal will die out (damped oscillations)
as shown in Fig. 10.8. On the other hand, if mA is greater than unity, mAv is more than v
and the output signal will built up (grouping oscillations) as shown in Fig. 10.9. However,
if mA is equal to unity, no change occurs in the output and we get an output with constant
magnitude (undamped oscillations) as shown in Fig. 10.10. Thus, to obtain sustained
(undamped) oscillations, the loop gain mA of a positive feedback amplifier must be
unity (one).
Mathematically
Overall gain of a positive feedback amplifier is given by the relation ;
A
A fb =
1 - Am
If Am = 1, then Afb = ¥
Infinity gain means there is output without any input. In other words an amplifier becomes
an oscillator. Hence, a positive feedback amplifier with unity gain (Am = 1) acts as an
oscillator.
It may be noted here that to start an oscillator, the loop gain must be slightly more than one.
10.7 TRANSISTOR OSCILLATOR

The continuous undamped oscillations can be obtained from an oscillatory circuit
(L-C circuit) if a correct amount of energy is supplied to it at correct phase. This can be
achieved by employing a transistor since it has the ability to amplify. A transistor is very
efficient energy converter i.e. it converts d.c. power to a.c. power.
When damped oscillations produced by the tank circuit are applied to the base of
transistor, it will reproduce the amplified oscillations in the collector circuit. The amplified
oscillations will possess more energy in the collector circuit than in the base circuit. If a
part of this collector - circuit energy is fed back by some means to the base circuit in
proper phase, then the losses will be compensated and continuous undamped oscillations
will be produced.
10.8 ESSENTIALS OF A TRANSISTOR OSCILLATOR
Figure 10.11 shows the block diagram of a transistor oscillator. It has the following
essential parts :
Oscillatory circuit
An oscillatory circuit contains inductive coil L and capacitor C connected in parallel
with each other. The frequency of oscillations depends upon the value of inductance of the
coil and capacitance of the capacitor, i.e.
1
fr =
2p LC
Fig. 10.11
Transistor amplifier
To compensate losses that occur in the oscillatory circuit, a source of energy is required.
That source of energy is combination of battery and transistor working as an amplifier.
The oscillations produced by the oscillatory circuit are fed at the input of a transistor
amplifier. The transistor amplifier amplifies these oscillations and an amplified output is
obtained. This amplified output of oscillations is due to the d.c. power supplied by the
battery. The output of the transistor thus obtained can now be supplied back to the oscillatory
circuit to compensate the losses.
Feedback circuit
This circuit is used to feedback a fraction of amplifier output to the oscillatory circuit
in correct phase so that it aid the oscillations and compensate the losses. It, in fact, provides
positive feedback.
10.9 DIFFERENT TYPES OF TRANSISTOR OSCILLATORS
A transistor can work as an oscillator to produce continuous undamped oscillations of
any desired frequency if oscillatory and feedback circuits are properly connected to it. The
basic principle of operation of all oscillators under different names is same, they differ only
in the way of feedback to supply losses to the oscillatory circuit.
The following are the important oscillators usually employed in electronic circuits :
1. Tuned collector oscillator.
2. Hartely oscillator.
3. Colpitt’s oscillator.
4. Phase-shift oscillator.
5. Wein Bridge oscillator.
6. Crystal oscillator.
Let us discuss these oscillators in turn for further details.
10.10 TUNED COLLECTOR OSCILLATORS
This circuit contains a tuned circuit in the collector of the transistor and hence the
name tuned collector oscillator.
Circuit analysis
This oscillator employs an oscillatory circuit L1-C1 in the collector as shown in Fig.10.12.
The frequency of oscillations depends upon the values of L1-C1 and is given by the expression
;
1
f=
2p L1C1
Thus, by setting the values of L1 and C1, oscillations of any desired frequency can be
obtained.The coilL2 in the base circuit is magnetically coupled to L1. In fact, L1 and L2
form the primary and secondary of a transformer.
R1, R2, RE and CE are the components which provide biasing and stabilisation to the
circuit. Capacitor (C) provides a low reactance path to oscillations.
Operation
As long as the switch is open, there is no collector current. When switch is closed, the
collector current starts rising, thus charging capacitor C1. The capacitor C1 will discharge
through coil L1 setting up oscillations of frequency,
1
f=
2p L1C1
Fig. 10.12
These oscillations which are set up in the oscillatory circuit will induce an e.m.f. in the
coilL2 magnetically linked with L1. The frequency of e.m.f. induced in coil L2 is the same
as that of oscillations in the oscillatory circuit but the magnitude will depend upon the
coupling and turn ratio between coil L2 and L1.
The e.m.f. induced in the coil L2 of frequency f = 1/ 2p L1C1 is applied between
base and emitter. This will increase the magnitude of the collector current due to amplifying
properties of the transistor. Of course, the increase in the magnitude of collector current is
due to the power supplied by the collector battery. The frequency of the amplified output
will remain the same i.e., f = 1/ 2p L1C1 . The amplified output in the collector circuit will
supply power to the oscillatory circuit L1-C1, thus compensating for the losses occurring in
it. Hence the oscillations in the oscillatory circuit will be undamped. The output is obtained
from the output coil linking magnetically with L1 as shown in Fig. 10.12.
It is worthwhile to mention here that the energy supplied to the oscillatory circuit to
overcome losses must be in phase with the generated oscillations. This condition has, in
fact, been fulfilled by the circuit. A phase difference of 180° is created in the e.m.f.’s of L1
and L2 through transformer action. A further phase shift of 180° is obtained between base
voltage (i.e. e.m.f. in L2) and output voltage due to the properties of the transistor. Therefore,
the energy supplied to the oscillatory circuit to overcome losses occurring in it is in phase
with the generated oscillations.
Example-10.1
An oscillatory circuit has L = 0.01 H and C = 10 pF, find the frequency of oscillations.
Solution :
1
Frequency of oscillations, f=
2p LC
where, L = 0.01 H ; C = 10 pF = 10 × 10–12F
1 106
f= = = .500 kHz (Ans.)
2p 0.01 ´ 10 ´ 10-12 2p 0.1
Example-10.2
The tuned collector oscillator employed in radio receiver makes use of an LC tuned
circuit with L1 = 0.05 mH and C1 = 30 pF. Find the frequency of oscillations.
Solution :
1
Frequency of oscillations, f=
2p L1C1
where, L = 0.05 mH = 0.05 × 10–3; C1 = 30 pF = 30 × 10–12F
1
\ f= = 4.109 MHz (Ans.)
2p 0.05 ´ 10-3 ´ 30 ´ 10-12
Example-10.3
Find the energy taken by feedback -winding in a tuned collector oscillator with oscillator
current = 2 mA and feedback voltage as 200 mV. Assume b for transistor as 100.
Solution :
Here, Oscillator current i.e. collector current, Ic = 2 mA
Current amplification factor, b = 100
Feedback voltage, Vb = 200 mV = 0.2 V
Ic 2 mA
Currentfed back i.e. base current, Ib = = = 0.02 mA
b 100
Power taken by the feedback winding = Ib × Vb = 0.02 mA x 0.2 V = 0.004 mW (Ans.)
10.11 HARTLEY OSCILLATOR
Hartley oscillator is probably the most popular oscillator and is commonly used in radio
receivers. It is because of its easy adaptability to a wide range of frequencies.
Circuit analysis
Hartley oscillator is similar to a tuned collector oscillator in operation. The circuit
arrangement of a hartley oscillator is shown in Fig. 10.13. It consists of two coils L1 and L2
wound over the same core. Thus mutual inductance exists between them. A capacitor C1
is connected across the combination of L1, L2 to form the L-C circuit. The resistor Rb
between the collector and base provides the necessary biasing. The capacitor C blocks the
d.c. component. The frequency of B oscillations is determined by L1, L2 and C1.
Operation
When switch S is closed, capacitor C1 is charged. This capacitor C1 discharges through
L1 and L2, setting up oscillations of frequency,
1 1
f= =
2p C1 (L1 + L 2 ) 2p C1 (L1 + L 2 + 2M)
Fig. 10.13
The oscillations between O and B are applied in the base circuit and appear in the
amplified form in the collector circuit. This amplified output has the same frequency as
that of oscillatory circuit and supplies the losses which are occurring in the oscillatory
circuit. Clearly, this energy is supplied by the collector battery. Thus energy is being
continuously supplied by the collector battery to make up the losses occurring in the oscillatory
circuit and hence undamped oscillations ate obtained.
It may be noted that energy supplied to the oscillatory circuit is of correct phase. It
can be easily explained. The coils L1 and L2 are magnetically linked with each other so that
points B and A are 180° out of phase. A further phase shift of 180° is produced by the
transistor due to its phase reversal properties. Thus energy from the collector circuit supplied
to oscillatory circuit is of correct phase and ensures proper (positive) feed back.
Example-10.4
In a transistor Hartley oscillator, if L1 =0.1 mH, L2 = 10mH, L2 = 10mH and mutual
inductance between the two coils M = 20 mH, calculate the value of capacitor C1 of
oscillator)’ circuit to obtain frequency of 4110 kHz.
Solution :
In Hatley oscillator, the two coils L1 and L2 are connected in series and coupled
magnetically. Therefore, total inductance of the coils,
L = L1 + L2 + 2M
= 100 mH + 10 mH + 2 × 20 mH (L1 = 0.1 mH = 10 mH)
= 150 mH
1
Frequency of oscillations f =
2p LC
1
or 4110 ´ 103 =
2p 150 ´ 10-6 ´ C
2
æ 1 ö
(2p) 2 ´ 150 ´ 10-6 ´ C = ç 3 ÷
è 4110 ´ 10 ø
1
or C= -6
= 10 pF (Ans)
(2p) ´ 150 ´ 10 ´ (4110 ´ 103 )2
2
10.12 COLPITT’S OSCILLATOR

Colpitt’s oscillator is similar to Hartley oscillator. The only difference is that in case of
Colpitt’s oscillator, coupling is capacitive instead of being inductive.
Circuit analysis
In the Colpitt’s oscillator, the tank circuit consists of an inductive coil L in parallel with
two capacitors C1 and C2 which are in series as shown in Fig. 10.14. The resistor Rb,
between the collector and base provides the necessary biasing. The capacitor C blocks the
d.c. component. The frequency of oscillations is given by :
1
f=
2p LCT
C1C2
where CT =
C1 + C2
Fig. 10.14
Operation
When the switch S is closed, capacitors C1 and C2 are charged with polarities as
shown in Fig. 10.14. These capacitors discharge through the coil L, setting up oscillations
of frequency,
1
f=
2p LCT
The oscillations across C2 are applied to the base circuit and appear in the amplified
form in the collector circuit. Of course, the amplified output in the collector circuit has the
same frequency as that of oscillatory circuit This amplified output in the collector circuit is
fed to the oscillatory circuit in order to supply the losses. In this way, oscillatory circuit is
continuously getting energy from the collector circuit to make up for the losses occurring in
it and hence ensures undamped oscillations. The energy supplied to the oscillatory circuit is
of correct phase and can be easily seen. It is clear that 180° phase difference is created
between points A and B i.e., input is 180° out of phase with output. A further phase shift of
180° is produced by the transistor action.
Example-10.5
Find the operating frequency of a transistor Colpitt’s oscillator if C1 = 30 pF, C2 =
60 pF and L = 10 mH.
C1C2 30 ´ 30 -12
Solution : Total capacitance, CT = C + C = 30 + 60 = 20pF = 20 ´ 10 F
1 2
Inductance of the coil, L = 10 mH = 10 ´ 10-6 H

1
Operating frequency, f=
2p LC
1
= = 11.25MHz (Ans)
2p 10 ´ 10 ´ 20 ´ 10-12
-6
10.13 PRINCIPLE OF PHASE SHIFT OSCILLATORS

One of the desirable features of an oscillator is that it should feed back energy of correct
phase to the oscillatory circuit to supply the losses. In all previous oscillators, a phase
Fig. 10.15
shift of 180° was obtained, due transformer action and a further phase shift of 180° was
obtained due to the transistorpropertiesi.e. a total phase shift of 360° was obtained. In
other words, the energy supplied was 360° out of phase i.e. in phase with the oscillatory
circuit. This provides a positive feedback.
In phase shift oscillators, a phase shift of 180° is obtained with a suitable phase shift
circuit instead of transformer action (as in Hartley oscillator). Further phase shift of 180°
is obtained due to the transistor properties. Thus, energy supplied to the oscillatory circuit,
to make up the losses, is of correct phase.
We know that there is a phase difference of 180° between the input and output) of a
common emitter circuit. Thus, if collector is directly connected to base as shown in Fig.10.15
(a), the feedback is negative (a phase difference of 180°). If we create a further phase
difference of 180° by connecting suitable phase shift circuit between collector and base as
shown in Fig. 10.15 (b), then the energy supplied to the oscillatory circuit will be 180 + 180
= 360° out of phase i.e. in phase.
Phase shift circuit
A phase shift circuit essentially consists of an RC network shown in Fig. 10.16 (a).
Let an alternating voltage applied to this circuit be V and the current flowing through it
be I.
Fig. 10.16
Then,
1
Impedance of the circuit, Z = R 2 + X c2 where Xc =
2pfC
V
\ I=
Z
The current leads the voltage [See Fig. 10.16 (b)] by an angle j.
Xc 1
tan f = =
R 2pfCR
1
\ f = tan -1 ...(i)
2pfCR
It follows, therefore, that the circuit creates a phase difference of f° between the
applied voltage and the resultant current flowing in the circuit. In other words, applied
voltage and the voltage across R have a phase difference of j° .
However, it is desired that this circuit should produce a phase shift j of 180° i.e. the
values of R and C of the network should be so selected that j is 180°. Since tan 180° = 0,
it is clear that this will necessitate very large values of C and R.
Therefore, in actual practice, it is common to use three similar RC sections as shown

in Fig. 10.17 (a). Each RC section is designed to produce a phase shift of 60°. In this way,
a total phase shift of 180° is obtained in the circuit as shown in the phasor diagram of Fig.
10.17 (b).
Fig. 10.17
10.14 R-C PHASE SHIFT OSCILLATOR
A phase shift oscillator employs an R-C network and is commonly called R-C phase
shift oscillator.
Circuit analysis
The phase shift oscillator is shown in Fig. 10.18. The collector is connected to the
base through phase shift network. It may be seen that the phase shift network consists of
three similar sections ; R1 C1, R2 C2 and R3 C3. The values are so selected that each
section produces a phase shift of 60°. Thus the total phase shift of 180° is produced by the
three sections.
Generally, R1, R2 and R3 are made equal. Similarly, C1, C2 and C3 are made equal.
Fig. 10.18
Operation
When the circuit is switched on, current through R3 starts increasing because of biasing.
This charging current induces voltage across R2 through C3. The voltage across R2 leads
the voltage across R3 by 60°. Since three R-C sections are provided, therefore, the phase
shift circuit produces a total phase shift of 60° × 3 = 180°. A further phase shift of 180° is
produced due to the transistor properties. So a total shift of 360° is produced. Therefore,
the fraction of the output fed to the input is in phase with it.
VDD VCC
RD RC
R1
gm.rd
R2
R1 C1 Rg CE
1
f=
2pÖ6 RC f=
1 1
2 pRC 6+4(RC/R)
C C C
R¢ C C C
R R R
R R
(a) (b)
Fig.10.19 : phase-shift oscillator circuits: (a) FET version; (b) BJT version
Rf
+VCC
–
R1
Op-amp
C C C
+ R R R
–VEE
Fig.10.20 : Phase-shift oscillator using op-amp.

Frequency of oscillations :
It can be shown that when R1 = R2 = R3 = R and C1 = C2 = C3 = C, the operating
frequency is given by ;
1 1
f= , b= and phase shift = 180°
2p CR 6 29
For loop gain bA to be greater than unity, A > 29.

Advantages
1. It does not require transformers or inductors, therefore, less bulky.
2. Cheap and simple circuit as it contains resistors and capacitors only.
3. Wave form is exceptionally pure and sinusoidal since the core saturation effect and
harmonic distortion are absent as no transformer is used.
Disadvantages
1. Feedback is less and it is difficult for the circuit to start oscillations. This is because of
high reactance of R and C. On the other hand, in a coil, the inherent reactance is low.
2. It gives only small output due to smaller feedback.
3. It requires high voltage battery Vcc > 12 V. It is because there is a *small feedback so
that a sufficiently high voltage is provided across R3 to begin with.
Example-10.6
A resistance of 10 KW is connected in series with a capacitor. If an alternating
voltage of I kHz is applied across the network, find the value of C for a phase shift of
60°.
Xc 1
Solution We know. tan f = =
R 2pfCR
f = 60°; R = 10 kW = 10 ´ 103 W; f = 1 kHz = 1000 Hz.
1
\ tan 60° =
2p ´ 1000 ´ C ´ 10 ´ 103
1
or 1.732 =
2p ´ 1000 ´ C ´ 10 ´ 103
1
or C= = 0.0092 mF (Ans.)
2p ´ 1000 ´ 10 ´ 103 ´ 1.732
Example-10.7
In a phase shift oscillator, each resistor in R-C network is 10 k while each capacitor
has a value of 0.01 mF. Find the operating frequency of the circuit. What is the phase
shift produced by each R-C section. Comment on the results.
Solution :
Operating frequency of a phase shift oscillator,
1
f=
2p CR 6
where, C = 0.01 mF = 0.01 ´ 10-6 F; R = 10 k = 10 ´ 103 W

1
\ f= -6 = 650 Hz (Ans)
2p ´ 0.01 ´ 10 ´ 10 ´ 103 6
Let the phase shift produced by each section be f °.
1 1
Then, tan f = = = 2.449
2pfCR 2p ´ 650 ´ 0.01 ´ 10-6 ´ 10 ´ 103
f = tan–1 2.449 = 67.79°
10.15 WEIN BRIDGE OSCILLATOR
In the Wein bridge oscillator, phase shift is produced by using two transistors. Each
transistor produces a phase-shift of 180° and hence a phase-shift of 360° is obtained. This
oscillator is a standard oscillator circuit for all frequencies in the range of 10 Hz to about 1
MHz. It is extensively used type of audio-oscillator since its output is free from circuit
fluctuations and ambient temperature.
Circuit analysis
The circuit arrangement of a Wein bridge oscillator is shown in Fig. 10.21. It is essentially
a two-stage amplifier with R-C bridge circuit. The bridge circuit has four arms
Fig. 10.21
C1 a
R1 R3
+VCC
–
d b
Output
Op-amp sinusoidal
R2 R4 signal
+
C2 c
–VEE
1
fa =
R1C1R2C2
Fig.10.22 Wien bridge oscillator circuit using op-amp amplifier

each containing components – R1C1 in series ; R2C2 in parallel ; R3 ; and R4. The transistor
Tr1 with its biasing network serves as an oscillator and amplifier while the other transistor
Tr2 with its biasing network serves as an inverter (i.e. it is used for phase reversal). The
frequency of oscillations is provided by the series element R1C1 and parallel elements
R2C2 of the bridge network.
Operation
When circuit is closed through switch S, the bridge circuit produces the oscillations of
frequency determined by the expression ;
1
f=
2p R1C1R 2 C 2
If R 1 = R 2 = R and C1 = C 2 = C then
1
f=
2pRC
The desired frequency of oscillations can be produced by varying the two capacitors
C1 and C2 simultaneously. These oscillations are fed to first transistor Tr1. After amplification
these oscillations are fed to the second transistor. It may be noted that first transistor Tr1
serves as an amplifier and second transistor Tr2 serves as an inverter. A total phase-shift of
360° (180° + 180°) is obtained at the output of the second transistor. A fraction of this
output energy is fed back to the oscillatory circuit (the bridge) at the upper terminal. This
positive feedback is to meet with the losses in the oscillator and hence undamped oscillations
are produced.
A negative feedback ensures stability and constant output. This negative feedback is
provided through the voltage divider (R3 and R4) to the input of Transistor Tr2. Usually, a
temperature sensitive tungsten lamp is used in place of R4. Its resistance increases with
current. As soon as, the amplitude of output tend to increase, more current would provide
more negative feedback. This brings back the output to its original value. A reverse action
would take place if the output tends to decrease.
Advantages
(i) It has far better stability.
(ii) Output is constant
(iii) Its working is quite simple and easy.
(iv) Overall gain is high as two transistors are employed.
(v) Frequency of oscillations can be easily adjusted by varying gang capacitors C1 and
C 2.
Disadvantages
(i) Costlier as more components are used.
(ii) Cannot be used to generate very high frequencies ( > 1 MHz).
Example-10.8
In the RC network of a Wein bridge oscillator R1 = R2 = 220 kW, determine the value
of each of the gang capacitor to obtain a frequency of 3 kHz at the output.
Solution
The frequency of oscillations obtained at the output of a Wein bridge oscillator is expressed
as ;
1
f=
2pRC
where, f = 3 kHz = 3000 Hz; R1 = R2 = R = 220 kW = 220 × 103W
1
\ 3000 =
2p ´ 220 ´ 103 ´ C
1
or C= = 241 pF (Ans.)
2p ´ 220 ´ 103 ´ 3000
10.16 LIMITATIONS OF RC AND LC OSCILLATORS
So far, we have studied the oscillators in which the oscillations were produced by the
oscillatory circuit containing either R and C or R and L in parallel. The major problem in
these circuits is that their frequency of operation does not remain perfectly constant. It is
because the values of resistors and inductors change with temperature. However, in some
of the applications it is necessary to maintain constant frequency with an extremely low
tolerance. For instance, in case of radio broadcasting the tolerance should not be more
than 0.002% otherwise the signals of nearby broadcasting stations will overlap. In such
applications, the use of RC and LC oscillators is avoided.
The solution to this problem is use of crystal oscillators. In crystal oscillators,
piezoelectric crystals are employed in place of RL or RC circuit The frequency of crystal
oscillator remains more or toss perfectly constant even if temperature changes.
10.17 PIEZOELECTRIC EFFECT AND CRYSTALS
When an ac voltage is applied across a crystal, it starts vibrating at the frequency
of supply voltage, this effect is known as piezoelectric effect and the crystals which
exhibit this effect are known as piezoelectric crystals. Conversely, when these crystals
are compressed or placed under mechanical strain to vibrate, they produce an ac voltage.
The known piezoelectric materials are Rochelle salt, quarts and tourmaline. Out of
the three, rochelle salts exhibit the greatest piezoelectric activity, but they are mechanically
very weak and could not beer the mechanical stresses. However, these are used to make
microphones, headsets and loudspeakers etc. On the other hand, tourmaline is most rugged
but shows the least piezoelectric property. Moreover, it is most expensive, therefore,
occasionally used at very high frequencies.
Quarts is the most suitable material as it exhibits the piezoelectric activity almost as
that of Rochelle salts and mechanical strength as that of tourmaline. Moreover, it is very
less expensive and readily available in nature. Hence, quarts crystal is invariably used hi rf
oscillators (i.e., crystal oscillators).
10.18 CHARACTERISTICS OF CRYSTAL
Quartz crystals are usually employed in crystal oscillators because of their high
mechanical strength, easy availability and simple manufacturing. The natural shape of this
crystal is hexagonal but it is cut in different ways i.e. perpendicular to x-axis or perpendicular
to v-axis. The piezoelectric properties of a crystal depend upon its cut.
Crystal frequency
The natural frequency of a crystal is given as
K
f=
t
where K is a constant which depends upon the dimensions of the crystal, the cut (i.e. y-cut
or y-cut) and its mounting. The above equation shows that the natural frequency of the
crystal is inversely proportional to its thickness i.e. the thinner the crystal greater is the
frequency and vice-versa. However, thin crystals have poor mechanical strength and may
break because of quick vibrations. This imposes limit to the frequency which can be obtained
from the crystals. In general practice, frequencies between 25 kHz to 5 MHz are obtained
with crystals.
Fig. 10.23
Crystal’s working
When a crystal is mounted between two plates, as shown in Fig. 10.23 (a), it forms a
capacitor Cm because of the fact that two metal plates separated by a dielectric (i.e.,
crystal) forms a capacitor. If an ac voltage is applied across the plates, the crystal starts
vibrating at the frequency of applied voltage. However, if the frequency of the crystal,
resonance takes place and crystal vibrations reach a maximum value.
Although the crystal has electromechanical resonance, but we can represent its action
by an equivalent electrical resonant circuit shown in Fig. 10.23 (b);
where, Cg = series capacitance due to air gap

Cm = mounting capacitance
R-L-C = electrical equivalent resonant circuit of the crystal
The crystal has two resonant frequencies viz series resonant frequency and parallel resonant
frequency.
(i) Series resonant frequency (fs): It is due to R-L-C branch and is given as ;
1
fs = Hz
2p LC
where L and C are in henry and farads respectively.
(ii) Parallel resonant frequency (fp): It is due to combined circuit i.e. Cm in parallel
with R-L-C circuit. The parallel resonant frequency is given as ;
1
fp = C ´ Cm
2p LCT where CT =
C + Cm
Usually, the value of Cm is much larger ( – 3.5 pF) than C, therefore, the frequencies
and fs are very close to each other. Otherwise fp is always more than fs. However, when
crystal is used in an oscillator, the oscillation frequency always lie between fs and fp.
10.19 TRANSISTOR CRYSTAL OSCILLATOR
When a constant high frequency (25 kHz to 5 MHz for radio broadcasting transmitters)
is required, a transistor crystal oscillator is always preferred.
Fig. 10.24
Circuit analysis
The circuit arrangement of a transistor crystal oscillator is shown in Fig. 10.24. A tank
circuit L1 – C1 is placed in the collector and the crystal is connected in the base circuit
through a feedback coil L2. Where L2 is inductively coupled to the coil L1.
The natural frequency of L1-C1 circuit is made nearly equal to the natural frequency of
crystal. Another coil L is inductively coupled to L1 to obtain output.
Operation
When power is turned on by closing the switch S, capacitor C1 is charged. When it
discharges through L1, it sets-up oscillations. As coil L2 is magnetically coupled to L1,
voltage is induced in this coil and hence power is fed back to the transistor in *positive
direction causing oscillator to produce oscillations. As crystal is connected in the base
circuit, therefore, its influence is much more than L1-C1 circuit. Thus, the frequency of
oscillations produced by the oscillator are controlled by the crystal. Consequently, the entire
circuit starts operating at the natural frequency of the crystal, hence the name crystal
oscillator.
Advantages
(i) As frequency of crystal is independent of temperature, these oscillators have a high
order of frequency stability.
(ii) The quality factor (Q) of crystal is very high (nearly 10 000 in comparison to about
100 of L-C tank).
Disadvantages
(i) Frequency of oscillations cannot be changed if desired.
Example-10.9
If L = 800 mH, C = 0.01 pF, R = 1000 W and Cm = 20 pF are the various values of an
ac equivalent circuit of a piezoelectric crystal. Determine fs and fp of the crystal.
1
Solution : We know, fs =
2p LC
where L = 800 mH = 0.8 H ; C = 0.01 pF = 0.01 × 10–12F ;
Cm = 20 pF
1
\ fs =
2p 0.8 ´ 0.01 ´ 10-12 = 1779.40 kHz (Ans.)
1
Now, fp =
2p LCT
C ´ Cm 0.01 ´ 20
where CT = = = 9.995 ´ 10-3 pF
C + Cm 0.01 + 20
1
\ fp = =1779.85 kHz (Ans.)
2 p 0.8 ´ 9.995 ´ 10 -3 ´ 10 -12
Hence, the frequency will lie between 1779.40 to 1779.85 kHz if this crystal is used in the
crystal oscillator.

Q.1 What is an oscillator ?
Ans. Oscillator may be defined as a circuit which generates an ac output signal of very high
frequency without requiring any externally applied input signal or it may be defined as an
electronic source of alternating current (or voltage) having sinusoidal or non-sinusoidal
(square, sawtooth or pulse) waveshape. It can also be defined as a circuit that converts dc
energy into very high frequency ac energy.
Q.2 What is the initial condition for oscillation to start ?
Ans. Initial condition for oscillation to start is loop gain b A > 1.
Q.3 What are the Barkhausen conditions of oscillations ?
Ans. Barkhausen conditions for sustained oscillations are :
(i) the loop gain of the circuit must be > 1 and
(ii) the phase shift around the circuit must be zero.
Q.4 Can every electronic oscillator be considered to be an amplifier with an infinite gain? If
yes, where from starting signal voltage comes ?
Ans. Yes. Starting signal voltage comes from noise inherent in the transistor or variation in
voltage of dc power supply.
Q.5 Why are L-C resonant circuit impractical at audio-frequencies ?
Ans. L-C resonant circuits are impractical at audio-frequencies because components required
in their construction for low-frequency operation are too bulky and heavy and expensive.
Q.6 How does Clapp oscillator circuit differ from Colpitt’s oscillator circuit in construction ?
Ans. Clapp oscillator circuit is a refinement of the Colpitt’s oscillator circuit. The only difference
is that the single inductor found in the tank circuit of the Colpitt’s oscillator is replaced by
a series L-C combination (inductor L in series with capacitor C).
Q.7 Why Clapp oscillator is preferred over the Colpitt’s oscillator ?
Ans. In a Colpitt’s oscillator, the resonant frequency is affected by the transistor and stray
capacitances but in a Clapp oscillator, the transistor and stray capacitances have no effect
on the oscillation frequency. Thus in Clapp oscillator the effect of transistor parameters on
the operation of the circuit is eliminated and the frequency stability is improved. That is
why, Clapp oscillator is preferred over Colpitt’s oscillator.
Q.8 How does Hartley oscillator differ from Colpitt’s oscillator in construction?
Ans. Hartley oscillator circuit is similar to Colpitt’s oscillator except that phase-shift network
consists of two inductors and one capacitor instead of two capacitors and one inductor.
Q.12 Why beat frequency oscillator has become obsolete now ?
Ans. Beat frequency oscillator has become obsolete now because its circuit is quite complicated.
Q.13 How does a signal generator differ from an ordinary oscillator?
Ans. The signal generator, like an ordinary oscillator, is a source of sinusoidal signals but it is also
capable of modulating its sinusoidal output signal with other signals. This is the main
difference between the signal generator and an ordinary oscillator.
Q.14 Why use of regulated power supply is essential for signal generators ?
Ans. Frequency of output voltage from a signal generator changes with the change in supply
voltage so use of regulated power supply is essential.
Q.15 Why are buffer amplifiers used in signal generators ?
Ans. Buffer amplifiers are used in the signal generators for isolating the oscillator circuit from
the output circuit so that any change in the circuit connected to the output does not affect
the frequency and amplitude of the oscillator output.
Q.16 Why are temperature compensating devices used in signal generators ?
Ans. In signal generators, oscillator output frequency varies with the variation in temperature,
so temperature compensating devices are used.
Q.17 Why in signal generators quartz crystal is used in place of an L-C oscillator ?
Ans. Q-factor of the L-C circuit for signal generator is required to be very high, say above
20,000. This can be achieved by using quartz crystal oscillator in place of L-C oscillator.
EXERCISE
1. A tuned collector has a fixed inductance of 100 uH and has to be tunable over the frequency
band of 500 KHz to 1500 KHz. Find the range of variable capacitor to be used.
[Ans. 113 -1015 pF]
2. A tuned collector oscillator employs a transformer whose primary inductance is 10 mH.The
capacitor connected across the primary has a capacitance of 100 pF. The d.c. resistance
of the primary coil is 10 ohm and the transistor used has hie = 1 KW , hre = 10–4, hfe = 50
and hoe = 10–4 A/V. Find the frequency of oscillation and the mutual inductance between
the primary and secondary coils required to sustain the oscillations.
[Ans. 159-2 kHz, 19-02 mH ]
3. A Hartley oscillator is to span a frequency range from 50 KHz to 150 KHz. The variable
capacitance has the values in the range 50 pF to 450 pF. The transistor to be used has
hfe = 50 and Dh = 0·5. Determine the values of the inductances. Neglect mutual inductance
between the coils and use CE circuit configuration.
[Ans. L1 = 0·225 mH and L2 = 22·28 mH]
4. For a Hartley oscillator, if self inductance of the two coils are L1 = 100 mH, L2 = 1 mH and
mutual inductance between the two coils is 20 mH. Find the frequency of oscillations at its
output for a capacitor of value 20 pF. [Ans. 1054kHz]
5. Determine the frequency of oscillation for a colpitt’s oscillator in which feedback network
consists of two capacitors of 100 pF and 20 pF with 100 mH coil across these two capaci-
tors. [Ans. 123·28 kHz]
6. A phase shift oscillator using a transistor has the parameter values RL = 3·3 kW, R = 5·6
kW and C = 0·01 mF. Calculate frequency of oscillations and hfe required for sustaining the
oscillations.
ppp
Operational Amplifier
11.1 INTRODUCTION
An operational amplifier (Op-amp), is a multistage, very high gain, direct coupled

differential amplifier.
The world operational stands for various mathematical operations like addition,
subtraction, multiplication, differentiation, integration etc. and amplifier is one that boosts
the input signal.
As this circuit performs both mathematical operations and amplifications, it is named
as op-amp.
This circuit can be used for designing filters and oscillator circuits.
11.2 CHARACTERISTICS OF OP-AMP

(i) High input impedance (Ideally ¥ )
(ii) Low output impedance (Ideally 0)
(iii) Can amplify dc as well as ac input signals
(iv) High bandwidth (Ideally ¥ )
(v) High value of differential gain (Ideally ¥ )
(vi) High value of CMRR (Common made rejection ratio)
(vii) High slew rate,
(viii) Stabilized output.
11.3 BLOCK DIAGRAM OF A TYPICAL OPERATIONAL AMPLIFIER
An operational amplifier being a multistage amplifier, consists of some basic building
blocks as shown in block diagram (fig 11.1).
Operational Amplifier 353
NON INVERTING
INPUT
LEVEL OUTPUT
INPUT INTERMEDIATE OUTPUT
SHIFTING
STAGE STAGE STAGE
STAGE
INVERTING
INPUT DUAL-INPUT DUAL-INPUT EMITTER COMPLEMENTARY
BALANCED OUTPUT UNBALANCED FOLLOWER SYMMETRY
DIFFERENTIAL OUTPUT WITH CONSTANT PUSH-PULL
AMPLIFIER DIFFERENTIAL CURRENT SOURCE AMPLIFIER
AMPLIFIER
Fig. 11.1 Block Diagram of a Typical Op-amp
The block diagram of an op-amp shown in fig 11.1 consists of a four stage direct
coupled amplifier in cascade. In summarized form, it can be explained as below.
The first stage/input stage is double-ended high-gain (60 db) differential amplifier
i.e. dual-input balanced output differential amplifier with a constant current source (in
order to increase CMRR). In this stage high gain is desirable so that there would be a
negligible effect on the output of any short-coming in the following stages. This is the
reason why this stage is generally responsible for most of the gain of op-amp. Also this
stage determines the input resistance of the op-amp. Output of this stage is taken between
collectors of two emitter biased circuits so that output remains balanced and the dc voltage
at output in quiescent condition maintains zero level.
The second stage, called the intermediate stage, is usually another differential
amplifier, which is driven by the output of first stage. In most amplifiers the intermediate
stage is dual input, unbalanced (single-ended) output differential amplifier in order to increase
the gain. The differential mode voltage gain of such an amplifier is half of the gain of the
dual-input balance output type differential amplifier. In this amplifier output is measured at
the collector of only one of the two transistors w.r.t. ground. In the quiescent condition
some dc voltage exists at the output terminal and there is no other collector voltage at
output to balance or nullify this output dc voltage. This is the reason why this type of
amplifier is called unbalanced output type differential amplifier. This unbalanced dc voltage
present at the output acts as an error voltage in the desired output signal.
The third stage, known as level shifting stage, is usually an emitter follower circuit
in order to shift the dc level at the output of the intermediate stage downward to zero volt
with respect to ground. It is worthmentioning here that error signal is developed in the
intermediate stage due to direct coupling and gets amplified in the succeeding stages. This
increase in dc level tends to shift the operating point of the succeeding stages which also
limits the output voltage swing or may distort the output signal. To overcome these problems,
use of a level translator (shifter) circuit becomes necessary to bring this dc level to zero
voltage (ground potential).
The final stage, called output stage, is usually a push-pull complementary amplifier.
This stage increases the output voltage swing and the current supplying capability of the
amplifier. A well designed output stage also provides low output resistance. The output of
the op-amp is the voltage measured at output of this final stage push-pull amplifier with
respect to ground.
Equivalent circuit of an op-amp (MC 1435)
Fig. 11.2 Equivalent circuit of the MC 1435 op-amp. [Courtesy of Motorola Semiconductor Inc.
11.4 SCHEMATIC SYMBOL OF AN OP-AMP

The schematic symbol of an op-amp is shown in fig 11.3 (a). A is the voltage gain, v1 is
non-inverting input and v2 is inverting input. The differential input is
vin or vd = v1 – v2
and output voltage, vout = A vin = A (v1 - v2)
Note that voltages VI, v2 and vout are node voltages. This means that they are always
measured with respect to ground. The differential input vin is the difference of two node
voltages v1 and v2.
NON-INVERTING
INPUT
NON-INVERTING
+ NON-INVERTING
INPUT
INVERTING A INPUT TERMINAL
INPUT
+
v1
v out b OUTPUT
v2 TERMINAL
INVERTING
INPUT
INVERTING
– (b) INPUT TERMINAL
–
(a)
Fig 11.3
Often, the common ground line is omitted and the schematic symbol becomes, as illustrated
in fig. 11.3(b).
Most widely used circuit symbol for an op-amp is shown in fig. 11.3(c). It essentially
consists of two input terminals and one output terminal. Here the inputs are marked with plus
(+) and minus (–) to indicate non-inverting and inverting inputs, respectively. A signal applied
to the plus input appears with the same polarity and amplified at the output, while an input
applied to the minus terminal appears amplified but inverted at the output.
It should be clearly understood that plus and minus signs never mean that the voltages
v1 and v2 are positive and negative respectively. It also does not imply that positive
voltage is to be applied to the terminal marked positive and negative voltage to the
terminal marked negative.
The output voltage is directly proportional to the input voltage which is the difference of
vl and v2 (i.e. vin = v – v2). The constant of proportionality is the voltage gain of the amplifier
and is denoted by English letter A.
The op-amp’s input can be single-ended or double-ended or differential input depending
whether the input voltage is applied to one input terminal only or to both. Similarly output can
also be either single- ended or double-ended. Most commonly used configuration is two input
terminals and one output terminal.
Op-amps have five basic terminals namely two input terminals (non-inverting input
terminal and inverting input terminal), one output terminal and two power supply terminals
(–ve bias supply terminal and + ve bias supply terminal). The significance of other terminals
varies with the type of the op-amp.
11.5 IDEAL OP-AMP

The op-amp is said to be ideal if it has the following characteristics.
1. Its open-loop gain A is infinite. When an op-amp is operated without any connection
between the output and any of the inputs (i.e. without feedback), it is said to be in the
open-loop condition. Infinite voltage gain means the voltage difference required
between the two inputs to produce any output voltage is zero.
2. Its input resistance (i.e. the resistance measured between inverting and non-inverting
terminals) Rin is infinite. It means that the input current (current drawn from the
source) is zero and so it does not load the source. It also means that an ideal op-amp
is a voltage controlled device.
3. Its output impedance Rout is zero i.e. the output voltage Vout does not depend on the
load resistance connected between the output terminals i.e. output voltage Vout is
independent of the current drawn by the load. The output thus can drive an infinite
number of other devices.
4. Perfect balance. Because of infinite voltage gain, the voltage between the inverting
and non-inverting terminals of input i.e. differential input voltage Vd = V2 - Vl is
essentially zero (i.e. Vx = V2) for infinite output voltage Vout. This implies that Vl and
V2 track each other i.e. a virtual short-circuit exist between the two input terminals
but with no current flowing between the two terminals, as Rin is infinite.
5. Infinite frequency bandwidth i.e. it has flat frequency response from dc to infinity so
that any frequency signal from zero to infinity Hz can be amplified without attenuation.
6. Drift of characteristics with temperature is nil.
7. Common mode rejection ratio (CMRR) is infinite so that amplifier is free from
undesired common-mode signals such as pickups, thermal noise etc
8. Slew rate is infinite so that output voltage changes occur simultaneously with input
voltage changes.
9. Output voltage is zero when input voltage is zero i.e. offset voltage is zero.
Because of having infinite input resistance and zero output resistance, ideal op-amp
behaves as an ideal voltage controlled voltage source (VCVS).
11.6 EQUIVALENT CIRCUIT OF AN OP-AMP
Fig 11.4 shows an op-amp equivalent
circuit, which is useful in analyzing the
basic operating principles of op-amps
and in observing the effects of NON-INVERTING
TERMINAL
feedback arrangements.
The voltage source A v d is an
equivalent. Thevenin voltage source, INVERTING
TERMINAL
and Rout is the Thevenin equivalent
resistance looking back into the output Fig. 11.4
terminal of the op-amp.
The output voltage of the circuit shown in fig 11.4 is given as
vout = A vd = A (v1 – v2)
where A is large signal voltage gain, vd is differential input voltage, v1 and v2 are the input
voltages at non-inverting and inverting terminals respectively with respect to ground.
Here output voltage is directly proportional to the algebraic difference of the two input
voltages which means the op-amp amplifies the difference between the two input voltages,
not the input voltages themselves. For this reason the polarity of the output voltage depends
on the polarity of the difference voltage vd .
11.7 IDEAL VOLTAGE TRANSFER CURVE
The curve drawn between output voltage
vout and input differential voltage v d
keeping gain A constant (Fig. 11.5)
represents the equation
vout = A vd = A (v1 – v2)
graphically. The curve shown in fig 11.5
is known as an ideal voltage transfer
curve, ideal because in drawing this curve
output offset voltage is assumed to be
zero. In normal op-amp use (with
negative feedback), the output offset
voltage is nearly zero and is ignored for
simplifying the calculations.
The curve shown in fig 11.5 reveals that
the output voltage uout cannot exceed the
positive and negative saturation voltages. Fig. 11.5
Positive and negative saturation voltages are specified by an output voltage swing
rating of the op-amp for given values of supply voltages. In other words it can be stated
that the output voltage uout increases in direct proportion to the input differential voltage vd
only until it attains the saturation value and then it becomes constant, as shown in fig 11.5.
11.8 BASIC OP-AMP CIRCUIT
The basic circuit of an op-amp is shown in fig. 11.6(a). An input signal V2 is applied
through a resistor R1 to the inverting or minus input terminal. The output voltage is fedback
through resistor R, to the same input terminal. The non-inverting or plus input terminal is
connected to earth. For determination of overall gain of the circuit i.e. some more details
of the op-amp unit will have to be considered.
Fig. 11.6 (b) shows the op-amp replaced by an equivalent circuit having input resistance
Rin and output voltage source and resistance. As an ideal op-amp has infinite input resistance
(i.e. Rin = ¥), zero output resistance (i.e. Rout = 0) and infinite voltage gain (i.e. A = ¥), the
connection for the ideal amplifier is illustrated redrawn in figs 11.6 (c) and 11.6 (d).
Using superposition theorem we can solve for the input voltage Vin in terms of the
components due to each of the sources.
For source V2 only (assuming — A Vin to be zero)

Rf
V1in = V2
R1 + R f
For source – A Vin only (assuming V1 to be zero)
Fig 11.6
V2 in =
R1
R1 + R f
b- AVin g
R f V2 A R1Vin
Total input voltage Vin = V1in + V2 in = -
R1 + R f R1 + R f
R f V2
or Vin = R + R (1 + A )
f 1
If A >> 1 and A R1 >> Rf as is usually true, then

Rf
Vin ~ V2
A R1
Vout -A Vin -A R f V2 - R f
= = =
V2 V2 V2 A R1 R1
It is obvious that the ratio of overall output to the input voltage is dependent only on the
values of resistors R1 and R, provided A is very large.
11.9 COMMON-MODE REJECTION RATIO (CMRR)

CMRR is defined as the ratio of differential
Ad
voltage gain to common-mode voltage gain
A CM A
and it is given as CMRR = d Fig 11.7
AC
If a differential amplifier is perfect, CMRR would be infinite because in that case
common-mode voltage gain AC would be zero.
Fig. 11.7 represents a linear active device with two input signals V1 and V2 and one
output signal Vout , each measured with respect to ground. In an ideal differential amplifier
the output signal Vout should be given as
Vout = A (V1 – V2)
where A is the gain of the differential amplifier.
Common to both the inputs will have no effect on the output voltage. However, in a
practical differential amplifier, the output not only depends upon the difference signal Vd of
the two input signals, but also upon the average level, called the common-mode signal VC
where
V1 + V2
Vd = V1 - V2 and VC =
2
Now let the output voltage Vout in fig 11.7 be expressed as a linear combination of two
input voltages as below
Vout =A1V1 + A2V2
where A1 is the voltage gain for input Vl with V2 grounded and A2 is the voltage gain for
the input V2 with V1 grounded.
Here
V1 = VC +
1
Vd
U|
V1 + V2
2
1 |
V by solving V d = V1 - V2 and VC =
2
2 |W
and V2 = VC - V d
Substituting the values of V1 and V2 from above equation in Vout =A1V1 + A2V2 ,
FG
1 1 IJ FG IJ
H
Vout = A 1 VC + Vd + A 2 VC - Vd
2 2 K H K
=
1
2
b g
A 1 - A 2 Vd + (A 1 + A 2 VC )
= A d Vd + A C VC
A1 - A 2
where A d =
2
b
and A C = A1 + A 2 g
and AC = (A1 + A2)
Here Ad is the voltage gain for the difference signal while AC is the voltage gain for the
common-mode signal.
Having measured Ad and AC for the amplifier, CMRR can be determined from the following
relation.
Ad
CMRR =
AC
The value of CMRR can also be expressed in logarithmic terms as
Ad
CMRR (log) = 20 log
AC
The expression for the output voltage can be given as
VO = A d Vd + A C VC
FG A V IJ
H K
C C
= A d Vd 1+ A . V
d d
FG
Þ Vout = A d Vd 1 +
1 VC IJ
H CMRR Vd K
Example-11.1
A differential dc amplifier has a differential mode gain of 100 and a common mode gain
0.01. What is its CMRR in db ?
Solution: Differential mode gain, Ad = 100
Common-mode gain, AC = 0.01
A d 100
CMRR = A = 0.01 = 10
4
CMRR in db, CMRR = 20log10 CMRR = 20 log10 104 = 20 × 4 = 80 db Ans

Example-11.2
For a given op-amp, CMRR = 105 and differential gain Ad = 105. Determine the common-
mode gain, AC of the op-amp. Solution: Differential voltage gain, Ad = 105
Solution : Differential voltage gain, Ad = 105
CMRR = 105
Ad
Q CMRR = A
C
Ad 105
Q Common-mode gain AC = = =1 Ans
CMRR 105
Example-11.3
A differential amplifier has inputs VS1 = 10 mV and VS2 = 9 mV. It has a differential mode
gain of 60 db and a CMRR of 80 db. Find the percentage error in the output voltage and
the error voltage. Derive the formula used in your calculations.
Solution : Inputs V1 = 10 m V and V2 = 9 mV
Difference signal Vd = V1 – V2 = 10 – 9 = 1 mV
V1 + V2 10 + 9
Common mode signal VC = = = 9.5 m V
2 2
60
Difference voltage gain Ad = 60 db or antilog = 1,000
20
80
CMRR = 80 db or antilog = 10,000
20
FG 1 . V IJ
Output voltage, Vout = A d Vd 1 +
H CMRR V K
c
L 1 ´ 9.5OP = 100095
= 1,000 × 1 mv M1 +
N 10,000 1 Q . V
Ad Vd = 1,000 × 1 m V = 1 V
So error voltage = Vout – Ad Vd = 1.00095 – 1.0 = 0.00095 V or 0.95 m V
Ans.
& error = Error voltage ´ 100 = 0.00095 ´ 100 = 0.095% Ans.

Vout 100095
.
Example-11.4
Sketch the circuit of summing circuit using op-amp to get
V0 = – V1 + 2V2 – 3 V3.
Solution : In a summing circuit output is given by
Vout = -
LM R f
V1 +
Rf R
V2 + f V3
OP
NR 1 R2 R3 Q
Comparing the above expression with the given expression for the output
i.e Vout = – V1 + 2 V2 – 3 V3 = – [V1 – 2 V2 + 3 V3]
Rf Rf Rf
we have = R = 1, R = 2, R = 3
1 2 3
Taking Rf = 6 kW we have
R1 = Rf = 6 kW
6 kW
V1
R 3 kW 6 kW
R 2 = f = 3 kW -V 2
2 – V0
2 kW
Rf +
R3 = = 2 kW V3
3
Fig. 11.8
The circuit is shown in fig 11.8
11.10 OP-AMP SPECIFICATIONS
11.10.1 DC Offset parameters
When Op-amp is given of input then it is expected that output voltage should be zero but it
is not the real case. There is same offset voltage at the output.
The output offset voltage can be due to
i) input offset voltage
ii) input offset current
iii) input bias current
i) Input offset voltage (VIO)
* It is the voltage that must be applied at the input terminals of an op-amp to null the
output.
* Smaller the value of input offset voltage, better the input terminals are matched.
* If A = gain of the op-amp.
Vo = AVi
æ R1 ö
= A ç VI0 - Vo ÷
è R1 + Rf ø
é R1 ù
Þ Vo ê1 + A¢ ú = AVI0
ë R1 + R f û
A
Þ Vo (offset) = VI0
R1
1+ A
R1 + R f
R1 + R f
= VI0
R1
Fig. 11.9
æ R ö
Þ Vo (offset) = ç1 + f ÷ VI0
è R1 ø
(ii) Input offset current (II0)

* The algebraic difference between the currents into inverting and non-inverting terminals
is referred as input offset current.
Fig. 11.10 (circuit showing input bias current) Fig. 11.11 (Equivalent current of Fig 11.10)
Let I B1 & I B2 are the bias currents. Let V01 & V02 are the output voltage due to the bias
currents I B1 & I B2 respectively..
æ -R f ö
V01 = IB1 R1 ç ÷
è R1 ø
æ R ö
V02 = I B2 R 2 ç1 + f ÷
è R1 ø
V0 (offset due to IB1 & I B2 ) = V02 + V01

considering R1 = R2 = R, R << Rf
and I I0 = IB2 - I B1 ,
We can get Vo (offset) = IB2 (R + R f ) - I B1 R f
= I B2 R f - I B1 R f
= R f (I B2 - IB1 )
Þ V0 (offset) = I I0 R f
* Total output offset voltage due to VI0 & I I0 is given by
V0 (offset) = V0 (offset due to VI0 ) +
V0 (offset due to II0 )

(iii) Input bias Current (IB)

It is the average of the currents that Flow into the inverting & non-inverting terminals of
the op-amp.
IB1 + I B2
IB =
2
11.10.2 AC offset parameters of Frequency Parameters
An op-amp is designed to be a high gain and wide bandwidth amplifier.
(i) Gain - Bandwidth product
Because op-amp is a direct coupled high gain differential amplifier. It has no input
coupling, output coupling and bypass capacitors. So unlike normal RC coupled amplifier at
lower frequencies the gain is maximum which is same as the mid frequency gain. At
higher frequencies, the voltage gain drops.
Normally the voltage differential gain
(AVD) of the op-amp has very large value.
As the frequency of the input signal increases
the gain becomes 1. This frequency (f1) is
known as unity gain bandwidth.
Another frequency (fc) is known as cut-off
frequency where gain drops by 3dB
compared to AVD.
fc, f1 & AVD are related as f1 = AVDfc Fig. 11.12
This is also called unity gain Bandwidth product.
Slew Rate.
Gain bandwidth (GBW) and rise time are both characteristics of small signals, where
peak output voltage Vpeak is less then 1 V. For many front-end applications this may be
adequate, but most power or driver stages must output larger signals. For larger signal
outputs, Vpeak > 1 V, the op-amp’s speed is limited by the slew rate.
The slew rate of an op-amp is defined as the maximum rate at which the output
voltage can change, no matter how large an input signal is applied.
d Vout
i.e. SR =
dt max
This is usually measured in V/m s. the instantaneous change in input voltage does not
appear instantaneously but slews so many volts in a given period of time.
The slew rate provides a parameter that specifies the maximum rate of change of the
output voltage when driven by a large step-input signal. If one tried to drive the output at a
rate of voltage change greater than slew rate, the output would not able to change fast
enough and would not vary over the full range expected, resulting in signal clipping or
distortion. In any case the output would not be an amplified duplicate of the input signal if
the op-amp slew rate is exceeded.
Slew Rate Equation. Since the slew rate on a data sheet is generally listed for unity gain,
let us consider the voltage follower circuit. Further more let us assume that input is a large-
amplitude and high-frequency sinusoidal wave. The equation of the input and output are as
given below:
Vin=Vpinsin w t andVout = VPoutsin w t
Rate of change of the output is
d Vout
= VP out w cos w t
dt
and the maximum rate of change of the output occurs when cos w t = 1 i.e.,
d v out
= VP out w
dt max
or slew rate SR = 2p f Vp out

where f is input frequency in Hz and Vp out is the peak value of the output sinusoidal wave
in volts.
Maximum Signal Frequency
The maximum frequency that an op-amp may operate at depends on both the bandwidth
(BW) and slew rate (SR) parameters of the op-amp. For a sinusoidal signal of general
form
v0 = K sin(2pft)
the maximum voltage rate of change can be shown to be
signal maximum rate of change = 2pfK V/s
To prevent distortion at the output, the rate of change must also be less than the slew rate,
that is,
2pfK < SR SR
wK < SR
SR
f£ Hz
2pK
so that SR
w£ rad / s
K
Additionally, the maximum frequency, f, is also limited by the unity-gain bandwidth.


Q.1 What is an operational amplifier ?
Ans. An operational amplifier, abbreviated as op-amp, is basically a multistage, very high gain,
direct-coupled negative feedback amplifier that uses voltage shunt feedback to provide a
stabilized voltage gain.
Q.2. What is voltage gain of a practical op-amp ?
Ans. Voltage gain of a practical op-amp is of the order of 105.
Q.3. State assumptions made for analyzing ideal op-amp.
Ans. Assumptions made for analyzing ideal op-amp are (i) infinite open-loop gain (ii) infinite
input impedance (iii) zero output impedance (iv) perfect balance (v) infinite frequency
bandwidth, (vi) infinite slew rate (vii) infinite common mode rejection ratio and (viii) nil drift
of characteristics with temperature.
Q.4. What is a voltage transfer curve of an op-amp ?
Ans. The curve drawn between output voltage and input differential voltage, for an op-amp,
keeping gain A constant is known as voltage transfer curve.
Q.5. What are differential gain and common mode gain of a differential amplifier?
Ans. When the difference of the two inputs applied to the two terminals of a differential amplifier
is amplified, the resultant gain is termed as differential gain. But when the two input terminals
are connected to the same input source then the gain established by the differential amplifier
is called the common mode gain.
Q.6. What is differential amplifier? Why is it needed?
Ans. The differential amplifier, as its name signifies, amplifies the difference between two input
signals. The need for differential amplifier arises in many physical measurements where
response from dc to many MHz is required. It is also the basic stage of an integrated op-
amp with difference input.
Q.7. Define CMRR.
Ans. CMRR is defined as the ratio of differential voltage gain to common-mode voltage gain and
it is given as CMRR = Ad/AC.
Q.8. A differential amplifier has differential mode gain of 100 and a common-mode gain of 0.01.
Calculate its CMRR in db.
Ad 100
Ans. CMRR = 20 log10 = 20 log10 = 20 log10 104 = 20 ´ 4 = 80
AC 0.01
Q.9. Why open-loop op-amp configurations are not used in linear applications ?
Ans. When an op-amp is operated in the open-loop configuration, the output either goes to positive
saturation or negative saturation levels or switches between positive and negative saturation
levels and thus clips the output above these levels. So open-loop op-amp configurations are
not used in linear applications.
Q.10. What measure(s) is/are taken against dc saturation of an op-amp?

Ans. Negative feedback is introduced to avoid dc saturation of op-amp.
Q.11. What kind of negative feedback is present in a non-inverting op-amp ?
Ans. Negative voltage series feedback.
Q.13. Why voltage follower circuit is an ideal device to serve as a buffer amplifier?
Ans. Voltage follower, because of its three unique characteristics of extremely high input
impedance, unity transmission gain and extremely low output impedance, is an ideal device
to serve as a buffer amplifier.
Q.14. What is an voltage follower?
Ans. Voltage follower is an electronic circuit in which output voltage tracks the input voltage
both in sign and magnitude.
Q.15. What are the advantages of using a voltage follower amplifier?
Ans. Voltage follower has three unique characteristics viz extremely high input impedance,
extremely low output impedance and unity transmission gain and is, therefore, an ideal
circuit device for use as a buffer amplifier.
Q.16. In what way is the voltage follower a special case of the non-inverting amplifier ?
Ans. If feedback resistor is made zero or R1 is made ¥ (by keeping it open-circuited) in a non-
inverting amplifier circuit, voltage follower is obtained.
Q.17. What is an inverting amplifier?
Ans. In an inverting amplifier, the input is connected to the minus or inverting terminal of op-amp.
Q.18. What are the applications of an inverting amplifier?
Ans. Inverting amplifier is a very versatile component and can be used for performing number
of mathematical stimulations such as analog inverter, paraphase amplifier, phase shifter,
adder, integrator, differentiator.
Q.19. Op-amp is used mostly as an integrator than a differentiator ?
Ans. Op-amp is mostly used as an integrator rather as a differentiator, because in differentiator
at high frequency, gain is high and so high frequency noise is also amplified which absolutely
abstract the differentiated signal.
Q.20. What will be the output waveshape of an op-amp integrator with a square-wave input?
Ans. The output voltage of an op-amp integrator with a square-wave input will be a ramp or
linearly changing voltage.
EXERCISE
1. What is an OP-AMP. Mention some of its applications.
2. As an active element the OP-AMP is said to be a two-port device. Explain.
3. Describe the characteristics of an ideal OP-AMP.
4. How are the ideal characteristics of an OP-AMP approached in an actual OP-AMP?
5. Draw schematic block diagram of the basic OP-AMP. Explain the significance of virtual
ground in basic inverting amplifier. How would you explain its existence?
6. Describe inverting and non-inverting OP-AMPs.
7. Why is the input pin in the non-inverting mode of the OP-AMP not considered to be at ground
potential, whereas the input pin the inverting mode is so treated?
8. What do you understand by closed loop and open loop gain of an OP-AMP, when a non-
inverting OP-AMP acts as a voltage follower?
9. Why is open-loop OP-AMP configuration not used in linear applications?
10. Draw the basic inverting amplifier with an input resistance RI and feedback resistance Rf .
Assuming the OP-AMP to be ideal, calculate the voltage gain of the inverting amplifier.
11. Define the common mode rejection ratio (CMRR) and explain the significance of a relatively
large value of CMRR.
12. What is meant by CMRR? Explain whether this should be very high or very low for an OP-
AMP amplifier.
13. What is meant by slew rate in an OP-AMP?
14. Draw the equivalent circuit of an OP-AMP and explain the various parameters used in the
equivalent circuit.
15. Define the following parameters with respect to OP-AMP:
(i) Input bias current
(ii) Input offset current
(iii) Input offset voltage
(iv) Output offset voltage
16. Draw the inverting and non-inverting amplifier circuits of an OP-AMP in closed loop
configuration. Obtain expression for the closed loop gain in these circuits.
17. Explain the virtual ground concept in an OP-AMP.
18. Draw the schematic diagram of a summing or adder amplifier. Derive the expression of
the output voltage.
19. Draw a circuit diagram that shows how the OP-AMP may be used to obtain the sum of
two input voltages. What precaution must be observed in the use of this circuit? How can
we use this circuit for finding the average (averager circuit)?
20. Explain how OP-AMP is used as a comparator.
21. Explain how OP-AMP is used as a difference amplifier. Show that drift is reduced in a
difference amplifier.
22. Draw the schematic diagram of a subtracter. Derive the expression for its output voltage.
23. Write a note on the use of an OP-AMP as an integrator and a differentiator.
24. Describe the function of an OP-AMP as (i) inverter, (ii) scale changer, (iii) phase shifter,
(iv) adder, (v) integrator, (vi) differentiator.
25. Draw the circuits when an OP-AMP is connected as (i) scale changer, (ii) adder, (iii)
phase shifter, and (iv) a differentiator.
26. Describe OP-AMP as low pass filter.
27. Draw the OP-AMP circuit of a voltage to current converter. Explain its operation.
28. Draw the current to voltage converter circuit and derive the expression for the output
voltage.
29. Explain how OP-AMP can be used as a zero crossing detector.
30. Draw the circuit of a square wave generator using an OP-AMP. Explain its operation by
drawing the capacitor voltage waveforms.
ppp
Application of Op-amp
12.1 INTRODUCTION
Op-amp has vast application as an amplifier, adder, subtractor, integrator, differentiator,
Fitters and also in oscillator circuits.
12.2 OPEN-LOOP OP-AMP CONFIGURATIONS
Open-loop means that there is no connection between input and output terminals either
direct or via another network. It means that output signal is not fedback in any form as part
of the input signal, and the loop that would have been formed with feedback is open. An
op-amp in open-loop configuration acts as a high-gain amplifier. The three open-loop op-
amp configurations are:
1. Differential amplifier
2. Inverting amplifier
3. Non-inverting amplifier
Ø Here output can be only +ve saturation or negative saturation, not in between.
12.3 CLOSED-LOOP OP-AMP CONFIGURATIONS
An op-amp that uses feedback is called a feedback amplifier and sometimes referred
to as a closed-loop-amplifier because the feedback forms a closed loop between the
input and the output. The feedback may be positive or negative. Negative feedback is of
four types viz voltage-series feedback, voltage shunt feedback, current series feedback
and current shunt feedback. Voltage-series feedback and voltage-shunt feedback are most
important and are widely used in amplifiers while current-series and current-shunt feedbacks
are seldom used.
Application of Op-amp 371
For most practical applications op-amp is used in closed loop configurations. The
most widely used closed configurations are
1. Voltage-series feedback amplifier or closed-loop non-inverting amplifier.
2. Voltage-shunt feedback amplifier or closed-loop inverting amplifier. The most basic type
is non-inverting voltage feedback. With this type of feedback, the input signal drives the
non-inverting input of an amplifier. A fraction of the output voltage is then fedback to the
inverting input. An amplifier with non-inverting voltage feedback tends to act like an ideal
voltage amplifier one with infinite input impedance, zero output impedance and constant
voltage gain.
12.4 OP-AMP AS INVERTING AMPLIFIER
If
I1 RF
A
–
R1 Ii = 0
Vid = 0 Op-amp V0
~ Vi +
OV
Fig. 12.1
Here the input is given to the inverting terminal, while non-inverting terminal is grounded.
By Virtual ground concept, two terminals are at same potential, So VA = 0.
Now I1 = If
Vi - 0 0 - V0
Þ =
R1 Rf
Þ V0 = -
FG R IJ V
HR K
f
i
1
V0 R
Þ AV = =- f
Vi R1
If Rf = R1 then V0 = – Vi i.e the invert of the input is obtained at the output.
12.5 OP-AMP AS NON-INVERTING AMPLIFIER

If
I1
A RF
OV –
R1
I=0 V0
Vid=0
+
~ Vi
Fig. 12.2
Here the input is given to non-inverting terminal and inverting terminal is grounded.
By virtual ground concept, VA = Vi
Now I1 = If
0 - Vi Vi - V0
Þ =
Ri RF
Þ
V0 V V
= i + i = Vi
LM 1 +
1 OP
R F R F R1 NRF R1 Q
Þ V0 = Vi 1 +
LM RF OP Þ AV =
V0 R
= 1+ F
N R1 Q Vi R1
If RF = 0W, i.e then V0 = Vi, i.e whatever the input, same appears at the output.
12.6 VOLTAGE FOLLOWER / VOLTAGE BUFFER / UNITY FOLLOWER
If
I1
A RF
–
Here RF = 0W R1 I=0
V0
Vid=0
+
Vi
Now V0 = AVid Fig. 12.3
where A = Gain of op-amp.

Þ V0 = A (V1 – V2) V1 = Voltage at +ve terminal
= A (Vi – V0) V2 = Voltage at –ve terminal.
= AVi – AV0
Þ V0 (1+A) = AVi
V0 A A
Þ = ~ {Q A > > 1 }
Vi 1 + A A
V0
Þ =~1
Vi
Þ V0 ~ Vi
As output voltage is same as input voltage, So it is buffer circuit.
Example-12.1
Design a non-inverting amplifier circuit that is capable of providing a voltage gain of 10.
Assume an ideal operational amplifier. (Resistor should not exceed 30 k W ).
Rf
Solution: It is known that Af = 1+
R1
Rf
Given that Af = 10 \ 1+ = 10
R1
or Rf = 9 R1
R1 may be taken as 3 k W so that Rf comes out to be 9 × 3 i.e. 27 k W, less than 30 k W Ans
Example-12.2
The variable resistance varies from 0 to 100 kW. Find out the maximum and the minimum
closed-loop voltage gains
Solution : From fig 2.11 R1. = 2 k W
Rf(min) = 0 and Rf(min) =100 kW
Rf FG IJ
Closed-loop voltage gain, A f = 1 + R
1 H K
R f (max) 100
So A f (max) = 1 + = 1+ = 51 Ans.
R1 2
R f (max) Fig. 12.4

and A f (max) = 1 + = 1 + 0 = 1 Ans.
R1
Example-12.3
An inverting amplifier has Rf = 500 kW and R1 = 5 kW. Determine the amplifier circuit
voltage gain, input resistance and output resistance. Determine also the output voltage and
input current if the input voltage is 0.1 V. Assume op-amp to be ideal one.
Solution : Resistance R1 = 5 k W
Feedback resistance, Rf = 500 k W
Input voltage, Vin = 0.1 V
Rf 500k W
Amplifier circuit voltage gain, A f = - R = - 5k W = -100
1
Amplifier circuit input resistance, Rin = R1 = 5 kW Ans

Amplifier circuit output resistance, Rout = Output resistance of op-amp = 0W Ans
Output voltage, Vout = Af Vin = - 100 x 0.l = 10 V Ans
Vin 01.
Input current, Iin = R = 5 ´ 1,000 = 0.02 mA Ans.
1
12.7 ADDER OR SUMMING AMPLIFIER

IF
V1
I1 R1 RF
I A
V2 –
I2 R2 0V Ii=0
Vid=0 V0
V3
I3 R3 +
0V
Fig. 12.5
Summing means the output is in the form of sum of its inputs.

Here there inputs are considered.
By Virtual ground concept VA = 0V.
Now If = I1 + I2 + I3
0 - V0 V1 - 0 V2 - 0 V3 - 0
Þ = + +
RF R1 R2 R3
V0 = - R F
LM V + V
1 2
+
V3 OP
Þ
NR R1 2 R3 Q
If RF = R1 = R2 = R3, then
V0 = - V1 + V2 + V3
12.8 SUBTRACTER
Here the two input signals are subtracted and is provided at the output.
This circuit can be designed in several ways. Two of them are explained here.
RF
1 RF
2
R1
– V R3
–
+ V0
~ V1 +
~ V2 R2
Stage - I Fig. 12.6 Stage - II

The stage - I is an inverting amplifier circuit.
R F1
Here V = - V1
R1
The 2nd stage is a summing amplifier circuit.
So V0 = - R F2
LM V + V OP 2
NR R Q
3 2
= - R F2
LM V - R V OP
2 F1
NR R Q
2 3
1
V0 = -
LM R F
V2 -
R F1 R F2
V1
OP
NR 2 R3 Q I
R3 I1
ii) Here VB = V1 R4
R1 + R 3 A
V2 –
R2 V0
By virtual ground concept, Vid=0 I = 0
V1 +
VA = VB B
R1
Now I1 = I R3 Fig. 12.7
Þ
V2 - VA VA - V0
=
V
Þ 0 = VA
1
+
1 V
- 2
LM OP
R2 R4 R4 R4 R2 R2 N Q
Þ V0 = VA 1 +
LM R4 OP
R
- 4 V2
N R2 Q
R2
R2 + R4 R3 R
Þ V0 = R2
.
R1 + R 3
V1 - 4 V2
R2
If R1 = R2 = R3 = R4 then
V0 = V1 – V2
If R1/R3 = R2/R4, then V0 = V1 – V2
12.9 INTEGRATOR / LOW PASS FILTER
Here output is the integration of input. Here the capacitor replaces the feedback
resistor.
If
I1
C
A
–
R Ii=0 V0
Vid=0
+
~ Vi 0V
Fig. 12.8
The current through a capacitor is
dQ d dv
I= = CV = C
dt dt dt
V is the potential difference across capacitor By virtual ground concept V A = 0V
Now I1 = If
Vi - 0
Þ
R1
d
b
= C 0 - V0
dt
g
CdV0
=-
dt
-1
Þ dV0 = Vi dt
R1C
Þ V0 ( t ) =
-1
R1C z
Vi ( t ) dt
-1
By Laplace transform, V0 (S) = Vi (S)
R1CS
V0 (S) -1
Þ =
Vi (S) R 1CS
12.10 SUMMING INTEGRATOR CIRCUIT

R1
V1
R2 C
V2 –
R3 V0
V3
+
Fig. 12.9
Here V0 ( t ) = -
1
C z FGH V1 ( t ) V2 ( t ) V3 ( t )
R1
+
R2
+
R3
IJ
K
dt
12.11 DIFFERENTIATOR / HIGH PASS FILTER

Here the output is the derivative of the input signal.
I1
I
R
A
Vi –
C Ii = 0 V0
Vid = 0
+
Fig. 12.10
By virtual ground concept, VA = 0.

Now I= I1
0 - V0
Þ C
d
dt
bVi - 0 =g R
dVi ( t )
Þ V0 ( t ) = - RC
dt
By Laplace transform,
V0 (S) = - RCS Vi (S)
V0 (S)
Þ = - RCS
Vi (S)
Example-12.4
The following circuit of fig 12.11, shows a controlled gain amplifier. What is the gain of the
amplifier circuit when (i) switch S is off (ii) when switch S is on ?
Solution: 10kW 20kW
(i) When switch S is off, the circuit is
reduced to that of differential amplifier, as _
+ +
illustrated in fig 12.12. ¥
5kW 5kW
For determination of gain of the non- Vin + Vout
inverting mode, inverting input is assumed S
to be zero and point 2 is grounded. Now
Amplifier circuit gain, Fig. 12.11
R 20k
A off non -inv = 1+ f = 1+ =3 20kW
R1 10K
2 10kW _
The amplifier circuit gain, Vin
d
A off = A off non - inv + A off inv i Vin
1 5kW 5kW
+
Vout
= (3 – 2) = 1 Ans Fig. 12.12

(ii) When switch S is on the circuit becomes an inverting amplifier, as shown in fig.12.13
- R f -20
Amplifier circuit gain, A on = = = -2 Ans
R1 10
20kW 20kW
10kW _ 10kW _
Vin Vin
5kW 5kW Vout 5kW Vout
+ +
5kW
Fig. 12.13
Example-12.5
Design an adder circuit using an op-amp to get the output expression as
Vout = – (V1 + 10 V2 + 100V3)
where V1, V2 and V3 are the inputs, Given that Rf = 100 kW .
Solution : The output of a summing circuit is,
Vout = - R f
LM V + V
1 2
+
V2OP LM
R R R
= - f V1 + f V2 + f V3
OP
NR R 1 2 R3 Q N R1 R2 R3 Q
i.e. - (V1 + 10V2 + 100 V3)
we get R1 = Rf = 100 kW Ans.
R f 100
R2 = = = 10 kW
10 10
R f 100
and R3 = = = 1 kW Ans.
100 100
Example-12.6
An op-amp as summing circuit has feedback resistor Rf =12 kW and the resistances on the
input sides are R 1 = 12 kW, R 2 = 2 kW and R 3 = 3 kW. The corresponding inputs are
V1 = + 9 V, V2 = –3 V and V3 = 1 V. Non-inverting terminal is grounded. Calculate the
output voltage.
Solution : Here Rf = 12 kW; R1 = 12 kW; R2 = 2kW and R3 = 3 kW,
V1 = 9 V; V2 = – 3 V and V3 = –1 V
V1 V2 V3 LM OP
Output voltage Vout = - R f R + R + R
1 2 3 N Q
= -12 k W
LM 9 + -3 + 1 OP
N12 kW 2k W 3 kW Q = – 9 + 18 + 4 = 13 V Ans.
Example-12.7
Sketch the circuit of summing circuit using op-amp to get
V0 = – V1 + 2V2 – 3 V3.
Solution : In a summing circuit output is given by
Vout = -
LM R f
V1 +
Rf R
V2 + f V3
OP
NR 1 R2 R3 Q
i.e Vout = – V1 + 2 V2 – 3 V3 = – [V1 – 2 V2 + 3 V3]
Rf Rf Rf
we have = R = 1, R = 2, R = 3
1 2 3
Taking Rf = 6 kW we have
6 kW
R1 = Rf = 6 kW
V1
3 kW 6 kW
Rf
R2 = = 3 kW -V 2 –
2 V0
2 kW
V3 +
Rf
R3 = = 2 kW
3
Fig. 12.14
The circuit is shown in fig 12.14
Example-12.8
The input to an op-amp differentiator circuit shown in fig. 12.15 is a sinusoidal voltage of
peak value of 10 mV and frequency 2 kHz. Determine the output voltage if R = 50 kW and
C = 2 mF.
Solution : The equation for the sinusoidal signal of peak value of 10 mV and frequency 2
kHz is given as
vin = Vmax sin 2 p f t = 10 sin 2 × 2,000 p t
C R
= 10 sin 4,000 p t mV Vi –
Scale factor C R = 2 × 10–6 × 50 × 103 = 0.1 V0
So output voltage,
+
d vc d
v out = -CR = -01
. (10 sin 4,000 p t) mV
dt dt
d Fig. 12.15
= – 0.1 × 10 (sin 4,000 pt) mV
dt
= 4,000 p cos 4,000 pt mV or 12.56 cos 4,000 p t mV Ans.
12.12 INSTRUMENTATION AMPLIFIER
This is a circuit that
provides an output based on the
difference between two inputs
(times scale factor). To permit
the adjustment of scale factor
of the circuit, a potentiometer
is provided.
The circuit of an
instrumentation amplifier is
given by,
Fig. 12.16
Here three op-amps are used. So a single quad op-amp IC is required other than resistors.
Let V1¢ & V2¢ are the output voltages of the op-amps having the inputs V1 & V2
respectively.
By virtual ground concept, VA = V2 & VB = V1
Applying KCL at A,
V2¢ - V2 V2 - V1
=
R1 RP
V2¢ V2 V2 V1
Þ - = -
R1 R1 R P R P
V2¢ æ 1 1 ö V1 æ R ö æR ö
Þ =ç + ÷ V2 - Þ V2¢ = ç 1 + 1 ÷ V2 - ç 1 ÷ V1
R 1 è R1 R P ø RP è RP ø è RP ø
Similarly by applying KCL at point ‘B’,
æ R ö æR ö
V1¢ = ç 1 + 1 ÷ V1 - ç 2 ÷ V2
è RP ø è RP ø
The Final stage op-amp configuration is nothing but a differential amplifier.
R6 R + R4 R
So V0 = . 3 V1¢ - 4 V2¢
R5 + R6 R3 R3
IF R1 = R 2 = R 3 = R 4 = R5 = R 6 = R
æ R ö æR ö
Then V1¢ = ç 1 + ÷ V1 - ç 2 ÷ V2
ç Rp ÷ è RP ø
è ø
æ R ö æ R ö
V2¢ = ç 1 + ÷ V2 - ç ÷ V1
ç Rp ÷ è RP ø
è ø
æ 2R ö
ç Rp ÷( 1
and V1¢ - V2¢ = ç1 + ÷ V - V2 )
è ø
Þ b
V0 = K V1 - V2 g
2R
Here scale factor, K = 1 +
Rp
Ø An instrumentation amplifier is a differential amplifier optimized for high input

impedance and high CMRR.
Ø It is typically used in applications in which a small differential voltage & a large
common mode voltage are the inputs.
12.13 CONTROLLED SOURCES

Operational amplifiers can be used to form various types of controlled sources. An
input voltage can be used to control the output voltage or current, or an input current can
be used to control an output voltage or current. These types of connections are suitable for
use in various instrumentation circuits. A form of each type of controlled source is provided
next.
Voltage-Controlled Voltage Source
An ideal form of a voltage source whose output V0 is controlled by an input voltage V\
is shown in Fig. 12.17. The output voltage is seen to be dependent on the input voltage
(times a scale factor k). This type of circuit
can be built using an op-amp as shown in
Fig. 12.18. Two versions of the circuit are
shown, one using the inverting input, the other
the noninverting input. For the connection of
Fig. 12.18a, the output voltage is
Rf
V0 = V1 = kV1 Fig. 12.17 Ideal voltage-controlled
R1 voltage source.
Fig. 12.18 Practical voltage-controlled voltage source circuits.

while that of Fig. 12.18b results in
æ R ö
Vo = ç 1 + f ÷ V1 = kV1
è R1 ø
Voltage-Controlled Current Source

An ideal form of circuit providing an output current controlled by an input voltage is that of
Fig. 12.19. The output current is dependent on the input voltage. A practical circuit can be
built, as in Fig. 12.20, with the output current through load resistor RL controlled by the input
voltage V1. The current through load resistor RL can be seen to be
V1
Io = = kV1
R1
Fig.12.19 : Ideal voltage- Fig. 12.20 : Practical voltage-

controlled current source. controlled current source.
Current-Controlled Voltage Source
An ideal form of a voltage source controlled by an input current is shown in Fig. 12.21.
The output voltage is dependent on the input current. A practical form of the circuit is built
using an op-amp as shown in Fig. 12.22. The output voltage is seen to be
Vo = -I1R L = kI1
Fig. 12.21 : Ideal current-controlled Fig. 12.22 : Practical form of

voltage source. current-controlled voltage source.
Current-Controlled Current Source
An ideal form of a circuit providing an output current dependent on an input current is
shown in Fig. 12.23. In this type of circuit, an output current is provided dependent on the
input current. A practical form of the circuit is shown in Fig. 12.24. The input current I1 can
be shown to result in the output current I0 so that
I1R1 æ R ö
Io = I1 + I2 = I1 + = ç 1 + 1 ÷ I1 = kI1
R2 è R2 ø
Fig. 12.23 Ideal current- Fig. 12.24 Practical form of

controlled current source current-controlled current source.
Example-12.9
(a) For the circuit of Fig. 12.25a, calculate IL.
(b) For the circuit of Fig. 12.25b, calculate V0.
Fig. 12.25 Circuits Example 12.8

Solution :
(a) For the circuit of Fig. 12.25a,
V1 8V
IL = = = 4 mA
R1 2 kW
(b) For the circuit of Fig. 12.25b,
Vo = - I1R 1 = -(10 mA)(2k W ) = -20 V
12.14 CLASSIFICATION OF FILTERS

An electric filter is usually a frequency-selective network that passes a specified
band of frequencies and blocks or attenuates signals of frequencies outside this band.
Filters may classified in a number of ways as follows :
1. Analog or digital filters.
2. Passive or active filters.
3. Audio-frequency (AF) or radio-frequency (RF) filters.
Depending on the type of techniques used in the process of analog signals the filters
may be analog or digital. Analog filters are designed to process analog signal using analog
techniques, while digital filters process analog signals using digital techniques.
Depending on the type of elements used in their construction, filters may be passive or
active. A passive filter is built with passive components such as resistors, capacitors and
inductors. Active filters, on the other hand, make use of transistors or op-amps (providing
voltage amplification, and signal isolation or buffering) in addition to resistors and capacitors.
The type of elements used dictates the operating frequency range of the filter.
Fig. 12.26 Ideal Response of Different Types of Filters

According to the operating frequency range, the filters may be classified as audio frequency
(AF) or radio-frequency (RF) filters.
Filters may also be classified as (i) low-pass, (ii) high-pass (iii) band-pass (iv) band
stop and (v) all pass. The filter circuit may be so designed that some frequencies are
passed from the input to the output of the filter with very little attenuation while others are
greatly attenuated.
Fig. 12.26 shows the frequency responses of the five types (mentioned above) of
filters. These are ideal responses and cannot be achieved in actual practice.
A filter that provides a constant output from dc upto a cut-off frequency fc and then
passes no signal above that frequency is called an ideal low-pass filter. The ideal response
of a low-pass filter is illustrated in fig. 12.26(a). The voltage gain (the ratio of output
voltage and input voltage i.e. Vout/Vin) is constant over a frequency range from zero to cut-
off frequency, fc. The output of any signal having a frequency exceeding fc will be attenuated
i.e. there will be no output voltage for frequencies exceeding cut-off frequency fc. Hence
output will be available faithfully from 0 to fc with constant gain, and is 0 from fc onward.
The frequencies between 0 and fc are, therefore, called the passband frequencies, while
the range of frequencies, those beyond fc, that are attenuated includes the stopband
frequencies. The bandwidth (BW) is, therefore, fc.
A filter that provides or passes signals above a cut-off frequency fc is a high-pass
filter, as idealized in fig. 12.26(b). The high-pass filter has a zero gain starting from zero to
a frequency fc, called the cut-off frequency, and above this frequency, the gain is constant,
as illustrated in fig. 12.26(b). Thus signal of any frequency beyond fc is faithfully reproduced
with a constant gain, and frequencies from 0 to fc will be attenuated.
When the filter circuit passes signals that are above one cut-off frequency and below
a second cut-off frequency, it is called a band-pass filter, as idealized in fig. 12.26(c). Thus
a band-pass filter has a pass band between two cut-off frequencies fc2 and fc1, where fc2 >
fc1 and two stop-bands : 0 < f< fc1 and f> fc2. The bandwidth of the band-pass filter is,
therefore, equal to fc2 – fc1 where fc1 and fc2 are lower and higher cut-off frequencies
respectively.
The band-stop or band-reject filter performs exactly opposite to the band-pass i.e. it
has a bandstop between two cut-off frequencies fc2 and fcl and two passbands : 0 < f < fc1
and f > fc2. The ideal response of a band-stop filter is illustrated in fig. 12.26(d). This is
also called a band-elimination or notch filter.
The ideal response of an all-pass filter is shown in fig. 12.26(e). This filter passes all
frequencies equally well, i.e., output and input voltages are equal in amplitude for all
frequencies. The important feature of this filter is that it provides predictable phase shift
for frequencies of different input signals.
12.15 CLASSIFICATION OF ACTIVE FILTERS
Fig 12.27 Frequency Response of Different Types of Active Filters

The most widely used active filters are (i) low-pass (ii) high-pass (iii) band-pass (iv)
band-stop or band reject (also called the band-elimination or notch) and (v) all-pass filters.
All of these filters use op-amps as the active elements and R-C networks.
The frequency response characteristics of all of the five types of active filters are
depicted in fig. 12.27, Dashed lines indicate the ideal response while the practical response
is depicted by solid curves in the figure.
A low-pass filter has a constant gain from 0 Hz to a high cut-off frequency fH.
Therefore the bandwidth is also fH. At high cut-off frequency fH the gain is reduced by 3
db and for f > fH it decreases with the increase in input frequency. The frequencies between
0 and fH are known as passband frequencies while the range of frequencies beyond fH
are attenuated and are therefore called the stop-band frequencies.
Frequency response of a low-pass filter is illustrated in fig. 12.27 (a). Here fH is higher
cut-off frequency and f is the operating frequency.
A high-pass filter with a stopband 0 < f < fL and a passband f > fL is shown in
fig.12.27(b). Here fL is the lower cut-off frequency and f is the operating frequency.
A bandpass filter has a passband between two cut-off frequencies fH and fL where
fH > fL and two stopbands at 0 < f < fL and f > fH. The bandwidth of the bandpass filter is,
therefore, equal to fH - fL. All these are obvious from the frequency response of a bandpass
filter illustrated in fig. 12.27 (c).
Band-stop filter is exactly opposite to the bandpass filter in performance i.e., it has a
bandstop between two cut-off frequencies fH and fL and i two passbands, 0 < f < fL and
f > fH. The frequency response of a band-stop filter is illustrated in fig. 12.27 (d). In figs.
29.2 (c) and 29.2 (d), fC is called the centre frequency, since it is approximately at the
centre of the passband or stopband.
12.16 FIRST-ORDER LOW-PASS BUTTERWORTH FILTER
A first-order low-pass Butterworth filter using an R-C network for filtering is illustrated
in fig. 12.28. The op-amp is used in the non-inverting configuration so that it does not load
the R-C network. Gain of the filter is determined by resistors R1 and Rf .
Fig.12.28 : One-Pole or First Order Low-Pass Butterworth Filter

Voltage at the non-inverting (+) input terminal (voltage across the capacitor C), by
voltage divider rule, is
- jX C
v1 = vi
R - jX C
1
Substituting –j XC = j2p fC
vin
in above equation we have v1 =
j2p f CR + 1
æ Rf ö
and the output voltage, vout = ç1 + R ÷ v1
è 1 ø
æ R ö vin
So vout = ç1 + f ÷
è R1 ø j2p f CR + 1
vout Af æ Rf ö
or v = 1 + j2pfCR where A f = ç1 + R ÷ , passband gain of the filter..
in è 1 ø
1
Substituting = f H (high cut-off frequency of the filter) in the above equation we
2pRC
have
vout Af
=
vin 1 + j f
fH
vout
where is the gain of the filter as a function of frequency and f is the frequency of
vin
input signal in Hz.
The gain magnitude and phase angle can be determined as,
v out Af
=
vin 1 + (f / f H )2
-1 æ f ö
and phase angle f = - tan ç f ÷
è Hø
1. For very low frequency i.e. f << f H ; v out / vin = A f
Af
2. For high cut-off frequency i.e. f = f H ; vout / vin = = 0.707 A f
2
vout
3. For frequency greater than high cut-off frequency i.e. f >> f H ; < Af
vin
The frequency f = fH is called the cut-off frequency because the filter gain at this
frequency is down by 3 db (= 20 log 0.707) from 0 Hz. Sometimes it is also called, – 3 db
frequency.
Frequency Scaling.
The procedure of converting a given cut-off frequency to a new cut-off frequency is
called the frequency scaling. Frequency scaling is accomplished as follows.
To obtain a new cut-off frequency, R or C (but not both) is multiplied by the ratio of
original cut-off frequency to the new cut-off frequency. In filter design the required values
of R and C are usually not standard. Besides, a variable capacitor is not commonly used.
Hence the capacitor is taken of a standard value and then the value of resistance R is
calculated for a desired cut-off frequency fH from the relation.
1
R=
2pf H C
This is because for a non-standard value of a resistor, a pot can be used.
Example-12.10
Design a low-pass filter having a cut-off frequency of 2 kHz with a passband gain of
2.5.
Solution : Cut-off frequency, fH = 2 kHz
Let the capacitor C be of 0.01 mF. Then
1 1
R= =
2pf H C 2p ´ 2 ´ 103 ´ 1 ´ 10-8 = 7.95 k W (practical value 8.2 k W)
Since the passband gain is 2.5, so
Rf
1+
R1 = 2.5 or Rf should be equal to 1.5 R1
Since Rf | | R1 = R
R f R1
or =R
R f + R1
1.5R1R1
or = 8.2 kW
1.5R1 + R1
2.5
or R1 = ´ 8.2 = 13.66 kW (say 15 kW) Ans.
1.5
and Rf = 13.66 × 1.5 = 20 k W Ans
12.17 SECOND-ORDER LOW-PASS BUTTERWORTH FILTER
Improved and considerably variable performance is achieved by going to a second-
order (rather than first order) active filter.
No doubt a second-order filter can be obtained by coupling two first-order active
filters, but this would not be economical because it needs two op-amps. A second-order
filter can be obtained simply by introducing an additional R-C network in the first-order
filter, as illustrated in fig. 12.29. Second-order filters are important because higher-order
filters are designed using them.
Fig. 12.29 Two-Pole or Second-Order Low-Pass Active Filter

The circuit illustrated in fig. 12.29 (a) is also called a two-pole low-pass filter because
it has two bypass circuits. The two poles of this circuit modify the cut-off frequency and
the response of the circuit. The gain of the second-order filter is set by R1 and Rf, while the
high cut-off frequency fH is determined by R, R', C and C', as given below.
1
High cut-off frequency, fH =
2p RR ¢CC¢
The voltage gain magnitude equation for a second-order low-pass Butterworth filter is
given as
v outt Af
=
vin æ f ö
4
1+ ç ÷
è fH ø
æ R ö
where A f = ç1 + f ÷ , the passband gain of the filter, f is the frequency of the input signal
è R1 ø
in Hz and fH is the high cut-off frequency in Hz.
Example-12.11
Design a second-order low-pass filter at a high cut-off frequency of 2 kHz. Solution :
High cut-off frequency, fH = 2 kHz
Let C' = C = 0.033 m F
1 1
Then R ¢ = R = =
2p f H C 2p ´ 2 ´ 10 ´ 0.033 ´ 10-6
3
= 2.4 k W (say 2.5 k W)

However, to minimize the effect of offset current (which may be quite important in a
low pass filter), the resistance at the inverting terminal must be equal to the resistance at
the inverting terminal.
R f R1 0.586 R12
So 2 R = R + R = Q R f = 0.586 R 1
f 1 1.586 R1
0.586 R1
or 2 ´ 2.4 kW = or R 1 = 13kW
1.586
R1 may be taken of a value of 15 kW and then Rf = 0.586 × 15 = 8.79kW
Rf may be taken a pot of 10 k W Ans
12.18 FIRST-ORDER HIGH-PASS BUTTERWORTH FILTER
High-pass active filter is the complement of low-pass active filter and is formed simply
by exchanging the place of resistors and capacitors in the frequency determining section
of the filter. Thus a first-order high-pass filter is formed from a first-order low-pass filter
by interchanging components R and C, as illustrated in fig. 12.30(a). Such a circuit passes
the high frequencies but blocks the low frequencies. The cut-off frequency is still given by
1
.Below this frequency, called the low cut-off frequency fL. The output voltage
2pRC
decreases at a rate of 20 db/decade. All frequencies higher than fL are in the passband
with the highest frequency determined by the closed-loop bandwidth of the op-amp.
The output voltage is given as
æ R ö j2p f RC
vout = ç1 + f ÷ vin
è R1 ø 1 + j2p f RC
vout é j f / fL ù
or = Af ê ú
vin ë1 + j(f / f L ) û
æ Rf ö
where A f = ç1 + R ÷ , the passband gain of the filter,,
è 1 ø
Fig. 12.30 First-Order High-Pass Butterworth Filter

1
fL =
2p RC , the low cut-off frequency in Hz, and
f is the frequency of the input signal.
The magnitude of the voltage gain is given as
vout A f .f / f L
=
vin 1 + (f / f L )2
Since high-pass filters are built from low-pass filters simply by exchanging the place
of resistors and capacitors in the frequency determining section of the filter, the design and
frequency scaling procedures are the same as for the low-pass filters.
12.19 SECOND-ORDER HIGH-PASS BUTTERWORTH FILTER

A second-order high-pass Butterworth filter can also be formed like a first-order high-
pass Butterworth filter, from a second-order low-pass Butterworth filter simply by
interchanging the frequency-determining resistors and capacitors, as illustrated in fig.12.31(a).
The voltage gain magnitude equation for the second-order high-pass filter is given as
vout Af
=
vin 1 + (f L / f )4
where Af = 1.586, passband gain for the second-order Butterworth response, f is frequency
of the input signal in Hz and fL is the low cut-off frequency in Hz.
Fig. 12.31 Second-Order High-Pass Butterworth Filter
EXERCISE
1. Calculate the voltage gain of an inverting amplifier, given that R1 = 8 kW and Rf = 56 kW.
[Ans : - 7]
2. For the inverting amplifier, R1 = 2 kW and Rf = 1 MW. Determine the following circuit
values: (i) Av (ii) R1 and (iii) R0. [Ans (i) -1000 (ii) 1 kW (iii) 0 W]
3. For inverting amplifier, let Rf = 250 kW, Rl = 10 kW and Vf = 0.5 V. Calculate (a) I, (b) the
voltage across Rf and (c) V0. [Ans : a) -0.5 mA, b) 12.5 V , c) +12.5 V]
4. Design an inverting amplifier with a gain of –5 and an input resistance of 10 kW.
[Ans: R1 = 10 kW and Rf = 50 kW]
5. Calculate the output voltage of an inverting amplifier, if R1 =50 kW, Rf = 500 kW and
V1 = 20.4 V. [Ans: 4 V]
6. Calculate the output voltage of non-inverting amplifier, if R1 = 50 kW, Rf = 500 kW and
Vi = 0.4 V. [Ans: 4.4 V]
7. Calculate the value of the feedback resistor given that Av = – 100 and R1 = 1 kW in the
case of an inverting amplifier. [Ans : 100]
8. Design an amplifier with a gain of + 10.

[Ans: Non inverting amplifier, choose R1 = 10 kW and Rf = 90 kW]
9. Calculate the voltage gain of non-inverting amplifier op-amp with R1 = 10 kW and
R2 = 2 kW. Find the output voltage when input is 200 mV. [Ans: 6 and 1.2 V]
10. Calculate the output voltage of a three input adder for the following values: R1 = 20 kW,
R2 = 40 kW, R3 = 60 kW and Rf = 100 kW, V1 = 20 mV, V2 = 40 mV and V3 = 60 mV.
[Ans: 0.2 V]
11. Calculate the output voltage of an adder for the following values: R1 = 250 kW, R2 = 500
kW, R3 = 1 MW, V1 = – 3 V, V2 = 3 V and V3 = 2 V. [Ans: 4 V]
12. In the subtracter circuit R1 = 5 kW , Rf = 10 kW , Vl = 4 V and V2 = 5 V. Find the value of
output voltage. [Ans: 2 V]
13. Calculate the output voltage of subtracter circuit if R1 = 2 kW, Rf = 10 kW, Vl = 3 V and
V2 = 6 V. [Ans: 15V]
14. The input of the differentiator is a sinusoidal voltage of peak value 5 mV and frequency
1 kHz. Find the output if R = 100 kW and C = 1 mF. [Ans: - p cos 2000 pt V]
15. A 10 mV, 5 kHz sinusoidal signal applied to the input of an op-amp integrator for which R =
100 kW and C = 1mF. Find the output voltage. [Ans: (10 2 / p ) cos 104 pt V]
16. Design an adder using an op-amp to get the output expression as V0 = - (0.1 V1 + V2+ 20V3),
where Vl ,V2 and V3 are the inputs.
[Ans : Rf = 10 kW, R1 = 100 kW, R2 = 10 kW and R3 = 0.5 kW]
ppp
395
Power Amplifier
13.1 INTRODUCTION
Almost in all the practical amplifiers, number of stages are cascaded to amplify a
weak signal to a sufficient level to operate the output device (i.e., loudspeaker etc.). In
such amplifiers, the function of first few stages is only to amplify voltage. But the last
stage is designed to provide maximum power to drive die output device. This final stage is
known as power amplifier stage.
Fig. 13.1
When a person speaks into a microphone, it converts the sound waves into electrical
signal. The electrical signal so produced is of very low voltage (a few mV). If this signal is
fed directly to the speaker, it will not be in position to drive the speaker. Therefore, voltage
level of the signal is first raised to sufficient level (a few volts) by passing it through a
number of stages of voltage amplifier. This amplified voltage signal is then fed to the final
stage of the multistage amplifier, which is capable to deliver the required power to drive
the speaker. The speaker finally converts the electrical signal into sound waves. Thus, a
large audience will be in position to hear the speech (or music from stereo, orchestra, tape
recorder, record player or any other such gadget). Thus, it is seen that at the final stage we
have to apply a power amplifier to transfer maximum power to the output device. In this
chapter we shall talk about the final stage (i.e., power amplifier) of a multi-stage amplifier.
13.2 VOLTAGE AND POWER AMPLIFIERS

In a multistage audio amplifier, the first few stages are of voltage amplifier and the
final stage is of power amplifier. The primary function of a voltage amplifier is to raise the
voltage level of the signal, whereas, the main function of a power amplifier is to feed large
amount of power to the load. Hence, the voltage amplifiers are designed to achieve maximum
voltage amplification. On the other hand, power amplifiers are designed to obtain maximum
power at the output. Let us study the design implications of two types of amplifiers :
13.2.1 Voltage amplifier
We have seen that voltage gain of an amplifier is given by the expression ;
RC
Av = b
R in
Therefore, the following features are required to be incorporated in such amplifiers :
1. Higher value of b. The transistor employed should have higher value of b(>100).
Hence the transistor should have thin base.
2. Low input resistance (Rin). The input resistance Rin of the transistor should be quite
low in comparison to that of collector load resistor RC.
3. High collector load resistance (RC)- The collector load resistance should be relatively
high. This condition is obtained by keeping low collector current ( ~ 1 mA). Since
collector junction is to carry a small current no heat sink is required.
4. R-C Coupling. As R-C coupling has smaller size, smaller weight, lower cost and
occupy less space, therefore, it is preferred to couple various stages of voltages
amplifiers by this coupling method.
Fig. 13.2 Fig. 13.3

13.2.2 Power amplifier
A power amplifier is required to deliver a larger amount of power to the load, hence
it has to handle a larger amount of power to the load, hence it has to handle large current.
Power Amplifier 397
To meet with these requirements, the following features are required to be incorporated in
such amplifiers :
1. Thicker base. Since the transistor employed in power amplifier is to handle larger
current, its base should be thick. The transistors having thicker base have smaller b.
2. Larger size of transistor. In power amplifiers, power transistors are employed which
are larger in size as they are to handle more current. When heavy current ( > 100
mA) flows through the transistor, more heat is produced at the collector junction. This
heat is required to be dissipated hence transistors of larger size are required. Moreover,
heat sinks are employed to improve the heat dissipation.
3. Low collector load resistance (RC)- The collector load resistance. RC should be of
smaller value. If its value is high, there will be more power loss in the resistor, moreover,
there will be larger voltage drop in it which will reduce the operating voltage. To avoid
these drawbacks low collector load resistance is employed.
4. Transformer Coupling. The foremost duty of a power amplifier is to transfer maximum
power to the output device i.e., speaker. This is only possible if input impedance is
equal to the output impedance. Hence, we have to match the impedance of loud
speaker, (nearly 8 W) to the output impedance of the amplifier or transistor (a few
kW). This can only be achieved by using a transformer at the output. The turns ratio
(Np/Ns) of the output transformer are designed in such a way that the load resistance
looking at the primary side,
2
æN ö
R ¢L = ç P ÷ R L
è NS ø
From the above discussion it is worth while to sum up the following points :
(i) Power amplifier is the last stage of a multistage amplifier whereas the first few
stages are voltage amplifiers.
(ii) For perfect impedance matching, transformer coupling is invariably employed with
power amplifier whereas in voltage amplifiers R-C coupling is preferred.
(iii) In power amplifiers, power transistors with suitable heat sink are employed. As they
are capable to carry heavy current and are able to dissipate heat developed at the
collector junction.
The circuit diagram of a voltage amplifier and a single ended power amplifier is shown in
Fig. 13.2 and 13.3 respectively.
13.3 COMPARISON OF VOLTAGE AND POWER AMPLIFIERS
The comparison between voltage and power amplifiers on the basis of coupling, output
power, collector current, output impedance, input voltage, b, RC etc. is given below in the
tabular form :
S.No. Particulars Power amplifier Voltage amplifier

1. Coupling invariably transformer coupling. usually R-C coupling
2. Output power very high low
3. Collector current very high ( > 100 mA) low ( ~ 1 mA)
4. Output impedance low (nearly 100 to 200 W) high (~ 10 kW)
5. Input voltage high (2 to 5 V) low (nearly 2 to 5 inV)
6. Current amplification b low (25 to 50) high ( > 100)
7. Collector load resistance RC low ( 5 to 25 W) high (5 to 10 k W)
13.4 PROCESS OF POWER AMPLIFICATION

While studying power amplifiers, an important question arises in the minds of the
readers i.e., “Does a power amplifier actually amplify power ?”
The straight forward answer to this question is “No” ; because amplification of power
contradicts the basic principles of physics i.e. law of conservation of energy.
In fact, a power amplifier, during operation, takes dc power from the supply connected
to the output circuit and converts it into useful ac signal power. The type of ac power
developed at the output of the power amplifier is controlled by the input signal. Thus, it can
be said that power amplifier is just a dc to ac power converter, whose action is controlled
by the input signal. Whatsoever power is developed that is fed to the load (e.g., loudspeaker
etc.).
13.5 SINGLE-ENDED TRANSISTOR POWER AMPLIFIER
A single-ended transistor power amplifier is shown in Fig. 13.3. The term single-
ended” is used to distinguish it from the push-pull amplifier to be discussed latter in this
chapter. It is basically a last stage of a multistage audio amplifier. The foremost duty of this
amplifier is to transfer maximum power to the output device i.e., loudspeaker. This is only
possible if input impedance is equal to the output impedance. Hence we have to match the
impedance of loudspeaker (low value a few ohm) to the output impedance of the amplifier
or transistor (high value a few kW). This can only be achieved by using a transformer at
the output. The turns ratio (n = Np/Ns) of the output transformer are designed in such a
way that the load resistance looking at the primary side be given as
R'L = n2RL
A single-ended power transistor suffers from poor efficiency and distortion. Therefore,
at the output usually push-pull arrangement is preferred.
Example-13.1
A power amplifier is operated from a 12 V dc supply. It gives an output of 3 W. Find
the maximum collector current in the circuit.
Solution :
Let IC be the maximum collector current.
Power Amplifier 399
Power = supply voltage × collector current
3 = 12 × IC
3
or IC = = 0.25 A = 250 mA (Ans.)
12
Example-13.2
A voltage amplifier operates from a 12 Vdc supply. If the collector load resistance
is 3 kW. Find the maximum collector current in the circuit. Comment on the result
obtained from this and previous example.
Solution : Let IC be the maximum collector current.
sup ply voltage V 12 V
IC = = CC = = 4 mA (Ans.)
Collector resistance R C 3 kW
Comments. These examples show clearly that a voltage amplifier handles small
current, whereas, power amplifier handles large current as well as large power.
Example-13.3
Determine the turn ratio of the output transformer to match an 8W speaker load to
an amplifier having effective load of 1.8 kW.
Solution . Let the turn ratio of output transformer be n ( = Np/Ns)
2
æN ö
We know that R ¢L = n R L = ç P ÷ R L
2
è NS ø
NP R L1 1800
or turn ratio, = = = 225 = 15 (Ans.)
NS RL 8
13.6 PERFORMANCE OF POWER AMPLIFIERS
The performance of a power amplifier is studied on the basis of quantities like collector
efficiency, distortion and power dissipation capability. These are discussed below :
13.6.1 Collector efficiency
The ratio of ac output power to the dc input power or zero signal power of a
power amplifier is known as collector efficiency.
As discussed in the previous article, a power amplifier just converts dc power received
from the source (battery) into ac power which fluctuates according to the input signal.
This ac power is supplied to the load. Thus, the ability of a power amplifier to convert dc
input power into ac output power is a measure of its effectiveness and is Known as
collector efficiency.
In fact, collector efficiency tells us the percentage of dc power converted into ac
power by the amplifier. For example, if the dc power supplied by the source (battery) is 10
W and ac output power is 3 W, then the collector efficiency is 30%. The greater the
collector efficiency, better is the amplifier.
Expression for collector efficiency
Now,
ac power output
Collector efficiency, h=
dc power input
Pac
or, h=
Pac
Vce Ic
or h=
VCC IC
where, Vce = the rms value of output signal voltage
Ic = the rms value of output signal current.
In load-line analysis, it is convenient to take the ac values in terms of peak-to-peak (p-p)
é V (p - p) ù 1
\ Vce = ê ce ú´ 2
ë 2 û
é I (p - p) ù 1
Ic = ê c ú´
ë 2 û 2
Vce (p - p) Ic (p - p) Vce (p - p) ´ Ic (p - p)
\ Pac = Vce ´ Ic = ´ =
2 2 2 2 8
Substituting this value in eqn. (i), we get;
Vce (p - p) ´ Ic (p - p)
Collector efficiency, h=
8 VCC IC
13.6.2 Distortion
The change of output waveform from the input waveform of an amplifier is known as
distortion.
When the output wave shape is not exact replica of the input wave shape, the amplifier
is said to have introduced some distortion. Usually, voltage amplifiers handle very small
signals, therefore, transistor acts as a linear device and distortion free amplification is
possible. However, power amplifiers are to handle larger signals, therefore, the problem of
distortion immediately arises. The amplifiers having less distortion are considered to be
better one.
13.6.3 Power dissipation capability
The ability of a power transistor to dissipate heat developed in it during operation
is known as its power dissipation capability.
Power Amplifier 401
A power transistor used in a power amplifier carries large current during operation.
This current heats up the collector junction. As we know, the rise in temperature influences
the operating conditions of the transistor. Therefore, the transistor used must be capable of
dissipating this heat to the surroundings. Usually, the heat dissipation capability of a transistor
is not sufficient. Hence, a heat sink is generally attached to a power transistor which
improves the heat dissipation and does not allow the temperature to rise beyond permissible
limits.
13.7 CLASSIFICATION OF POWER AMPLIFIERS
We have already seen that transistor power amplifiers usually handle large signals.
Many of them are’ driven so hard by the input signals that the collector current reaches
either in the cut-off or in the saturation regions during its peak values. Therefore, the usual
practice to classify power amplifiers is according to their mode of operation i.e., the portion
of the input cycle during which the collector current flows through the circuit.
Hence, they are classified as (i) class-A power amplifier (ii) class-B power amplifier
(iii) class-C power amplifier (iv) class-AB power amplifier (v) Class-D power amplifier.
13.7.1 Class-A Amplifiers
The power amplifiers in which the operating point is so adjusted that the collector
current flows during whole cycle of the input signal are known as class-A amplifiers.
Fig. 13.4 Fig. 13.5

A power amplifier circuit is shown in Fig. 13.4. It may be noted that load (speaker) is
connected to the collector through an output transformer. By the use of transformer perfect
impedance matching is obtained so that maximum power is delivered to the load.
For class-A operation of the amplifier, the biasing circuit (R1, R2 and RE) is so adjusted
that the operating point Q lies in the middle of die ac load line (See Fig. 13.5). Moreover,
collector current flows at all times throughout the whole cycle so that no pan of the signal
is cut-off. Thus, the output waveshape obtained in this case is exact replica of the input
waveshape, therefore, such amplifiers have least distortion. However, they suffer from
the following demerits ;
(i) their output power is low and

(ii) their collector efficiency is less than 50% (about 35%).
13.7.2 Class-B Amplifiers
current flows only during the positive half-cycle of the input signal are known as
class-B amplifiers.
For class-B operation of the
amplifier, the biasing circuit is so
adjusted that the operating point Q lies
at the collector cut-off voltage (See
Fig. 13.6) i.e. zero collector current
IC = 0. In other words, no biasing
circuit is needed in this case. During
positive half-cycle of the signal, the
input circuit is forward biased and
hence collector current flows. But,
during negative half-cycle of the signal,
the input circuit is reverse biased and
hence no collector current flows. It
may be noted that the output obtained
from class-B amplifier is just like an
amplified half-wave rectification. Fig. 13.6
In a class-B amplifier, since the negative half-cycle of the signal is cut-off, it suffers
from a severe distortion. However, the points in favour of this amplifier are :
(i) higher power output
(ii) higher collector efficiency (50 to 60%)
Such amplifiers are mostly used for power amplification in push-pull arrangement. It
will be discussed latter in this chapter.
13.7.3 Class-C Amplifiers
The power amplifiers in which collector current flows for less than half-cycle of
the input signal are shown as class-C amplifiers.
In class-C amplifiers, some reverse bias is given to the base. Therefore, some potential
of the positive half-cycle is utilised to wipe off this effect. Hence, the collector current
starts flowing only when the base is forward biased i.e., for the period less than half-cycle
(See Fig. 13.7) of the input signal.
Such amplifiers are never used for power amplification because of severe distortion
in the output. However, they are used as tuned amplifiers (in rf range) i.e., to amplify a
narrow band of frequencies because of their higher collector efficiency (nearly 80%).
Power Amplifier 403
Fig. 13.7
13.7.4 Class-AB Amplifiers
current flows for more than half-cycle but less than full-cycle of the input signal are
known as class-AB amplifiers.
For class A-B operation of the amplifier, the biasing circuit is so adjusted that the
operating point Q lies near the cut-off voltage (See Fig. 13.8). During a small portion of
negative half-cycle and for complete positive half-cycle of the signal, the input circuit is
forward biased and hence collector current flows. But during a small portion (less then
half-cycle) of the negative half cycle, the input circuit is reverse biased and
Fig. 13.8
hence no collector current flows during this period.
13.8 EFFICIENCY RATING

The maximum theoretical efficiency ratings of Class-A, B, C amplifiers are :
Amplifier Maximum theoritcal
efficiency rating (rmax)
Class - A 25%
Class - B 78.5%
Class - C 99%
Series Fed Class A power amp.
The following diagram shows the series Fed class A power amplifier.
VCC
IC RC
RB
Vo
IB
Co
Cr
Vi
Fig.13.9
DC bias operation
In biasing analysis, all ac sources and capacitors are cut off.
VCC - VBE
Here I B = , IC = bI B
RB
and VCE = VCC – ICRC
Following the transistor characteristic showing load line and Q-point.
So it input power is
Pi (dc) = VCC ICQ VCC
RC
VCC VCC 2
and Pi (dc) = VCC . =
max 2R C 2R C
IC IBQ
Q
ì VCC / R C ü
íQ IC (max) = ý
î 2 þ
O ICE VCC VCE
Q
Fig.13.10
Power Amplifier 405
AC Operation
When input ac signal is applifed then the output will vary from its dc bias. Operating
voltage and current. The variatioins are shown below.
IC
VCC Input signal
RC
Output
current
swing
VCE
VCC
Output voltage swing
Fig.13.11
P O(ac) = VC(rms) IC(rms) ...(a)
= IC2 (rms)R C ...(b)
2
VCE (rms)
= ...(c)
RC
The output power may be expressed using peak signal.
VCE (P) IC (P)
So Po (ac) = . (From equation(a))
2 2
VCE (P) IC (P)
= ...(d)
2
IC2 (P)
or Po (ac) = R C (From equation (b)) ...(e)
2
2
VCE (P)
or Po (ac) = (From equation (c)) ...(f)
2R C
It can also be expressed using peak to peak signal.
VCE (P - p) IC (p - P)
Po (ac) = (From (d))
8
IC2 (p - P)
= R C (From (e))
8
2
VCE (p - P)
= (From (f))
8R C
2
VCC ì VCC ü
Po (ac) = íQ ac VCE (P - p) = VCC & IC (p - P) = ý
max 8R C î max max RC þ
Efficiency (h)
It is the amount of ac power delivered from dc source.
Pa (ac)
%h = ´ 100
Pi (dc)
The maximum efficiency is given as
2
VCC / 8R C 1
%hmax = 2
´ 100 = ´ 100 = 25%
VCC / 2R C 4
But generally it is less then 25%
13.9 CALCULATIONS FOR MAXIMUM COLLECTOR EFFICIENCY OF A
CLASS-A POWER AMPLIFIER
The circuit diagram of a class-A power amplifier is shown in Fig. 13.12. The load is
connected in the collector circuit either directly or through a coupling transformer.
For determining maximum collector efficiency, refer to the output characteristics shown
in Fig. 13.13. At zero signal conditions, the effective resistance in the collector circuit is
almost zero since the primary winding resistance of the transformer is very small and can
be neglected. Therefore, dc load line is just a line passing through VCC and is parallel to the
axis of collector current IC - Draw the ac load line which cuts the dc load line at Q (operating
point) such that Q lies at the centre of ac load line.
Fig. 13.12 Fig. 13.13

Power Amplifier 407
In order to obtain maximum ac power output and hence maximum collector efficiency,
the peak value of collector current due to signal alone should be equal to zero signal
collector current IC
When the positive half-cycle is at its peak ;
Total collector current = 2 IC
and Vce= 0
When the negative half-cycle is at its peak ;
The collector current =0
and Vce = 2 VCC
\ Peak-to-peak collector-emitter voltage,
Vce(p – p) = 2 Vcc
Peak-to-peak collector current,
Vce (p - p) 2 VCC
Ic (p - p) = 2 IC = =
RL R ¢L
where, R ¢L = effective value of load resistance RL when referred to
primary side
i.e. R ¢L = n2RL
DC power input, Pdc = VCC IC = IC 2 R ¢L ... (i) (Q VCC = I C R ¢L )
Vce (p - p) ´ Ic (p - p) 2 VCC ´ 2 IC
Max. ac power output, Pac = =
8 8
1 1
= VCC IC = IC 2 R ¢L
2 2
Maximum collector efficiency,
Pac
hmax = ´ 100
Pdc
Substituting the value of Pdc and Pac from eqn. (i) & (ii), we get,
IC 2 R ¢L
hmax = ´ 100 = 50%
2 ´ IC 2 R ¢L
The above expression shows that a class-A amplifier has a maximum collector
efficiency of 50%. It means in class-A amplifier maximum 50% of dc power supplied can
be converted into ac power output. However, in actual practice, the collector efficiency of
a class-A amplifier is always less than 50% (about 35%) due to power loss in the primary
of transformer.
It may be noted here that maximum power is dissipated in the transistor in zero signal
conditions i.e.,
Max. power dissipated by the transistor, Pdis = VCC IC
While selecting the transistor we must be careful that its power rating should be > Pdis.
Example-13.4
For a power transistor working in class-A operation has zero signal power
dissipation of 8 W. If the ac output power is 3 W, determine (i) power rating of
transistor (it) collector efficiency.
Solution :
Power rating of transistor = zero signal power dissipation = 8 W (Ans.)
Now Pdc = 8 W and Pac = 3 W
Pdc 3
\ Collector efficiency,, h= ´ 100 = ´ 100 = 37.5% (Ans.)
Pac 8
Example-13.5
For a power amplifier working in class-A operation, the zero signal collector
current is 100 mA. Ifdc supply voltage VCC = 12 V, determine (i) the maximum ac
power output
(ii) the power rating of transistor and (iii) the maximum collector efficiency.
Solution :
VCC IC 12 V ´ 100 mA
Max. ac power output, Pac(max.) = = = 0.6 W (Ans.)
2 2
DC input power, Pdc = VCC IC = 12 V × 100 mA = 1.2 W
As maximum power is dissipated in the zero signal conditions,
Power rating of transistor = 1.2 W (Ans.)
Pac(max.) 0.6 W
Maximum collector efficiency, h= ´ 100 = ´ 100 = 50% (Ans.)
Pdc 1.2 W
Example-13.6
The transistor of a class-A power amplifier is supplied from a6V battery. If the
maximum collector current change is 30mA,find the power transferred to an 8W
loudspeaker when
(i) it is connected directly in the collector circuit
(ii) it is coupled through a transformer for max. power. Also determine the
turn ratio of the coupling transformer.
Solution : Here, Max. collector current change, DIC = 30 mA
Max. collector-emitter voltage change, DA CE = 6V
Loudspeaker resistance, RL = 8 W
Power Amplifier 409
(i) When loudspeaker is connected directly in the collector circuit (See Fig. 13.14)
Max. voltage across loudspeaker = DIC × RL = 30 mA × 8 W = 240 mV
Power delivered to the loudspeaker = 240 mV × 30 mA = 7.2 mW (Ans.)
This power is very small to drive the speaker.
Fig. 13.14 Fig. 13.15

(ii) When loudspeaker is connected through a coupling transformer (See Fig. 13.15)
D VCE 6V
Output impedance of the transistor = D I = 30 mA = 200 W
C
For maximum power transfer, the load resistance referred to primary side must be
equal to output impedance of the transistor i.e., R ¢L = 200 W.
Now, R ¢L = n 2 R L
R ¢L 200
\ turn ratio n= = = 25
RL 8
or n=5
Now, Secondary voltage, i.e., voltage across the speaker
Vp VCC 6
VS = = = = 1.2 V
n n 5
VS 1.2 V
Load current = = = 0.15 V
RL 8W
\ Power transferred to the speaker = ILVL = IL × Vs = 0.15 × 1.2 = 0.18 W = 180 mW
This power is much more (25 times) than the first case and is capable of driving the load.
Example-13.7
For class-A, CE transistor amplifier, the operating point is located at IC = 250 mA
and VCE = 8 V. Due to input signal the output collector current goes in between 450
mA and 40 mA. The VCE swings between 15 V and 1 V. Determine (i) the output power
delivered (ii) the input power (iii) collector-efficiency (iv) power dissipated by the
transistor.
Solution : Here, IC = 250 mA ; VCE = 8 V (zero signal or dc conditions)
IC (max) = 450 mA ; IC(min.) = 40 mA ù

ú (ac conditions)
VCE (max) = 15 V ; VCE(min) = 1V úû
\ Vce (p – p) = VC (max) – VCE (min.) = 15 – 1 = 14 V

Ic (p – p) = IC (max) – IC (min) = 450 – 40 = 410 mA
(i) Output power delivered or ac power output
Vce (p - p) ´ Ic (p - p) 14 V ´ 410 mA
Pac = = = 717.5 mW (Ans)
8 8
(ii) Input power i.e. dc input power
Pdc = VCE × IC = 8 × 250 = 2000 mW (Ans.)
Pac 717.5
(iii) Collector efficiency, h = ´ 100 = ´ 100 = 35.87 % (Ans.)
Pdc 2000
(iv) Power dissipated by the transistor
Pdis = Pdc – Pac = 2000 – 717.5
= 1282.5 mW = 1.2825 W (Ans.)
13.10 TRANSISTOR TEMPERATURE CONTROL BY HEAT SINKS
Power transistors are employed which are to handle large currents. Because of heavy
current these transistors are heated up during operation. As transistor is a temperature
dependent device, we have to apply some method to dissipate this excessive heat produced
in it and to keep the temperature of the transistor within the permissible limits. The device
used for this purpose is called heat sink.
Heat sink is just a sheet of metal which improves the heat dissipation ability of
power transistor and keeps its temperature within the permissible limits.
The quantity of heat to be dissipated depends upon the surface area of the heat sink.
Therefore, heat sinks are designed in various shapes. However, the modem trend is that
power transistors are mounted on the chassis or body. Then chassis or body acts as a heat
sink.
Power Amplifier 411
Mathematical analysis
The permissible power dissipation of the transistor is very important term for power
transistors. The permissible power rating of a transistor is determined from the expression :
Tj(max) - Tamb
Ptotal =
q
where, Ptotal = total power dissipated within the transistor In watts
Pj(max.) = maximum permissible junction temperature i.e., 90°C for Ge and
150°C for Si transistors)
Tamb = ambient temperature i.e., temperature of surrounding air in oC.
q = thermal resistance i.e., resistance to heat flow from junction to
the surrounding air. Its units are °C/watt.
The value of q is usually given in the transistor manual. Low value of q means heat
flows easily from junction to surrounding air i.e., more dissipation and smaller rise in
temperature. In fact, heat sink reduces the value of q appreciably resulting in increase in
power dissipation.
Example-13.8
A transistor AC 128 is used as a medium power transistor. Its thermal resistance
is 0.29° C/mW when no heat sink is provided. The maximum junction temperature is
90°C. If the ambient temperature is 25°C, find
(i) the maximum power dissipation that can be allowed ;
(ii) the maximum power dissipation that can be allowed with aluminium heat sink of
12.5 cm2 area which reduces the thermal resistance q to 0.08°C/mW. Comment on the
results.
Solution : (i) When no heat sink is used
Tj(max) = 90° ; Tamb = 25°C ; q = 0.29°C/mW
Tj(max) - Tamb 90 - 25
\ Ptotal = = = 224 mW (Ans.)
q 0.29
Tj(max) = 90° ; Tamb = 25°C ; q = 0.08°C/mW
Tj(max) - Tamb 90 - 25
\ Ptotal = = = 812.5 mW (Ans.)
q 0.08
For instance, if Vcc = 12 V, then
Without heat sink ;
224 mW
IC(max) = = 18.67 mA (Q Ptotal = VCE ´ IC )
12 V
812.5 mW
With heat sink ; IC(max) = = 67.6 mA
12 V
Thus, the same transistor can work at much higher collector current when used
with heat sink.
Example-13.9
An Si transistor dissipates 2 W during working, tf maximum junction temperature
is 150°C, find (i) the maximum ambient temperature at which it can be operated.
Assume value of q for the transistor with its heat sink to be 0.02 oC/mW.
(ii) If in place of this transistor another equivalent Ge transistor having Tj (max) =
90°C is applied at what temperature it can be operated.
Comment on the result.
Solution :
When SI transistor is used ;
Ptotal = 2W = 2000 mW ; q = 0.02°C/mW and Tj(max.) = 150oC
Tj(max .) - Tamb
Now, Ptotal =
q
150 - Tamb
or 2000 =
0.02
\ Ambient temperature, Tamb = 150 – 2000 × 0.02 = 110°C (Am.)
(ii) When Ge transistor is used;
Ptotal = 2000 mW ; q = 0.02°C/mW andTj(max.) = 90oC
Tj(max.) - Tamb
Now Ptotal =
q
90 - Tamb
or 2000 =
0.02
or, Ambient temperature, Tamb = 90 – 2000 × 0.2 = 50°C (Ans.)
13.11 COLLECTOR DISSIPATION CURVE AND ITS IMPORTANCE
Under working conditions, when current flows through the collector of a transistor,
some power is lost at the collector junction known as collector dissipation. This power is
expressed as :
Ptotal = Vce × Ic
where Ptotal = power lost at collector junction
Vce = rms value of collector-emitter voltage
Ic = rms value of collector current
Power Amplifier 413
Since the maximum power that a transistor can dissipate without overheating is constant,
therefore,
Vce × Ic = constant
It represents the equation of a hyperbola. If a curve is plotted, as per this equation, on
the output characteristics of a transistor, a hyperbolic curve is obtained as shown in Fig.
13.16. This hyperbolic curve is called collector dissipation curve.
Importance of this curve
The collector dissipation curve
represents the actual operating
region for the transistor. In Fig.
13.16. The region left of the curve
is the operating region as marked.
It means that the load line selected
must lie below or to the left of this
curve. However, if the collector
current and voltage are so selected
that load line lies to the right of this
curve, then the collector dissipation
of the transistor will exceed than
the permissible limits. This will
result in destruction of transistor Fig. 13.16
due to overheating.
Hence, while designing a power transistor amplifier, it is utmost important to draw its
power dissipation curve along with the load line on the output characteristics. The design is
allowed only if the load line lies to the left of this curve. However, if the load line comes to
the right side of this curve, the circuit value have to be adjusted to bring it on the left of the
curve.
13.12 STAGES OF A PRACTICAL POWER AMPLIFIER
Usually, a practical power amplifier is an audio-amplifier. Its function is to amplify a
weak signal sufficiently strong to operate a loudspeaker or other output devices. To achieve
this goal, a power amplifier generally has the following three stages :
(i) Voltage amplification stage
(ii) Driver stage
(iii) Outputstage orpowerstage.
Alltheabovestagesareshownin theblockdiagram ofapoweramplifier(SeeFig.13.17).
Fig. 13.17
(i) Voltage amplification stage. Usually, the signal received, by the power amplifier
at the input is of very low voltage level (< 10 mV). Therefore, two or more voltage
amplification stages are employed at the start to raise the voltage level of the signal.
Generally, these stages are connected by R-C coupling because of its better frequency
response.
(ii) Driver stage. The stage that immediately precedes the output stage is called
the driver stage. It receives the signal from the last voltage amplification stage and supplies
the necessary power to the output stage. Generally, class-A power amplifier is employed
in this stage. Moreover, it is coupled to the output stage by transformer coupling. While
designing, the main concentration is to obtain maximum power gain from this stage.
(iii) Output or Power stage. The output of the driver stage is fed to the output
stage. This is the final stage of a power amplifier and load is connected to this stage
through an output transformer. This stage, generally employs class-B amplifiers in push-
pull arrangement. Here, the main concentration is to obtain maximum power gain.
13.13 DRIVER STAGE
In a power amplifier, the stage that preceeds the output stage is called a driver stage.
In fact, this stage provides the necessary drive (i.e., base current and voltage) to the
output stage and hence the name driver stage. It is essentially a class-A amplifier, its
circuit is shown in Fig. 13.18. It may be noted that this stage is coupled
Fig. 13.18
to the output stage through a coupling transformer. Hie primary of the transformer is
connected in the collector circuit and acts as a collector load. The secondary is usually a
centre-tapped which provides the necessary input for the push-pull amplifier. The coupling
transformer also provides the necessary impedance matching so that maximum power can
be transferred.
Power Amplifier 415
13.14 OUTPUT STAGE

The basic purpose of the output stage is to provide maximum power to the load. To
achieve this goal an output transformer is used which provides the necessary impedance
matching.
If a single transistor is used in the output stage then we have to employ it as class-A
amplifier for faithful amplification. It has been discussed earlier that these amplifiers have
very poor power efficiency (nearly 35%) and as transistors are mostly operated from
batteries which is a costly source of power, therefore, such a low efficiency cannot be
tolerated.
In order to obtain higher efficiency, two transistors in class-B operation (h nearly
60%) are employed, at the output stage. The arrangement in which these transistors are
connected is called push-pull arrangement. In this case, one transistor amplifies the positive
half cycle whereas the other transistor amplifiers the negative half-cycle of the signal.
Thus, the whole signal is amplified.
13.15 PUSH-PULL AMPLIFIER
It has already been discussed that class-A amplifiers have faithful amplification but
they suffer from poor efficiency (about 35%). Therefore, class-B amplifiers, which have
higher efficiency, are used at the output stage in push-pull arrangement. Almost all the
audio power amplifiers used in transistor radio receivers, tape recorders, record player
etc. make use of this arrangement because these systems are usually operated by batteries
(or cells) where efficiency is of prime importance.
Fig. 13.19
13.15.1 Circuit analysis
A simple circuit arrangement of a push-pull amplifier is shown in Fig. 13.19. Here,
two transistors Tr1 and Tr2 are placed back-to-back. Both the transistors are operated in
class-B operation i.e., the collector current is almost zero in the absence of the signal. The
input signal is given to the circuit from the driver stage through a driver transformer. The
secondary of the driver transformer is centre tapped which supplies equal and opposite
voltages to the base circuits of the two transistors. On the other hand, centre tap primary
of the output transformer is connected in the collector circuit and load (loudspeaker) is
connected at the secondary side. By designing proper turn ratio of the output transformer,
a suitable impedance matching is obtained to get maximum output across the load. The
supply voltage +VCC is connected between the centre tap of output transformer and the
base as shown in Fig. 13.19.
13.15.2 Operation
The input signal appears across the secondary terminal AB of the driver transformer.
During the first half-cycle (+ve) of the signal, end A becomes positive and end B negative.
This will make the base-emitter junction of transistor Tr1 forward biased and that of transistor
Tr2 reverse biased. The current will be conducted through transistor Tr1 only (as shown by
the solid arrows). Whereas, transistor Tr2 is in the cut-off state and will not conduct any
current. Therefore, first half-cycle of the signal is amplified by the transistor Tr1 and appears
in the upper half of the primary of output transformer.
During the second half-cycle (-ve) of the signal, end B becomes positive end A negative.
This will make the base-emitter junction of transistor Tr2 forward biased (conducting state)
and that of transistor Tr1 reverse biased (cut-off state). Hence, current is conducted by the
transistor Tr2 only (as shown by the dotted arrows). Consequently, this half-cycle of the
signal is amplified by T& and appears in the lower half of the output transformer primary.
The centre tapped primary of the output transformer combines the two halves of the
cycle and forms a complete sine wave output in the secondary. By proper impedance
matching, maximum power can be transferred to the load. In this case, the load resistance
RL when referred to the primary side, its value will be ;
2
æ 2N ö
R ¢L = ç 1 ÷ R L
è N2 ø
where, N1 = No. of primary turns between centre tap and either end of
the output transformer
N2 = No. of secondary turns.
13.15.3 Advantages
The following are the prominent advantages of push-pull amplifiers :
(i) Their collector efficiency is quite high ( ~ 75%) due to class-B operation.
(ii) Distortion free output is obtained.
(iii) They give more ac output power per device,
(iv) The dc components for output currents of two devices oppose each other magnetically
in the core of the output transformer. This eliminates tendency of the core to saturate.
(v) As the output transformer does not saturate, therefore, it requires less ferromagnetic
material. That is why output transformers used for push-pull amplifier circuits are
Power Amplifier 417
lighter, smaller and less expensive than transformers of comparable quality that are
used in single-ended circuits.
13.15.4 Disadvantages
(i) Two identical transistors are required.
(ii) It requires two equal and opposite voltages at the input, therefore, driver stage has to
be employed.
(iii) If the parameters of the two transistors differ, there will be unequal amplification of
the two halves of the signal which introduces more distortion.
13.16 COMPLEMENTARY-SYMMETRY PUSH-PULL AMPLIFIER
We have seen that in an ordinary push-pull amplifier, two centre-tap transformers, one at
the input and the other at the output, are required. A complementary-symmetry push-pull
amplifier works on the same principle i.e., for the first half-cycle one transistor conducts
and the other remains in the cut-off state and in the second half-cycle the action is reversed.
Both the transistors work in class-B operation.
Circuit analysis
The circuit arrangement of a complementary-symmetry push-pull amplifier is shown
in Fig. 13.20. The circuit employs two transistors, one npn and the other pnp. The important
point to note is that no centre tap transformer is employed. However, an ordinary output
transformer (not centre tapped) is employed for impedance matching to get maximum
output across the load. The dc supply is provided by the centre tap battery or by two
separate batteries of half the voltage.
Fig, 13.20
Operation
The input signal appears across the terminal AB. During the positive half-cycle of the
input signal, the transistor Tr1 (npn) conducts current while transistor Tr2 (pnp) does not
conduct as it is at cut-off state. During the negative half-cycle of the input signal, the
transistor Tr2 (pnp) conducts while transistor Tr1 (npn) does not. Hence, npn transistor
amplifies the positive half-cycle whereas pnp transistor amplifiers the negative half-cycle.
The amplified signal appears across the primary which is transferred to the secondary or
the load.
Advantages
(i) This circuit does not require centre-tap transformers. Hence, its weight and cost is
less,
(ii) At the input driver stage is not necessary.
(iii) Efficiency is high.
Disadvantages
(i) It is difficult to get a pair of transistors (npn and pnp) having exactly same
characteristics.
(ii) We require two batteries although of half the voltage.
13.17 HARMONIC DISTORTION IN POWER AMPLIFIERS
Since power amplifiers are to handle large signals, distortion is always introduced in
the output i.e., the wave shape of the output is never exact replica of the wave shape of
the input signal. Harmonic distortion is the prominent one. No doubt that a large amount of
harmonic distortion is present in class-B operation (output wave shape is half-cycle) but it
is also present to some extent (because of the non-linearity of transistors) in class-A
operation.
Mathematical analysis
If Vin = Vin Sin cot is the input sinusoidal signal applied to a *power amplifier, the
waveform of the output signal can be represented as
i0 = I0 + h sin wt + I2 sin 2wt + I3 sin 3wt + ...... ...(i)
where, I0 = dc component
I1 = peak value of the first harmonic (or the fundamental)
I2 = peak value of the second harmonic and so on
The harmonic distortion for each of these components is then defined as
I2
Second harmonic distortion, D 2 =
I1
I3
Third harmonic distortion, D3 =
I1 and so on ...(ii)
The total distortion or distortion factor may be defined as

D = D2 2 + D32 + D 4 2 + ..... ... (iii)
Power Amplifier 419
The distortion affects the output power. When distortion occurs, the output power
calculated on the basis of non-distortion is no longer correct rather output power due to the
fundamental component on the distorted signal is
I12 R L
P1 = .... (iv)
2
The total power due to all the harmonic components ;
RL
P = (I12 + I 2 2 + I32 + ...)
2
é æ I ö2 æ I ö2 ù I 2R
or P = ê1 + ç 2 ÷ + ç 3 ÷ + ....ú 1 L
ê è I1 ø è I1 ø ú 2
ë û
or P = (1 + D 2 2 + D32 + ....)P1 .... (v)
Substituting the value from eqn. (iii), we get,
P = (1 + D2)P1 .... (vi)
13.18 DISTORTION IN PUSH-PULL AMPLIFIERS
In a push-pull amplifier, half-cycle of the signal is amplifier by one transistor and the
other half-cycle is amplified by the other transistor. When we apply a sinusoidal signal of
frequency co at the input of the amplifier, we get opposite-phased base currents represented
by the following equations :
Ib1 = Ib sin wr ... (i)
Ib2 = Ib sin (wt +p) ... (ii)
We have already discussed that due to nonlinearity of the ‘transistor, even if the input
is sinusoidal, the output current contains harmonics. The output i.e., collector current of
first transistor is then represented as
ic1 = I0 + I1 sin wt + I2 sin 2wt + I3 sin 3wt + ...... ...(iii)
As the collector current of second transistor is 180° (n radians) out of phase, it can be
represented as
ic2 = I0 + I1 sin (wt + p) + I2 sin 2(wt + p) + I3 sin 3(wt + p) ......
or ic2 = I0 + I1 sin (wt + p) + I2 sin (2wt + 2p) + I3 sin (3wt + 3p) ......
or ic2 = I0 – I1 sin wt + I2 sin 2wt – I3 sin 3wt + ...... ...(iv)
Since matched pair of complementary transistors are available in the market, therefore,
we assume that the characteristics of the two transistors are identical.
In a push-pull amplifier, the voltage induced in the secondary of the output transformer
is proportional to the difference of the two collector currents i.e:, ic1 – ic2. Then the output
voltage will be given as
vout = k (ic1 – ic2)
or vout = k [2 I1 sin wt + 2 I3 sin 3wt + ......]
or vout = 2 k ( I1 sin wt + I3 sin 3wt + ......] ...(v)

where k is a constant of proportionality.
The power developed in the load RL depends upon the output voltage (vout).
It is important to note here that no even harmonic term appear in the output
voltage equation. Hence the output is free from even harmonics.
The above discussion already shows that in a push-pull amplifier, the distortion is
much reduced.
All the harmonic terms produced in the power amplifiers do not have the same
magnitude. Their magnitudes are in decreasing order i.e., the magnitude of second harmonic
is more than the third and the magnitude of third harmonic is more than the fourth and so
on. In fact, for all practical purposes, the second harmonic is considered to be the most
objectionable since rest of the harmonic terms are very small in magnitude and hence
neglected.
In push-pull amplifiers, all even harmonics are cancelled. Therefore, in the absence
of second harmonic, we say that the distortion in the output of a push-pull amplifier is
almost negligible in comparison to a single-ended power amplifier.
Q.1 Why a power amplifier is always preceded by a voltage amplifier.

Ans. Signal voltage at the input is quite small but a large voltage input signal is necessitated so as
to provide large power at the output. So voltage amplifier is required for raising the voltage
level of the weak input signal before it is fed to the power amplifier ?
Q.2 Why power amplifiers are called large signal amplifiers ?
Ans. Power amplifiers are required to handle large voltage signals so as to deliver large power
at the output. That is why power amplifiers are called large signal amplifiers.
Q.3 What is the collector junction temperature for Ge and Si in case of transistor power
amplifier ?
Ans. The collector junction temperature for Ge lies in the range of 150° C to 225° C while in
case of silicon, it ranges 60° to 100° C.
Q.4 What is meant by power dissipation capacity of a power transistor ?
Ans. Power dissipation capacity of a power transistor is its capability to dissipate the heat
developed in it.
Q.5 Why a class A power amplifier is cooler in the presence of signal than in the absence of
signal ?
Ans. With the zero signal applied at the input of the class A power amplifier, ac power developed
across the load reduces to zero and therefore, all the power drawn from collector supply
Vcc is wasted in the form of heat. Thus, a power transistor dissipates maximum power
Power Amplifier 421
under zero-signal condition. Thus the device is cooler in the presence of signal than in the
absence of signal.
Q.6 What is the maximum collector circuit efficiency of transformer-coupled class A power
amplifier?
Ans. 50 percent
Q.7 Why a stepdown transformer is used in the output circuit of a power amplifier ?
Ans. For transfer of maximum power from amplifier to the output device matching of amplifier
output impedance with the impedance of the output device is necessary and this is
accomplished by using a stepdown transformer of suitable turn-ratio at the output.
Q.8 Comment on the maximum efficiency of class B operation.
Ans. The maximum possible value of efficiency for class B operation is 78.5%. The efficiency
of class B operation exceeds that of class A operation because with zero excitation there
is no current in class B operation whereas power is drawn from supply source in class A
operation.
Q.9 What is the use of class C amplifiers ?
Ans. The use of class C amplifiers is limited for a fixed frequency, as occurs in communication
circuits.
Q.10 Why class D power amplifiers are becoming more and more popular ?
Ans. Class D power amplifiers are becoming popular because of their very high efficiency
(above 95 %).
Q.11 What is the maximum collector circuit efficiency of a complementary push-pull class B
power amplifier?
Ans. Maximum collector circuit efficiency of a .class B complementary push-pull power amplifier
is 78.5%.
Q.12 Why the power rating of a power transistor is required to be reduced when it is operated
above ambient temperature of 25° C ?
Ans. The heat flow from the transistor junction to the surroundings depends on the difference of
junction temperature and the ambient temperature. As the ambient temperature increases,
rate of heat flow and so the power rating of the transistor decreases. Thus the power
rating of a power transistor is required to be reduced when operated above ambient
temperature of 25° C.
Q.13 Define thermal resistance of a power transistor.
Ans. Thermal resistance is defined as the resistance to heat flow between two temperature
points.
EXERCISE
1. What is an audio power amplifier? What is its need?
2. What is an audio power amplifier? Explain the difference between a voltage and power
amplifier.
3. What do you understand by class A, B and C power amplifiers?
4. Define and explain the following terms as applied to power amplifiers (i) Collector efficiency,
(ii) Power dissipation capability and (iii) Overall gain.
5. Describe a transistor class A power amplifier with resistive load. How power is distributed
in it.
6. Calculate the expressions for collector efficiency and overall efficiency of class A, CE
amplifier with resistive load.
7. Describe a transistor class A power amplifier with output transformer as load. Discuss its
working and find an expression for its efficiency.
8. Show that maximum collector efficiency of class A transformer coupled power amplifier is
50%.
9. Discuss class B power amplifier and calculate its overall efficiency.
10. What are the advantages of push-pull amplifier?
11. Draw the circuit diagram of a push-pull amplifier. Explain its operation. Discuss the
advantages and disadvantages.
12. Explain the difference between a voltage and a power amplifier. Define and explain
(a) Collector efficiency (b) distortion and (c) power dissipation capability as applied to
power amplifiers. Show that the maximum collector efficiency of class A push-pull amplifier
is 50%.
13. Draw the circuit of a class 8 push-pull amplifier and explain its operation. Derive an ex-
pression for its maximum conversion efficiency.
14. Explain
(a) Why does collector efficiency play important part in power amplifiers?
(b) Why does the output stage employ push-pull arrangement.
15. What do you mean by a tuned amplifier? Explain a single tuned inductively coupled transis-
tor amplifier.
16. Describe a double tuned amplifier.
17. (a) Explain in brief the function of tank circuit in tuned voltage amplifier,
(b) Explain the effect of changing Q of the coil used in tank circuit, on its band-width.
18. For a class A power amplifier, the maximum and minimum values of collector-emitter
voltages are 20 V and 4 V respectively. Vcc = 25 V. Determine overall efficiency of the
amplifier. [Ans. 16%]
Power Amplifier 423
19. A power amplifier working in class-A operation has a transformer as load. If the trans-
former has a turn-ratio of 10 and the secondary load is 100 W, find the maximum a.c.
power output. Given that zero signal collector current is 0-1 A.
[Ans. (Pac)max = 50 W]
20. A power transistor working in class-A operation carries zero signal collector current of 50
mA. Determine (i) the. maximum ac power output, (ii) power rating of transistor and
(iii) the maximum collector efficiency when the collector supply voltage is 9 V.
[Ans. (i) 225 mW, (ii) 450 mW, (iii) 50%]
21. A transformer coupled class A transistor power amplifier uses a transistor with b = 100
and supplies to load of 8 W connected across the secondary of the transformer. If the
maximum and minimum values of collector-emitter voltage and currents are 20 V and 2-4
V and 225 mA and 25 mA respectively, then determine (i) appropriate value of zero signal
collector current, (ii) zero signal base current, (iii) d.c. power input, (iv) a.c. power output
(v) transformer turn-ratio, (vi) collector efficiency and (vii) transformer power rating.
[Ans. (i) 125 mA, (ii) 1·25 mA, (iii) 1·4W,(iv) 0·44 W,(v) 3·317:1,
(vi) 31·43 % (vii) 14 W]
22. A class B push-pull amplifier is supplied with Vcc = 50 V. The signal swings the collector
voltage down to Vmin = 10 V. The dissipation in both transistors in total is 40 W. Find the
total power and conversion efficiency.
[Ans. 107·62 W, 62·81 %]
ppp

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2019 First Edition

Chapter-1 Bipolar Junction Transistor (BJT) 1-23

Chapter-3 Field Effect Transistors & Biasing 56-94

Chapter-5 Small Signal Analysis of FET 156-185

Chapter-7 Frequency Response of Amplifiers 210-258

Chapter-8 Compound Configurations 259-289

Chapter-10 Sinusoid Oscillators 327-351

Chapter-11 Operational Amplifier 352-369

Chapter-12 Application of Op-amp 370-394

E(n) Fig. 1.3 E(p) Fig. 1.4

PNP Transistor NPN Transistor

Base a) Construction Base

1.10 CHARACTERISTICS OF TRANSISTOR CONFIGURATION

Output voltage = VCB Fig. 1.10

1.11.1 Input Characteristic

0.5 1.0 1.5

SATURATION ACTIVE REGION

COLLECTOR BASE VOLTAGE, V CB IN VOLTS

1.11.3 Current Amplification factor (a)

1.12 COMMON - EMITTER CONFIGURATION (CE)

1.12.2 Output characteristics

current gain for this configuration is iB = 1

larger than unity. The transistor must

corresponding change in collector 1

base junction completely breaks down Fig. 1.15

The output resistance of CE configuration is less than that of CB configuration as the

Comparing it with equation IC = bIB + ICEO

1.13 COMMON COLLECTOR CONFIGURATION

1.14 RELATION BETWEEN a, b & g

Fig. 1.18 Fig. 1.19

Fig. 1.20 Fig. 1.21

SHORT QUESTION AND ANSWERS

Q.1 Explain why an ordinary junction transistor is called bipolar?

Q.23 What is faithful amplification ?

1. For a transistor connected in common base configuration, if IC = 0·95 mA and IB = 50 mA,

BJT Biasing & Stabilisation

Fig. 2.1 Fig. 2.2

Applying KVL in input loop, IB

I C Q = bI BQ = (50)( 47.08mA ) = 2.35mA

(b) VCE Q = VCC - I C R C

2.4.2 Self / Emitter-Stabilized bias circuit

VCC Fig. 2.10

VCC - VBE 20V - 0.7 V

Determine the levels of I CQ and VCE Q 18 V

(50)(1.2 kW) > 10 (22 kW) 22 kW 1.2 kW

I C Q = bI B = (50)( 39.6 mA ) = 1.98 mA

2.4.4 DC feedback biasing

Solving for IB gives

= 20 V – (1.86 mA)(4.7 kW)

Þ VTh – IBRTh = 3.1

R 2 VCC R 1R 2 Fig. 2.25

The Circuit connected to transistor Fig. 2.30

results in (120)(1.1kW) > 10(10 kW)

Applying Kirchhoff’s voltage law around the base-emitter loop yields

Determine VCE Q and IE for the network of

Fig. 2.39 Determining RTh. Fig. 2.40 Determining E Th

VCC + VEE 20V + 20V 40V

2.5 BIAS STABILIZATION

S VBE = DI C DVBE I CO & b = Cons tan t

2.7.3 Stability factors in different Bias Circuit

VCC - VBE Fig. 2.42

2.8 DESIGN GUIDELINES OF TRANSISTORS BIASING CIRCUITS

SHORT QUESTION AND ANSWERS