UNIT – I

1. Explain the ASIC Design flow with a neat flow chart.

2. Differentiate channel and channel less gate array based ASIC design.
3. Illustrate internal structure of Configurable Logic Block (CLB) with an example.
4. Discuss field programmable gate array with a neat diagram.
5. Illustrate Programmable Logic Array and Programmable Array Logic design with an
example.
6. Illustrate the information of ASIC cell Library with an example.
7. What is CBICs? State the important features of CBICs.
8. Differentiate between Full custom, Semi-Custom, FPGA and Gate Array based ASIC
Design Styles.
9. Discuss the Economics of the ASIC Design.
10. Discuss the fixed and Variable cost of ASIC Design.
 UNIT – II
1. Calculate the logical effort for 2 input NAND and NOR gate, and show logical effort for
inverter is equal to 1.
2. Assume 4bit multiplicand a 3 a 2 a1 a0 and 4bit multiplier b 3 b 2 b1 b0 produce partial
products and sum of partial product and represent same using half adder and full adder.
3. Calculate the logical effort and logical area of single stage AOI221 and OAI221 cell.
4. Discuss any two techniques used to reduce the number of adders and delay in multiplier.
5. Explain the reduction of partial products in array multiplier using canonical signed digit
(CSD).
6. Discuss the parasitic capacitance in the CMOS device.
7. Discuss how to predict the delay in single stage and multistage cells.
8. Discuss how the delay is reduced using Carry save adder (CSA) and Ripple carry adder
(RCA) with neat Datapath layout.

UNIT – III
1. Draw the IEEE recommended dimensions and their constructions for logic gate symbols
NAND gate and XOR gate.
2. Explain the Hierarchical design with suitable example.
3. Explain the vectored instances and buses for 16-bit D-latch and draw the diagram for 4-
bit D-latch.
4. Discuss the vectored instances for 16-bit D-Latch.
5. Discuss the local nets and external nets in the ASIC design?
6. Explain the Schematic ICONs and Symbols with suitable examples.
7. Discuss the floating gate avalanche MOS (FAMOS) with a neat diagram.
8. Differentiate between Metal-Metal Antifuse and Poly-diffusion Antifuse with neat
diagram.
9. Explain the following program technologies with relevant diagram
i. Antifuse programmable Technology
ii. EEPROM programmable Technology.
10. Explain the different I/O requirements in the ASIC I/O cells.
11. Discuss the Xilinx configured Static RAM with neat diagram.
 UNIT – IV

1. Discuss the types of simulation available in ASIC.

2. Explain the CFI connectivity model with example.
3. Identify and explain the standard tool used to exchange the information between EDA
tools.
4. Discuss the CAD Framework Initiative (CFI) model with neat diagram.
5. Explain the following partitioning methods
i. Kernighan–Lin Algorithm
ii. Constructive Partitioning

UNIT – V

1. Discuss the various steps involved in the floorplanning with neat diagram.
2. Discuss goals and objectives of Floorplanning.
3. Discuss goals and objectives of placement.
4. Explain the Iterative Placement Improvement for cell placement Design.
5. Explain the Eigen value algorithm for cell placement in ASIC Design.
6. Discuss Min-cut algorithms for cell placement in ASIC Design.
7. Illustrate the Input Output padding and Power planning in the floorplanning with neat
diagram.