DIGITAL CIRCUITS-2 - REPORTS

OVERALL ANALYSIS COMPARISON REPORT

SOLUTION REPORT

ALL(16) CORRECT(4) INCORRECT(7) SKIPPED(5)

Q. 1

24 MHz clock frequency is applied to a cascaded counter of MOD-3, MOD-4

and MOD-5 counters. The lowest output frequency and the overall MOD value
of the cascaded counter are
FAQ Have any Doubt ?

A 600 kHz, 60

B 400 kHz, 60 Your answer is Correct

Solution :
(b)

C 400 kHz, 120

D 600 kHz, 120

QUESTION ANALYTICS

Q. 2

Consider the following statements.

1. A flip-flop can store 1-bit information
2. Race around condition occurs in a level triggered J-K flip-flop when both the
inputs are 1
3. Master slave configuration is used in flip-flops to store 2 bits of data
4. A transparent latch consists of a D-type flip-flop
Which of these statements are correct?
FAQ Have any Doubt ?

A 1 and 2
 A 1 and 2

B 1, 3 and 4 Your answer is Wrong

C 1, 2 and 4 Correct Option

Solution :
(c)
Master slave configuration stores 1-bit of data.

D 2 and 3

QUESTION ANALYTICS

Q. 3

A certain 8-bit successive approximation type analog to digital converter has full
scale voltage of 2.65 V. If the conversion time for VA = 1.5 V is 75 μs, then the
conversion time for VA = 2 V is
FAQ Have any Doubt ?

A 75 μs Correct Option

Solution :
(a)
For successive approximation type of converter, the conversion time is
independent of VA. Hence, option (a) is correct.

B 25 μs

C 225 μs

D 150 μs

QUESTION ANALYTICS

Q. 4

Assume that the initial value of Q is 0. After applying the clock signal to the
given circuit, the subsequent states of Q will be
 FAQ Have any Doubt ?

A 0, 1, 0, 1, 0 Your answer is Wrong

B 1, 0, 1, 0, 1 Correct Option

Solution :
(b)

C 0, 0, 0, 0, 0

D 1, 1, 1, 1, 1

QUESTION ANALYTICS

Q. 5

The resolution of a 10-bit analog to digital convertor is ____________ %.

FAQ Have any Doubt ?

0.097 (0.07 - 0.12) Correct Option

Solution :
0.097 (0.07 - 0.12)

Your Answer is 97.6

QUESTION ANALYTICS

Q 6
Q. 6

A modulo-16 ripple counter uses J-K flip-flops. If the propagation delay of each
flip-flop is p ns and the maximum clock frequency that can be used is 5 MHz,
then the value of p will be _________.
FAQ Have any Doubt ?

50 Correct Option

Solution :
50

Your Answer is 2758.6

QUESTION ANALYTICS

Q. 7

The mod-number of the asynchronus counter shown in the figure is

___________.

FAQ Have any Doubt ?

24 Your answer is Correct24

Solution :
24
It is 5-bit ripple counter that can count from 0 - 23. At 11000 the output of
the NAND gate is LOW. This will clear all FFs. So it is a mod-24 counter.

QUESTION ANALYTICS
Q. 8

Consider the counter circuit and propagation delay table shown below:

(Assume all the devices are ideal except for some propagation delay).
What is the maximum clock frequency that can be applied to the above counter?
FAQ Have any Doubt ?

A 125 kHz

B 100 kHz Correct Option

Solution :
(b)

C 200 kHz

142 85 kHz
 D 142.85 kHz

QUESTION ANALYTICS

Q. 9

Find the minimum number of flip-flops required to design a sequential circuit

whose state diagram is given below?

FAQ Have any Doubt ?

A 2 Correct Option

Solution :
(a)
 B 3 Your answer is Wrong

C 4

D 5

QUESTION ANALYTICS

Q. 10

Consider a sequential circuit using three J-K flip-flops and one AND gate as
shown in figure. Output (z) of the circuit becomes ‘1’ after every N-clock cycles.
The value of N is ___________
 FAQ Have any Doubt ?

A 6 Your answer is Correct

Solution :
(a)

It is MOD-6 counter. So, output z will be 1 after 6 clock pulses

B 7

C 10

D 12

QUESTION ANALYTICS

Q. 11

An 8-bit digital ramp ADC with a 40 mV resolution uses a clock frequency of

2.5 MHz and a comparator with threshold voltage VT = 1 mV. The digital output
for VA = 6 V is
FAQ Have any Doubt ?

A 10010111 Correct Option

Solution :
(a)

B 10010110
 C 10111110

D 10111111

QUESTION ANALYTICS

Q. 12

Consider the following circuit

Initially the counter is at “000”. After 9 clock pulses, the state of LEDs is
(assume +VCC and 0 are used to represent logic-1 and logic-0 respectively)
FAQ Have any Doubt ?

A only LED1 and LED 2 are ON

B only LED 2 and LED 3 are ON

C only LED 1 and LED 3 are ON Correct Option

Solution :
(c)
 D All LED’s are ON

QUESTION ANALYTICS

Q. 13

The MOD-number of the asynchronous counter shown in the figure below is

FAQ Have any Doubt ?

24 Your answer is Correct24

Solution :
24

QUESTION ANALYTICS

Q. 14

Consider the circuit shown below, initially both the flip-flops were cleared.

The modulus of the given counter circuit (i.e. the number of used states) is
________.
FAQ Have any Doubt ?

3 Correct Option

Solution :
3
 QUESTION ANALYTICS

Q. 15

The initial contents of a 4-bit serial-in-parallel out, right shift, shift register is
shown in the given figure is 0110. By the end of 7th clock pulse from initial
state, the number of times the LED will be in ON state is __________.
(Assume logic 1 as + 5 V and logic 0 as –5 V)

FAQ Have any Doubt ?

3 Correct Option

Solution :
3

Your Answer is 5

QUESTION ANALYTICS
 Q

Q. 16

Consider the counter circuit designed using J-K Flip-Flops as shown in figure.

The MOD value of the counter is ___________.

(Assume all the elements are ideal)
FAQ Have any Doubt ?

2 Correct Option

Solution :
2
 Your Answer is 3

QUESTION ANALYTICS