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Goal 3

 Flip Flops
 RS Flip Flop
 D Flip Flop
 J-K Flip Flop

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Flip Flop FF
A synchronous bistable device. The term synchronous means that the output changes state only at a
specified point on the Clock. That is, change in the output occur in synchronization with the clock. FF
devices are a 1 bit memory devices. Unlike combinational logic the output of a flip flop retain its state
(value) even after the removal of the input and the clock. Asynchronous means that the output of the device
will change its state independent of the clock. Asynchronous control signals override the clock. A flip flop
may have asynchronous control signals for setting (output is high) or clearing (output is low) the output and
it may have either 1 or 2 inputs depending on the type of the flip flop. All synchronous flip flops have a
clock input and 2 outputs. The figure below show a generic logic symbol of a flip flop.

There are 2 basic types of Flip Flops


1) Edge Triggered FF: The output of the flip flop can change only during clock pulse transition.
Clock pulse transition can be positive edge clock transition or negative edge clock transition.
2) Level Sensitive FF: The output of the flip flop can change as long as the clock pulse level is
positive (high) or negative (low).

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 SR (Set and Reset) Flip Flop

S: If active (High) and the clock goes from low to high the output Q will be set to high.
R: If active (High) and the clock goes from low to high the output Q will be reset to low

Logic Symbol Truth Table

Example of operation:

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 D Flip Flop 74LS74

Q = D when the clock goes from low to high (Positive edge transition).

Truth Table
Logic Symbol
The Asynchronous control signals PRE and CLR override the clock and the input D when one of
them is active.
PRE : If active (Low) then Q = High and Q = Low
CLR : If active (Low) then Q = Low and Q = High.

Example of operation:

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 JK Flip Flop 74LS112

Note that the clock is inverted that is when the clock goes from high to low (negative edge transition)
the output will respond to the inputs.
J (Jump): If active (High) and the clock goes from high to low the output Q will be set to high.
K (Kill): If active (High) and the clock goes from high to low the output Q will be reset to low.

Logic Symbol Truth Table


The Asynchronous control signals PRE and CLR override the clock and the J and K inputs when
one of them is active.
PRE :If active (Low) then Q = High and Q = Low
CLR : If active (Low) then Q = Low and Q = High.

Example of operation:

Example of operation with PRE and CLR :


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 Applications of Flip Flop
 2-bit asynchronous counter: It is asynchronous counter beacuase the FF-B clock is controlled by
FF-A output QA and not by the clock (CLK) so the output QA is the clock for FF-B. The outputs
QA and QB will go from 00 to 11 with QA being the LSB and QB being the MSB.

 4-bit asynchronous counter: The outputs Q0 , Q1 , Q2 , and Q3 will go from 0000 (010) to 1111
(1510) with Q0 being the LSB and Q3 being the MSB.

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 2-bit synchronous counter: It is synchronous counter beacuase both flip flops are clocked by a
single clock (CLK) and both flip flops will respond to the input at the same time instance. The
outputs Q0 and Q1 will go from 00 to 11 with Q0 being the LSB and Q1 being the MSB.

 4-bit asynchronous counter: The outputs Q0 , Q1 , Q2 , and Q3 will go from 0000 (010) to 1111
(1510) with Q0 being the LSB and Q3 being the MSB.

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 Flip Flop Data Sheets

D Flip Flop 74LS74

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JK Flip Flop 74LS112

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