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Flip Flops
RS Flip Flop
D Flip Flop
J-K Flip Flop
S: If active (High) and the clock goes from low to high the output Q will be set to high.
R: If active (High) and the clock goes from low to high the output Q will be reset to low
Example of operation:
Q = D when the clock goes from low to high (Positive edge transition).
Truth Table
Logic Symbol
The Asynchronous control signals PRE and CLR override the clock and the input D when one of
them is active.
PRE : If active (Low) then Q = High and Q = Low
CLR : If active (Low) then Q = Low and Q = High.
Example of operation:
Note that the clock is inverted that is when the clock goes from high to low (negative edge transition)
the output will respond to the inputs.
J (Jump): If active (High) and the clock goes from high to low the output Q will be set to high.
K (Kill): If active (High) and the clock goes from high to low the output Q will be reset to low.
Example of operation:
4-bit asynchronous counter: The outputs Q0 , Q1 , Q2 , and Q3 will go from 0000 (010) to 1111
(1510) with Q0 being the LSB and Q3 being the MSB.
4-bit asynchronous counter: The outputs Q0 , Q1 , Q2 , and Q3 will go from 0000 (010) to 1111
(1510) with Q0 being the LSB and Q3 being the MSB.