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8 7 6 5 4 3 2 1

CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
A 0004536627 PRODUCTION RELEASED 2015-07-21

D D

N71 MLB "DARWIN"


LAST_MODIFICATION=Tue Aug 28 14:17:32 2015

PAGE <CSA> CONTENTS SYNC DATE PAGE <CSA> CONTENTS SYNC DATE
1 1 TABLE OF CONTENTS 31 47 I/O:DOCK FLEX B2B
2 3 SYSTEM:BOM TABLES 32 49 I/O:BUTTON FLEX B2B
3 4 SYSTEM:N71 SPECIFIC 33 BASEBAND:RADIO SYMBOL
C 34 page1
C
4 6 SYSTEM:MECHANICAL
5 7 SOC:JTAG,USB,XTAL 35 ELNA & UAT ANT FEED
6 8 SOC:PCIE 36 FE: ANT CONNECTORS AND UAT TUNER
7 9 SOC:CAMERA & DISPLAY 37 WLAN LAT 2.4GHZ BAW BPF
8 10 SOC:SERIAL & GPIO 38 DEBUG CONN & TEST POINTS
9 11 SOC:OWL 39 CELLULAR BASEBAND: POWER1
10 12 SOC:POWER (1/3) 40 CELLULAR BASEBAND: POWER2
11 13 SOC:POWER (2/3) 41 CELLULAR BASEBAND: CONTROL AND INTERFACES
12 15 SOC:POWER (3/3) 42 CELLULAR BASEBAND: GPIOS
13 20 NAND 43 CELLULAR PMU: CONTROL AND CLOCKS
14 21 SYSTEM POWER:PMU (1/3) 44 CELLULAR PMU: SWITCHERS AND LDOS
15 22 SYSTEM POWER:PMU (2/3) 45 CELLULAR PMU: ET MODULATOR
16 23 SYSTEM POWER:PMU (3/3) 46 CELLULAR TRANSCEIVER: POWER
17 24 SYSTEM POWER:CHARGER 47 CELLULAR TRANSCEIVER: PRX PORTS
18 30 SYSTEM POWER:BATTERY CONN 48 CELLULAR TRANSCEIVER: DRX/GPS PORTS
19 31 SENSORS:MOTION SENSORS 49 CELLULAR TRANSCEIVER: TX PORTS
20 32 CAMERA:FOREHEAD FLEX B2B 50 CELLULAR FRONT END: LB PAD
B 21 33 CAMERA:REAR CAMERA B2B 51 CELLULAR FRONT END: MB PAD B
22 35 CAMERA:STROBE DRIVER 52 CELLULAR FRONT END: HB PAD
23 36 AUDIO:CALTRA CODEC (1/2) 53 CELLULAR FRONT END: 2G PA
24 37 AUDIO:CALTRA CODEC (2/2) 54 CELLULAR FRONT END: LB ASM
25 38 AUDIO:SPEAKER DRIVER 55 CELLULAR FRONT END: MB-HB ASM
26 40 AUDIO:ARC DRIVER 56 CELLULAR FRONT END: DIVERSITY
27 41 DISPLAY:POWER 57 SIM
28 42 TOUCH:ORB & MESA B2B 58 WIFI/BT: WIFI/BT MODULE
29 45 DISPLAY:KEPLER B2B STOCKHOLM 59
30 46 I/O:TRISTAR 2
TABLE

BOM 639-00263 (BETTER,DB30) BOM 639-01058 (SUPREME,B30)


A TABLE OF CONTENTS A
BOM 639-00265 (ULTRA,DB30) BOM 639-01098 (BETTER,DB30C) DRAWING TITLE
SCHEM,SINGLE,BRD,N71
SCH 051-1902 BOM 639-00266 (SUPREME,DB30) BOM 639-01100 (ULTRA,DB30C) DRAWING NUMBER
051-1902
SIZE
D
Apple Inc.
BRD 820-5507 BOM 639-01056 (BETTER,B30) BOM 639-01099 (SUPREME,DB30C) R

NOTICE OF PROPRIETARY PROPERTY:


REVISION

BRANCH
A.0.0

MCO 056-01060 BOM 639-01057 (ULTRA,B30) BOM 939-01627 (BETTER,DARWIN) THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
PAGE
1 OF 49
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SCHEMATIC & PCB BOM CALLOUTS TABLE_5_HEAD


ALTERNATE BOM OPTIONS TABLE_A T_HEAD
SOC/PMU SUB BOMS TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM
PART NUMBER TABLE_5_ITEM

D 051-1902 1 SCH,SINGLE_BRD,N71 SCH CRITICAL ?


TABLE_5_ITEM
138S00032 138S0831 ALTERNATE C0610 TY,2.2UF,0201
TABLE_A T_ITEM

NOT ALL REFERENCE DESIGNATORS LISTED.


USED ~116 TIMES IN DESIGN.
685-00069 1 SUBBOM,SINGLE,BRD,MAUI,N71 SUBBOM_SOC COMMON
TABLE_5_ITEM
D
820-5507 1 PCBF,SINGLE_BRD,N71 PCB CRITICAL ? TABLE_A T_ITEM

338S00120 1 IC,PMU,ANTIGUA,A0,D2255A1,OTP-AL,WLCSP380 U2000 MAUI


TABLE_5_ITEM
138S00049 138S0831 ALTERNATE C0610 KYOCERA,2.2UF,0201 USED ~116 TIMES IN DESIGN. TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-00263 EEEE_G2KM CRITICAL EEEE_16G_DB30 TABLE_A T_ITEM

118S0631 1 RES,MF,100 OHM,1%,1/32W,01005 R0730 MAUI


TABLE_5_ITEM
155S0660 155S0513 ALTERNATE FL3100 MURATA,FERR,22-OHM USED ~7 TIMES IN DESIGN. TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-00265 EEEE_G2KN CRITICAL EEEE_64G_DB30 TABLE_A T_ITEM

131S0307 1 CAP,CER,NP0/C0G,100PF,5%,16V,01005 C0730 MAUI


TABLE_5_ITEM
138S00005 138S00003 ALTERNATE C2000 TY,15UF,0402 USED ~63 TIMES IN DESIGN. TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-00266 EEEE_G2KL CRITICAL EEEE_128G_DB30 TABLE_A T_ITEM

339S00112 1 PROD FUSED, H DRAM U0600 MAUI


TABLE_5_ITEM
138S00048 138S00003 ALTERNATE C2000 KYOCERA,15UF,0402 USED ~63 TIMES IN DESIGN. TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-01056 EEEE_GKF9 CRITICAL EEEE_16G_B30 TABLE_A T_ITEM

117S0161 1 RES,MF,0 OHM,1/32W,01005 R0651 MAUI


TABLE_5_ITEM
138S0702 138S0657 ALTERNATE C2111 MURATA,4.3UF,0610 USED ~3 TIMES IN DESIGN.
825-6838 1 EEEE CODE FOR 639-01057 EEEE_GKFC CRITICAL EEEE_64G_B30 TABLE_A T_ITEM

TABLE_5_ITEM
118S0764 118S0717 ALTERNATE R2250 PANASONIC,3.92K-OHM,0201
TABLE_5_HEAD

825-6838 1 EEEE CODE FOR 639-01058 EEEE_GKF8 CRITICAL EEEE_128G_B30 TABLE_A T_ITEM

USED ~19 TIMES IN DESIGN. PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM
138S00006 138S0835 ALTERNATE C1106 TY,4.3UF,0402 TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-01098 EEEE_GLHL CRITICAL EEEE_16G_DB30C TABLE_A T_ITEM

338S00122 1 IC,PMU,ANTIGUA,D2255A1,OTP-ZL,WLCSP380 U2000 MALTA


TABLE_5_ITEM
152S2052 152S1929 ALTERNATE L2060 CYNTEC,1UH,1608 TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-01100 EEEE_GLHR CRITICAL EEEE_64G_DB30C TABLE_A T_ITEM

118S00009 1 RES,MF,3.01KOHM,1%,1/32W,01005 R0730 MALTA


TABLE_5_ITEM
155S0773 155S0453 ALTERNATE FL3110 TY,FERR,120-OHM,01005 USED ~61 TIMES IN DESIGN. TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 639-01099 EEEE_GLHM CRITICAL EEEE_128G_DB30C TABLE_A T_ITEM

131S0307 1 CAP,CER,NP0/C0G,100PF,5%,16V,01005 C0730 NOSTUFF


TABLE_5_ITEM
377S0168 377S0140 ALTERNATE DZ3150 TDK,VARISTOR,6.8V,100PF,01005 USED ~9 TIMES IN DESIGN. TABLE_5_ITEM

825-6838 1 EEEE CODE FOR 939-01627 EEEE_GR09 CRITICAL EEEE_16G_DARWIN TABLE_A T_ITEM

339S00124 1 M DEV FUSED, M DRAM U0600 MALTA


155S00067 155S0581 ALTERNATE FL4200 TDK,FERR,240-OHM,0201 USED ~8 TIMES IN DESIGN. TABLE_5_ITEM

TABLE_A T_ITEM

118S00025 1 RES,MF,330 OHM,1%,1/32W,01005 R0651 MALTA


155S00012 155S00009 ALTERNATE L3100 MURATA,CHOKE,65-OHM,0605 USED ~11 TIMES IN DESIGN.
TABLE_A T_ITEM

138S0706 138S0739 ALTERNATE C3302_RF USED ~17 TIMES IN DESIGN.


S3E NAND BOM OPTIONS 138S0945 138S0739 ALTERNATE C3302_RF
MURATA,CAP,CER,1UF,20%,10V,X5R,0201

KYOCERA,CAP,CER,1UF,20%,10V,X5R,0201
TABLE_A T_ITEM

USED ~17 TIMES IN DESIGN.


PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS:
TAB E_ALT_HE D

T BLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_A T_ITEM TAB E_ALT_IT M

T BLE_5_ITEM
155S00095 155S00068 ALTERNATE FL1280 FERR BD,100 OHM,25%,100MA,2 OHM,01005 685-00070 685-00069 ALTERNATE SUBBOM_SOC SUBBOM,SINGLE,BRD,MALTA,N71

335S00039 1 NAND,1YNM,16GX8,S3E,64G,T,SLGA70 U1500 CRITICAL NAND_16G TABLE_A T_ITEM

T BLE_5_ITEM
138S0648 138S0652 ALTERNATE C3650 TY,4.7UF,0402 USED ~12 TIMES IN DESIGN.
335S00075 1 NAND,1YNM,64GX8,S3E,MLB,64G,H,SLGA70 U1500 CRITICAL NAND_64G TABLE_A T_ITEM

132S0400 132S0436 ALTERNATE C1280 CAP,CER,X5R,0.22UF,20%,6.3v,01005 USED ~2 TIMES IN DESIGN.


C 335S00079 1 NAND,1YNM,128GX8,S3E,TLC,128G,H,SLGA70 U1500 CRITICAL NAND_128G
T BLE_5_ITEM

155S0960 155S0941 ALTERNATE FL3151 FEER BD,70 OHM,25%,300MA,0.4 DCR,01005


TABLE_A T_ITEM

USED ~9 TIMES IN DESIGN. SOC ALTERNATES C


TABLE_A T_ITEM TAB E_ALT_HE D

138S00024 138S0986 ALTERNATE C1107 CAP,CER,3-TERM,7.5UF,20%,4V,0402 USED ~7 TIMES IN DESIGN. PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD

TABLE_A T_ITEM
PART NUMBER
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 335S00066 335S0946 ALTERNATE U0900 IC,EEPROM,16KX8,1.8V,I2C,WLCSP4
TAB E_ALT_IT M

PART NUMBER 339S00113 339S00112 MAUI U0600 PROD FUSED, M DRAM


TABLE_A T_ITEM

TABLE_ALT_ITEM

335S00074 335S00039 NAND_16G U1500 HYNIX 16G SLGA70 C DIE


155S0653 155S0511 ALTERNATE FL4600 FERR BD,33 OHM,25%,750MA,0.09DCR,0201
USED ~4 TIMES IN DESIGN.
TAB E_ALT_IT M

339S00114 339S00112 MAUI U0600 PROD FUSED, S DRAM


TABLE_ALT_ITEM

335S00078 335S00075 NAND_64G U1500 HYNIX 64G SLGA70


TABLE_ALT_ITEM TAB E_ALT_IT M

335S00064 335S00075 NAND_64G U1500 SANDISK 64G SLGA70 1Z 339S00125 339S00124 MALTA U0600

335S00065 335S00079 NAND_128G U1500 SANDISK 128G SLGA70


TABLE_ALT_ITEM POWER INDUCTOR ALTERNATES 339S00126 339S00124 MALTA U0600
M PROD FUSED, H DRAM, ATK

M PROD FUSED, S DRAM, ATK


TAB E_ALT_IT M

TAB E_ALT_HE D

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: TAB E_ALT_IT M

PART NUMBER 339S00127 339S00124 MALTA U0600 M PROD FUSED, M DRAM, SCK
TAB E_ALT_IT M TAB E_ALT_IT M

152S00120 152S00077 ALTERNATE L2070 TAIYO 2016 1.0UH 0.65MM 339S00128 339S00124 MALTA U0600 M PROD FUSED, H DRAM, SCK

CARBON/ACCEL BOM OPTIONS


TAB E_ALT_IT M TAB E_ALT_IT M

152S00118 152S00075 ALTERNATE L3700 TAIYO 2016 1.2UH 339S00129 339S00124 MALTA U0600 M PROD FUSED, S DRAM, SCK

T BLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


T BLE_5_ITEM

338S1163 1 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U3030 NOSTUFF

117S0202 1 RES,MF,20 OHM,5%,1/32W,01005 R3030 NOSTUFF


T BLE_5_ITEM

ACTIVE DIODE ALTERNATE INDUCTOR SUB BOMS


TAB E_ALT_HE D

T BLE_5_ITEM

117S0202 1 RES,MF,20 OHM,5%,1/32W,01005 R3031 NOSTUFF PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: TABLE_5_HEAD

PART NUMBER PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


T BLE_5_ITEM

TAB E_ALT_IT M TABLE_5_ITEM

117S0202 1 RES,MF,20 OHM,5%,1/32W,01005 R3032 NOSTUFF 376S00106 376S00047 ALTERNATE Q2300 DIODES INC. ACT DIODE 685-00081 1 SUBBOM,SINGLE,BRD,CYNTEC,N71 SUBBOM_IND COMMON
T BLE_5_ITEM

TABLE_5_ITEM

138S0831 1 CAP,CER,X5R,2.2UF,20%,6.3V,0201 C3031 NOSTUFF 152S00074 6 IND,PWR,SHLD,1.0UH,3.6A,0.060 OHM,2016 L2000,L2002,L2010,L2012,L2020,L2030 CYNTEC


T BLE_5_ITEM

TABLE_5_ITEM

132S0316 1 CAP,CER,X5R,0.1UF,20%,6.3V,01005 C3032 NOSTUFF 152S00074 5 IND,PWR,SHLD,1.0UH,3.6A,0.060 OHM,2016 L2040,L2050,L2300,L3300,L4021 CYNTEC


B 338S00017 1 IC,CARBON,MPU-6700-12,LGA16 U3010 INVENSENSE_CARBON
T BLE_5_ITEM

T BLE_5_ITEM
SHIELD PART NUMBERS 152S00081 6 IND,PWR,SHLD,0.47UH,3.8A,0.048 OHM,2012 L2001,L2003,L2011,L2013,L2021,L2041 CYNTEC
TABLE_5_ITEM

B
TABLE_5_HEAD

338S1163 1 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U3030 INVENSENSE_CARBON REFERENCE DESIGNATOR(S) BOM PART#


OPTION QTY DESCRIPTION
T BLE_5_ITEM

TABLE_5_ITEM TABLE_5_HEAD

117S0202 1 RES,MF,20 OHM,5%,1/32W,01005 R3030 INVENSENSE_CARBON 806-02895 1 SHIELD,EMI,UPPER FRONT,WTOP,N71 SH0500 COMMON PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
T BLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

117S0202 1 RES,MF,20 OHM,5%,1/32W,01005 R3031 INVENSENSE_CARBON 806-04588 1 SHIELD,EMI,LOWER FRONT,CLOSED,NOMU,N71 SH0501 COMMON 152S00117 6 IND,PWR,SHLD,1.0UH,3.6A,0.060 OHM,2016 L2000,L2002,L2010,L2012,L2020,L2030 TAIYO
T BLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

117S0202 1 RES,MF,20 OHM,5%,1/32W,01005 R3032 INVENSENSE_CARBON 806-03994 1 SHIELD,EMI,SA,OPEN,N71 SH0502 COMMON 152S00117 5 IND,PWR,SHLD,1.0UH,3.6A,0.060 OHM,2016 L2040,L2050,L2300,L3300,L4021 TAIYO
T BLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

138S0831 1 CAP,CER,X5R,2.2UF,20%,6.3V,0201 C3031 INVENSENSE_CARBON 806-02897 1 SHIELD,EMI,UPPER BACK,WTOP,N71 SH0503 COMMON 152S00121 6 IND,PWR,SHLD,0.47UH,3.8A,0.048 OHM,2012 L2001,L2003,L2011,L2013,L2021,L2041 TAIYO
T BLE_5_ITEM

TABLE_5_ITEM

132S0316 1 CAP,CER,X5R,0.1UF,20%,6.3V,01005 C3032 INVENSENSE_CARBON 806-02898 1 SHIELD,EMI,LOWER BACK,WTOP,N71 SH0504 COMMON


T BLE_5_ITEM

TAB E_ALT_HE D

338S00087 1 IC,CARBON 1.1,MPU-6800-00,LGA16 U3010 INVENSENSE_STANDALONE_CARBON


PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TAB E_ALT_IT M

685-00080 685-00081 ALTERNATE SUBBOM_IND SUBBOM,SINGLE,BRD,TAIYO,N71

A A
PAGE TITLE

SYSTEM:BOM TABLES
DRAWING NUMBER SIZE

Apple Inc. 051-1902 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TESTPOINTS N71 I2C DEVICE MAP


I2C BUS DEVICE BINARY 7-BIT HEX 8-BIT HEX

I2C0 ANTIGUA PMU 1110100X 0X74 0XE8


POWER AMUX CHESTNUT 0100111X 0X27 0X4E

D VOLTAGE=0V
TP00
1
A POWER GROUND 16 PMU_AMUX_AY TP16
1
A
MUON 1100010X 0X62 0XC4 D
TP-P6 TP-P55
ROOM=TEST ROOM=TEST
I2C1 TIGRIS 1110101X 0X75 0XEA
PP5V0_USB TP01
1 PMU_AMUX_BY TP17
1 ARC DRIVER 1000001X 0X41 0X82
31 30 17 A VBUS 16 A
TP-P6 TP-P55
ROOM=TEST ROOM=TEST SPEAKER AMP 1000000X 0X40 0X80

18 17 PP_BATT_VCC TP02
1
A
MOJAVE TRISTAR 0011010X 0X1A 0X34
TP-P6
ROOM=TEST
VBATT MESA_TO_BOOST_EN TP18
1 I2C2 ALS 0101001X 0X29 0X52
TP03
1
28 27 A
A TP-P55
TP-P6 ROOM=TEST DISP EEPROM 1010001X 0X51 0XA2
ROOM=TEST

PP16V5_MESA TP19
1
28 27 A
TP-P55
OWL UNUSED N/A N/A N/A
TP05
1
ROOM=TEST
A
TP-P55
ROOM=TEST LCM ISP I2C0 REAR CAM TBD TBD TBD

TP20 LED DRIVER 1100011X 0X63 0XC6


29 PP_LCM_BL_CAT1_CONN 1
A
TP-P55
ROOM=TEST

RESET 29 PP_LCM_BL_CAT2_CONN TP21


1
A
ISP I2C1 FRONT CAM 0010000X 0X10 0X20

TP-P55
PMU_TO_SYSTEM_COLD_RESET_L TP06
1 SOC & BB RESET ROOM=TEST TOUCH I2C MESON 1000000X 0x40 0x80
A
C
33 16 9 5
TP-P55
ROOM=TEST TP22 MAMBA 1100000X 0x60 0xC0 C
29 PP_LCM_BL_ANODE_CONN 1
A
TP-P55 DOPPLER 1011000X 0x58 0xB0
DFU ROOM=TEST

SEP I2C SEP EEPROM 1010001X 0x51 0xA2


33 8 FORCE_DFU TP07
1
TP-P55
A
FORCE DFU PROCEDURE: SUPER SCREW
ROOM=TEST 1. FROM OFF MODE SHORT TP07 TO PP07
2. PLUG IN E75 CABLE TO FORCE DFU TP23
1
PP07
P4MM-NSM
A
SM
TP-P80
PP1V8 1
21 20 17 14 13 12 9 8 7 6 5 3
33 29 PP
ROOM=TEST
ROOM=TEST
BOOTSTRAPPING:BOARD REV
PP08
33 8 DFU_STATUS
P4MM-NSM
1
SM
PP
BOARD ID
ROOM=TEST
BOOT CONFIG
E75
TP08 8 OUT BOARD_REV3 R0400 1ROOM=SOC 2 1.00K PP1V8 3 5 6 7 8 9 12 13 14 17 20 21
31 30 TRISTAR_DP1_CONN_P 1
A 01005 MF 5% 1/32W 29 33

TP-P55 NOSTUFF
ROOM=TEST
TRISTAR USB 8 OUT BOARD_REV2 R0401 1ROOM=SOC 2 1.00K
01005 MF 5% 1/32W
TRISTAR_DP1_CONN_N TP09
1 NOSTUFF
31 30 A
TP-P55 BOARD_REV1 R0402 1ROOM=SOC 2 1.00K
B ROOM=TEST
8 OUT
01005 MF 5% 1/32W B
TRISTAR_DP2_CONN_P TP10
1 BOARD_REV[3:0]
31 30
TP-P55
A 8 OUT BOARD_REV0 R0403 1ROOM=SOC 2 1.00K FLOAT=LOW, PULLUP=HIGH
01005 MF 5% 1/32W 1111 PROTO1
ROOM=TEST TRISTAR DEBUG UART 1110 PROTO2

TRISTAR_DP2_CONN_N TP11
1
1101
1100
EVT
EVT DOE 3 (MAMBA LDO)
31 30 A NOSTUFF 1011 CARRIER
TP-P55
ROOM=TEST 8 OUT BOARD_ID4 R0404 1ROOM=SOC 2 1.00K 1010 CARRIER 2 (I2C0 SCL)
01005 MF 5% 1/32W SELECTED --> 1001 DVT
PP_TRISTAR_ACC1 TP12
1 NOSTUFF
31 30 A
TP-P55 8 OUT BOARD_ID3 R0405 1ROOM=SOC 2 1.00K BOARD_ID[4:0]
ROOM=TEST 01005 MF 1/32W FLOAT=LOW, PULLUP=HIGH
TRISTAR ACCESSORY ID 5%

PP_TRISTAR_ACC2 TP13
1 ACCESSORY POWER SELECTED --> 00100 N71 MLB
31 30
TP-P55
A 8 OUT BOARD_ID2 R0406 1ROOM=SOC 2 1.00K 00101 N71
00110 N66
DEV
MLB
01005 MF 5% 1/32W
ROOM=TEST
NOSTUFF BOOT_CONFIG[2:0]
TP14
1 BOARD_ID1 R0407 1ROOM=SOC 2 1.00K FLOAT=LOW, PULLUP=HIGH
A 8 OUT
01005 MF 1/32W
TP-P55 5% 000 SPI0
ROOM=TEST 001 SPI0 TEST MODE
NOSTUFF SELECTED --> 010 NVME0 x2 MODE
8 OUT BOARD_ID0 R0408 1ROOM=SOC 2 1.00K 011 NVME0 x2 TEST MODE
01005 MF 1/32W
TRISTAR_CON_DETECT_L TP15
1
5% 100
101
NVME0 x1 MODE
NVME0 x1 TEST MODE
31 30 A
TP-P55 110 SLOW SPI0 TEST MODE
ROOM=TEST 111 FAST SPI0 TEST MODE
NOSTUFF
8 OUT BOOT_CONFIG2 R0409 1ROOM=SOC 2 1.00K
01005 MF 5% 1/32W
A ROOM=SOC
A
8 OUT BOOT_CONFIG1 R0410 1 2 1.00K PAGE TITLE
01005 MF 5% 1/32W
SYSTEM:N71 SPECIFIC
NOSTUFF DRAWING NUMBER SIZE
8 BOOT_CONFIG0 R0411 1ROOM=SOC 2 1.00K 051-1902 D
OUT
01005 MF 5% 1/32W Apple Inc. REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
RESISTOR STUFF = HIGH '1' THE INFORMATION CONTAINED HEREIN IS THE
RESISTOR NOSTUFF = LOW '0' PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PENINSULA STANDOFFS
BS0506 BS0507
STDOFF-2.2OD0.25H-0.50-1.70
ROOM=ASSEMBLY

1 1
STDOFF-2.6OD0.5H-0.5-1.7-TH
ROOM=ASSEMBLY
860-8396
50_AP_UAT_FEED 33
TOP-SIDE BOTTOM-SIDE
860-7846 50_AP_WIFI_5G_CONN_ANT 33
STOCKHOLM FEED FIDUCIALS
1 NORTH_AC_GND_SCREW BS0505
4
STDOFF-2.56OD1.4ID.99H-SM FD0501
806-02971 FID
D BS0508
ROOM=ASSEMBLY 0P5SM1P0SQ-NSP
1
D
2.7X1.94X0.25 ROOM=ASSEMBLY
RING-TH1 860-00109
ROOM=ASSEMBLY 1 FD0502
AP_TO_STOCKHOLM_ANT FID
SHIM WASHER 33 0P5SM1P0SQ-NSP
1
ROOM=ASSEMBLY

1 BS0503 FD0503
FID
STDOFF-2.6OD0.81H-TH 0P5SM1P0SQ-NSP
ROOM=ASSEMBLY 1
860-00096
ROOM=ASSEMBLY
FD0505
FID
0P5SM1P0SQ-NSP
1
ROOM=ASSEMBLY

FD0510
FID
0P5SQ-SMP3SQ-NSP
1

BS0501 1 1
BS0502
ROOM=ASSEMBLY
STDOFF-2.85OD1.4ID-0.84H
ROOM=ASSEMBLY STDOFF-2.85OD1.4ID-0.84H FD0511
860-00111 860-00111 ROOM=ASSEMBLY FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
PLATED SLOTTED THRU-HOLE FD0512
CL0502 FID
C TH-NSP 0P5SQ-SMP3SQ-NSP
1
C
SOUTH DC CURRENT BLOCKING CAPS 1
SL-1.20X0.40-1.50X0.70-NSP ROOM=ASSEMBLY

SOUTH_AC_GND_SCREW FD0514
4 32
UPPER SHIELD FID
0P5SQ-SMP3SQ-NSP
OMIT_TABLE 1
1 C0540 1 C0541 1 C0542 1 C0543 UPPER SHIELD 1 ROOM=ASSEMBLY
220PF 100PF 56PF 4.7PF OMIT_TABLE SH0503 FD0515
10% 5% 5% +/-0.1PF
2 10V
X7R-CERM 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G
SM FID
1 0P5SQ-SMP3SQ-NSP
01005 01005 01005 01005
ROOM=ASSEMBLY ROOM=ASSEMBLY ROOM=ASSEMBLY ROOM=ASSEMBLY SH0500 SHLD-EMI-UPPER-BACK-N61
1
SM ROOM=ASSEMBLY
ROOM=ASSEMBLY

SHLD-EMI-UPPER-FRONT-N61 FD0504
ROOM=ASSEMBLY FID
0P5SM1P0SQ-NSP
1

NORTH DC CURRENT BLOCKING CAPS ROOM=ASSEMBLY

NORTH_AC_GND_SCREW 4

FD0513
1 C0550 1 C0551 1 C0552 1 C0553 CLIP-RETENTION-COAX-DOUBLE FID
220PF 100PF 220PF 100PF 0P5SQ-SMP3SQ-NSP
10%
2 10V
5%
2 16V
10%
2 10V
5%
2 16V DUAL RF COAX CLIP 1 CL0501
SM
32 4 SOUTH_AC_GND_SCREW 1
X7R-CERM NP0-C0G X7R-CERM NP0-C0G ROOM=ASSEMBLY
01005 01005 01005 01005
ROOM=ASSEMBLY ROOM=ASSEMBLY ROOM=ASSEMBLY ROOM=ASSEMBLY ROOM=ASSEMBLY
806-01802
B B

LOWER SHIELD LOWER SHIELD


OMIT_TABLE OMIT_TABLE
1 1
SH0501 SH0504
SM SM

SHLD-EMI-LOWER-FRONT-N61 SHLD-EMI-LOWER-BACK-N61
ROOM=ASSEMBLY ROOM=ASSEMBLY

SA SHIELD
OMIT TABLE
A 1
SH0502 A
SM PAGE TITLE

SYSTEM:MECHANICAL
SHLD-EMI-SA-N71 DRAWING NUMBER SIZE
ROOM=ASSEMBLY
Apple Inc. 051-1902 D
REVISION
SOUTH TUBE STANDOFF R
A.0.0
BS0500 NOTICE OF PROPRIETARY PROPERTY: BRANCH
STDOFF-2.70OD1.84ID-0.88H-TH THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
1 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
860-7862 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 5 OF 49
TODO:UPDATE REF DES ROOM=ASSEMBLY
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 4 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MAUI - USB, JTAG, XTAL

D VDD12_PLL_LPDP:1.14-1.26V @2mA MAX


D
VDD12_PLL_SOC: 1.14-1.26V @12mA MAX
VDD12_PLL_CPU: 1.14-1.26V @2mA MAX
VDD18_USB: 1.71-1.89V @20mA MAX
R0600 VDD18_XTAL:1.62-1.98V @2mA MAX
PP1V2 1
0.00 2 PP1V2_PLL PP1V8
15 7 6 3 6 7 8 9 12 13 14 17 20 21 29
VOLTAGE=1.2V 33
0%
1/32W
MF 1 C0600 1 C0601 1 C0602 1 C0603 1 C0612 FL0610
01005 1KOHM-25%-0.2A
ROOM=SOC 0.1UF 0.1UF 0.01UF 0.01UF 0.1UF
20% 20% 10% 10% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V PP1V8_XTAL 1 2
X5R-CERM X5R-CERM X5R X5R X5R-CERM VOLTAGE=1.8V
01005 01005 01005 01005 01005 0201
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC 1 C0611 1 C0610 ROOM=SOC

0.1UF 2.2UF
20% 20%
2 6.3V 2 6.3V
X5R-CERM
X5R-CERM 0201
01005 ROOM=SOC
ROOM=SOC

PP3V3_USB 15

NOTE:LPDP RECEIVES UNFILTERED 1.2V CKPLUS_WAIVE=PWRTERM2GND

AS IT IS UNUSED 1 C0620 VDD33_USB:3.14-3.46V @5mA MAX

VDD12_UH1_HSIC0 AP21

VDD12_PLL_CPU AF13

VDD18_USB AL21

VDD33_USB AN20

VDD18_XTAL AL34
0.1UF

VDD12_UH2_HSIC1 C15

VDD12_PLL_LPDP F22
U20
T19
W19
20%
6.3V
2 X5R-CERM
01005

VDD12_PLL_SOC
ROOM=SOC

C C
OMIT_TABLE
CRITICAL
U0600
MAUI-2GB-25NM-DDR-H
AN22 UH1_HSIC0_DATA FCMSP ANALOGMUX_OUT AP24 AP_TO_PMU_AMUX_OUT
NC OUT 16
AN21 UH1_HSIC0_STB SC58980B0B-A040
NC
SYM 1 OF 14 P3MM-NSM
SM
C16 1
NC
D15
UH2_HSIC1_DATA ROOM=SOC PP PP0600
NC UH2_HSIC1_STB ROOM=SOC
USB_D_P AT20 USB_AP_DATA_P BI 30
Y32 JTAG_SEL USB_D_N AT19 USB_AP_DATA_N 30
BI
P3MM-NSM
SM
AC32 1
NC
AB31
JTAG_TRST* PP PP0601
NC JTAG_TDO ROOM=SOC
AA32 JTAG_TDI USB_VBUS AP19 USB_VBUS_DETECT
NC IN 17

30 SWD_DOCK_BI_AP_SWDIO AB32 JTAG_TMS


BI
30 SWD_DOCK_TO_AP_SWCLK AA31 JTAG_TCK USB_ID AR19NC
IN

33 16 9 3 PMU_TO_SYSTEM_COLD_RESET_L AC31 COLD_RESET*


IN
H33 USB_REXT AP18 USB_REXT
30 27 16 9 IN PMU_TO_OWL_ACTIVE_READY CFSB
1
ROOM=SOC
P3MM-NSM 16 OUT AP_TO_PMU_TEST_CLKOUT AR23 TST_CLKOUT R0640
SM 200
1 1%
PP0610 PP 1/32W
MF
AP_TO_NAND_RESET_L AN23
B 13 OUT S3E_RESET* 2 01005
ROOM=SOC B
WDOG H32 HOLD_RESET 16 Y33 AP_TO_PMU_WDOG_RESET OUT
AF6 TESTMODE
AL22 FUSE1_FSRC XI0 AK35 XTAL_AP_24M_IN
AG25 FUSE2_FSRC XO0 AL35 XTAL_AP_24M_OUT 1
R0650 CRITICAL
511K ROOM=SOC
1%
1/32W OMIT_TABLE Y0600
1.60X1.20MM-SM
MF
2 01005
R0651 24.000MHZ-30PPM-9.5PF-60OHM
ROOM=SOC
1
0.00 2 SOC_24M_O 1 3
0%
1/32W 2 4
MF
01005
1 C0650 1 C0651
ROOM=SOC 12PF 12PF
5% 5%
2 16V
CERM 2 16V
01005
ROOM=SOC
CERM
01005 XW0650
SHORT-10L-0.1MM-SM
ROOM=SOC 1 2
AP_XTAL_GND
VOLTAGE=0.0V
ROOM=SOC

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC:JTAG,USB,XTAL
DRAWING NUMBER SIZE

Apple Inc. 051-1902 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 5 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MAUI - PCIE INTERFACES


VDD12_PCIE_REFBUF:1.08-1.26V @50mA MAX
VDD12_PCIE_TXPLL: 1.08-1.32V @10mA MAX
VDD12_PCIE: 1.14-1.26V @115mA MAX
XW TO ISOLATE C0442,3 FROM C0740,1.
XW0740 VDD085_PCIE:0.802-TBDV @TBDmA MAX
D 15 7 5 PP1V2
SHORT-10L-0.1MM-SM
1 2 PP1V2_XW
VOLTAGE=1.2V
PP_FIXED 7 11 14
D
ROOM=SOC
1 C0740 1 C0741 1 C0742 1 C0743 1 C0752 1 C0751 1 C0750
2.2UF 1.0UF 0.1UF 0.1UF 0.1UF 1.0UF 2.2UF
20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R 2 6.3V
X5R-CERM
0201 0201-1 01005 01005 01005 0201-1 0201

AK28
AK25
AL24
AL27

VDD12_PCIE_TXPLL AL26

VDD12_PCIE_REFBUF AJ26

AH28
AJ25
AL23
AJ29
AL29
AJ24
AK27
AJ27
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

VDD12_PCIE

VDD085_PCIE
1 C0731
0.1UF
20%
2 6.3V
X5R-CERM
01005
ROOM=SOC

PCIE_EXT_C AP29 PCIE_EXT_C


OMIT_TABLE
C0701 1 2 0.1UF
13 IN PCIE_NAND_TO_AP_RXD0_P ROOM=SOC 20% X5R-CERM PCIE_NAND_TO_AP_RXD0_C_P AM30 PCIE_RX0_P CRITICAL PCIE_REF_CLK0_P AN35 PCIE_AP_TO_NAND_REFCLK_P OUT 13
6.3V 01005
PCIE_NAND_TO_AP_RXD0_N PCIE_NAND_TO_AP_RXD0_C_N AN30 PCIE_RX0_N AP35 PCIE_AP_TO_NAND_REFCLK_N
13 IN
C0702 1 2 0.1UF U0600 PCIE_REF_CLK0_N OUT 13

ROOM=SOC 20% X5R-CERM MAUI-2GB-25NM-DDR-H


6.3V 01005
FCMSP PCIE_REF_CLK1_P AN34 PCIE_AP_TO_WLAN_REFCLK_P OUT 33

SC58980B0B-A040 PCIE_REF_CLK1_N AP34 PCIE_AP_TO_WLAN_REFCLK_N OUT 33

C0703 1 2 0.1UF SYM 2 OF 14


13 PCIE_AP_TO_NAND_TXD0_P ROOM=SOC 20% X5R-CERM PCIE_AP_TO_NAND_TXD0_C_P AT32 PCIE_TX0_P PCIE_REF_CLK2_P AM32 PCIE_AP_TO_BB_REFCLK_P 33
OUT 6.3V 01005 OUT
AR32 ROOM=SOC
PCIE_REF_CLK2_N AN32
PCIE LINK 0

13 PCIE_AP_TO_NAND_TXD0_N PCIE_AP_TO_NAND_TXD0_C_N PCIE_TX0_N PCIE_AP_TO_BB_REFCLK_N 33


OUT
C0704 1 2 0.1UF OUT
ROOM=SOC 20% X5R-CERM PP1V8 3 5 7 8 9 12 13 14 17 20 21 29
PCIE_REF_CLK3_P AM31NC
6.3V 01005 33
NOSTUFF
C PCIE_REF_CLK3_N AN31NC
1
R0720
100K
1
R0721
100K
1
R0722
100K
C
C0705 1 2 0.1UF 5% 5% 5%
13 PCIE_NAND_TO_AP_RXD1_P ROOM=SOC 20% X5R-CERM PCIE_NAND_TO_AP_RXD1_C_P AM28 PCIE_RX1_P 1/32W 1/32W 1/32W
IN 6.3V 01005 MF MF MF
13 PCIE_NAND_TO_AP_RXD1_N PCIE_NAND_TO_AP_RXD1_C_N AN28 PCIE_RX1_N 2 01005 2 01005 2 01005
IN
C0706 1 2 0.1UF ROOM=SOC ROOM=SOC ROOM=SOC
ROOM=SOC 20% X5R-CERM
6.3V 01005 PCIE_CLKREQ0* AT11 PCIE_NAND_TO_AP_CLKREQ_L 13
BI
PCIE_CLKREQ1* AP12 PCIE_WLAN_TO_AP_CLKREQ_L 33
BI
C0707 1 2 0.1UF PCIE_CLKREQ2* AR12 PCIE_BB_BI_AP_CLKREQ_L BI 33

PCIE_AP_TO_NAND_TXD1_P ROOM=SOC 20% X5R-CERM PCIE_AP_TO_NAND_TXD1_C_P AT31 PCIE_TX1_P PCIE_CLKREQ3* AT12


13 OUT 6.3V 01005 NC
13 PCIE_AP_TO_NAND_TXD1_N PCIE_AP_TO_NAND_TXD1_C_N AR31 PCIE_TX1_N NOTE:CLKREQ_L PULL-UP FOR BB IN RADIO_MLB_MIMO SECTION
OUT
C0708 1 2 0.1UF
ROOM=SOC 20% X5R-CERM
6.3V 01005

C0709 1 2 0.1UF PCIE_PERST0* AR10 PCIE_AP_TO_NAND_RESET_L OUT 13

33 PCIE_WLAN_TO_AP_RXD_P ROOM=SOC 20% X5R-CERM PCIE_WLAN_TO_AP_RXD_C_P AM27 PCIE_RX2_P PCIE_PERST1* AT10 PCIE_AP_TO_WLAN_RESET_L 33
IN 6.3V 01005 OUT
PCIE LINK 1

33 PCIE_WLAN_TO_AP_RXD_N PCIE_WLAN_TO_AP_RXD_C_N AN27 PCIE_RX2_N PCIE_PERST2* AP11 PCIE_AP_TO_BB_RESET_L 33


IN
C0710 1 2 0.1UF
PCIE_PERST3* AR11
OUT
ROOM=SOC 20% X5R-CERM NC
6.3V 01005

C0711 1 2 0.1UF 1 1 1
33 OUT PCIE_AP_TO_WLAN_TXD_P ROOM=SOC 20% X5R-CERM PCIE_AP_TO_WLAN_TXD_C_P AT28 PCIE_TX2_P PCIE_EXT_REF_CLK_P AR33 R0700 R0701 R0702
6.3V 01005
AR28 100K 100K 100K
33 PCIE_AP_TO_WLAN_TXD_N PCIE_AP_TO_WLAN_TXD_C_N PCIE_TX2_N PCIE_EXT_REF_CLK_N AT33 5% 5% 5%
OUT
C0712 1 2 0.1UF 1/32W
MF
1/32W
MF
1/32W
MF
ROOM=SOC 20% X5R-CERM
6.3V 01005 2 01005
ROOM=SOC 2 01005
ROOM=SOC 2 01005
ROOM=SOC

C0715 1 2 0.1UF
B 33 IN PCIE_BB_TO_AP_RXD_P ROOM=SOC 20%
6.3V
X5R-CERM
01005
PCIE_BB_TO_AP_RXD_C_P AM26 PCIE_RX3_P PCIE_RX_TX_BYPASS_CLK_P AT29 B
PCIE LINK 2

33 PCIE_BB_TO_AP_RXD_N PCIE_RX3_N PCIE_BB_TO_AP_RXD_C_N AN26


PCIE_RX_TX_BYPASS_CLK_N AR29
IN
C0716 1 2 0.1UF
ROOM=SOC 20% X5R-CERM
6.3V 01005

C0717 1 2 0.1UF
33 PCIE_AP_TO_BB_TXD_P ROOM=SOC 20% X5R-CERM PCIE_AP_TO_BB_TXD_C_P AT26 PCIE_TX3_P
OUT 6.3V 01005
33 PCIE_AP_TO_BB_TXD_N PCIE_AP_TO_BB_TXD_C_N AR26 PCIE_TX3_N
OUT
C0718 1 2 0.1UF
ROOM=SOC 20% X5R-CERM
6.3V 01005

AM25 PCIE_RX4_P
NC
AN25 PCIE_RX4_N
NC

PCIE_RCAL_P
OMIT_TABLE OMIT_TABLE
1
AR24 PCIE_TX4_P PCIE_RCAL_P AT30
R0730 1 C0730
NC 100 100PF
AT24 PCIE_TX4_N PCIE_RCAL_N AR30 1% 5%
NC 1/32W 2 16V
MF NP0-C0G
2 01005 01005
ROOM=SOC ROOM=SOC
PCIE_RCAL_N

A SYNC MASTER=N/A SYNC_DATE=N/A A


PAGE TITLE

SOC:PCIE
DRAWING NUMBER SIZE

Apple Inc. 051-1902 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 6 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MAUI - CAMERA & DISPLAY INTERFACES

D D

0.756-0.893V @11mA MAX 1.62-1.98V @23mA MAX


14 11 6 PP_FIXED PP1V8 3 5 6 7 8 9 12 13 14 17 20 21
29 33

1 C0814 1 C0801 1 C0802 1 C0815


0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% NOTE:VDD12_LPDP SHOULD BE POWERED
2 6.3V 2 6.3V 2 6.3V 2 6.3V

E10
E13

D13

D10

E11
E14
X5R-CERM X5R-CERM X5R-CERM X5R-CERM

E8

E7
D8
01005 01005 01005 01005 EVEN WHEN LPDP IS NOT USED
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

VDD085_MIPI

VDD18_MIPI
15 6 5 PP1V2

PP1V8 3 5 6 7 8 9 12 13 14 17 20 21

E25
E27
F24
E23
29 33

U0600 1
R0804 1
R0805 1
R0806 1
R0807

VDD12_LPDP
MAUI-2GB-25NM-DDR-H 1.00K 1.00K 1.00K 1.00K
5% 5% 5% 5%
FCMSP 1/32W 1/32W 1/32W 1/32W
MF MF MF MF
SC58980B0B-A040 2 01005 2 01005 2 01005 2 01005
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

C 21

21
IN MIPI_RCAM_TO_AP_DATA0_CONN_P
MIPI_RCAM_TO_AP_DATA0_CONN_N
B8
A8
MIPI0C_DATA0_P
MIPI0C_DATA0_N
SYM 3 OF 14
CRITICAL
ISP_I2C0_SCL G31
ISP_I2C0_SDA G32
I2C_ISP_TO_RCAM_SCL
I2C_ISP_BI_RCAM_SDA
OUT 21 22

21 22
C
IN BI
ROOM=SOC U0600
21 IN MIPI_RCAM_TO_AP_DATA1_CONN_P A9 MIPI0C_DATA1_P ISP_I2C1_SCL F35 I2C_ISP_TO_FCAM_SCL OUT 20
MAUI-2GB-25NM-DDR-H
MIPI_RCAM_TO_AP_DATA1_CONN_N B9 MIPI0C_DATA1_N ISP_I2C1_SDA G34 I2C_ISP_BI_FCAM_SDA A29 LPDP_AUX_P FCMSP
21 IN BI 20
NC
B29 LPDP_AUX_N SC58980B0B-A040
NC
21 MIPI_RCAM_TO_AP_DATA2_CONN_P A13 MIPI0C_DATA2_P SYM 4 OF 14
IN A33 LPDP_TX0_P
21 IN MIPI_RCAM_TO_AP_DATA2_CONN_N B13 MIPI0C_DATA2_N R0808 NC
B33 LPDP_TX0_N
CRITICAL
AP_TO_RCAM_CLK_R 33.2 2 AP_TO_RCAM_CLK NC ROOM=SOC
SENSOR0_CLK D33 1 OUT 21
1% MF 1/32W
21 IN MIPI_RCAM_TO_AP_DATA3_CONN_P B14 MIPI0C_DATA3_P SENSOR0_RST D32 AP_TO_RCAM_SHUTDOWN_L OUT 21 01005
ROOM=SOC NC
A32 LPDP_TX1_P
21 IN MIPI_RCAM_TO_AP_DATA3_CONN_N A14 MIPI0C_DATA3_N R0809 NC
B32 LPDP_TX1_N
AP_TO_FCAM_CLK_R 33.2 2 AP_TO_FCAM_CLK
SENSOR1_CLK F33 1 OUT 20
A31 LPDP_TX2_P
1% MF 1/32W
21 IN MIPI_RCAM_TO_AP_CLK_CONN_P A12 MIPI0C_CLK_P SENSOR1_RST E34 AP_TO_FCAM_SHUTDOWN_L OUT 20 01005 NC
ROOM=SOC B31 LPDP_TX2_N
21 IN MIPI_RCAM_TO_AP_CLK_CONN_N B12 MIPI0C_CLK_N NC
A30 LPDP_TX3_P
RCAM_REXT D12 MIPI0C_REXT NC
SENSOR0_ISTRB D34 NC NC
B30 LPDP_TX3_N
29 OUT MIPI_AP_TO_LCM_DATA0_P A3 MIPID_DATA0_P SENSOR0_XSHUTDOWN F32 AP_TO_STOCKHOLM_DWLD_REQUEST OUT 33
D24
NC LPDP_CAL_DRV_OUT
29 MIPI_AP_TO_LCM_DATA0_N B3 MIPID_DATA0_N
OUT
SENSOR1_ISTRB C35 NC D25
NC LPDP_CAL_VSS_EXT
SENSOR1_XSHUTDOWN C34 AP_TO_MUON_BL_STROBE_EN OUT 27
29 OUT MIPI_AP_TO_LCM_DATA1_P B4 MIPID_DATA1_P AL4
NC EDP_HPD
29 OUT MIPI_AP_TO_LCM_DATA1_N A4 MIPID_DATA1_N MIPICSI_MUXSEL G35 NC
H35 DP_WAKEUP
MIPI1C_REXT D14 FCAM_REXT NC
B6 MIPID_DATA2_P
NC
NC
A6 MIPID_DATA2_N MIPI1C_DATA0_P B17 MIPI_FCAM_TO_AP_DATA0_P IN 20

MIPI1C_DATA0_N A17 MIPI_FCAM_TO_AP_DATA0_N IN 20


A7 MIPID_DATA3_P
NC
B NC
B7 MIPID_DATA3_N MIPI1C_DATA1_P B19
MIPI1C_DATA1_N A19
MIPI_FCAM_TO_AP_DATA1_P
MIPI_FCAM_TO_AP_DATA1_N
IN
IN
20

20
B
29 OUT MIPI_AP_TO_LCM_CLK_P A5 MIPID_CLK_P
29 OUT MIPI_AP_TO_LCM_CLK_N B5 MIPID_CLK_N MIPI1C_CLK_P A18 MIPI_FCAM_TO_AP_CLK_P IN 20

MIPI1C_CLK_N B18 MIPI_FCAM_TO_AP_CLK_N IN 20


LCM_REXT D9 MIPID_REXT

1
R0801 1
R0802 1 R0803
4.02K
4.02K 4.02K 1%
1% 1% 1/32W
1/32W 1/32W MF
MF MF 2 01005
01005 2 01005 2 ROOM=SOC
ROOM=SOC ROOM=SOC

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC:CAMERA & DISPLAY


DRAWING NUMBER SIZE

Apple Inc. 051-1902 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 7 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MAUI - GPIO & SERIAL INTERFACES


PP1V8 3 5 6 7 8 9 12 13 14 17 20 21
29 33

R09001 R09011 R09021 R09031 R09041 R09051


D 1.00K
1%
1/32W
2.2K
5%
1/32W
2.2K
5%
1/32W
2.2K
5%
1/32W
1.33K
1%
1/32W
1.33K
1%
1/32W
D
MF MF MF MF MF MF
01005 2 01005 2 01005 2 01005 2 01005 2 01005 2
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

R0920
I2S_AP_TO_CODEC_MCLK 33.2 2 I2S_AP_TO_CODEC_MCLK_R I2C0_AP_SCL
24 OUT 1 P34 I2S0_MCK I2C0_SCL E31 OUT 8 16 27 33

26 I2S_AP_TO_ARC_MCLK 1% 24 9 I2S_AP_OWL_TO_CODEC_XSP_BCLK R34 I2S0_BCLK


U0600 I2C0_SDA D35 I2C0_AP_SDA 8 16 27 33
OUT 1/32W OUT FCMSP BI
25 OUT I2S_AP_TO_SPEAKERAMP_MCLK MF 24 9 OUT I2S_AP_OWL_TO_CODEC_XSP_LRCLK N34 I2S0_LRCK SC58980B0B-A040
AP_TO_HP_HS3_CTRL C1 01005
31 OUT GPIO_0
U0600 ROOM=SOC 24 9 IN I2S_CODEC_TO_AP_OWL_XSP_DIN N35 I2S0_DIN I2C1_SCL AH1 I2C1_AP_SCL OUT 8 17 25 26 30 33
31 OUT AP_TO_HP_HS4_CTRL D2 GPIO_1 I2S_AP_TO_CODEC_XSP_DOUT M33 I2S0_DOUT I2C1_SDA AG4 I2C1_AP_SDA
MAUI-2GB-25NM-DDR-H 24 OUT BI 8 17 25 26 30 33
33 32 16 IN BUTTON_VOL_UP_L D1 GPIO_2
FCMSP
R0921 SYM 6 OF 14
MAUI-2GB-25NM-DDR-H
BUTTON_VOL_DOWN_L F1 GPIO_3 33.2 2 I2S_AP_TO_ARC_MCLK_R I2C2_AP_SCL
33 32 16 IN
SC58980B0B-A040
1 M4 I2S1_MCK I2C2_SCL L31 OUT 8 20 29
SPEAKERAMP_TO_AP_INT_L E2 GPIO_4 I2S_AP_TO_BT_BCLK M3 CRITICAL I2C2_AP_SDA
25 IN
SYM 5 OF 14
1% 33 OUT I2S1_BCLK ROOM=SOC I2C2_SDA M32 BI 8 20 29
AP_TO_SPEAKERAMP_STAYIN_ALIVE F3 1/32W
25 OUT GPIO_5 TMR32_PWM0 AE1 NC MF 33 I2S_AP_TO_BT_LRCLK P1 I2S1_LRCK
01005 OUT
25 OUT AP_TO_SPEAKERAMP_RESET_L F2 GPIO_6 CRITICAL TMR32_PWM1 AF2 NC ROOM=SOC 33 I2S_BT_TO_AP_DIN N3 I2S1_DIN
PP1V8 3 5 6 7 8 9 12 13 14 17 20 21
IN 29 33
33 OUT AP_TO_BT_WAKE H3 GPIO_7 ROOM=SOC TMR32_PWM2 AF3 NC 33 I2S_AP_TO_BT_DOUT L4 I2S1_DOUT
OUT
33 OUT AP_TO_BB_RESET_L G3 GPIO_8 OMIT_TABLE R0922 R09061 R09071
33 OUT PCIE_AP_TO_WLAN_DEV_WAKE J1 GPIO_9 UART0_RXD AE3 UART_AP_DEBUG_RXD IN 30 33 1
33.2 2 I2S_AP_TO_SPEAKERAMP_MCLK_R U32 2.2K 2.2K
I2S2_MCK 5% 5%
22 OUT AP_TO_LED_DRIVER_EN H4 GPIO_10 UART0_TXD AE4 UART_AP_DEBUG_TXD OUT 30 33 1% 26 25 24 I2S_AP_TO_CODEC_ASP_BCLK V33 I2S2_BCLK SEP_SPI0_SCLK W3 NC 1/32W 1/32W
1/32W OUT MF MF
28 OUT AP_TO_TOUCH_RESET_L K1 GPIO_11 MF 26 25 24 I2S_AP_TO_CODEC_ASP_LRCLK U33 I2S2_LRCK SEP_SPI0_MISO AA4 NC 01005 2 01005 2
01005 OUT ROOM=SOC ROOM=SOC
29 OUT AP_TO_LCM_RESET_L J3 GPIO_12 UART1_CTS* K31 UART_BT_TO_AP_CTS_L IN 33
ROOM=SOC 26 25 24 I2S_CODEC_TO_AP_ASP_DIN T33 I2S2_DIN SEP_SPI0_MOSI U2 NC
IN
16 IN PMU_TO_AP_IRQ_L K2 GPIO_13 UART1_RTS* K32 UART_AP_TO_BT_RTS_L OUT 33
26 25 24 I2S_AP_TO_CODEC_ASP_DOUT V34 I2S2_DOUT
OUT
33 OUT AP_TO_BB_PCIE_DEV_WAKE J4 GPIO_14 UART1_RXD L33 UART_BT_TO_AP_RXD IN 33

33 OUT AP_TO_STOCKHOLM_DEV_WAKE L2 GPIO_15 UART1_TXD L32 UART_AP_TO_BT_TXD OUT 33


20 ALS_TO_AP_INT_L AM3 I2S3_MCK SEP_I2C_SCL V3 I2C_SEP_TO_EEPROM_SCL 8
IN OUT
3 IN BOARD_ID3 K3 GPIO_16 33 I2S_AP_TO_BB_BCLK AM4 I2S3_BCLK SEP_I2C_SDA Y4 I2C_SEP_BI_EEPROM_SDA 8
OUT BI
NC_AP_TO_STOCKHOLM_SIM_SEL L3 GPIO_17 UART2_CTS* AT23
NC 33 I2S_AP_TO_BB_LRCLK AN2 I2S3_LRCK
OUT
C 3

26
IN
OUT
BOOT_CONFIG0
AP_TO_ARC_RESET_L
N1
AH2
GPIO_18
GPIO_19
UART2_RTS*
UART2_RXD
AR20 CAM_EXT_LDO_EN
AP23
NC
OUT 21
33

33
IN I2S_BB_TO_AP_DIN
I2S_AP_TO_BB_DOUT
AP1
AN1
I2S3_DIN
I2S3_DOUT SEP_GPIO0 Y3 NC
C
OUT
33 29 9 IN LCM_TO_OWL_BSYNC AH3 GPIO_20 UART2_TXD AP22
NC SEP_GPIO1 AB4 NC
26 IN ARC_TO_AP_INT_L AH4 GPIO_21 30 16 TRISTAR_TO_AP_INT R32 I2S4_MCK PP1V8_ALWAYS 8 12 15 17
IN
33 OUT BB_TO_AP_GPS_TIME_MARK (AP TO BB) AJ1 GPIO_22 UART3_CTS* N4 UART_STOCKHOLM_TO_AP_CTS_L IN 33
24 I2S_AP_TO_CODEC_MSP_BCLK R31 I2S4_BCLK
OUT
26 OUT AP_TO_ARC_STAYIN_ALIVE AJ2 GPIO_23 UART3_RTS* P3 UART_AP_TO_STOCKHOLM_RTS_L OUT 33
24 I2S_AP_TO_CODEC_MSP_LRCLK V32 I2S4_LRCK
OUT PP1V8
33 IN BB_TO_AP_RESET_DETECT_L AJ3 GPIO_24 UART3_RXD R3 UART_STOCKHOLM_TO_AP_RXD IN 33
24 I2S_CODEC_TO_AP_MSP_DIN P31 I2S4_DIN
3 5 6 7 8 9 12 13 14 17 20 21
29 33
IN
3 IN BOOT_CONFIG1 AJ4 GPIO_25 UART3_TXD R2 UART_AP_TO_STOCKHOLM_TXD OUT 33
24 I2S_AP_TO_CODEC_MSP_DOUT P32 I2S4_DOUT
OUT
33 3 FORCE_DFU AK1 GPIO_26 NOSTUFF
IN
33 3 OUT DFU_STATUS AP3 GPIO_27 UART4_CTS* J33 UART_WLAN_TO_AP_CTS_L IN 33
R09411 R09101 1
R0909
BOOT_CONFIG2 AN4 J34 UART_AP_TO_WLAN_RTS_L 10K 10K 10K
3 IN GPIO_28 UART4_RTS* OUT 33 5% 5% 5%
1/32W 1/32W 1/32W
3 IN BOARD_ID4 AP4 GPIO_29 UART4_RXD J35 UART_WLAN_TO_AP_RXD IN 33
3 BOARD_ID2 AD4 SPI0_MISO MF MF MF
IN 01005 2
CODEC_TO_AP_PMU_INT_L AP5 GPIO_30 UART4_TXD K33 UART_AP_TO_WLAN_TXD 01005 2 2 01005
24 16 IN OUT 33
3 IN BOARD_ID1 AC3 SPI0_MOSI ROOM=SOC ROOM=SOC ROOM=SOC
33 OUT AP_TO_BB_RADIO_ON_L AR2 GPIO_31 3 BOARD_ID0 AB2 SPI0_SCLK
IN
13 OUT AP_TO_NAND_FW_STRAP AR3 GPIO_32 UART5_RTXD T32 SWI_AP_BI_TIGRIS BI 9 17 AD3 SPI0_SSIN ROOM=SOC
NC
29 IN TOUCH_TO_AP_INT_L AR4 GPIO_33 R0940
BOARD_REV3 AP6 GPIO_34 SPI_CODEC_TO_AP_MISO P33 PMU_TO_AP_SOCHOT0_R_L 0.00 2 PMU_TO_AP_SOCHOT0_L
3 IN 24 IN SPI1_MISO SOCHOT0 AM1 1 IN 16
3 IN BOARD_REV2 AT3 GPIO_35 ROOM=SOC 24 SPI_AP_TO_CODEC_MOSI V35 SPI1_MOSI
0% MF
01005
1/32W
OUT
3 IN BOARD_REV1 AT4 GPIO_36 PP0906 24 OUT SPI_AP_TO_CODEC_SCLK N32 SPI1_SCLK
BOARD_REV0 AR6 GPIO_37 UART6_RXD AF1 UART_ACCESSORY_TO_AP_RXD P2MM-NSM SPI_AP_TO_CODEC_CS_L M31 AP_TO_PMU_SOCHOT1_L
3 IN IN 30
SM 24 OUT SPI1_SSIN SOCHOT1 AM2 OUT 16
33 OUT AP_TO_BB_COREDUMP AP7 GPIO_38 UART6_TXD AE2 UART_AP_TO_ACCESSORY_TXD OUT 30 PP
1
33 IN BB_IPC_GPIO AT5 GPIO_39 ROOM=SOC 29 SPI_TOUCH_TO_AP_MISO E33 SPI2_MISO
IN
33 32 16 8 IN BUTTON_RINGER_A AP8 GPIO_40 UART7_RXD J31 R0960 29 OUT SPI_AP_TO_TOUCH_MOSI E35 SPI2_MOSI
33 OUT AP_TO_BB_MESA_UP_L AP9 GPIO_41 UART7_TXD J32 NC SPI_AP_TO_TOUCH_SCLK 1
0.00 2 SPI_AP_TO_TOUCH_SCLK_R F34
29 OUT SPI2_SCLK
28 OUT MAMBA_EXT_LDO_EN AP10 GPIO_42 01005 0% 1/32W MF SPI_AP_TO_TOUCH_CS_L F31 SPI2_SSIN CPU_ACTIVE_STATUS H31
29 OUT NC
ROOM=SOC 28 SPI_MESA_TO_AP_MISO AA2 SPI3_MISO
B R0930
0.00 2 28
IN
OUT SPI_AP_TO_MESA_MOSI Y2 SPI3_MOSI CLK32K_OUT H34 AP_TO_TOUCH_CLK32K_RESET_L OUT 29 B
28 OUT SPI_AP_TO_MESA_SCLK 1 SPI_AP_TO_MESA_SCLK_R AA3 SPI3_SCLK
NAND_SYS_CLK AM24
01005 0% 1/32W MF MESA_TO_AP_INT AC4 AP_TO_NAND_SYS_CLK_R
28 SPI3_SSIN
IN
R0945
1
0.00 2 AP_TO_NAND_SYS_CLK OUT 13

PP1V8 3 5 6 7 8 9 12 13 14 17 20 21 0%
29 33 1/32W
MF
ANALOG_PROX 01005
1 PIN J31 (UART7_RXD) SHOULD BE ROOM=SOC
R0911
1.00K BRIEFLY SWITCHED TO PD TO CHECK STATE.
5%
1/32W STUFF R0911 FOR ANALOG PROX.
MF
2 01005
ROOM=SOC NOSTUFF R0911 FOR DOPPLER PROX.
PROX_SELECT

ANTI-ROLLBACK EEPROM BUTTON PULL-UP RESISTORS I2C PROBE POINTS


128kbit
APN:335S0946 ROOM=SOC
P3MM-NSM
PP1V8_SDRAM SM
DEFAULT_RESISTOR_191000OHM_2_1 12 14 15 16 24 27 30 31 33
33 27 16 8 I2C0_AP_SCL 1
21 20 17 14 13 12 9 8 7 6 5 3 PP1V8
PP
PP0900
33 29 1
R0950 1
R0951 33 27 16 8 I2C0_AP_SDA 1
CRITICAL 191K 100K
PP
PP0901
A1

1 C0900 ROOM=SOC 1% 5% P3MM-NSM


SM
1.0UF 1/32W 1/32W ROOM=SOC
20%
VCC

MF MF
2 6.3V
X5R 2 01005
ROOM=SOC 2 01005
ROOM=SOC
0201-1 BUTTON_MENU_KEY_L ROOM=SOC
A ROOM=SOC U0900
M34128-FCS6_P/T
33 28 16 9

33 32 16 8 BUTTON_RINGER_A 33 30 26 25 17 8 I2C1_AP_SCL
P3MM-NSM
1
SM
SYNC_MASTER=N/A SYNC_DATE=N/A A
B1 SCL WLCSP SDA A2 I2C_SEP_BI_EEPROM_SDA BI 8
PP
PP0902 PAGE TITLE
PP1V8_ALWAYS I2C1_AP_SDA 1
I2C_SEP_TO_EEPROM_SCL IN 8
8 12 15 17 33 30 26 25 17 8 PP
PP0903 SOC:SERIAL & GPIO
VSS

1 SM
R0952 P3MM-NSM
ROOM=SOC
DRAWING NUMBER SIZE
220K
Apple Inc. 051-1902 D
B2

5%
1/32W ROOM=SOC REVISION
MF P3MM-NSM R
2 01005
ROOM=SOC 29 20 8 I2C2_AP_SCL 1
SM A.0.0
33 32 16 9 BUTTON_HOLD_KEY_L PP
PP0904 NOTICE OF PROPRIETARY PROPERTY: BRANCH
29 20 8 I2C2_AP_SDA 1
PP
SM
PP0905 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
P3MM-NSM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
ROOM=SOC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
9 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 8 OF 59
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1

MAUI - OWL POWER STATE CONTROL PROBE POINTS


ROOM=SOC
P3MM-NSM
SM
30 27 16 9 5 PMU_TO_OWL_ACTIVE_READY 1
PP PP1021
ROOM=SOC
P3MM-NSM
SM

D 16 11 9 PMU_TO_OWL_SLEEP1_READY 1
PP PP1023 D

U0600
MAUI-2GB-25NM-DDR-H
FCMSP
SC58980B0B-A040
SYM 7 OF 14
16 OUT OWL_TO_PMU_SLEEP1_REQUEST AD30 OWL_DDR_REQ CFSB_AOP W33 PMU_TO_SYSTEM_COLD_RESET_L IN 3 5 16 33

PMU_TO_OWL_SLEEP1_READY AB33
C 16 11 9 IN

SPI_OWL_TO_COMPASS_CS_L AF35
OWL_DDR_RESET*

OWL_FUNC_0
OMIT_TABLE
CRITICAL
AWAKE_REQ AA33
AWAKE_RESET* AD32
OWL_TO_PMU_ACTIVE_REQUEST
PMU_TO_OWL_ACTIVE_READY
OUT 16 C
19

19
OUT
COMPASS_TO_OWL_INT AH32 OWL_FUNC_1
ROOM=SOC
IN 5 9 16 27 30
1
SM
PP
PP1002
IN AL2 DWI_PMU_TO_PMGR_MISO P2MM-NSM
PMGR_MISO IN 16
19 OUT DISCRETE_ACCEL_TO_OWL_INT2 AG32 OWL_FUNC_2
PMGR_MOSI AL1 DWI_PMGR_TO_PMU_BACKLIGHT_MOSI OUT 16 27 PP1V8
19 IN ACCEL_GYRO_TO_OWL_INT1 AG31 OWL_FUNC_3 3 5 6 7 8 12 13 14 17 20 21 29
PMGR_SCLK0 AK4 DWI_PMGR_TO_PMU_SCLK OUT 16
NOSTUFF
33

19 OUT SPI_OWL_TO_ACCEL_GYRO_CS_L AG30 OWL_FUNC_4


PMGR_SSCLK1 AL3 DWI_PMGR_TO_BACKLIGHT_SCLK 1
19 IN ACCEL_GYRO_TO_OWL_INT2 AF33 OWL_FUNC_5
OUT 27
R1002
19 OUT SPI_OWL_TO_PHOSPHOROUS_CS_L AE34 OWL_FUNC_6 RT_CLK32768 AD31 PMU_TO_OWL_CLK32K IN 16
1.00K
5%
33 29 8 LCM_TO_OWL_BSYNC AF34 OWL_FUNC_7 1/32W
IN AE33 SWD_AP_PERIPHERAL_SWCLK MF
OWL_SWD_TCK_OUT OUT 13 33
9 OWL_TO_PMU_SHDN_BI_TIGRIS_SWI AF31 OWL_FUNC_8 AD35 2 01005
ROOM=SOC
OWL_SWD_TMS0 NC
19 IN PHOSPHORUS_TO_OWL_IRQ AF32 OWL_FUNC_9
OWL_SWD_TMS1 AC33 SWD_AP_BI_BB_SWDIO BI 33

19 IN SPI_OWL_TO_DISCRETE_ACCEL_CS_L AH31 OWL_I2CM_SCL SWD_TMS2 U31 SWD_AP_BI_NAND_SWDIO BI 13

19 OUT DISCRETE_ACCEL_TO_OWL_INT1 AH33 OWL_I2CM_SDA SWD_TMS3 T31


NC
19 IN SPI_IMU_TO_OWL_MISO AK31 OWL_SPI_MISO HOLD_KEY* U3 BUTTON_HOLD_KEY_L IN 8 16 32 33

19 OUT SPI_OWL_TO_IMU_MOSI AK32 OWL_SPI_MOSI


SKEY* W4 NC
19 OUT SPI_OWL_TO_IMU_SCLK AL33 OWL_SPI_SCLK
MENU_KEY* V4 BUTTON_MENU_KEY_L IN 8 16 28 33
33 IN UART_BB_TO_OWL_RXD AJ32 OWL_UART0_RXD
33 OUT UART_OWL_TO_BB_TXD AK33 OWL_UART0_TXD

33 OUT OWL_TO_WLAN_CONTEXT_B AH30 OWL_UART1_RXD


33 OUT OWL_TO_WLAN_CONTEXT_A AJ31 OWL_UART1_TXD

29 IN TOUCH_TO_OWL_ACCEL_DATA_REQUEST AJ34 OWL_UART2_RXD


29 OUT UART_OWL_TO_TOUCH_TXD AJ33 OWL_UART2_TXD

24 8 OUT I2S_AP_OWL_TO_CODEC_XSP_BCLK AD34 OWL_I2S_BCLK

B 24 8 IN I2S_CODEC_TO_AP_OWL_XSP_DIN
NC
AA34
AE32
OWL_I2S_DIN
OWL_I2S_MCK
B
OWL_I2S_LRCK
24 8 OUT I2S_AP_OWL_TO_CODEC_XSP_LRCLK AE31

OWL SYSTEM SHUTDOWN OPTION


NOSTUFF
R1020
1
10 2 1/32W SWI_AP_BI_TIGRIS BI 8 17
MF 5% 01005
ROOM=SOC

9 OWL_TO_PMU_SHDN_BI_TIGRIS_SWI NOSTUFF
A R1021
10 SYNC_MASTER=N/A SYNC_DATE=N/A A
1 2 1/32W OWL_TO_PMU_SHDN OUT 16 PAGE TITLE
MF 5%
ROOM=SOC
01005
SOC:OWL
DRAWING NUMBER SIZE

Apple Inc. 051-1902 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 9 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PP_SOC 14

MAUI - CPU, GPU & SOC RAILS AA17 W23


1 C1150
10UF
1 C1151
10UF
0.825V @4.7A MAX
0.725V @TBDA MAX

AA19 U0600 Y14 20% 20%


MAUI-2GB-25NM-DDR-H 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
AA23 Y16 0402-9 0402-9 XW1120
SHORT-10L-0.1MM-SM
AB14 FCMSP Y20 ROOM=SOC ROOM=SOC
14 10 PP_GPU SC58980B0B-A040
1 2 BUCK2_PP_SOC_FB OUT 14
AB16 Y22 ROOM=SOC
0.8V @10.5A MAX SYM 9 OF 14
AB20 Y24
1 C1100 1 C1101 XW1110
1 C1103 1 C1104 1 C1105 SHORT-10L-0.1MM-SM AB22 Y26

D 20%
10UF
2 6.3V
20%
10UF
2 6.3V
2.2UF
20% 20%
2.2UF 2.2UF
20%
1
ROOM=SOC
2 BUCK1_PP_GPU_FB OUT 14 AB24 CRITICAL
ROOM=SOC
VDD_SOC G29 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC D
CERM-X5R
0402-9
CERM-X5R
0402-9
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
AB26
OMIT_TABLE
AA27 C1153 C1154 C1155 C1156 C1157
ROOM=SOC ROOM=SOC
0201 0201 0201 AC17 F17 4.3UF 1UF 1UF 0.47UF 0.47UF
ROOM=SOC ROOM=SOC ROOM=SOC 20% 20% 20% 20% 20%
AC19 F20 4V 4V 4V 6.3V 6.3V
TP1120
0.50MM AC23 L29 CERM
0402
CERM
0402
CERM
0402
CERM
0402
CERM
0402
SM 1 3 1 3 1 3 1 3 1 3
PP
1 PP_GPU 10 14 AD16 N29
AD20 V28
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AA7 G15 2 4 2 4 2 4 2 4 2 4
AD22
C1106 C1107 C1108 C1109 C1110 C1111 AA9 U0600 W13
AD24
4.3UF 7.5UF 4.3UF 7.5UF 4.3UF 7.5UF AA11 MAUI-2GB-25NM-DDR-H T12
20% 20% 20% 20% 20% 20% AD26
4V 4V 4V 4V 4V 4V AB6 FCMSP M6
CERM CERM CERM CERM CERM CERM AE5
0402 0402 0402 0402 0402 0402 AB10 SC58980B0B-A040 U9 L22
1 3 1 3 1 3 1 3 1 3 1 3 AE15
AB12 SYM 8 OF 14 V12 L24
AE17
AC13 W9 L26
2 4 2 4 2 4 2 4 2 4 2 4 CRITICAL AE19
AD6 M12 L28
ROOM=SOC AE23
AD8 M18 M1
OMIT_TABLE AF14
AD10 N15 M5
AF16
AD12 N21 M7
AF20
AE7 N9 M9
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AF22
AE9 F10 M11
C1112 C1113 C1114 C1115 C1116 C1117 AE11 H14
AF24
M13
1UF 1UF 1UF 1UF 0.47UF 0.47UF AF26
20% 20% 20% 20% 20% 20% AE13 H16 M17
4V 4V 4V 4V 6.3V 6.3V AG17
CERM CERM CERM CERM CERM CERM AF8 H20 M21
0402 0402 0402 0402 0402 0402 AG19
1 3 1 3 1 3 1 3 1 3 1 3 AF10 H22 M23
AG23
AF12 H6 M25
AH16
2 4 2 4 2 4 2 4 2 4 2 4 AH6 H8 M27
AH20
AH8 J11 M29
AH22
C AH10
AH12 VDD_CPU
J13
J17
AH24
M35
N6
C
AH26
AJ5 J19 N10
AJ15
AJ7 J23 N12
AJ17
PP_CPU AJ9 J7 N14
14 10 AJ19
0.625V @TBDA MAX AJ11 K10 N16
AJ23
0.9V @10.5A MAX AJ13 K14 N18
1.0V @12.5A MAX AK14
1 C1120 1 C1121 1 C1122 1 C1123 1 C1124 1 C1125 AK6 K16
J29
G19
10UF 10UF 2.2UF 2.2UF 2.2UF 2.2UF AK10 K20 VDD_SOC N22
20% 20% 20% 20% 20% 20%
G23
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM AL7 K22 N24
0402-9 0402-9 0201 0201 0201 0201 AK22
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AL9 K6 N26
F6
AL11 K8 N28
TP1100
0.50MM L11
F14
SM
AM6 N30
1 PP_CPU AL15
PP 10 14 AM8 L13 N33
AM5
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AM10 L15 P9
G25
C1126 C1127 C1128 C1129 C1130 C1131 AN7 L17
G27
P11
7.5UF 7.5UF 4.3UF 7.5UF 4.3UF 4.3UF AN11 L19 P13
20% 20% 20% 20% 20% 20% H24
4V 4V 4V 4V 4V 4V AL13 VDD_GPU L21 P15
CERM CERM CERM CERM CERM CERM H26
0402 0402 0402 0402 0402 0402 Y8 M24 P17
1 3 1 3 1 3 H28
1 3 1 3 1 3 Y10 L7 VSS P19
J27
Y12 L9 P21
2 4 2 4 2 4 2 4 2 4 2 4 K24
AM12 F8 P23
K26
M8 P25
K28
N11 P27
L27
N13 P29
L23
N17 P35
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC M26
B C1132 C1133 C1134 C1135 C1136 C1137
N19
P10
M28
R4
R6
B
4.3UF 7.5UF 1UF 1UF 1UF 1UF G11
AL19
R8
20% 20% 20% 20% 20% 20% N7
4V 4V 4V 4V 4V 4V P12 R10
CERM CERM CERM CERM CERM CERM N27
0402 0402 0402 0402 0402 0402 P14 R12
1 3 1 3 1 3 1 3 1 3 1 3 P24
P16 R14
P26
2 4 2 4 2 4 2 4 2 4 2 4 P20 M19
P28
R15 R18
R17
R19 R20
R27
G13 R22
R29
R9 R24
T22
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC T10 R26
T26
C1138 C1139 C1140 C1141 T14
T7
R28
0.47UF 0.47UF 0.47UF 0.47UF T16 R30
20% 20% 20% 20% T28
6.3V 6.3V 6.3V 6.3V U11 T1
CERM CERM CERM CERM U17
0402 0402 0402 0402 V14 T2
1 3 1 3 1 3 1 3 V8
V16 R33
V20
G7 T9
2 4 2 4 2 4 2 4 V22
R23 T11
V24
G9 T13
V26
H10 T15
W7
T24 T17
XW1100
SHORT-10L-0.1MM-SM P22
W11
P7
BUCK0_PP_CPU_FB 2 1 Y28
14 OUT W17 T23
ROOM=SOC
N23 AJ20 VDD_SOC_SENSE T25
G17 T27
AK21
A G21
T18
VSS_SOC_SENSE T30
T35 SYNC_MASTER=N/A SYNC_DATE=N/A A
P2MM-NSM PAGE TITLE
T20 U6
PP1100
SM
PP
1
U10 SOC:POWER (1/3)
ROOM=SOC AP_CPU_SENSE_P Y6 VDD_CPU_SENSE VDD_GPU_SENSE G20 U12 DRAWING NUMBER SIZE

P2MM-NSM AP_CPU_SENSE_N Y7 VSS_CPU_SENSE VSS_GPU_SENSE H19 Apple Inc. 051-1902 D


SM REVISION
1
PP1101 PP R
A.0.0
ROOM=SOC P2MM-NSM
P2MM-NSM
AP_SOC_SENSE_N 1
SM NOTICE OF PROPRIETARY PROPERTY: BRANCH

PP1102
SM
1
PP AP_GPU_SENSE_N PP PP1104 THE INFORMATION CONTAINED HEREIN IS THE
ROOM=SOC PROPRIETARY PROPERTY OF APPLE INC.
ROOM=SOC THE POSESSOR AGREES TO THE FOLLOWING: PAGE

NOTE:AP_GPU_SENSE_P PROBE LOCATION @ R2205.2 16 IN AP_GPU_SENSE_P P2MM-NSM


SM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 11 OF 49
AP_SOC_SENSE_P 1
PP PP1105 II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
ROOM=SOC IV ALL RIGHTS RESERVED 10 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MAUI - POWER SUPPLIES


DDR IMPEDANCE CONTROL
1.06 - 1.17V @635mA MAX
D INTERNALLY SUPPLIES VDDQ 14 11 PP1V1 D
1
14 11 PP1V1 R1200 1R1201 1R1202 1
R1203 1 R1204 1 R1205
240 240 240 240 240 240
1% 1% 1% 1% 1% 1%
1 C1240 1 C1241 1 C1242 1 C1243 1 C1244 1 C1248 1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF 1/32W
MF
1/32W
MF
10UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2 01005 2 01005 2 01005 2 01005
20% 20% 20% 20% 20% 20% ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC 2 01005
ROOM=SOC 2 01005
ROOM=SOC
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0402-9 0201 0201 0201 0201 0201 A20 DDR0_RREF C21 DDR0_RREF
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
A22 U0600 DDR1_RREF AP17 DDR1_RREF
B11 MAUI-2GB-25NM-DDR-H DDR2_RREF V31 DDR2_RREF
B15 FCMSP DDR3_RREF P5 DDR3_RREF
ROOM=SOC ROOM=SOC ROOM=SOC B23 SC58980B0B-A040
C1245 C1246 C1247 B25 SYM 11 OF 14 DDR0_ZQ B21 DDR0_ZQ
4.3UF 1UF 0.47UF D16 VDDIO11_DDR0 ROOM=SOC DDR3_ZQ P2 DDR3_ZQ
20% 20% 20%
4V 4V 6.3V D20 CRITICAL
CERM CERM CERM OMIT_TABLE
0402 0402 0402 D22 DDR0_RET* C18 PMU_TO_OWL_SLEEP1_READY 9 16
1 3 1 3 1 3 IN
E15 DDR1_RET* AP15
E17 DDR2_RET* Y31
2 4 2 4 2 4
E19 DDR3_RET* U4 FL1280
E21 1.1V @7mA MAX 100OHM-25%-0.12A
F19 PP1V1_DDR_PLL 1 2 PP1V1 11 14
AK18 VOLTAGE=1.1V 01005
AN19 ROOM=SOC
AR18
VDDIO11_PLL_DDR W26 1 C1280
P8 0.22UF
AR21 20%
0.8V @TBDA MAX AR8 2 6.3V
X5R
0.9V @TBDA MAX 01005-1
AT13 ROOM=SOC
1.0V @1.0A MAX
C 14 7 6
0.802-TBDV @1.1A MAX
PP_FIXED AA15
U0600 AC11 PP_CPU_SRAM 14
AT16
AM14 VDDIO11_DDR1
C
AA21 MAUI-2GB-25NM-DDR-H AC7 AM16
ROOM=SOC ROOM=SOC ROOM=SOC FCMSP AC9 ROOM=SOC ROOM=SOC ROOM=SOC
AA25 AM18
1 C1200 C1201 C1202 C1203 AB18 SC58980B0B-A040 AA13 C1220 C1221 C1222 1 C1223 AM20 D19 PP1V1_SDRAM
10UF 4.3UF 1UF 0.47UF 0.47UF 1UF 4.3UF 2.2UF AN17
12 14 15
20% 20% 20% 20% AC15 VDD_CPU_SRAM AG11 20% 20% 20% 20% AR15
2 6.3V 4V 4V 6.3V 6.3V 4V 4V 2 6.3V 1.06 - 1.17V
CERM-X5R CERM CERM CERM AC21 SYM 10 OF 14 AG7 CERM CERM CERM X5R-CERM AN13 VDDIO11_RET_DDR W31
0402-9 0402 0402 0402 0402 0402 0402 0201
ROOM=SOC 1 3 1 3 1 3 AC25 AG9 1 3 1 3 1 3 ROOM=SOC AN15 T4
CRITICAL
AD14 ROOM=SOC AK12
AD18 OMIT_TABLE
2 4 2 4 2 4 2 4 2 4 2 4
AE21 H12
AB29 DDR0_SYS_ALIVE C19 SYSTEM_ALIVE 13 16 17
AE25 H18 IN
V29 DDR1_SYS_ALIVE AP16
AF18 R21
0.8V @0.5A MAX Y29 DDR2_SYS_ALIVE W32
AG15 U15
PP_GPU_SRAM 14 Y35 DDR3_SYS_ALIVE T3
AG21 J15
AB35
AH25 J21 ROOM=SOC ROOM=SOC ROOM=SOC
AG34
AH14 J9 C1224 C1225 C1226 1 C1227 M34 VDDIO11_DDR2
AH18 K12 4.3UF 1UF 4.3UF 2.2UF
20% 20% 20% 20% R35
AJ21 K18 4V 4V 4V 2 6.3V
X5R-CERM T29
AK16 M10 CERM CERM CERM 0201
VDD_GPU_SRAM 0402 0402 0402 ROOM=SOC T34
F12 M14 1 3 1 3 1 3
AA30
G10 M16
2 4 2 4 2 4 U30
V18 M20
AC30
AL17 P18
J25 R11
L25 R13
N25 U13 AA1
B R25
VDD_FIXED
V10 AC2 B
R7 M22 V6
AN6 W2
U25 H2
W15 M2
W21 U5 VDDIO11_DDR3
W25 P6
Y18 T6
F21 U1
F26 N5
AB28 R5
AC27 W5
G18
AK20
F16
R16
T8
V7
U19
W27
U27
AF4
AF27
U21

A SYNC MASTER=N/A SYNC DATE=N/A A


PAGE TITLE
0.756-TBDV @44mA MAX
15 PP0V8_OWL AH29
SOC:POWER (2/3)
DRAWING NUMBER SIZE
AD29
1 C1250 AF29
VDD_LOW
Apple Inc. 051-1902 D
1.0UF REVISION
20% R
2 6.3V
X5R
A.0.0
0201-1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=SOC
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
12 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 11 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

A1
A2
A11
U0600
MAUI-2GB-25NM-DDR-H
AF23
AF25
AF30
AN12
AN14
AN18
U0600
MAUI-2GB-25NM-DDR-H
E12
E16
E18
MAUI - POWER SUPPLIES
A16 FCMSP AG1 AN29 FCMSP E20
A21 SC58980B0B-A040 AG2 AN33 SC58980B0B-A040 E22
A24 SYM 13 OF 14 AG3 AP2 SYM 14 OF 14 E24
A25 CRITICAL AG6 AP13 CRITICAL E26
D A27 ROOM=SOC AG8 AP14 ROOM=SOC E29 1.70-1.95V @100mA(TBD) MAX D
A34 AG10 AP20 E32
33 31 30 27 24 16 15 14 8 PP1V8_SDRAM A10 U14
A35 OMIT_TABLE AG14 AP25 OMIT_TABLE F4 A26 U0600 U16
AA6 AG16 AP26 F5 MAUI-2GB-25NM-DDR-H
AA8 AG18 AP27 F7
1 C1300 1 C1301 1 C1302 AD1
FCMSP
U18
2.2UF 2.2UF 2.2UF AH35 U22
AA10 AG20 AP30 F9 20% 20% 20% SC58980B0B-A040
2 6.3V 2 6.3V 2 6.3V AT22 VDD1 U24
X5R-CERM X5R-CERM X5R-CERM SYM 12 OF 14
AA12 AG22 AP31 F11 0201 0201 0201 AT7 U26
AA14 AG24 AP32 F13 ROOM=SOC ROOM=SOC ROOM=SOC
G1 CRITICAL U28
AA16 U7 AP33 F15 L35 ROOM=SOC U35
AA18 AG29 AR1 F18 1.06-1.17V @1.3A(TBD) MAX
V1
AA20 AG33 AR5 D18 15 14 11 PP1V1_SDRAM A15 OMIT_TABLE V5
AA22 AG35 AR9 F23 A23
AA29
AA24 AH5 AR14 E30 1 C1310 1 C1312 1 C1313 1 C1314 AB34
U29
AA26 AH7 AR16 F25 10UF 2.2UF 2.2UF 2.2UF AD2
20% 20% 20% 20% V9
N8 AH9 AR25 F27 2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
AH34
V11
AA28 AH11 AR34 F28 0402-9 0201 0201 0201 AR13
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC V13
AA35 AH13 AR35 F29 AR17
V15
AB1 AH15 AT1 G4 AR22
V17
C17 AH17 AT2 G5 C1311 (2.2UF) MOVED TO PP1V1 AR7
V19
AB3 AH19 AT6 G6 TO HELP WITH DDR PI (SAME AS N66). ROOM=SOC ROOM=SOC AT15 VDD2 V21
AB5 AH21 AT8 G8 C1316 C1317 B10
V23
AB7 AH23 AT9 G12 1UF 1UF B26
20% 20% V25
AB9 AH27 AT14 G14 4V 4V G2
CERM CERM V27
AB11 AJ6 AT17 G16 0402 0402 L34
1 3 1 3 W30
AB13 AJ8 AT18 E6 N2
W1
AB15 AJ10 AT21 G22 R1
2 4 2 4 W6
U34
C AB17
AB19
AJ12
AJ14
AT25
AT34
G24
G26 V2
W10
W12
C
AB21 AJ16 AT35 G28 W35
1.62-1.98V @41mA MAX W14
AB23 AJ18 B1 G33
21 20 17 14 13 12 9 8 7 6 5 3 PP1V8 F30 W16
AB25 W8 B2 H1 33 29
H30 W18
AB27 AJ22 B16 H7
AB30 AG12 B20 H9
1 C1320 1 C1321 1 C1322 1 C1323 K30 W20
10UF 2.2UF 2.2UF 2.2UF M30 VDDIO18_GRP1 W22
AC1 AK24 B22 H11 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
N31 VSS W24
AC6 AJ28 B24 H13 0402-9 0201 0201 0201 P30 W28
AC8 B27 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AK2 H15 H5 W29
AC10 AK3 B34 H17 K5 VDDIO18_GRP2 W34
AC12 AK5 B35 E28 AN9 Y1
AC14 VSS VSS AK7 C2 H21 AA5 Y9
AC16 AK9 C3 VSS VSS H23 AC5 Y11
VDDIO18_GRP3
AC18 AK11 C4 H25 AG5 Y13
AC20 AK13 C5 H27 VDDIO18_GRP10:1.62-1.98V @8mA MAX AL5 Y15
AC22 AK15 C6 H29 VDDIO18_LPOSC:1.62-1.98V @1mA MAX AM23 VDDIO18_GRP4 Y17
AC24 B28 C7 J2
19 14 PP1V8_IMU_OWL AE28 Y19
AC26 AK17 C8 J5 AG28 VDDIO18_GRP10 (OWL) Y21
T5 M15 C9 J6 1.62-1.98V @1mA MAX
17 15 8 PP1V8_ALWAYS Y5 VDDIO18_GRP11 (AON) Y23
AC28 AP28 C10 J30 Y25
AC34 AK26 C11 J8 AG26 VDD18_LPOSC Y27
AC35 AK30 C12 J10 21 20 17 14 13 12 9 8 7 6 5 3
33 29
PP1V8 AM22 VDD18_FMON Y34
AD5 AK34 C13 J12 AD13 VDD18_UVD
VDD18_FMON :1.62-1.98V @1mA MAX AC29
AD7 AK29 C14 J14 VDD18_UVD :1.62-1.98V @5mA MAX
1 C1330 AN24 VDD18_AMUX AD28
AD9 AL6 C20 J16 2.2UF AG13
VDD18_AMUX :1.62-1.98V @1mA MAX 20% AE27
AD11 AL8 C22 J18 VDD18_TSADC:1.645-1.89V @2mA MAX 2 6.3V AK8
B AD15 AL10 C23 J20
X5R-CERM
0201
ROOM=SOC
AB8
N20 VDD18_TSADC
AG27
AJ30
B
AD17 AL12 C24 J22 AJ35
AD19 AF28 C25 J24 U23
AK19
AD21 AL14 C26 J26 AK23
AT27
AD23 AM29 C27 J28 D31
AD25 AL16 C28 K7 G30
AD27 AR27 C29 K9 L30
AD33 AL18 C30 K11 P4
AE6 Y30 C31 K13 U8
AE8 AL20 C32 K15 V30
AE10 AL25 C33 K17 A28
AE12 AL28 D3 K19 AL32
AE14 AL30 D4 K21 T21
AE16 AL31 D5 K23
AE18 AM7 D6 K25
AE20 AM9 D11 K27
AE22 AM11 D17 K29
AE24 AM13 D21 K34
AE26 AM15 D23 K35
AE29 AM17 D26 L1
AE30 AM19 D27 L5
AE35 AM21 D28 L6
AF5 AM33 D29 K4
AF7 AM34 D30 L8
AF9 AM35 E1 L10

A AF11
AF15
AN3
AN5
E3
E4
L12
L14 SYNC_MASTER=N/A SYNC_DATE=N/A A
AF17 AN16 E5 L16 PAGE TITLE

AF19 AN8 D7 L18 SOC:POWER (3/3)


AF21 AN10 E9 L20 DRAWING NUMBER SIZE

Apple Inc. 051-1902 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

S3E NAND
R1530
PP1V8 1
24.9 2 PP1V8_NAND_AVDD
21 20 17 14 13 12 9 8 7 6 5 3
33 29 VOLTAGE=1.8V
1%

D
1/32W
MF
01005
1 C1530
2.2UF
1 C1531
0.1UF
D
ROOM=NAND 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 01005
13 NAND_AGND ROOM=NAND ROOM=NAND
VOLTAGE=0V

1 C1534 1 C1520 1 C1521 1 C1522 1 C1524 1 C1525 1 C1523


10UF 15UF 15UF 10UF 0.1UF 100PF 10UF
20% 20% 20% 20% 20% 5% 20%
6.3V 6.3V 6.3V
2 CERM-X5R 2 6.3V
X5R 2 6.3V
X5R 2 CERM-X5R 2 6.3V
X5R-CERM 2 16V
NP0-C0G 2 CERM-X5R
0402-9 0402-1 0402-1 0402-9 01005 01005 0402-9
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

PP3V0_NAND 15

1 C1500 1 C1501 1 C1502 1 C1503


15UF 15UF 15UF 15UF EXTRA CAPS ADDED
1 C1532 1 C1526 1 C1527 1 C1528 1 C1529 1 C1533 EXTRA CAPS ADDED
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V FOR UF BLOCKING
1.0UF 0.1UF 1.0UF 220PF 33PF 8.2PF X5R X5R X5R X5R
20% 20% 20% 10% 5% +/-0.5PF FOR UF BLOCKING 0402-1 0402-1 0402-1 0402-1 AND DESENSE
2 6.3V
X5R 2 6.3V
X5R-CERM 2 6.3V
X5R
10V
2 X7R-CERM 2 16V
NP0-C0G-CERM 2 16V
NP0-C0G-CERM AND DESENSE
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
0201-1 01005 0201-1 01005 01005 01005 MITIGATION.
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND MITIGATION.

1 C1504 1 C1506 1 C1510 1 C1511 1 C1512 1 C1513 1 C1516 1 C1514 1 C1515


1.0UF 1.0UF 220PF 0.1UF 33PF 8.2PF 100PF 56PF 1UF
20% 20% 10% 20% 5% +/-0.5PF 5% 2% 20%
2 6.3V
X5R 2 6.3V
X5R 2 10V
X7R-CERM 2 6.3V 2 16V 2 16V 2 16V 2 50V 2 6.3V
15 PP0V9_NAND 0201-1 0201-1 01005
X5R-CERM
01005
NP0-C0G-CERM
01005
NP0-C0G-CERM
01005
NP0-C0G
01005
NP0-C0G
0201
X5R
0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
1 C1548 1 C1540 1 C1541 1 C1542 1 C1543 1 C1546 1 C1547
10UF 15UF 15UF 10UF 10UF 1.0UF 1.0UF
20% 20% 20%
C 6.3V
2 CERM-X5R
0402-9
20%
2 6.3V
X5R
0402-1
20%
2 6.3V
X5R
0402-1
6.3V
2 CERM-X5R
0402-9
6.3V
2 CERM-X5R
0402-9
20%
2 6.3V
X5R
0201-1
20%
2 6.3V
X5R
0201-1
1 C1517 1 C1507 1 C1508 1 C1505
DEFAULT_CAPACITOR_56.000000pF_2_1
C
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND 1.0UF 100PF 100PF 10UF
20% 5% 5% 20%
6.3V
2 6.3V
X5R 2 16V
NP0-C0G 2 16V
NP0-C0G 2 CERM-X5R
0201-1 01005 01005 0402-9
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
1 C1550 1 C1551 1 C1554

OB10

OF10

OA10

OD10

OG10
0.1UF 0.1UF 1000PF

OB0

OF0

OA0

OD0

OG0
M4
J5

J7

K4
K6

C3

E5

A3
A7
F2
J1
J9
R3
R7

A5

R5
20% 20% 10%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
01005

PCI_AVDD_CLK1
PP1V8 01005 01005

PCI_AVDD_H
PCI_AVDD_CLK2

PCI_VDD1
PCI_VDD2

AVDD1

VREF

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VCC
VCC
VCC
VCC
VCC
VCC
21 20 17 14 13 12 9 8 7 6 5 3
33 29 ROOM=NAND ROOM=NAND ROOM=NAND
NOSTUFF
1
1 C1560 R1560
0.01UF 10K
1%
10%
2 6.3V 1/32W
MF
U1500
X5R
01005 2 01005
ROOM=NAND
ROOM=NAND NAND_VREF VLGA
NOSTUFF 8 AP_TO_NAND_SYS_CLK D2 CLK_IN EXT_D0 G3 PMU_TO_NAND_LOW_BATT_BOOT_L 16
IN IN
1 C1561 1
R1561 PINUSE=BI
VER-1 EXT_D1 J3 AP_TO_NAND_FW_STRAP 8
PCIE_AP_TO_NAND_REFCLK_P H8 IN
10K 13 6 IN PCIE_REFCLK_P H2
0.01UF 1% PCIE_AP_TO_NAND_REFCLK_N H6 PINUSE=BI BOMOPTION=OMIT_TABLE EXT_D2 NC
10% 1/32W 13 6 IN PCIE_REFCLK_M E3
2 6.3V MF EXT_D3 NC
X5R ROOM=NAND
01005 2 01005
ROOM=NAND 6 OUT PCIE_NAND_TO_AP_CLKREQ_L G9 PCIE_CLKREQ* ROOM=NAND EXT_D4 E7
NC P3MM-NSM
ROOM=NAND F6 SM
M6 EXT_D5 NC 1
PCIE_NAND_RESREF PCI_RESREF CRITICAL C7 PP1520
PP
EXT_D6 NC
PINUSE=BI
1 PCIE_AP_TO_NAND_TXD0_P M8 PCIE_RX0_P EXT_D7 B8 SYSTEM_ALIVE
R1501 13 6 IN
PCIE_AP_TO_NAND_TXD0_N K8 PINUSE=BI
PCIE_RX0_M
IN 11 16 17
R1520
3.01K 13 6 IN
EXT_NCE G1 PCIE_AP_TO_NAND_RESET_L IN 6 1
0.00
2 SWD_AP_BI_NAND_SWDIO
1% PINUSE=BI BI 9
1/20W 13 6 PCIE_AP_TO_NAND_TXD1_P N5 PCIE_RX1_P 0% MF 01005 1/32W
MF IN F4 SWD_AP_BI_NAND_SWDIO_R
PINUSE=BI EXT_NRE
2 201
ROOM=NAND 13 6 IN PCIE_AP_TO_NAND_TXD1_N N3 PCIE_RX1_M ROOM=NAND

B 6 OUT PCIE_NAND_TO_AP_RXD0_P P8 PINUSE=BI


PCIE_TX0_P
PINUSE=BI
EXT_NWE C5 SWD_AP_NAND_SWCLK_R R1521
0.00
B
PCIE_NAND_TO_AP_RXD0_N N7 PCIE_TX0_M EXT_RNB G5 1 2 SWD_AP_PERIPHERAL_SWCLK IN 9 33
6 OUT NC 0% MF 01005 1/32W
PINUSE=BI M2 H4
6 OUT PCIE_NAND_TO_AP_RXD1_P PCIE_TX1_P EXT_CLE NC
ROOM=NAND
K2 PINUSE=BI
6 OUT PCIE_NAND_TO_AP_RXD1_N PCIE_TX1_M D4
EXT_ALE 1
PP
SM
PP1521
P3MM-NSM
5 AP_TO_NAND_RESET_L F8 RESET* ROOM=NAND
IN
D8 TRST*
NC
NAND_ZQ D6 ZQ

VSSA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
R1500
B2

B4
B6
OE10
G7
L3
L5
L7
P2
P4
P6
OC0
OC10
OE0
34.8
0.5%
1/32W
MF 13 NAND_AGND
2 01005
ROOM=NAND

PCIE RECEIVE-SIDE PROBE POINTS


ROOM=NAND
P3MM-NSM
SM
13 6 PCIE_AP_TO_NAND_REFCLK_P 1
PP
PP1500
13 6 PCIE_AP_TO_NAND_REFCLK_N 1
PP
SM
PP1501
P3MM-NSM
ROOM=NAND

A ROOM=NAND
P3MM-NSM
SM
SYNC_MASTER=N/A SYNC DATE=N/A A
13 6 PCIE_AP_TO_NAND_TXD0_P 1 PAGE TITLE
PP
PP1502 NAND
13 6 PCIE_AP_TO_NAND_TXD0_N 1
PP
SM
PP1503 DRAWING NUMBER SIZE
P3MM-NSM
ROOM=NAND Apple Inc. 051-1902 D
REVISION
R
ROOM=NAND
P3MM-NSM
A.0.0
PCIE_AP_TO_NAND_TXD1_P 1
SM NOTICE OF PROPRIETARY PROPERTY: BRANCH
13 6 PP
PP1504 THE INFORMATION CONTAINED HEREIN IS THE
13 6 PCIE_AP_TO_NAND_TXD1_N 1 PROPRIETARY PROPERTY OF APPLE INC.
PP
PP1505 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SM
P3MM-NSM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
15 OF 49
ROOM=NAND SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 13 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ANTIGUA PMU - Buck Supplies

CRITICAL
D U2000 OMIT_TABLE
L2000
D
D2255A080UXUVAI2 1.0UH-20%-3.6A-0.060OHM
15 VCC_MAIN_SNS V3 VDD_MAIN_SNS CSP
IN A3 BUCK0_LX0 2 1 PP_CPU 10
33 28 27 26 25 24 22 21 17 15 PP_VCC_MAIN R6 SYM 2 OF 5 B3 PIQA20161T-SM CRITICAL VOLTAGE=1.03V
F10 ROOM=PMU BUCK0_LX0 OMIT_TABLE 0.625V/0.9V/1.03V
1 C2085 1 C2086 1 C2087 1 C2088 L13
C3 ROOM=PMU 1 C2000 1 C2001 1 C2002 1 C2003 1 C2004 1 C2005

BAT/USB
L2001 15UF 15UF 15UF 15UF 15UF 15UF
10UF 10UF 10UF 10UF L5 VDD_MAIN 20% 20% 20% 20% 20% 20%
20% 20% 20% 20% 0.47UH-20%-3.8A-0.048OHM 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V

12.5A MAX
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
R8 X5R X5R X5R X5R X5R X5R
A5 BUCK0_LX1 1 2 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1

BUCK0
0402-9 0402-9 0402-9 0402-9 L4 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU B5 PIQA20121T-SM CRITICAL
BUCK0_LX1 OMIT_TABLE
A4 C5 ROOM=PMU
B4
VDD_BUCK0_01 L2002
C4 1.0UH-20%-3.6A-0.060OHM 1 C2006 1 C2007 1 C2008 1 C2009 1 C2010
1 C2089 1 C2090 1 C2091 1 C2092 A8
A7 BUCK0_LX2 1 2 15UF
20%
15UF
20%
15UF
20%
15UF
20%
15UF
20%
2.2UF 2.2UF 2.2UF 2.2UF B7 PIQA20161T-SM CRITICAL
20% 20% 20% 20% B8 BUCK0_LX2 OMIT_TABLE 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
2 6.3V 2 6.3V 2 6.3V 2 6.3V VDD_BUCK0_23 C7 ROOM=PMU 0402-1 0402-1 0402-1 0402-1 0402-1
X5R-CERM X5R-CERM X5R-CERM X5R-CERM C8 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
L2003
0.47UH-20%-3.8A-0.048OHM
A16
B16
A9 BUCK0_LX3 2 1
VDD_BUCK1_01 B9 PIQA20121T-SM CRITICAL
C16 BUCK0_LX3 OMIT_TABLE
C9 ROOM=PMU
1 C2093 1 C2094 1 C2095 1 C2096 A12
2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% B12
VDD_BUCK1_23 BUCK0_FB F8 BUCK0_PP_CPU_FB IN 10
2 6.3V 2 6.3V 2 6.3V 2 6.3V

BUCK INPUT
X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
C12 L2010
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 1.0UH-20%-3.6A-0.060OHM
J17
J18
A17 BUCK1_LX0 2 1 PP_GPU 10
VDD_BUCK2 B17 PIQA20161T-SM CRITICAL VOLTAGE=0.9V
C J19 BUCK1_LX0
C17
OMIT_TABLE
ROOM=PMU 1 C2012
15UF
1 C2013
15UF
1 C2014
15UF
1 C2015
15UF
1 C2016
15UF
0.70V/0.80V/0.9V
C
1 C2097 1 C2098 1 C2099 T18 L2011

10.5A MAX
20% 20% 20% 20% 20%
2.2UF 2.2UF 100PF T19 VDD_BUCK3 0.47UH-20%-3.8A-0.048OHM 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V

BUCK1
20% 20% 5% X5R X5R X5R X5R X5R
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 16V
NP0-C0G V12
A15 BUCK1_LX1 1 2 0402-1
ROOM=PMU
0402-1
ROOM=PMU
0402-1
ROOM=PMU
0402-1
ROOM=PMU
0402-1
ROOM=PMU
0201 0201 01005 B15 PIQA20121T-SM CRITICAL
ROOM=PMU ROOM=PMU ROOM=PMU Y12 BUCK1_LX1 OMIT_TABLE
VDD_BUCK4 C15 ROOM=PMU
Z12
L2012
N17 1.0UH-20%-3.6A-0.060OHM 1 C2017 1 C2018 1 C2019 1 C2020 1 C2021 1 C2011
N18
VDD_BUCK5
A13 BUCK1_LX2 1 2 15UF 15UF 15UF 15UF 15UF 15UF
N19 B13 PIQA20161T-SM CRITICAL 20% 20% 20% 20% 20% 20%
BUCK1_LX2 OMIT_TABLE 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
C13 ROOM=PMU 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
J1 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
J2 VDD_BUCK6 L2013
0.47UH-20%-3.8A-0.048OHM
E1 A11 BUCK1_LX3 2 1
E2 VDD_BUCK7 B11 PIQA20121T-SM CRITICAL
BUCK1_LX3 OMIT_TABLE
C11 ROOM=PMU
E17
E18
VDD_BUCK8 BUCK1_FB F12 BUCK1_PP_GPU_FB 10
E19 IN
L2020
29 21 20 17 13 12 9 8 7 6 5 3 PP1V8 U18 1.0UH-20%-3.6A-0.060OHM
33
V18 H17 BUCK2_LX0 1 2 PP_SOC 10

4.7A MAX
CRITICAL

BUCK2
Y18 BUCK3_SW1 H18 PIQA20161T-SM VOLTAGE=0.825V
BUCK2_LX0 OMIT_TABLE 0.725V/0.825V
Z18 H19 ROOM=PMU 1 C2022 1 C2023 1 C2024 1 C2025 1 C2026
PP1V8_TOUCH VOLTAGE=1 8V U16 BUCK3_SW2 L2021 15UF 15UF 15UF 15UF 15UF
29 28 20 0.47UH-20%-3.8A-0.048OHM 20% 20% 20% 20% 20%
19 12 PP1V8_IMU_OWL U15 BUCK3_SW3 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
VOLTAGE=1.8V K17 BUCK2_LX1 2 1 0402-1 0402-1 0402-1 0402-1 0402-1

B 11 PP1V1 V16
BUCK2_LX1
K18
K19
PIQA20121T-SM CRITICAL
OMIT_TABLE
ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
B
VOLTAGE=1.1V Y16
BUCK4_SW1
Z16 BUCK2_FB J14 BUCK2_PP_SOC_FB IN 10

L2050 L2030
1.0UH-20%-3.6A-0.060OHM
1.1A MAX

1.0UH-20%-3.6A-0.060OHM
BUCK5

11 7 6 PP_FIXED 2 1 BUCK5_LX0 M17


R18 BUCK3_LX0 1 2 PP1V8_SDRAM

1.5A MAX
VOLTAGE=0.85V PIQA20161T-SM CRITICAL M18 8 12 15 16 24 27 30 31 33

BUCK3
OMIT_TABLE BUCK5_LX0 BUCK3_LX0 R19 PIQA20161T-SM CRITICAL VOLTAGE=1.8V
1 C2050 1 C2051 ROOM=PMU M19 OMIT_TABLE
20%
15UF
20%
15UF XW2050
SHORT-10L-0.1MM-SM
XW2030 ROOM=PMU
SHORT-10L-0.1MM-SM
1 C2030 1 C2031 1 C2032
2 6.3V 2 6.3V 2 1 BUCK5_FB M13 BUCK5_FB V19 BUCK3_FB 1 2 15UF 15UF 100PF
X5R X5R BUCK3_FB 20% 20% 5%
0402-1 0402-1 ROOM=PMU ROOM=PMU 2 6.3V 2 6.3V 2 16V
ROOM=PMU ROOM=PMU X5R X5R NP0-C0G
0402-1 0402-1 01005
L2060 U17 ROOM=PMU ROOM=PMU ROOM=PMU
1UH-20%-1.2A-0.320OHM
400mA MAX

V17
BUCK6

21 20 PP1V2_CAMERA 2 1 BUCK6_LX0 H1 VBUCK3_SW Y17


VOLTAGE=1.2V 0603 H2 BUCK6_LX0 Z17
ROOM=PMU
1 C2060 1 C2061 1 C2062 CRITICAL
15UF 15UF 100PF
20% 20% 5% 21 BUCK6_FB J5 BUCK6_FB
16V IN

4.7A MAX
2 6.3V 2 6.3V 2 NP0-C0G CRITICAL L2040

BUCK4
X5R X5R 01005
0402-1 0402-1 1.0UH-20%-3.6A-0.060OHM
ROOM=PMU ROOM=PMU ROOM=PMU L2070
1.0UH-20%-2.25A-0.15OHM V11 BUCK4_LX0 1 2 PP1V1_SDRAM 11 12 15
PP_CPU_SRAM 2 1 BUCK7_LX0 F1 Y11 PIQA20161T-SM CRITICAL VOLTAGE=1.1V
1.1A MAX

11
BUCK4_LX0 OMIT_TABLE
BUCK7

VOLTAGE=1.0V PIXB2016FE-SM F2 BUCK7_LX0 Z11 ROOM=PMU


0.80V/0.90V/1.0V 1 C2070 1 C2071 ROOM=PMU 1 C2040 1 C2041 1 C2042 1 C2043 1 C2044
15UF 15UF XW2070 L2041 15UF 15UF 15UF 15UF 100PF
SHORT-10L-0.1MM-SM 0.47UH-20%-3.8A-0.048OHM 20% 20% 20% 20% 5%
20% 20% 2 1 BUCK7_FB C1 BUCK7_FB 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 16V
2 6.3V
X5R 2 6.3V
X5R V13 BUCK4_LX1 1 2 X5R
0402-1
X5R
0402-1
X5R
0402-1
X5R
0402-1
NP0-C0G
01005
A 0402-1
ROOM=PMU
0402-1
ROOM=PMU
ROOM=PMU

L2080 BUCK4_LX1
Y13
Z13
PIQA20121T-SM CRITICAL
OMIT_TABLE
ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
SYNC_MASTER=N/A SYNC DATE=N/A A
1.0UH-20%-2.25A-0.15OHM XW2040 PAGE TITLE

11 PP_GPU_SRAM 2 1 BUCK8_LX0 F17


BUCK4_FB T9 BUCK4_FB
SHORT-10L-0.1MM-SM
1 2
SYSTEM POWER:PMU (1/3)
1.1A MAX

VOLTAGE=1.0V PIXB2016FE-SM F18 DRAWING NUMBER SIZE


BUCK8

ROOM=PMU BUCK8_LX0 ROOM=PMU


0.80V/0.90V/1.0V 1 C2080 1 C2081 CRITICAL F19
V15 Apple Inc. 051-1902 D
15UF 15UF
20% 20% XW2080 Y15 R
REVISION
2 6.3V
X5R 2 6.3V
X5R
SHORT-10L-0.1MM-SM VBUCK4_SW A.0.0
0402-1 0402-1 2 1 BUCK8_FB C19 BUCK8_FB Z15
NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=PMU ROOM=PMU ROOM=PMU
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 14 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ANTIGUA LDO SPECS


ANTIGUA PMU - LDOs LDO#

LDO1 (A)
ADJ.RANGE

2.5-3.3V
ACCURACY
+/-1.4%
MAX.CURRENT

50mA

LDO2 (B) 1.2-2.0V +/-2.5% 50mA

LDO3 (A) 2.5-3.3V +/-1.4% 50mA


33 28 27 26 25 24 22 21 17 14 PP_VCC_MAIN LDO4 (D) 0.7-1.2V +/-2.5% 100mA
D D
1 C2120 1 C2121 1 C2122 LDO5 (F) 2.5-3.3V +/-2.5% 1000mA
10UF 10UF 10UF
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V LDO6 (C1) 1.2-3.6V +/-2.5% 150mA
CERM-X5R CERM-X5R CERM-X5R
0402-9 0402-9 0402-9
XW2105
SHORT-10L-0.1MM-SM
ROOM=PMU ROOM=PMU ROOM=PMU LDO7 (C) 2.5-3.3V +/-25mV 250mA

14 OUT VCC_MAIN_SNS 2 1 LDO8 (C) 2.5-3.3V +/-25mV 250mA


ROOM=PMU
PLACE_NEAR=U2000.U1:2mm 1 C2123 1 C2124 1 C2125 LDO9 (C) 2.5-3.3V +/-25mV 250mA
10UF 10UF 10UF
20% 20% 20% LDO10 (G) 0.7-1.2V +/-5.5% 1335mA
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0402-9 0402-9 0402-9
ROOM=PMU ROOM=PMU ROOM=PMU LDO11 (C) 2.5-3.3V +/-25mV 250mA

LDO12 (E) 1.8V +/-5% 10mA

1 C2126 1 C2127 CRITICAL LDO13 (C) 2.5-3.3V +/-25mV 250mA


10UF 10UF OMIT_TABLE
20% 20% LDO14 (H) 0.8-1.5V +/-2.5% 250mA
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
U2000
0402-9 0402-9 D2255A080UXUVAI2
ROOM=PMU ROOM=PMU CSP LDO15 (B) 1.2-2.0V +/-2.5% 50mA
M3 SYM 1 OF 5
VDD_LDO1_3 ROOM=PMU
V2 VDD_LDO2
14 12 11 PP1V1_SDRAM M2 VDD_LDO4 VOLTAGE=3.3V
U1 VLDO1 M1 PP3V3_USB 5 LDO1

LDO INPUT
C2130 1 C2131 1
U2 VDD_LDO5 VLDO2 V1 VOLTAGE=1.8V PP1V8_VA 24 25 26 LDO2
2.2UF 2.2UF VLDO3 L1 PP3V0_TRISTAR 19 27 30 31 33 LDO3
20% 20% L2 VDD_LDO6
6.3V 6.3V VLDO4 N1 VOLTAGE=0.8V PP0V8_OWL LDO4
X5R-CERM 2 X5R-CERM 2 Y6 11

C 0201
ROOM=PMU
0201
ROOM=PMU Y4
VDD_LDO7
VDD_LDO8 VLDO5
T1
T2
VOLTAGE=3.0V PP3V0_NAND 13 LDO5 C
Y3 VDD_LDO9
VLDO6 K1 VOLTAGE=3.3V PP3V3_ACC 30 LDO6
Y9
VBYPASS K2
Z9 VDD_LDO10
VLDO7 Z6 VOLTAGE=3.0V PP3V0_PROX_ALS 20 LDO7
R3

LDO
VDD_LDO11 VOLTAGE=2.775V
Y5 VLDO8 Z4 PMU_LDO8 LDO8
VDD_LDO13 VOLTAGE=2.85V
VLDO9 Z3 PP2V85_CAM_AVDD_PMU 20 LDO9
33 31 30 27 24 16 14 12 8 PP1V8_SDRAM Y7 VDD_LDO14 XW2100
N2 VLDO9_FB Y2 CAM_AVDD_FB 1 2
VDD_LDO15 PLACE_NEAR=U2000.Y2:2mm
VOLTAGE=0.9V
C2132 1 K3
Y8 ROOM=PMU SHORT-10L-0.1MM-SM PP0V9_NAND 13 LDO10
VDD_BYPASS VLDO10 Z8
2.2UF
20% VOLTAGE=3.0V
6.3V 2 P12 VPP_OTP VLDO11 R2 PP3V0_PROX_IRLED 20 LDO11
X5R-CERM VOLTAGE=1.8V
0201 VLDO12 K6 PP1V8_ALWAYS 8 12 17 LDO12
ROOM=PMU VOLTAGE=3.0V
VLDO13 Z5 PP3V0_MESA 28 LDO13
VLDO14 Z7 VOLTAGE=1.2V PP1V2 5 6 7 LDO14
VLDO15 P2 VOLTAGE=1.8V PP1V8_MESA 28 LDO15

U2000 VPUMP U19 PMU_VPUMP


D2255A080UXUVAI2 1 C2100 1 C2101 1 C2103 1 C2105 1 C2107 1 C2109 1 C2111 1 C2113 1 C2115
CSP 47NF 2.2UF 2.2UF 2.2UF 4.3UF 2.2UF 4.3UF 2.2UF 4.3UF
VPUMP:10nF min. @ 4.6V 20% 20% 20% 20% 20% 20% 20% 20% 20%
SYM 5 OF 5 2 6.3V
D10
ROOM=PMU
J15 2 6.3V
X5R-CERM X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 4V
X5R-CERM 2 6.3V
X5R-CERM 2 4V
X5R-CERM 2 6.3V
X5R-CERM 2 4V
X5R-CERM
01005 0201 0201 0201 0610 0201 0610 0201 0610
D11 J16 ROOM=PMU
CRITICAL ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
D12 OMIT_TABLE J3
D13 J4 U2000
D14 K15 D2255A080UXUVAI2 NOSTUFF
D15 K16 CSP
1 C2102 1 C2104 1 C2106 1 C2108 1 C2110 1 C2112 1 C2114
SYM 4 OF 5 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
D16 L15 A1 L9 20% 20% 20% 20% 20% 20% 20%
ROOM=PMU 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
B D17
D18
L16
M14
A10
A14
CRITICAL
OMIT_TABLE
M8
M9 ROOM=PMU ROOM=PMU
X5R-CERM
0201
ROOM=PMU
X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
ROOM=PMU
X5R-CERM
0201
ROOM=PMU
X5R-CERM
0201
ROOM=PMU
X5R-CERM
0201
ROOM=PMU
B
D2 M15 A18 N10
D5 M16 A19 N12
D6 N14 A2 N13
D7 N15 A6 N9
D8 N16 B1 P10
D9 P13 B10 P11
D3 P14 B14 P18
E10 P15 B18 P19
E11 P16 B19 P5
E12 P17 B2 R10
E13 R13 B6 R11
D4 NC NC R14 C10 R12
E15 R15 C14 R9
E16 R16 C18 T16
E3 R17 C2
VSS
T3 PMU_VSS_RTC 16
E4 T10 C6 T6 NOTE: T3 IS XTAL REF GND
E5 T11 D1 T8
E7 T12 D19 U3
E8 T13 E14 U9
E9 T14 G1 V10
F14 T15 G17 V14
F15 T17 G18 V8
F16 U10 G19 V9
F3 U11 G2 Y1

A F4
G14
U12
U13
H7
J6
Y10
Y14 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
G15 U14 K12 Y19
G16 U4 K7 Z1 SYSTEM POWER:PMU (2/3)
G3 U5 L17 Z10 DRAWING NUMBER SIZE

G4 U6 L18 Z14 Apple Inc. 051-1902 D


H15 V4 L19 Z19 REVISION
R
H16 V5 L6 Z2 A.0.0
H3 V6 L7 NOTICE OF PROPRIETARY PROPERTY: BRANCH

H4 THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
21 OF 49
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 15 OF 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CONTROL PIN NOTES:


ANTIGUA PMU - GPIOs, NTCs NOTE (1):INPUT PULL-DOWN 100-300k
NOTE (2):INPUT PULL-DOWN 1M
NOTE (3):INPUT PULL-UP OR DOWN 100k-300k
NOTE (4):OUTPUT OPEN-DRAIN, REQUIRES PULL-UP

D D

CRITICAL
OMIT_TABLE
33 31 30 27 24 15 14 12 8 PP1V8_SDRAM U2000
D2255A080UXUVAI2
1 1 CSP
R2260 R2261 SYM 3 OF 5
100K 100K AP_TO_PMU_WDOG_RESET P7 PMU_IREF
5% 5% 5 IN RESET_IN1 (3)ROOM=PMU IREF K5
1/32W 1/32W
MF MF 30 IN TRISTAR_TO_PMU_HOST_RESET P8 RESET_IN2 (3)

RESETS
2 01005 2 01005 AP_TO_PMU_SOCHOT1_L