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g1
Fig. 1 Thyristor based dual converter structure.
Three phase mains are connected to the ac inputs A, g2
B and C for phase-A, phase-B and phase-C
g3
respectively. Considering a phase sequence of ABC,
the phase angle control range is π/6 ≤ α ≤ 2π/3. g4
Within the operating control range (π/6 ≤ α ≤ 2π/3),
two thyristors (one from the top row and the other g5
from the bottom row) of the converter conducts the
dc output load current. The overlapping of g6
conduction of two thyristors are π/6. For three phase
Fig. 2 Six state pulses for the ac/dc converter.
ac input voltages given in (1), the firing angle α is
calculated considering the positive zero crossing of 3. PROPOSED CONTROLLER
phase A voltage va as the reference.
3.1 Hybrid Circuit for Six-State Pulse Generation
v a = Vm sin(ωt ) The proposed scheme is shown in Fig. 3. A total of
vb = Vm sin(ωt − 2π / 3) 128 different shifted patterns are stored in EPROMs.
vc = Vm sin(ωt − 4π / 3) To have exactly π/3 radians shifting in the six-state
(1) real time pulses, the stored pattern are chosen to be a
Considering inductive load, the output voltage is multiple of 6. In the proposed design each pattern has
given by, 6x64=384 bits.
~ ~ 3 Phase Supply Vs
ZCD Phase
3 α+π / 3 LPF
∫
Phase A Detector
Va = vab d (ωt )
π α
Vcc
= ∫
Vm sin(ωt − 5π / 6)d (ωt ) Overload P0.4 Divide
Fopen P3.1 VCO Forward Reverse
Excitation P0.5 by 384
π α (2)
Phase A
Phase B
P0.6
P0.7
O/L P3.2
9
Converter Converter
7 A0-A8
A9-A15 6 Forward
Simplification of (2) yields, Direction P2.0-P2.6 D0-D5
P3.3 Amplifier
Position P3.4 Stored PWM
Mode P0.1 CE
P3.5 Pattern Reverse
(CC/CS) Amplifier
V 3 3 F/R P3.6
Va = m cos(α − π / 6)
Isolation
AT89C51
π (3) P1.0-P1.7
8
ADC0804
+Vcc
DB0-DB7 Position
Potentiometer
From (3), it is evident that the converter gives
Fig. 3 Proposed control scheme using hybrid circuit
maximum dc output of Vm 3 3 / π at α = π / 6 and
for generating synchronized six-state pulses for the
zero dc output at α = 2π / 3 , giving a control range of ac/dc converter.
π/2 radians. Six state pulses, each spaced at π/3 The centre frequency of the PLL-VCO is set to
radians are required for the converter. For the P 384*50=19.2 kHz considering the nominal supply
converter, the pulse sequences are g1, g2, g3, g4, g5 frequency to be 50Hz. The PLL takes few cycles to
and g6 for the thyristors T1,, T2, T3, T4, T5 and T6. For synchronize with the supply frequency. Hence the
inductive load, each thyristor may conduct for π converter should not be turned ON during the capture
radians. Hence the gate pulse of a thyristor should be period; otherwise, there will be unwanted high
extended for duration of π radians once fired. Typical voltage output from the converter. To ensure error
firing pulses for the converter are shown in Fig. 2. free operation, the AT89C51 sends a disable signal at
For the reverse converter, the pulse sequences are P0:1 line connected to the PWM EPROM and the
same as the forward converter, however, the gating associate firing circuitry during the first few cycles.
signals g1, g2, g3, g4, g5 and g6 are applied to the The AT89C51 microcontroller supervises the
thyristors T*1, T*2, T*3, T*4, T*5 and T*6. operation of the controller and makes necessary
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diagnostics. The AT89C51 is programmed according scan pulses in a fundamental period in synchronism
to the following algorithm: with the phase-A voltage reference. The phase
detector PD2 of CD4046 is used that produces in-
Controller Algorithm phase pulses at Cin with the reference at Sin when the
1) Initialize the reference voltage output Vref. Set PLL is in locked condition. The Q9 and Q10 lines of
Vout = 0; Vδ = 0. Disable EPROM output. the 14-bit binary counter (CD4040) are connected to
2) Check the field circuit at P0.5. If field circuit is an AND gate. The output of the AND gate is
open goto step 17, else goto step 3. connected to the asynchronous RESET input of
3) Check the phase sequence from the signals at CD4040. Thus the CD4040 is reset after a count
pins P0.6 and P0.7. If phase sequence is not value of 384. The inverted Q9 signal is connected to
correct, disable the EPROM then goto step 16. the phase detector input (Cin pin of CD4046). The
4) Delay for some time so that the PLL can lock the waveform at Cin pin of CD4046 has a duty cycle of
input supply frequency. 66% in locked condition.
4049
5) Check the mode of operation at pin P3.5. If
constant motor speed is needed (mode=0), then
set Vchange = 0, otherwise read the ADC data Cin VCO OUT Clock Q9
connected at port P1 and set Vchange = ADC data. Phase A
Sin
Q10
74LS14
3.2 The Phase Locked Loop (PLL) Circuit 4N35
The PLL circuit is shown in Fig. 4 and is the crucial Fig. 5 Overload protection incorporated from two
part of the controller. It is designed to generate 384 phases of the ac side.
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Rectifier Output Voltage
The output of 4N35 is buffered with inverters to 600
Voltage (V)
generate TTL logic level voltage that feds the P0.4 400
pin of AT89C51. Figure 5 shows the over-current 200 Phase A Phase B Phase C
protection circuit used in the proposed scheme. 0
Vcc
D1 D3
Phase C D5 0 1 2 3 4 5 6
R1 R2 Angle (Rad)
Neutral D6
D4 D2 P0.5 Fig. 7 Three phase voltages and controlled rectifier
74LS14 output voltage for a phase angle of 600, the rms
4N35
phase voltage is 240V.
Field (-) Field (+)
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