[0002]

Currently, flash memory, one kind of electrically rewritable nonvolatile memory

unit, is widely used as a device for storing programs and data. Flash memory is a memory
element whose memory content can be erased and written repeatedly by making the
voltage that is impressed during rewriting higher than the voltage during reading. In other
words, rewriting is performed by impressing pulse-like voltage on the memory element,
and applying current to the gate insulator and injecting electrons into the memory
element and withdrawing the electrons.
In this way, degradation of flash memory is essentially unavoidable because
current must be applied to the gate insulator each time rewriting is performed. Owing to
this, flash memory has the characteristics that rewriting can no longer be done when the
degradation of the memory element progresses, and there is a limit to the number of times
that rewriting can be done. Therefore, a technique that impresses an appropriate pulse
voltage on the memory element at an appropriate pulse width during rewriting has
become important.

[0013]
A description is provided below about the erasure operation for nonvolatile
memory NVM.
(1) The control unit FCU receives an erase command from the outside such as the CPU
and controls so that the initial setting information required for erasure is transmitted from
the memory MRY inside the memory unit FMU to the control unit FCU and is stored in
the second register REG2 inside the control unit FCU. After that, the control unit FCU
writes back the initial setting information (the initial erase voltage information) inside the
second register REG2 to the first register REG1 inside the first control circuit PE1 of the
memory unit FMU.
(2) The second control circuit PE2 of the control unit FCU issues an erase start flag to the
memory unit FMU and the counter CNT inside the control unit FCU. Owing to this, the
memory unit FMU starts the erasure operation, and the counter CNT inside the control
unit FCU starts the count operation.
(3) The memory unit FMU controls the power supply circuit PSC based on the
information that is written in the erase start flag and first register REG1 and implements
erasure of the memory cell transistor of the memory MRY. For example, the first control
circuit PE1 supplies the erase voltage to the main electrode of the memory cell transistor
based on the erase start flag.
(4) After the first control circuit PE1 of the memory unit FMU detects the end of the first
erasure operation, it issues an erase end flag to the control unit FCU. At the end of the
erasure operation the fact that the impressed voltage for erasure has returned to the initial
voltage is detected. For example, a detection circuit detects that the erase voltage has
become larger than the baseline level and sets the end flag, and stops the supply of the
erase voltage. Owing to this, the second control circuit PE2 of the control unit FCU stops
the counter CNT inside the control unit FCU, and the erase voltage impression time (Tp)
corresponding to the count number is measured.
(5) The counter CNT inside the control unit FCU transmits the measurement results
(count number) to the second control circuit PE2 of the control unit FCU.
(6) The second control circuit PE2 of the control unit FCU sets the voltage level in
accordance with the measurement results and sets to the first register REG 1 inside the
memory unit FMU. For example, the second control circuit PE2 determines the erase
voltage that is next impressed on the main electrode of the memory cell transistor based
on the measurement results of the counter CNT.
(7) Steps (2) to (6) above are run until it reaches the prescribed number of erasures.
(8) Erase verify is run.
[0014]
As shown in FIG. 3, when the voltage of the charge pump circuit of the power
supply circuit PSC is higher than the prescribed voltage (e.g., V1), the supply current
decreases, and the pump capacity decreases. Accordingly, the second control circuit PE2
sets as indicated below the relationship between the count number of the counter CNT
and the voltage increase/decrease range.
(a) If the count number of the counter CNT is large, the charge pump capacity of the
power supply circuit is determined to be insufficient, and erasure is performed at high
capacity by lowering the erase voltage. The erase voltage at this time is set for example at
V1, and the decreased voltage range is Vd.
(b) When the erase voltage remains low, Vth fluctuation is difficult (Vth cannot be made
deep), so the erase voltage is raised at the point when the count number of the counter
CNT becomes smaller. The erase voltage at this time is set for example at V2, and the
increased voltage range is Vi. Here, Vi is set at Vid. By this means, it is possible to
raise the erase voltage.
(c) (a) and (b) above are repeated.

[0026]
With reference to FIG. 6A and FIG. 6B, the memory cell (also called the
“memory cell transistor”) MC is formed on a substrate 20, and comprises a control gate
(CG) 21, charge accumulation part 22, memory gate (MG) 23, source region 24, and
drain region 25. The control gate 21 is formed through the medium of an insulation layer
(not shown) on the surface of the P-type silicon substrate. The charge accumulation part
22 is formed by an ONO (oxide-nitride-oxide) film composed of silicon oxide film (not
shown), silicon nitride film (not shown) and silicon oxide film (not shown), on the side
wall of the control gate 21. A memory gate 23 with a sidewall structure is formed on the
ONO film. A source region 24 and a drain region 25 are respectively formed by injecting
N-type impurities on the substrate to the left of the control gate 21 and to the right of the
memory gate 23. Viewed from the direction perpendicular to the substrate 20, a part of
the memory gate 23 and a part of the source region 24 overlap, and a part of the control
gate 21 and a part of the drain region 25 overlap.

[Claim 1]
A semiconductor device, which comprises a memory unit, and a control unit that
controls the memory unit,
 the memory unit comprises a memory that is composed of a nonvolatile memory
element and stores the setting information required for rewriting, a first control circuit
that has a first register and a rewrite end flag, and a power supply circuit that generates a
rewrite voltage,
the control unit comprises a second control circuit that has rewrite start flag, a
counter that measures the rewrite voltage impression time based on the rewrite start flag
and rewrite end flag, and a second register that stores the next rewrite voltage based on
the rewrite voltage impression time,
wherein when the control unit receives a command to rewrite the memory, it reads
out the setting information required for rewriting from the memory, and performs write
back to the second register.
[Claim 2]
In the semiconductor device in Claim 1,
the memory comprises a memory cell transistor that has a charge accumulation
part, and memorizes the data based on the changes in the threshold voltage in accordance
with the load amount of the charge accumulation part,
the power supply circuit comprises a voltage generation circuit that generates a
rewrite voltage for supply to one main electrode of the memory cell register during the
rewriting operation, and a detection circuit that detects the output voltage of the voltage
generation circuit and compares it with the baseline level,
wherein the first control circuit supplies the rewrite voltage to the main electrode
based on the rewrite start flag,
the detection circuit detects the fact that the rewrite voltage is smaller than the
baseline level and sets the rewrite end flag,
the counter starts the count by the rewrite start flag, and ends the count by the
rewrite end flag, and
the second control circuit determines the rewrite voltage that is next impressed on
the main electrode based on the count results of the counter.