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5 4 3 2 1

ZZZ
ZZZ1

0605 Change P/N for ZEJ00

PCB DAZ@
DA60012D000 HDMI 45@
PCB 125 LA-A791P REV0 M/B 3 RO0000003HM
D D

S1

FRAME
EC0MV000200

Compal Confidential
S4

FRAME
EC0MV000200
for GLONASS
@

C C

Schematics Document

ZEJ00
LA-A791P
B B

2013-05-27
REV:0.2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/09 2014/11/09 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 1 of 28
5 4 3 2 1
5 4 3 2 1

ZEJ00 block diagram


D D

Max. support VRAM size : 2GB. switching


Battery
Charger P22 P22
DDR3L 1GB (4Gb X16 *2 Pcs) I2C
HDMI
CONN. P6

P7 Battery Input
External Memory Interface LDO Output
HDMI BUCK Output

LVDS MT8193 RGB USB 2.0


LCM micro USB,OGT
P7 P17
CONN. PWM
MT6320
P7 PMIC

C
AUDIO C

I2C, LDO OUTPUT


S7300B + BUCK OUTPUT
Touch Sensor EINT
Vibrator CONN CHARGER
Board CONN.
P14 P14 MT8389W/MT8125 I2S, SPI, EINT, I2C D MIC
MIC P16
HP R/L

KCOL & KROW


Cortex-A7 GPIO POUT P23~P25
Button (Power on/reset) P Sensor
P15
P8

5M Camera MIPI,I2C 1.2GHz Quad-Core HP+MIC jack


P10 P Sensor P8
Conn SIM Card
Front Camera YUV,I2C
P8
P18
P10

combo JACK
GPIO Speaker R
Audio S/W
Speaker
Gyro+ G AMP P16
P12
sensor I2C, EINT P12
MPU 6050
B P12 BSI Speaker L B

26MHz
I2C, EINT

JTAG
UART1
UART2
Debug Port UART4 PCM, UART3, EINT NH520T/NH520*
P11 WIFI/BT
P4,P5 MSDC3
WIFI
BT4.0
GPS* GPS
MSDC0 MSDC1
P9

eMMC micro SD Russian Sku


8G/16G P17
P13 UART1, EINT MT3332 GPS

GLONASS

A A

P21

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/03 2013/11/03 Title
Issued Date Deciphered Date Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 2 of 28
5 4 3 2 1
5 4 3 2 1

D D

Voltage Rails
MT6320 Power Plane Function Power Level IDLE Sleep mode I2C address
VCORE_PMU VCORE switching output 0.75 ~ 1.3 ON Low voltage
Address(8bit)
VPROC_PMU VPROC switching output 0.75 ~ 1.3 ON Low voltage Device Address(7 bit)
Write Read
VTCXO_1_PMU LDO output for TCXO 2.8V ON OFF
VCAMA_PMU LDO output for camaera analog 2.8V ON Gating by SW
Gyro (MPU-6050) 0x68 0xD0 0xD1
VSRAM_PMU LDO output used for 1.2V SRAM 1.2V ON Low voltage
G-sensor (MPU-6050) 0x68 0xD0 0xD1
VDD28_6583 LDO output used for 2.8V IO 2.8V ON Gating by SW
Touch screen (S7300B) 0x20 0x40 0x41
VGP2_PMU LDO output for camaera 1.8V 1.8V ON Gating by SW
Camera 0.3M 0x21 0x42 0x43
VEMC_3V3_PMU LDO output for eMMC&P-sensor 3.3V ON Gating by SW
Camera 5M 0x36 0x6C 0x6D
C VMCH_PMU LDO output for SD card 3.3V ON Gating by SW
PMIC C

VGP5_PMU LDO output for Touch panel 2.8V ON Gating by SW


Charger 0x6B 0xD6 0xD7
DDR3VCCIO LDO output for DDR3L 1.35V ON Gating by SW
Battery 0x55 0xAA 0xAB
Gating by SW
VDD18_6583 LDO output used for 1.8V IO 1.8V ON Gating by SW
VRF18_PMU LDO output for RF_MT6167 1.8V ON Gating by SW

Main board ID BOM structure


MB_ID0 MB_ID1 Name Function
B B

0 0 EVT 3G@ 3G only


0 1 DVT WIFI_ONLY@ WIFI ONLY
1 0 PVT DAZ@ PCB
1 1 MP EMC@ for EMC request
NH520@ AW-NH520
NH520_EMC@ GPS EMC
GLONASS@ MT3332

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/03 2013/11/03 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 3 of 28
5 4 3 2 1
5 4 3 2 1

U201

3G@
SA00006SG00
S IC MT8389WK/A 1.2G FCCSP 515P CPU 0_0402_5% -22mil U201F
R1632 R1627
1 2 AG17 T3 1 2
VDD18_6583 DVDD18_MD DVDD18_MIPITX VDD18_6583
U201 R1633 T2 0_0402_5% -22mil
WIFI_ONLY@ 1 2 AH14 DVSS18_MIPITX
VA_PMU AVDD18_MD 1 1 1
0_0402_5% -22mil 1 1 1 AD16 L7 C1637 C1638 C1639
C1607 C1608 C1609 AE17 AVSS18_MD DVDD18_MIPIRX M6
SA00006S510 AVSS18_MD DVSS18_MIPIRX

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402


D 2 2 2 D

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402


S IC MT8389WK/A 1.2G FCCSP 515P CPU AJ12 H1
2 2 2 AD12 AVDD18_AP DVDD18_MIPIIO K6
0_0402_5% -22mil AE13 AVSS18_AP DVSS18_MIPIIO
AVSS18_AP
R1635 R1628
1 2 AH19 AB28 1 2 VUSB_PMU
VTCXO_1_PMU AVDD28_DAC AVDD33_USB_P0
R1636 AD27 0_0402_5% -22mil 0_0402_5% -22mil
1 2 AJ11 AVDD18_USB_P0 AB26 R1652 1 2
VDD18_6583 DVDD18_PLLGP AVSS33_USB_P0 VUSB_PMU
0_0402_5% -22mil 1 2 VSIM1_PMU
R1637 AF29 R1653 0_0402_5% @
1 2 M16 AVDD33_USB_P1 AC26 1 2
VDD18_6583 AVDD18_MEMPLL AVDD18_USB_P1 VDD18_6583
0_0402_5% -22mil 1 1 1 M15 AE28 2 2 1 R1629 0_0402_5% -22mil
C1610 C1618 C1621 AVSS18_MEMPLL AVSS33_USB_P1 C1640 C1641 C1673

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402


2 2 2 MT8389E1_PCDDR3 1 1 2

@ 8125 footprint

1.8V IO for DDR


1.2V IO for DDR2
DDR3VCCIO 1.5V IO for DDR3
1.35V IO for DDR3L : Default
U201B
C R1639 C
C5 H10 1 2
GND DVDD18_EMI VM_PMU
C8 H19 1 1 1 1 1
C21 GND DVDD18_EMI H20 C1665 C1661 C1662 C1663 C1664 0_0805_5%
C24 GND DVDD18_EMI J10
GND DVDD18_EMI

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402


D7 J11

2.2U_0402_6.3VM
D9 GND DVDD18_EMI J17 2 2 2 2 2
D11 GND DVDD18_EMI J18
D18 GND DVDD18_EMI J19
D20 GND DVDD18_EMI J20
D22 GND DVDD18_EMI K13
J6 GND DVDD18_EMI K15
J14 GND DVDD18_EMI K20
K10 GND DVDD18_EMI
K11 GND R24 0_0402_5% -22mil 1 R1654 2
GND DVDD18_MC0 VEMC_1V8_PMU
K12 U1 0_0402_5% -22mil 1 R1640 2 VMC_PMU
K16 GND DVDD33_MC1 Y1 0_0402_5% -22mil 1 R1641 2
GND DVDD33_MC2 VDD28_6583
K17 AE25 0_0402_5% -22mil 1 R1645 2 VDD18_6583
K18 GND DVDD28_BPI AG23
L24 GND DVDD28_BSI AJ22 0_0402_5% -22mil 1 R1643 2
GND DVDD18_BSI VDD18_6583
P11 J29 0_0402_5% -22mil 1 R1658 2 VDD18_6583
P12 GND DVDD18_NML1 Y24 0_0402_5% -22mil 1 R1659 2
GND DVDD28_NML2 VDD18_6583
P13 AF1
P14 GND DVDD18_NML3 F1 0_0402_5% -22mil 1 R1644 2
GND DVDD18_NML4 VDD18_6583
P15 W8
P16 GND DVDD18_MC12
R10 GND N10 0704 ADD C1687 C1686 FOR RF
GND DVDD 2 1 1 1 1 1 1 1 1
R11 N11 C431 C1656 C1657 C1658 C1659 C1660 C1667 C1670 C1671
R13 GND DVDD N12
1U_0402_6.3V6K

GND DVDD
0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402


R14 N13
R16 GND DVDD N14 1 2 2 2 2 2 2 2 2
R18 GND DVDD N15 EMC@ EMC@
R20 GND DVDD N16
GND DVDD 1 12P_0402_50V8 1 12P_0402_50V8
T8 N17
T9 GND DVDD P10 C1687 C1686
GND DVDD DVDD <23>
T11 P17
T13 GND DVDD P18 DVDD 2 1 R1648 2 2
GND DVDD VCORE_PMU
T14 P19 2 1 1 DVDD
B
T16 GND DVDD P20 C457 0_0805_5%
B
GND DVDD 1 1 1 1 1
T18 R17 C1651 C1652 C1653 C1654 C1655
1U_0402_6.3V6K

10U_0402_6.3V6M

10U_0402_6.3V6M
T20 GND DVDD R19 C434 C454 C455
GND DVDD 1 2 2 2 EMC@ 1 1 1 1
0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

U8 T17 22UF 6.3V M X5R 0805 H1.25 33P 50V J NPO 0402 C1674 C1675 C1676 C1677
U11 GND DVDD T19 2 2 2 2 2 R1655 C1756 @ @ @
GND DVDD

0.1U 10V X7R 0402_NC

0.1U 10V X7R 0402_NC

0.1U 10V X7R 0402_NC


12P_0402_50V8
U16 U17 1 2 EMC@
U18 GND DVDD U19 0_0402_5% -22mil 1 2 2 2 2
V6 GND DVDD U20
V7 GND DVDD V17 1 @ 2
GND DVDD DVDD_GPU_R <23>
V8 V20 R1657 0_0402_5%
V11 GND DVDD W20 R1649 0_0603_5%
V16 GND DVDD DVDD_GPU 1 @ 2
GND VGPU_PMU
V18 T10 1 1 2 1
V19 GND DVDD_GPU U9 C1649 C1650 C436 C453
W11 GND DVDD_GPU U10 DVDD_GPU
1U_0402_6.3V6K

10U_0402_6.3V6M

GND DVDD_GPU
0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

W16 V9
W19 GND DVDD_GPU V10 2 2 1 2 DVDD_DVFS <23>
W24 GND DVDD_GPU R1650
GND 2 1 1 EMC@
AA6 R12 DVDD_DVFS 1 2 33P 50V J NPO 0402 C1678 C1679
GND DVDD_DVFS VPROC_PMU C1757

12P_0402_50V8
AD20 R15 1 1 1 1 1 2 1 1 @
GND DVDD_DVFS

0.1U 10V X7R 0402_NC


AD24 T12 C1644 C1645 C1646 C1647 C1648 C446 C449 C450 C451 0_0805_5% EMC@
GND DVDD_DVFS T15 1 2 2
DVDD_DVFS
22UF 6.3V M X5R 0805 H1.25

U12
10U_0402_6.3V6M

10U_0402_6.3V6M
1U_0402_6.3V6K

DVDD_DVFS 2 2 2 2 2 1 2 2
0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

U13
DVDD_DVFS U14 R1660
DVDD_DVFS U15 1 2
AB11 DVDD_DVFS V12 GND_DVDD_DVFS <23>
AD11 VPROC_FB DVDD_DVFS V13
GND_VPROC_FB DVDD_DVFS V14 0_0402_5% -22mil DVDD_DVFS
DVDD_DVFS V15
DVDD_DVFS W12
A1 DVDD_DVFS W15 DVDD_SRAM <23>
NC DVDD_DVFS 1 EMC@ 1 1
A29 R1651 C1680 C1681 C1682
AJ1 NC W13 DVDD_SRAM 1 2 @ @
NC DVDD_SRAM VSRAM_PMU
0.1U 10V X7R 0402_NC

0.1U 10V X7R 0402_NC


12P_0402_50V8
AJ29 W14 1 1 2 1
NC DVDD_SRAM C1642 C1643 C447 C448 0_0603_5% -35mil 2 2 2

A A
10U_0402_6.3V6M
1U_0402_6.3V6K

2 2 1 2
0.1U 10V +-10% X7R 0402

0.1U 10V +-10% X7R 0402

MT8389E1_PCDDR3

DVDD_SRAM
@ 8125 footprint
1
EMC@
C1683
12P_0402_50V8

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/03 2013/11/03 Title
Issued Date Deciphered Date MT8377 - Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 4 of 28
5 4 3 2 1
5 4 3 2 1

VDD18_6583 VDD18_6583 VDD18_6583 VDD18_6583 VDD18_6583

2
R1520 R1522 R1524 R1526 R1528
GLONASS@ @ @ @ @

VDD18_6583 10K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5%

1
0530 Update u201 pcb footprint for layout nc -p MB_ID0 MB_ID1 GPIO_0 GPIO_1 GPIO_2

1
R207 R208

2
4.7K_0402_5%

4.7K_0402_5%
R1521 R1523 R1525 R1527 R1529
NH520@ @ @ @ @
U201A

2
10K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5%

1
AF18 AJ24
D TX_IP UL_I_P1 BPI1_BUS0 BPI1_BUS0 D
AF17 AG26
<12,5> SCL3 TX_IN AF19 UL_I_N1 BPI1_BUS1 AJ27 BPI1_BUS1
<12,5> SDA3 TX_QP UL_Q_P1 BPI1_BUS2 BPI1_BUS2
AF20 AH28
TX_QN UL_Q_N1 BPI1_BUS3 AF27 @ PAD TP1370

VDD18_6583
AG13
AG14 UL_I_P2
BPI1_BUS4
BPI1_BUS5
AG28
AF26
BPI1_BUS4
@ PAD TP1371 Reserve
AF14 UL_I_N2 BPI1_BUS6 AJ25 @ PAD TP1372
UL_Q_P2 BPI1_BUS7 BPI1_BUS7

DVDD28_BPI
AF13 AG27
UL_Q_N2 BPI1_BUS8 AH26 BPI1_BUS8
R217 R218
BPI1_BUS9 BPI1_BUS9
1

1
AJ16 AH24
4.7K_0402_5%

4.7K_0402_5%
RX_IP DL_I_P1 BPI1_BUS10 BPI1_BUS10
AH16 AF24
RX_IN AH18 DL_I_N1 BPI1_BUS11 AJ28 BPI1_BUS11
RX_QP DL_Q_P1 BPI1_BUS12 BPI1_BUS12
0531 Change BOM for MTK AH17 AH25 U201D
RX_QN DL_Q_N1 BPI1_BUS13 AE26 BPI1_BUS13 <6> ED[0..31]
2

AG15 BPI1_BUS16 AH27 @ PAD TP1390 C11 F12


ED31
RXD_BBIP DL_I_P2 BPI1_BUS17 @ PAD TP1362 RDQ31 RCS_ RCS0_R <6>
SCL2 AG16 AE24 DDR3VCCIO ED30 C7 E14
RXD_BBIN AF15 DL_I_N2 BPI1_BUS18 @ PAD TP1361 B12 RDQ30 RCS1_ RCS1_R <6>
SDA2 ED29
RXD_BBQP DL_Q_P2 RDQ29
AF16 AF28 ED28 B5 E16
RXD_BBQN DL_Q_N2 VM0 VM0 RDQ28 RWE_ /EWR <6>
AH29 1 ED27 B11 C14
VM1 VM1 RDQ27 RRAS_ /ERAS <6>

1
VGP2_PMU C205 ED26 A5 B15
RDQ26 RCAS_ /ECAS <6>
AE20 8.06K +-1% 0402 ED25 A12 E13
BSI1A_CS0 BSI-A_EN RDQ25 RCKE ECKE <6>
AG18 AH22 R209 0.1U 10V +-10% X7R 0402 ED24 C6
VBIAS BSI1A_CLK BSI-A_CK 2 RDQ24
AG20 AH21 ED23 D8 A21
WG_GGE_PA_VRAMP APC1 BSI1A_DATA0 BSI-A_DAT0 RDQ23 RDQM0 EDQM0 <6>
AG19 AE21 EVREF ED22 C10 C18
BSI-A_DAT1

1 2
TP1359PAD @ AH20 APC2 BSI1A_DATA1 AG22 <6> EVREF B7 RDQ22 RDQM1 A8 EDQM1 <6>
2 R210 R212 DCOC_Flag BSI-A_DAT2 ED21
TXBPI1 BSI1A_DATA2 RDQ21 RDQM2 EDQM2 <6>
1

1 ED20 D10 C9
4.7K_0402_5%

4.7K_0402_5%

EDQM3 <6>

1
C1754 AE23 8.06K +-1% 0402 C206 C207 ED19 D6 RDQ20 RDQM3
AF21 BSI1B_CS0 RDQ19

DVDD28_BSI
18P_0402_50V8J AF23 R211 1U 10V K X5R 0402 ED18 A9 F23
BSI1C_CLK BSI1B_CLK RDQ18 RDQS0 EDQS0 <6>
EMC@ 1 AH23 AE22 ED17 B8 E20

2
<8> POUT_1 BSI1C_DATA BSI1B_DATA 2 RDQ17 RDQS1 EDQS1 <6>

0.1U 10V +-10% X7R 0402


ED16 B9 E6
2

2
RDQ16 RDQS2 EDQS2 <6>
ED15 C23 F9
B17 RDQ15 RDQS3 E23 EDQS3 <6>
MT8389E1_PCDDR3 ED14
<10,5> SCL1 RDQ14 RDQS0_ /EDQS0 <6>
ED13 A24 F20
<10,5> SDA1 B18 RDQ13 RDQS1_ F6 /EDQS1 <6>
Power by CAM_IO ED12
@ 8125 footprint ED11 C22 RDQ12 RDQS2_ E9 /EDQS2 <6>
/EDQS3 <6>
ED10 D19 RDQ11 RDQS3_
ED9 B24 RDQ10 H16
RDQ9 RCLK0 EDCLK <6>
ED8 A17 H15
B20 RDQ8 RCLK0_ H12 EDCLK_B <6>
VDD18_6583 0521 DEL X602 ED7
C20 RDQ7 RCLK1 H13 EDCLK1 <6>
ED6
RDQ6 RCLK1_ EDCLK1_B <6>
ED5 D21
R219 R220 ED4 C19 RDQ5 G25
RDQ4 NLD15
1

ED3 B21 D28


4.7K_0402_5%

4.7K_0402_5%

ED2 D23 RDQ3 NLD14 F28


ED1 A20 RDQ2 NLD13 F25
ED0 B22 RDQ1 NLD12 E26
RDQ0 NLD11 H25
2

EVREF H14 NLD10 J28


H18 VREF NLD9 E28
VREF NLD8 C29
C <14,5> SCL0 NLD7 C
Power by CTP C15 G28
<14,5> SDA0 <6> EBA2 C12 RBA2 NLD6 H28
<6> EBA1 RBA1 NLD5
B14 B28
<6> EA[0..14] <6> EBA0 D12 RBA0 NLD4 G27
EA14
EA13 D17 RA14 NLD3 H27
EA12 B13 RA13 NLD2 G26
EA11 F16 RA12 NLD1 C28
EA10 D14 RA11 NLD0
EA9 F17 RA10 B29
EA8 F18 RA9 NRNB D27
EA7 C17 RA8 NCLE H26
EA6 E18 RA7 NALE F29
TP1366PAD @ RA6 NWEB
URXD4 EA5 C16 J25
<11> URXD4 SCL0 <14,5> A13 RA5 NREB E29
UTXD4 EA4
<11> UTXD4 SDA0 <14,5> A15 RA4 NCEB0 H29
EA3
TP1369PAD @ SCL1 <10,5> RA3 NCEB1
EA2 D13
SDA1 <10,5> E12 RA2 N19
SCL2 EA1
<9> URXD3 SCL2 <7> RA1 TP_MEMPLL
SDA2 0509 Change EA0 E11 N18
<9> UTXD3 SDA2 <7> RA0 TN_MEMPLL
SCL3 <12,5> E17 E15
SDA3 <12,5> <6> ERESET_ DDR3RSTBREXTDN
<TESTMODE> URXD2 1
<11> URXD2

1
Connect to VIO18 : Enter Test Mode UTXD2 C1611
<11> UTXD2
EMC@ MT8389E1_PCDDR3 R204
Connect to GND : Normal mode GPIO_SUB_CMPDN <10>

12P_0402_50V8
GPIO_1 68 +-1% 0402
GPIO_2 2 @
<FSOURCE_P> CABC_ENABLE1
@ 8125 footprint

2
Connect to VGP6 (2v0) : w/i EFUSE program GPIO_0
URXD1
Connect to GND : w/o EFUSE program <21> URXD1 CABC_ENABLE0
UTXD1 MB_ID1
<21> UTXD1

AA29
AA26
AA28
W26

W28

W25

AG5

W27
AH5
AE9
AF9

AF5
Y27
Y26
Y29
Y25

V24

V25

Y28

V29
V28

AJ6
D2
C1
B3

A2
B1
F4

U201C
UTXD1
URXD1
UCTS1
URTS1

UTXD2
URXD2
UCTS2
URTS2

UTXD3
URXD3

UTXD4
URXD4

SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3

PWM1
PWM2
PWM3
PWM4
SPI1_MO
SPI1_CSN

SPI1_MI
SPI1_CLK
U201E
EMC@
1 2 SYSCLK1 AJ19 R29 P8 AD1
<7> CLK1_BB_R2 AJ14 CLK26M1 SYSRSTB SYSRST_B <11,15,23,7> R7 TCP DPIVSYNC AC2 DPI_VSYNC <7>
R634 0_0402_5% VDD28_NML2
CLK26M2 VDD28_NML2 VDD28_NML2 TCN DPIHSYNC DPI_HSYNC <7>
AJ21 R3 AF4
P25 EXT_CLK_EN E5 @ PAD TP1358 P3 TDP0 DPIDE AJ2 DPI_DE <7>
<23,7> RTC32K1V8 RTC32K_CK SRCLKENAI SRCLKENAI <9> TDN0 DPICK DPI_PCLK <7>
P26 P4
L25 SRCLKENA AF22 SRCLKENA <23,7> R4 TDP1 AE5
TESTMODE SRCLKENA2 SRCLKENA2 <23>
EINT0 : Gyro-Sensor TDN1 DPIR0 DPI_R0 <7>
D24 P29 EMC@ EINT1 : SIM R1 AG3
FSOURCE_P SRCVOLTEN SRCVOLTEN <23,7> TDP2 DPIR1 DPI_R1 <7>
EINT2 : G-Sensor R2 AB2
R28 L29 P7 TDN2 DPIR2 AD5 DPI_R2 <7>
0_0402_5%
<23> WATCHDOG_B WATCHDOG PWRAP_SPI0_CSN M29
PWRAP_SPI0_CSN <23>
1 R636 2 EINT3 : PMU MT6320 P6 TDP3 DPIR3 AF2
DPI_R3 <7>
U24 PWRAP_SPI0_CLK M26 PWRAP_SPI0_CLK <23> TDN3 DPIR4 AD2 DPI_R4 <7>
<11> MCU_JTCK JTCK PWRAP_SPI0_MI PWRAP_SPI0_MI <23> 1 DPIR5 DPI_R5 <7>
Close to MT6583 U28 M28 EINT5 : CTP M4 AC4
B <11> MCU_JTDO JTDO PWRAP_SPI0_MO PWRAP_SPI0_MO <23> <10> RCP RCP DPIR6 DPI_R6 <7>
<11> MCU_JTRST_B
T25 L28
PWRAP_EVENT <23>
@ C1736 EINT6 : MT3332 <10> RCN
N4 AG2
DPI_R7 <7>
B
JTRST_B PWRAP_EVENT RCN DPIR7

MIPI function only


R201 U29 33P 50V J NPO 0402 5/23 ADD FOR RF EINT8 : MT6628 BGF L1
<11> MCU_JTDI JTDI 2 <10> RDP0 RDP0
5.11K +-1% 0402 U25 K25 EINT9 : MT6628 WiFi M1 AC1
2 1 <11> MCU_JRTCK V26 JRTCK ADC_CLK K26 ADC_CLK <24> <10> RDN0 N3 RDN0 DPIG0 AB5 DPI_G0 <7>
<11> MCU_JTMS JTMS ADC_WS K28 ADC_WS <24> <10> RDP1 M3 RDP1 DPIG1 AH1 DPI_G1 <7>
ADC_DAT_IN ADC_DAT_IN <24> EINT10 : HEADSET <10> RDN1 RDN1 DPIG2 DPI_G2 <7>
USB_VRT AD28 M27 M2 AD3
1 R222 2 AE27 USB_VRT DAC_CLK L26 DAC_CLK <24> N2 RDP2 DPIG3 AD6 DPI_G3 <7>
VBUS USB_VBUS DAC_WS DAC_WS <24> RDN2 DPIG4 DPI_G4 <7>
4.99M +-1% 0402 AC27 L27 P2 AA5
<17> USB_DP AB27 USB_DP_P0 DAC_DAT_OUT DAC_DAT_OUT <24> P1 RDP3 DPIG5 AH2 DPI_G5 <7>
90 Ohm <17> USB_DM USB_DM_P0 RDN3 DPIG6 DPI_G6 <7>
1 R221 2 R26 N25 AA2
1M_0402_1% differential
<17> USB_ID IDDIG SIM1_SCLK M25
SIM1_SCLK <24>
L4 DPIG7 DPI_G7 <7>
2 R1765 1 0_0402 AE29 SIM1_SIO P28 SIM1_SIO <24> <10> CMDAT9 K4 RCP_A AC3
USB11_DP
<18> USB11_DP_P USB_DP_P1 SIM1_SRST SIM1_SRST <24> 5/22 gpio change for SW <10> CMDAT8 RCN_A DPIB0 DPI_B0 <7>
2 R1766 1 0_0402 USB11_DM AD29 M24 UART1: Debug/MT3332 L3 AC5
<18> USB11_DM_N USB_DM_P1 SIM2_SCLK N24 @ PAD TP1374 <10> CMVREF K3 RDP0_A DPIB1 AG1 DPI_B1 <7>
0605 Change bom structure SIM2_SIO UART2: <10> CMHREF RDN0_A DPIB2 DPI_B2 <7>
AB25 N28 05/20 Change GPIO from SOC to PMIC K2 AB4
<23> CHD_DP CHD_DP_P0 SIM2_SRST <10> CMDAT7 RDP1_A DPIB3 DPI_B3 <7>
<23> CHD_DM
AA25
CHD_DM_P0
Add TP1378 0808 LTE_ON_OFF# GPS_OFF# LTE_RESET UART3: MT6628 <10> CMDAT6
L2
RDN1_A DPIB4
Y5
DPI_B4 <7>
T28 AE2
EINT0 T27
EINT_GY <12> add GPIO PIN for GPIO_SW LED_Signal_EN 0522 UART4: Debug J4 DPIB5 AD4
DPI_B5 <7>
B2 EINT1 T26 @ PAD TP1378 <10> CMDAT5 H4 RCP_B DPIB6 AA1 DPI_B6 <7>
<9> DAICLK C2 MRG_I2S_PCM_CLK EINT2 R27 GPIO_SW1 <12> <10> CMDAT4 J3 RCN_B DPIB7 DPI_B7 <7>
<9> DAIPCMIN MRG_I2S_PCM_RX EINT3 EINT_PMU <23> RDP0_B
C3 R25 MB_ID0 I2C0 : CTP H3
<9> DAISYNC E2 MRG_I2S_PCM_SYNC EINT4 AE8 MB_ID0 Change from AH4 to R25 J2 RDN0_B G3
<9> DAIPCMOUT
E1 MRG_I2S_PCM_TX EINT5 AH8
EINT_CTP <14> I2C1 : Sub Camera <10> CMDAT3
J1 RDP1_B CMMCLK H2
CMMCLK <10>
<9> DAIRST DAI_RSTB EINT6 MT8389_EINT_MT3332 <21> <10> CMDAT2 RDN1_B CMRST CMRST <10>
EINT7
AG8
LED_Signal_EN <7> I2C2 : CMPCLK
G4
CMPCLK <10>
AG9 AJ8 5/22 add LED_Signal EN gpio pin for panel F2
<7> I2S0_CK
AH9 I2S_CLK EINT8 AF8
EINT_6628_BGF <9> I2C3 : G/GYRO sensor MIPI_VRT R6 CMPDN G2
CMPDN <10>
<7> I2S0_WS I2S_WS EINT9 EINT_6628_WIFI <9> VRT CMFLASH
I2S0_DAT_IN
AJ9
I2S_DATA_IN EINT10_AUXIN2
AD10
EINT_HP <8>
I2C4 (PMIC) : Charger IC
AD8 AE10
<7> I2S0_DAT_OUT CHG_TEMP <22> I2C5 (PMIC) :

1
I2S_DATA_OUT EINT11_AUXIN3 AF10
EINT16_AUXIN4 MT8193_INT <7> 0509 Change I2C6 (PMIC) : R203 MT8389E1_PCDDR3
AJ3 ADD C79 FOR EMI 8/1 1.5K_0402_1%
AH11 LSCE0B AJ5 MT8389_GPIO_GPS_EN<21>
TP1357PAD @
AH10 AUXIN0 LSCE1B AG4 5/10 1
GPIO_CTP_RST <14> @ 8125 footprint

2
AUXIN1 LSCK AH3 MODE4/6 : MD1/2_GPS_SYNC DPI1_CK <7>
C79 I2S :
AF12 LSDA AE6 GPIO_6628_GPS_SYNC <9>
EMC@
AUX_XP LSA0 LED_EN <7>
AE11 AH6 0.1U 10V +-10% X7R 0402
AE12 AUX_XM LRSTB AH4 GNSS_HRST <21> 2
AG12 AUX_YP
DVDD33_MC2 DVDD33_MC1
LPCE0B AF6
GPIO_HDMI_POWER_EN <7> MSDC0 : eMMC Close to MT6583
MSDC2_SDWPI

MSDC1_SDWPI

AUX_YM LPCE1B AH7 MT8389_GPIO_FRAME_SYNC <21> MSDC1 : SD Card


MSDC0_RSTB
MSDC3_DAT3
MSDC3_DAT2
MSDC3_DAT1
MSDC3_DAT0

MSDC2_DAT3
MSDC2_DAT2
MSDC2_DAT1
MSDC2_DAT0

MSDC1_DAT3
MSDC1_DAT2
MSDC1_DAT1
MSDC1_DAT0

MSDC0_DAT7
MSDC0_DAT6
MSDC0_DAT5
MSDC0_DAT4
MSDC0_DAT3
MSDC0_DAT2
MSDC0_DAT1
MSDC0_DAT0
MSDC3_CMD

MSDC2_CMD

MSDC1_CMD

MSDC0_CMD

LPTE LCM_BL_EN <7>


MSDC2_INSI

MSDC1_INSI
MSDC3_CLK

MSDC2_CLK

MSDC1_CLK

MSDC0_CLK

AH12 VDD18_6583 MSDC2 : GPIO (2.8V)


REFP @ PAD TP1360
AH13 AE7
REFN DISP_PWM LCD_PWM <7> MSDC3 : MT6628
1

C213
1U 10V K X5R 0402
MT8389E1_PCDDR3
2

D3
D4
B4
A4
C4
D5

W5
W2
Y4
V4
W3
W4
V5
Y3

T5
V2
T4
V1
U2
U5
U6
Y2

D26
B27
A27
A25
D25
B25
C26
B26
C27
A28
E25

@ AH4 NEED CHANGE


eMMC_RST <13>

2
8125 footprint eMMC_CMD <13>
eMMC_CLK <13>
R1869 @ @ R1872
A A
Close to MT6583 eMMC_DAT0 <13>
10K_0402_5% 10K_0402_5%
<9> MC3DA3 eMMC_DAT1 <13>

1
<9> MC3DA2 eMMC_DAT2 <13>
<9> MC3DA1 eMMC_DAT3 <13>
GPIO_CTP_RST
<9> MC3DA0 eMMC_DAT4 <13>
<9> MC3CLK eMMC_DAT5 <13>
EINT_CTP
<9> MC3CMD eMMC_DAT6 <13>
eMMC_DAT7 <13>
0603 ADD PULL HIGH
<9> GPIO_6628_GPS_LNA_EN 0730 change bom structure for MTK recommend
<9> GPIO_6628_PMU_EN MC1INSI <17>
LCM_RST_2V8
LCM_STBY_2V8 MC1CM <17>
MC1CK <17>
MC1DA0 <17>
MC1DA1 <17>
MC1DA2 <17>
MC1DA3 <17>
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/11/03 2013/11/03 Title
Issued Date Deciphered Date MT8377 - Baseband
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 5 of 28
5 4 3 2 1
5 4 3 2 1

ZZZ

U5 U6 EDCLK
DDR3L NAN 256Mx16@

2
EVREF M8 E3 ED3 EVREF M8 E3 ED20 X76521BOL01
<5,6> EVREF VREFCA DQL0 <5,6> EVREF VREFCA DQL0
H1 F7 ED6 H1 F7 ED19 100_0201_5% ALT. GROUP PARTS NANYA 1G ZEJ00
VREFDQ DQL1 F2 ED2 VREFDQ DQL1 F2 ED22
1 DQL2 1 DQL2
C61 EA0 N3 F8 ED5 C69 EA0 N3 F8 ED23 R525 ZZZ
EA1 P7 A0 DQL3 H3 ED1 EA1 P7 A0 DQL3 H3 ED18

1
A1 DQL4 A1 DQL4

0.1U 6.3V K X5R 0201


EA2 P3 H8 ED4 0.1U 10V +-10% X7R 0402 EA2 P3 H8 ED21 EDCLK_B
2 EA3 N2 A2 DQL5 G2 ED0 2 EA3 N2 A2 DQL5 G2 ED16
EA4 P8 A3 DQL6 H7 ED7 EA4 P8 A3 DQL6 H7 ED17
EA5 P2 A4 DQL7 EA5 P2 A4 DQL7
EA6 R8 A5 EA6 R8 A5 EDCLK1 HYN 256Mx16@
A6 A6 DDR3L
EVREF EA7 R2 D7 ED8 EVREF EA7 R2 D7 ED30 X76521BOL02
A7 DQU0 A7 DQU0

2
D D
EA8 T8 C3 ED13 EA8 T8 C3 ED29 ALT. GROUP PARTS HYNIX 1G ZEJ00
EA9 R3 A8 DQU1 C8 ED14 EA9 R3 A8 DQU1 C8 ED28 100_0201_5%
1 A9 DQU2 1 A9 DQU2
C66 EA10 L7 C2 ED15 C65 EA10 L7 C2 ED25
EA11 R7 A10/AP DQU3 A7 ED10 EA11 R7 A10/AP DQU3 A7 ED24 R526
A11 DQU4 A11 DQU4

0.1U 6.3V K X5R 0201


EA12 N7 A2 ED9 0.1U 10V +-10% X7R 0402 EA12 N7 A2 ED31 0605 Change bom X76 Part number

1
2 EA13 T3 A12 DQU5 B8 ED12 2 EA13 T3 A12 DQU5 B8 ED26 EDCLK1_B
EA14 T7 A13 DQU6 A3 ED11 EA14 T7 A13 DQU6 A3 ED27
M7 A14 DQU7 M7 A14 DQU7
A15/BA3 A15/BA3
ED0 DDR3VCCIO DDR3VCCIO
ED1 EBA0 M2 B2 EBA0 M2 B2
ED2 EBA1 N8 BA0 VDD D9 EBA1 N8 BA0 VDD D9
ED3 EBA2 M3 BA1 VDD G7 EBA2 M3 BA1 VDD G7 Vendor X76 level BOM structure
ED4 BA2 VDD K2 BA2 VDD K2
ED5 VDD K8 VDD K8
ED6 VDD N1 VDD N1 NANYA-1G X76521BOL01 NAN 256Mx16@
ED7 J7 VDD N9 J7 VDD N9
ED8
<5> EDCLK
K7 CK VDD R1
<5> EDCLK1
K7 CK VDD R1 HYNIX-1G X76521BOL02 HYN 256Mx16@
<5> EDCLK_B K9 CK VDD R9 <5> EDCLK1_B K9 CK VDD R9
ED9 ECKE ECKE
ED10 CKE/CKE0 VDD CKE/CKE0 VDD
ED11
ED12 RODT1_R K1 A1 RODT2_R K1 A1
ED13 RCS0_R L2 ODT/ODT0 VDDQ A8 RCS1_R L2 ODT/ODT0 VDDQ A8
ED14 /ERAS J3 CS/CS0 VDDQ C1 /ERAS J3 CS/CS0 VDDQ C1
ED15 /ECAS K3 RAS VDDQ C9 /ECAS K3 RAS VDDQ C9
ED16 /EWR L3 CAS VDDQ D2 /EWR L3 CAS VDDQ D2
ED17 WE VDDQ E9 WE VDDQ E9
ED18 VDDQ F1 VDDQ F1
ED19 F3 VDDQ H2 F3 VDDQ H2
<5> EDQS0 DQSL VDDQ <5> EDQS2 DQSL VDDQ
ED20 C7 H9 C7 H9
<5> EDQS1 DQSU VDDQ <5> EDQS3 DQSU VDDQ
ED21
ED22 U5 U6
ED23 E7 A9 E7 A9 @ @
<5> EDQM0 D3 DML VSS B3 <5> EDQM2 D3 DML VSS B3
ED24
<5> EDQM1 DMU VSS <5> EDQM3 DMU VSS
ED25 E1 E1
ED26 VSS G8 VSS G8 NANYA-1G SA00006UM10 SA00006UM10
ED27 G3 VSS J2 G3 VSS J2
<5> /EDQS0 DQSL VSS <5> /EDQS2 DQSL VSS 256M16 NT5CC256M16BP-DI 256M16 NT5CC256M16BP-DI
C ED28 B7 J8 B7 J8 C
<5> /EDQS1 DQSU VSS M1 <5> /EDQS3 DQSU VSS M1
ED29
ED30 VSS M9 VSS M9 U5 U6
<5> ED[0..31] VSS VSS
ED31 P1 P1 @ @
ERESET_ T2 VSS P9 ERESET_ T2 VSS P9
RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 HYNIX-1G SA00005AV50 SA00005AV50
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

R65 256M16/1600 H5TC4G63AFR-PBA 256M16/1600 H5TC4G63AFR-PBA

1
R71
240_0201_1% J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 240_0201_1% L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
2

L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8

2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
<5> EBA1 VSSQ E8 VSSQ E8
<5> /EWR VSSQ VSSQ
F9 F9
<5> ECKE VSSQ G1 VSSQ G1
<5> EBA0 VSSQ VSSQ
G9 G9
<5> ERESET_ VSSQ VSSQ
<5> EBA2
96-BALL 96-BALL
<5> /ERAS
SDRAM DDR3 SDRAM DDR3
<5> /ECAS
H5TC4G63MFR-PBA 96P H5TC4G63MFR-PBA 96P
@ DDR3VCCIO @ DDR3VCCIO
DDR3L DDR3L

1
R75 @ @ R73
0_0201_5% 1K_0201_1%
2

2
RCS0_R RODT1_R RODT2_R RCS1_R
<5> RCS0_R <5> RCS1_R
1

1
R77 R70
@ R76 R72 @
1K_0402_1% 1K_0201_1% 1K_0201_1% 1K_0402_1%
2

2
B
U5 Test Point B
/ERAS
TP01 PAD @
/ECAS
TP02 PAD @
/EWR
TP03 PAD @
DDR3VCCIO DDR3VCCIO
DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO
0.1U 6.3V K X5R 0201

EBA1
TP06 PAD @
1 1 1 1 1 1 1 1
C71 C56 C60 C67 C1619 C1630 C1634
C78
0.1U 10V +-10% X7R 0402 0.1U 10V +-10% X7R 0402 2.2U_0402_6.3VM 2.2U_0402_6.3VM 2.2U_0402_6.3VM
0.1U 10V +-10% X7R 0402 2 2 2 2 2 2 2 0.1U 10V +-10% X7R 0402 2
<5> EA[0..14]
EA0
EA1 EA9
TP13 PAD @
EA2 DDR3VCCIO DDR3VCCIO
EA3 DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO
0.1U 6.3V K X5R 0201

0.1U 6.3V K X5R 0201

0.1U 6.3V K X5R 0201


EA4
0.1U 6.3V K X5R 0201

0.1U 6.3V K X5R 0201

EA5 1 1 1 1 1 1 1 1
EA6 C62 C70 C74 C54 C1620 C1629 C1633 C57 ED15
TP18 PAD @
EA7
EA8 2.2U_0402_6.3VM 2.2U_0402_6.3VM 2.2U_0402_6.3VM
EA9 2 2 2 2 2 2 2 2 0606 DEL 4 PCS TEST POINT
EA10 U6 Test Point
EA11
EA12 DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO /ERAS
TP19 PAD @
EA13 /ECAS
TP20 PAD @
EA14 1 1 1 1 1 1 1 1 1 /EWR
TP21 PAD @
0.1U 6.3V K X5R 0201

C73 C58 C63 C68 C1626 C1632 C1636 C76 C1669


EBA0
TP23 PAD @
0.1U 10V +-10% X7R 0402 0.1U 10V +-10% X7R 0402 2.2U_0402_6.3VM 2.2U_0402_6.3VM 2.2U_0402_6.3VM 0.1U 6.3V K X5R 0201 2.2U_0402_6.3VM
2 2 2 2 2 2 2 2 2
0.1U 10V +-10% X7R 0402

DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO DDR3VCCIO

1 1 1 1 1 1 1 1 1
0.1U 6.3V K X5R 0201

0.1U 6.3V K X5R 0201

0.1U 6.3V K X5R 0201

C64 C72 C75 C59 C1627 C1631 C1635 C77 C1668


A A
0.1U 6.3V K X5R 0201

2.2U_0402_6.3VM 2.2U_0402_6.3VM 2.2U_0402_6.3VM 0.1U 6.3V K X5R 0201 2.2U_0402_6.3VM


2 2 2 2 2 2 2 2 2 ED21
TP34 PAD @
ED30
TP35 PAD @
ED31
TP36 PAD @

DDR3VCCIO

1
C1617
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/11/03 2013/11/03 Title
2.2U_0402_6.3VM
Issued Date Deciphered Date Memory (DDR3)
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 6 of 28
5 4 3 2 1
5 4 3 2 1

NEED CHECK DEL OR NOT?


VGP6_PMU for LCM 3.3V
LCM_DIMO_R
CABC_ENABLE1 <5> Differential Signal !
0526 Change net name No Through Hole ! JP1
CABC_ENABLE0 <5> 1
LVDS_SHUTDOWN_N L3502 DLP11TB800UL2L_4P 100 ohm - Impedance HTPLG
VGP1_PMU VCD_VDD HDMI_DAT2_P 1 2 2 HP_DET
HDMI_DAT2_P_C 3 Utility
LCM_RIN0-_C 4 3LCM_RIN0- 4 D2+
D2_Shield

2
HDMI_DAT2_M 4 3 HDMI_DAT2_M_C 5
need check vcom 0513 R5131 @ R5132 HDMI_DAT1_P_C 6 D2-
0_0402_5% 1 2LCM_RIN0+ 7 D1+
0_0402_5% -22mil LCM_RIN0+_C EMC@
D1_Shield
HDMI_DAT1_M_C 8 20
JP8 L3507 DLP11TB800UL2L_4P HDMI_DAT1_P 4 3 HDMI_DAT0_P_C 9 D1- GND0 21

1
D0+ GND1

1
1 LCM_VDD EMC@ 10 22
1 2 LCM_RIN1-_C 4 3LCM_RIN1- HDMI_DAT0_M_C 11 D0_ShieldGND2 23
2 3 HDMI_DAT1_M 1 2 HDMI_CK_P_C 12 D0- GND3
3 4 13 CK+
4 5 LCM_RIN1+_C 1 2LCM_RIN1+ L3501 DLP11TB800UL2L_4P HDMI_CK_M_C 14 CK_Shield
5 6 0527 ADD GND FOR Dummy pin HDMI_CEC 15 CK-
6 EMC@ CEC
7 L3505 DLP11TB800UL2L_4P 16
7 8 LCM_RIN0-_C HDMI_SC 17 DDC/CEC_GND
8 EMC@ SCL
9 LCM_RIN0+_C LCM_RIN2-_C 4 3LCM_RIN2- L3503 DLP11TB800UL2L_4P HDMI_SD 18
9 10 HDMI_DAT0_P 1 2 HDMI_VCC 19 SDA
D 10 11 LCM_RIN1-_C +5V D
11 12 LCM_RIN1+_C LCM_RIN2+_C 1 2LCM_RIN2+ 5V_DDC
12 13 HDMI_DAT0_M 4 3 0_0402_5% -22mil
13 CONN@
14 LCM_RIN2-_C L3506 DLP11TB800UL2L_4P 1 R5150 2
14 15 LCM_RIN2+_C EMC@
15 EMC@ 1

1
16 LCM_CLKIN-_C 4 3LCM_CLKIN- C4224 C4225
16 17 LCM_CLKIN-_C HDMI_CK_P 4 3
17 18 LCM_CLKIN+_C 0.1U_0402_25V4Z 10U_0603_25V6M

2
18 19 LCM_CLKIN+_C 1 2LCM_CLKIN+ 2
19 20 LED_ID1 HDMI_CK_M 1 2
20 21 LED_ID2 L3508 DLP11TB800UL2L_4P
21 22 L3504 DLP11TB800UL2L_4P
22 EMC@
23 2 R5154 1 LCD_PWM_R 5/22 ADD L for RF require EMC@
23 24 0_0402 5/24 swap for layout
24 25 HTPLG
25 +LEDVDD
26
31 26 27
G1 27

2
32 28
33 G2 28 29 LED_Signal_EN_R
34 G3 29 30 0_0402_5% -22mil need check GPIO_HDMI_POWER_EN 0_0402
G4 30 NEED CHECK LCM_EL_EN 3.3V_R 1 R5192 2 U4030 R5162
3.3V
1 7
<5> GPIO_HDMI_POWER_EN SHDN TP

1
6 0_0402_5% -22mil
C4241 2 1 0.1U_0402_16V4Z 2 C- HDMI_HPD
1 R5194 2 0_0402_5% MT8193_AVDD33_HDMI C4242 2 1 0.1U_0402_16V4Z GND 5 2 R5165 1
3.3V VIN VBAT

2
@ C4243 2 1 0.1U_0402_16V4Z 5V_DDC 3
C4244 2 1 0.1U_0402_16V4Z VOUT 4 D812
C+ 2 1 1

1U_0603_10V6K
C4245 2 1 0.1U_0402_16V4Z C4229 TVNST52302AB0 SOT523

1
VDD18_6583

C4228
C4226 C4227 @
LED_ID1 LCM_VDD DEL R FOR Layout 0521 1U 6.3V K X5R 04021U 6.3V K X5R 0402 0.1U_0402_25V4Z
LED_ID2 R5169 1 2 0_0201_5% 1 2 2

1
1 2
1

C4230 1 20.1U_0402_25V4Z MT8193_DVDDIO18_1 R5171 1 2 0_0201_5%


R5179 R5183 C4219 C1755 C4231 1 20.1U_0402_25V4Z MT8193_DVDDIO18_2 R5173 1 2 0_0201_5% 0521 ADD
1U 6.3V K X5R 0402

10K_0402_5% 10K_0402_5% 18P_0402_50V8J C4232 1 20.1U_0402_25V4Z MT8193_DVDDIO18_DPI


R5174 1 2 0_0201_5%
2 1 EMC@
2

VAST_PMU 0521 Change P to 0201


C4233 1 2 MT8193_AVDD28 R5175 1 2 0_0201_5%
VTCXO_1_PMU VDD18_6583
0.1U_0402_25V4Z R5176 2 1 0_0201_5% VDD18_6583 LCM_VDD
VTCXO_2_PMU
1 R5178 2 @
0_0402_5% -22mil
U1A 16V rating

2
VAST_PMU_R C4234 2 1 0.1U_0402_16V4Z
C4235 2 1 0.1U_0402_16V4Z C8 R5197 2 1 0_0402 R214 R1756 05/20 ADD R1754
CK_SEL SRCLKENA <23,5>
C4236 2 1 0.1U_0402_16V4Z D6 R5193 2 1 0_0402 100K_0402_5% 10K_0402_5%
EN_BB SRCVOLTEN <23,5>
C4237 2 1 0.1U_0402_16V4Z B9 D8 R5191 2 1 0_0402
NLD0 RESET_N SYSRST_B <11,15,23,5>
C4238 2 1 0.1U_0402_16V4Z D9 control D7 R5190 2 1 0_0402

1
NLD1 INT MT8193_INT <5>
C4239 2 1 0.1U_0402_16V4Z B10 A7 R5187 2 1 0_0402
NLD2 RTC_32K_CK RTC32K1V8 <23,5>

2
G
C C4240 2 1 0.1U_0402_16V4Z C9 NFI_CPU E11 C
A10 NLD3 SCL E12 SCL2 <5>
U1B
NLD4 SDA SDA2 <5>
D10 3 1 LED_Signal_EN_R
B11 NLD5 <5> LED_Signal_EN

D
3.3V_R A3 D11 NLD6
DVDDIO33_18_NFI E4 VAST_PMU_R A11 NLD7 A14 DPI_B0 Q2 BSS138W-7-F_SOT323-3
MT8193_AVDD33_HDMI C1 DVDD12_1 E7 D12 NREB DPI0D0 C13 DPI_B1
VAST_PMU_R K3 AVDD33_HDMI DVDD12_2 E8 B12 NWEB DPI0D1 B14 DPI_B2
VAST_PMU_R L1 AVDD12_HDMI_C
AVDD12_HDMI_D
DVDD12_2
DVDD12_2
F8 C12 NALE
NCLE
MT8193 DPI0D2
DPI0D3
D13 DPI_B3
F4 G8 B13 B15 DPI_B4
H3 AVSS12_HDMI DVDD12_2 H10 NRNB BGA-150 DPI0D4 A15 DPI_B5 3.3V VEMC_3V3_PMU
AVSS12_HDMI DVDD12_3 DPI0D5
power domain

K4 J9 C14 DPI_B6
AVSS12_HDMI DVDD12_4 B7 DPI0D6 E13 DPI_B7
MT8193_AVDD28 L2 DVSS12 G5 B6 DPI0 DPI0D7 E15 DPI_G0 1 R5205 2
M4 AVDD28 DVSS12 G6 0530 Update u1 pcb footprint for layout nc -p C5 NFRBN DPI0D8 E14 DPI_G1
AVSS28 DVSS12 G7 B5 NFCLE DPI0D9 G14 DPI_G2 0_0603_5% -35mil
3.3V_R P2 DVSS12 G9 A5 NFALE DPI0D10 F13 DPI_G3
VAST_PMU_R R1 AVDD33_PLLGP DVSS12 G12 C4 NFWEN DPI0D11 H14 DPI_VSYNC 5V_DDC
N3 AVDD12_VPLL DVSS12 F5 B3 NFREN DPI0VSYNC G13 DPI_HSYNC
AVSS12_VPLL DVSS12 H7 A2 NFCEN DPI0HSYNC H15 RGB_CK R5170

1.8K +-1% 0402


DVSS12 NFD7 DPI0CK

1
3.3V_R R10 H8 B2
VAST_PMU_R R2 AVDD33_LVDSA DVSS12 H9 A1 NFD6
N6 AVDD12_LVDSA DVSS12 H11 B1 NFD5 NFI_NAND
M8 AVSS12_LVDSA DVSS12 H12 C2 NFD4 J13 DPI_R0
M7 AVSS12_LVDSA DVSS12 J6 D4 NFD3 DPI1D0 J14 DPI_R1 HDMI_SC

2
AVSS12_LVDSA DVSS12 J7 C3 NFD2 DPI1D1 J15 DPI_R2 DDC_SC1 R5172 2 HDMI_SC
3.3V_R R11 DVSS12 J8 D5 NFD1 DPI1D2 K13 DPI_R3 0_0201_5% HDMI_SD
DVDDIO33_DGO DVSS12 J11 0605 Change R5218 P/N FOR LOAD BOM NFD0 DPI1 DPI1D3 L15 DPI_R4 5V_DDC
MT8193_DVDDIO18_DPI J12 DVSS12 K6 DPI1D4 L14 DPI_R5
DVDDIO18_33_DPI DVSS12 DPI1D5

2
K7 R5218 1 2 2.49K_0402_1% D1 M14 DPI_R6 R5177
DVSS12 HDMI_EXT_RES DPI1D6

1
MT8193_DVDDIO18_2 A8 K8 HDMI_CK_M F2 N14 DPI_R7 D814

1.8K +-1% 0402


MT8193_DVDDIO18_1 A13 DVDDIO18_33 DVSS12 K9 HDMI_CK_P F1 CLK_M DPI1D7 N15 DPI1_CLK TVNST52302AB0 SOT523
DVDDIO18_33 DVSS12 P10 HDMI_DAT0_M F3 CLK_P DPI1CK @
1 R5219 2 N13 DVSS12 HDMI_DAT0_P G3 CH0_M 0521 Change R to 0201
0_0201_5% EFUSE HDMI_DAT1_M H1 CH0_P R5182

MT8193

1
HDMI_DAT1_P H2 CH1_M HDMI M12 R5220 1 2 0_0201_5% DDC_SD1 2 HDMI_SD
CH1_P I2S_BCK I2S0_CK <5>
HDMI_DAT2_M H4 (analog) I2S L13 R5222 1 2 0_0201_5% 0_0201_5%
CH2_M I2S_LRCK I2S0_WS <5>
HDMI_DAT2_P J4 L12 R5223 1 2 0_0201_5%
CH2_P I2S_DATA I2S0_DAT_OUT <5>
<BOM Structure>
3.3V Q26 AO3413_SOT23-3
0604 Change D815 for ME HDMI_HPD P15 N1
1 3 MT8193_AVDD33_HDMI DDC_SD R14 HTPLG HDMI XTALI N2
D

D815 DDC_SC R15 HDMISD (digital) DCXO XTALO L4 MT8193_CLKBUF_1 0521 Change P to 0201
1 R5225 2 2 1 HDMI_CEC P14 HDMISCK CLKBUF1 L5 MT8193_CLKBUF_2
3.3V CEC CLKBUF2
27K +-1% 0402 M3 MT8193_CLKBUF_3
G
2

3.3V RB551V-30_SOD323-2 CLKBUF3 1 R5226 2 0_0201_5% MT8193_CLKBUF_1


<5> CLK1_BB_R2
@ @
1 R5221 2 1 R5230 2 0521 Change P to 0201 1 R5227 2 100_0201_5% P3
47K +-5% 0402 47K +-5% 0402 LCM_RIN0- P4 TP_VPLL L10 X605 C4248
B 0530 add R5230 and NC R5221 FOR MTK LCM_RIN0+ R4 AO0N G0 K11 3 4 2 1 MT8193_CLKBUF_2 B
VDD18_6583 AO0P B5 OUT GND <9> CLK2_WCN_R
0730 change R5227 bom structure LCM_RIN1- N4 M10
AO1N B4
1

D for MTK recommend LCM_RIN1+ N5 LVDS RGB N10 1000P_0402_50V7K


2 QL1 LCM_RIN2- P6 AO1P B3 L11
BSS138W-7-F_SOT323-3 LCM_RIN2+ R6 AO2N B2 P11 2 1 R5228 1 2 0_0402 MT8193_CLKBUF_3
G <24> SYSCLK_PMU
LCM_CLKIN- N7 AO2P B1 R13 GND IN
S
3

LCM_CLKIN+ N8 AOCK0N B0 N11


AOCK0P VCLK 26MHZ_7.3PF_TZ1689A
LCM_RIN3- R8 P13
LCM_RIN3+ P8 AO3N HSYNC N12
AO3P VSYNC
0605 Change Q26 QL1 P/N FOR LOAD BOM
0605 DEL R5224

0527 ADD R5229 FOR power consumption measure @


1 2 Backlight
R1662 0_0603_5%
<5> DPI_B0 LCM_VDD 0526 Change net name
<5> DPI_B1 VDD18_6583
<5> DPI_B2 VBAT +LEDVDD
U8 W=60mils
<5> DPI_B3
U87
<5> DPI_B4
1 R5229 2 6 1 1 6
<5> DPI_B5 IN OUT 1 2 3 VCCA VCCB 4 1 2
0_0402 <5> LCD_PWM LCD_PWM_R
<5> DPI_B6 A B
0.1U_0402_25V6

1 R151 1K_0402_1% 5 2 R205 33_0402_5%


<5> DPI_B7
1

2 1 3 5 C2650 C2651 DIR GND


FLAG SET
1U_0402_6.3V6K
C605

10U_0603_25V6M

@ R1656 100K_0402_5% SN74AVC1T45DCKR_SC70-6


1

1 R1663 SA000029A00
2

<5> DPI_R0 4 2 2
<5> DPI_R1 <5> LCM_BL_EN EN(/EN)
GND
30K_0402_1%

<5> DPI_R2 0604 Change U8.3 to U8.4 G527ATP1U_TSOT23-6


<5> DPI_R3
1

2
2

<5> DPI_R4
<5> DPI_R5
R1646
<5> DPI_R6
100K_0402_5%
<5> DPI_R7
2

0605 DEL U8 FOR LOAD BOM VBAT


R5145 1 EMC@ 2 0_0402_5% DPI1_CLK 5/22 ADD backlight circuit
<5> DPI1_CK 1 2
R5147 1 EMC@ 2 0_0201_5% RGB_CK 0627 update u8 and ADD R1656 R1663 R1642 0_0402_5%
<5>
<5>
DPI_PCLK
DPI_DE @ PAD TP1393
@ 3.3V
1

1 0704 Change C2650 FOR ME C1615


<5> DPI_VSYNC 0704 Change U8
<5> DPI_HSYNC 5/23 ADD FOR RF @ C1748 2.2U_0603_10V6K VCD_VDD
2

33P 50V J NPO 0402 U21


2 1 R387
<5> DPI_G0 IN 5 1 2
A <5> DPI_G1 OUT A
2
<5> DPI_G2 GND
R415 C1685 0_0603_5%
<5> DPI_G3
2 1 3 4 2 1
<5> DPI_G4 @ PAD TP1394 <5> LED_EN

1
SHDN SET
<5> DPI_G5 @ PAD TP1395
0_0402_5% NCT3705U-33_SOT23-5 3300P_0402_50V7K C1616 4.7U_0603_6.3V6K
<5> DPI_G6 @ PAD TP1397
1

2
<5> DPI_G7 @ PAD TP1300

R1638 0605 Change U21 PN for LOAD BOM


100K_0402_5% 0605 ADD C1685 DEL R1685
2

0704 change C1616 and c1685

0606 update R1638 TO @


0613 update R1638
5/22 ADD 3.3v circuit
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/11/03 2013/11/03 Title
Issued Date Deciphered Date LCD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 7 of 23

5 4 3 2 1
5 4 3 2 1

Earphone RECEIVER
<5> EINT_HP
VDD18_6583

close to IC close to connector

1
R1690
D D
1 1 470K_0402_5%
C1699 C1700

2
33P 50V J NPO 0402 R1691 33P 50V J NPO 0402 0704 add c6 for EMI
2 2 1 2 R1692 1 2 HP_MP3L
<12> AU_HPL_R
33_0402_5% 0_0603_5% -35mil
1 1 R1693 0_0402_5% -22mil
C1701 C1702 EMC@ FBMA-L11-160808-700LMT_2P AUDJACK_GND 1 2 AUDJACK_GND_R
L843 1 2 AUDJACK_L
R1694 0605 Update JP2 PCB Footprint
100P_0402_50V8J 100P_0402_50V8J EMC@ FBMA-L11-160808-700LMT_2P
2 R1695 2 1 2 EMC@ L844 1 2 ADDJACK_DET_R
2 1 2 R1696 1 HP_MP3R 47K +-5% 0402 L845 1 2 FBMA-L11-160808-700LMT_2P AUDJACK_R JP2
<12> AU_HPR_R
1 33_0402_5% 0_0603_5% -35mil 1 L846 1 2 FBMA-L11-160808-700LMT_2P AUDJACK_MIC AUDJACK_MIC 1
EMC@ AUDJACK_GND_R 4
C1703 C1704 1 AUDJACK_L 2
33P 50V J NPO 0402 33P 50V J NPO 0402 EMC@
2 2 C6 680P_0402_50V7K
2 Microphone: 6k~13k Ohm AUDJACK_R 3

1 2 C1705 EMC@
TV: 75 Ohm ADDJACK_DET_R 5
1000P_0402_50V7K

0.1U 6.3V K X5R 0201


HP_MIC
ADDJACK_DET_R <12>
1000P_0402_50V7K 1 2 C1706 EMC@ 1 CONN@

3
@ @ C55
1000P_0402_50V7K 1 2 C1707 EMC@ R1 R2
D1 0_0402_5% 0_0402_5% D2 ADD C55 FOR EMI 0807
EMC@ EMC@ 2
TVNST52302AB0 SOT523 TVNST52302AB0 SOT523

1
1

1
EMC@

2
L847
C FBMA-L11-160808-700LMT_2P C
EMC@
VDD18_6583
VDD18_6583 VEMC_3V3_PMU

1
Single via to GND plane

2
R213 R1754 05/20 ADD R1754
100K_0402_5% @ @ 10K_0402_5%

1
2
G
need check POUT @
3 1 POUT
P-SENSOR CNN <5> POUT_1

D
JP16 Q1 BSS138W-7-F_SOT323-3
1
VEMC_3V3_PMU 1
POUT 2 2 R8 1 0603 ADD R8
3 2 5 0_0402_5% 0605 DEL PAD and H1 GND
4 3 G1 6 0606 update H1 PCB Footprint
4 G2 LTE@
H1
ACES_88460-0401 HOLEA

ME@ 2
Pull high R move to MB

1
LTE@ C1
2P_0402_50V8C
0605 Change P/N FOR LOAD BOM 1
R5 LTE@ @
U2 470_0402_5% LTE@

Earphone MICPHONE POUT 2 R4


0_0402
1 POUT_R

CTRL
1
2
3
OUT
VSS
CTRL
CX
VDDHI
VREG
6
5
4
2
+3VS_P
P_VREG
1 2 R6 1
0_0402_5% 2
CAP
R7
0_0402
1
VEMC_3V3_PMU

3
IQS1280000EBTSR TSOT23 6P

2
B B
LTE@ 2 1 2 1 D3
R1755 C2 C3 C4 C5 LTE@
05/20 ADD R1755 LTE@ 10K_0402_5% TVNST52302AB0 SOT523

100P_0402_50V8J

1U_0402_6.3V4Z

100P_0402_50V8J

1U_0402_6.3V4Z
MICBIAS1 1 2 1 2 0528 add d3 for EMI

1
LTE@ LTE@ LTE@ LTE@
2

Close to BB Close to MIC 1K_0402_1% GND of C1709(10uF) and headset


R1699
should tie together and single via
C1708
1

1 2 AU_VIN1_N1 1
C1709
2
to GND plane
<24> AU_VIN1_N
10U_0603_6.3V6M
2

0.1U 10V +-10% X7R 0402 1


C1710
Close to JP2
1.5K_0402_1%
R1700
1 33P 50V J NPO 0402 2
C1711 2 1 R1701
<24> ACCDET
1

1K_0402_1%
100P_0402_50V8J 1
2 HP_MIC
C1712
33P 50V J NPO 0402 tie together and single via to GND plane 1
C1713 2 C1714 @
1 2 HP_MIC
<24> AU_VIN1_P
0.1U_0402_25V4Z
A 2 A
0.1U 10V +-10% X7R 0402

releate to MIC Detect

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/03 2013/11/03 Title
Issued Date Deciphered Date Audio,I/O,Audio board Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 8 of 28
5 4 3 2 1
5 4 3 2 1

<21> GLONASS_RF

05/20 add R1705 and R1706 for RF require

2
R1705
GLONASS@ 0_0402_5%
0605 Change bom structure
0613 change R1704 bom structure

1
2
U819 JP4_GPS R1704 Change bom structure to EMC@ NH520_EMC@ NH520_EMC@
JP3_WLAN EMC@ EMC@ EMC@ 2 R1704 R1706 U820 NH520_EMC@

GND
2 R1703 C1716 GND1 1 50 Ohm 1 2 50 Ohm 1 2 C1717 1 2 50 Ohm 4 1 GPS_RF
GND1 1 50 Ohm 1 2 50 Ohm C1715 1 2 50 Ohm 3 1 50 Ohm 1 2 50 Ohm WIFI_BT_ANT 3 SIG 0_0402_5% 0_0402_5% Output Input
3 SIG OUT IN GND2 EMC@ 18P_0402_50V8J
GND2 1 1
1 0_0402_5% 1 18P_0402_50V8J RFBPF2012080AM0T62_3P 18P_0402_50V8J C1720 C1721
C1718 C1719 EMC@ IPEX_20279-001E-01 @ @
D D
IPEX_20279-001E-01 @ @ 0530 UPDATE U819 FOR RF CONN@ 0.1U_0402_10V7K 0.1U_0402_10V7K

GND
GND
GND
0.1U_0402_10V7K 0.1U_0402_10V7K 0604 UPDATE U819 FOR RF 2 2
CONN@
2 2

5
3
2
SAFEB1G57KB0F00R14_5

U822 U822

PK29S004M00 PK29S004R00
AW-NH520(MT6228) AW-NH520T(MT6628T)
NH520@ GLONASS@

MT6620_1V8 0530 ADD FOR WIFI Vendor 0530 ADD FOR WIFI Vendor
0_0402 0_0402
R1708 @ @ R1713
1 2 PAD PAD 1 2
RTC32K2V8 <21,23>
2 TP1384
0.1U_0402_10V7K TP1385 RTCCLK_O
@ PAD TP1391
EMC@
C1722 OSC_IN_6620 2 1
2 1 CLK2_WCN_R <7>
0.1U_0402_10V7K 0_0402_5% R635
@ GLONASS@ SYNC -----> BPI_BUS8
C1723

60
59
58
57
56
52
28

15

40

34

33

35
U822

6
5
VBAT 1
change to SH00000RT00

DVDDIO_SD1

ANTSEL3
ANTSEL2
GND
GND
GND
GND
GND
GND
GND

EEDI

OSC_IN
RTCCLK_O
RTCCLK
0_0603_5% -35mil EMC@ 4
1 R1707 2 <5> GPIO_6628_PMU_EN 14 PMU_EN
VBAT_6620
1 2 LXB_6620 11 VBAT 1
LXB SYSRST_B DAIRST <5>
2 2 L848 2.2UH_LQM2HPN2R2MJ0L_1A_20%
C1724 C1725 12 3 OSC_EN_6620
8 BUCKOUT OSC_EN
C C
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K WF_PA_LDOOUT 42
1 1 GPS_SYNC GPIO_6628_GPS_SYNC <5>
7
9 WF_PA_VDD TLDO
13 DVDDIO18 54
GND_SMPS FSOURCE 1
C1726 NH520_EMC@
TLDO 36
TCXO_LDO
AW-NH520 @ PAD TP1380

2
41 MT6620 module 2 .033U 16V K X7R 0402 @ C1727
DVDDIO28 BGF_INT_B EINT_6628_BGF <5> 2
2 2 2 32 10 33P_0402_50V8J
VRTC_6620 VRTC WIFI_INT_B EINT_6628_WIFI <5>
C1729 C1730 C1731 C1728 2 1 55 ALL_INT_B
@ PAD TP1381

1
ALL_INT_B

4
NH520@ 1U_0402_6.3V6K C1733 U824 L849 C1734
4.7U_0603_6.3V6K

0.1U_0402_10V7K

C1732 0_0402 1U_0402_6.3V6K SD1_DAT1_6620 20 39 50 Ohm 1R1709 2


NH520_EMC@ 1 2 6 3 1 2 2 1 GPS_RF

Vcc
NH520@ U823 R1710 1 1 1 SD1_DAT2_6620 17 SD1_DAT1 GPS_ANT_P 6.8NH +-5% LQG15HS6N8J02D 0402 33P_0402_50V8J RF_OUT RF_IN 5.6NH_LQG15HS5N6S02D_5%
OSC_IN_6620 2 1 3 4 1 2 SD1_DAT3_6620 21 SD1_DAT2 50 PCM1SYNC_6620 NH520_EMC@ 5 NH520_EMC@ 470P 50V J NPO 0402
OUT Vcc SD1_CMD_6620 19 SD1_DAT3 PCM1SYNC 49 PCM1IN_6620 ENABLE NH520_EMC@
2 SD1_CMD PCM1IN
1000P_0402_50V7K SD1_CLK_6620 18 48 PCM1OUT_6620 Add offpage.1102.
Close to MT6620

GND

GND
SD1_CLK PCM1OUT

1
I2S_DATA_OUT
NH520@ C1735 SD1_DAT0_6620 16 47 PCM1CLK_6620

FM_AUOUT_R

6.8NH +-5% LQG15HS6N8J02D 0402


FM_AUOUT_L
SD1_DAT0 PCM1CLK

I2S_DATA_IN
FM_TX_OUT
2 1 1U_0402_6.3V6K 0_0402 @

FM_AUIN_R
FM_AUIN_L
GND GND 1 1 R1714 2 23 38 L850 BGU7005_XSON6_1P45X1

FM_RX_N
FM_RX_P
WiFi_ANT
<5> UTXD3

1
UART1_URXD RF_I_CAL

I2S_CLK
BT_ANT
26MHZ_10PF_7L26002009 1 2 22 37 NH520_EMC@

I2S_WS
<5> URXD3 UART1_UTXD AUX_REF
NH520@ R1720
0_0402 0530 DEL TEST POINT FOR RF

2
change to SJ000004W00 0530 ADD R1714 AND R1720 FOR RF AW-NH520 0_0402

53
51

29
30
31

27
26
24
25

43
46
44
45
AWAVE_AW-NH520_60P R1712
1 2
GPIO_6628_GPS_LNA_EN <5>

WIFI_BT_ANT
Compal footptint Close to U824
IF GPS have to pass AGPS IOT, recommend to
reserve an external GPS LNA between U824
pin3 and U822 pin39

B B

R1716 @
OSC_EN_6620 1 2
SRCLKENAI <5>
0_0201_5%
2

R1868
10K_0402_5%
R1715 0_0402_5% -22mil
VRTC_6620 1 2 VRTC XTEST EEDI ANTSEL_3
1

2.8V TCXO or OSC 0 0 0 Default


clock setting 1.8V TCXO or OSC 0 1 0
XTAL 0 0 1
external clock mode 0 1 1
SD1_CMD_6620 0_0201_5% 1 R1717 2 PCM1CLK_6620
MC3CMD <5> DAICLK <5>
SD1_DAT3_6620 0_0201_5% 1 R1718 2 PCM1SYNC_6620
MC3DA3 <5> DAISYNC <5>
XTEST ANTSEL_2 ANTSEL_1
SD1_DAT2_6620 0_0201_5% 1 R1719 2 PCM1OUT_6620
MC3DA2 <5> DAIPCMIN <5>
WIFI :SDIO1 0 0 0 Default
SD1_DAT1_6620 0_0201_5% 1 R1721 2 PCM1IN_6620 WIFI host
MC3DA1 <5> DAIPCMOUT <5>
interface WIFI :SDIO2 0 0 1
SD1_DAT0_6620 0_0201_5% 1 R1722 2
MC3DA0 <5>
WIFI :SPI 0 1 0
SD1_CLK_6620 0_0201_5% 1 R1711 2
MC3CLK <5>
EMC@ WIFI :reserved 0 1 1
1 R1723
5/23 ADD FOR RF
A @ C1749 VDD18_6583 2 1 MT6620_1V8 A
33P 50V J NPO 0402 XTEST ANTSEL_0
1

2 0_0402_5% -22mil BT/common host


C1737
interface UART1 0 0 Default
2

2.2U_0603_10V6K SDIO2 0 1

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/03 2013/11/03 Title
Issued Date Deciphered Date BT, FM, GPS, WiFi (MT6628)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 9 of 28
5 4 3 2 1
5 4 3 2 1

Sub Camera
Sub Camera 0531 Change L1 L2 L3 R1731 FOR MTK

2 EMC@ 1
0_0402_5% R1737
L1 05/20 SWAP FOR Layout
1 2 MIPI_D1_P
<5> RDP1 1 2 EMI10
EMI1 @ 1 8 GPIO_MAIN_CMPDN
<5> CMPDN
1 8 SUB_DAT8 4 3 MIPI_D1_N 2 7 GPIO_MAIN_CMRST
<5> CMDAT8 <5> RDN1 4 3 <5> CMRST
2 7 SUB_VREF 3 6 SENSOR_SDA
<5> CMVREF 3 6 <5> SDA1 4 5
SUB_DAT6 05/20 DEL EM12 CMMI21T-900Y-N_4P SENSOR_SCL
<5> CMDAT6 <5> SCL1
4 5 SUB_DAT9 2 1
<5> CMDAT9
0_0402_5% R1736 0 +-5% 8P4R 0804
0 +-5% 8P4R 0804 EMC@ EMC@
D D
EMC@

2 1
0_0402_5% R1735
EMC@
EMI3 EMI4 L2 05/20 Change C1745 from 0603 to 0805
1 8 SUB_PCLK 1 8 SUB_DAT7 1 2 MIPI_D0_P
<5> CMPCLK <5> CMDAT7 <5> RDP0 1 2
2 7 2 7 SUB_HREF
3 6 <5> CMHREF 3 6
SUB_DAT5 SUB_DAT2 @
<5> CMDAT5 <5> CMDAT2
4 5 SUB_DAT4 4 5 SUB_DAT3 4 3 MIPI_D0_N
<5> CMDAT4 <5> CMDAT3 <5> RDN0 4 3
0 +-5% 8P4R 0804 0 +-5% 8P4R 0804 CMMI21T-900Y-N_4P
EMC@ EMC@
2 1
0_0402_5% R1734
EMC@

2 1
0_0402_5% R1733
R1724 EMC@
L3
2V8 2 1 AVDD2.8V_CAM 1 2 MIPI_CLK_P
VCAMA_PMU <5> RCP 1 2
0_0402_5% -22mil @ @
2

2
0.1U_0402_16V4Z 4 3 MIPI_CLK_N
<5> RCN 4 3
C1738
2.2U_0603_10V6K C1739 CMMI21T-900Y-N_4P
1

1
2 1
0_0402_5% R1732
R1725
EMC@
1V8 2 1 DOVDD1.8V_CAM
VGP2_PMU
2 1 SENSOR_MCLK
<5> CMMCLK
0_0402_5% -22mil @ 0_0402_5% R1731
2

2 0.1U_0402_16V4Z
EMC@
C C1740 C
2.2U_0603_10V6K C1741
1

2V8 VCAMA_PMU 2 R1727 1 AVDD2.8V_CAM_5M

0_0402_5% -22mil 2

2
47U_0805_6.3V6M 0.1U_0402_16V4Z
C1745
@ C1746

1
1

Acer reserve
1V8 VGP2_PMU 2 R5256 1 DOVDD1.8V_CAM_5M

0_0402_5% -22mil @
2
0.3M connector

2
@ C1742 0.1U_0402_16V4Z
C1744
2.2U_0603_10V6K C1747

1
1 22P_0402_50V8J JP5

29 30 DOVDD1.8V_CAM
SENSOR_MCLK 27 29 30 28 DOVDD1.8V_CAM
25 27 28 26 AVDD2.8V_CAM
SENSOR_SCL 23 25 26 24 AVDD2.8V_CAM
SUB_DAT9 21 23 24 22
SUB_DAT8 19 21 22 20 SENSOR_SDA
SUB_DAT3 17 19 20 18 SUB_HREF
SUB_DAT7 15 17 18 16
SUB_DAT6 13 15 16 14 0521 Change P1 for ME
SUB_DAT5 11 13 14 12
SUB_DAT4 9 11 12 10
SUB_DAT2 7 9 10 8 23
R1726 5 7 8 6 SUB_VREF GND 22
SUB_PCLK 1 2 SUB_PCLK_R 3 5 6 4 21 GND
EMC@ 1 3 4 2 19 21 20 AVDD2.8V_CAM_5M
1 2 GPIO_SUB_CMPDN <5> 17 19 20 18
0_0402_5% DOVDD1.8V_CAM_5M
CONN@ 15 17 18 16 SENSOR_MCLK
B
SENSOR_SDA 13 15 16 14 GPIO_MAIN_CMRST B

2 SP020015H00 GPIO_MAIN_CMPDN 11
9
13
11
14
12
12
10
SENSOR_SCL
@ MIPI_D1_N MIPI_D1_P
C1743 0527 change to G1 Camera MIPI_CLK_P 7 9 10 8
22P_0402_50V8J 5 7 8 6 MIPI_CLK_N
1 MIPI_D0_N 3 5 6 4 MIPI_D0_P
1 3 4 2
1 2
JP7
0528 PIN6 Shout to gnd
CONN@
EMI

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/03 2013/11/03 Title
Issued Date Deciphered Date Camera
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 10 of 23
5 4 3 2 1
5 4 3 2 1

D D

Common Debug

JP6

1 2
<15,23> PWRKEY 1 2 3 1 2 4
R1728
<15,23,5,7> SYSRST_B 3 4
0_0402_5% -22mil 5 6
<15,24> KCOL0 7 5 6 8 URXD2 <5>
<15,24> KROW0 9 7 8 10 UTXD2 <5>
11 9 10 12
13 11 12 14
C C
15 13 14 16
17 15 16 18
19 17 18 20 MCU_JRTCK <5>
19 20 MCU_JTDO <5>
21 22
23 21 22 24 MCU_JTMS <5>
23 24 MCU_JTDI <5>
25 26
<5> URXD4 27 25 26 28 MCU_JTRST_B <5>
<5> UTXD4 29 27 28 30 MCU_JTCK <5>
31 29 30 32
33 31 32 34
35 33 34 36
37 35 36 38
39 37 38 40
39 40

G
G
G
G
44
43
42
41
PANAS_AXT440124
CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/11/03 2013/11/03 Title
Issued Date Deciphered Date SD Card,Debug,USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZEJ00 -LA-A791P
Date: Thursday, August 08, 2013 Sheet 11 of 28
5 4 3 2 1
5 4 3 2 1

0_0402_5%
R4902
0529 2.85V earlier than 1.8V +VDD_GYRO33
1
1 2 VDD28_6583 MPU-6515
C4172
R4903 0.1U_0402_10V7K 0529 2.85V earlier than 1.8V
0_0402_5% -22mil
1 2 U4029 2 6/20 Update
VEMC_1V8_PMU
@ 0513 change
3 13 10K_0402_5% NEED PULL UP?? U4032
0_0402_5% RESV/CCS# VDD 1 R4907 2
VDD18_6583
VDD18_6583 1 R4901 2 +VDD_GYRO18 8 +VDD_GYRO18 8 13 +VDD_GYRO33
@ VLOGIC 12 GYRO_INT 1 2 0530 DEL R4909 R4911 VDDIO VDD
INT EINT_GY <5>
1
C4171 R4908 0_0402_5%
D D
0.01UF_0402_25V7K 14 24 R4915 1 @ 2 0_0402_5%
RESV/DRDY 24 1 2 0_0402_5% 7 SDA / SDI 23 SDA3 <12,5>
I2C_GYRO_SDA R4912 R4914 1 2 0_0402_5%
SDA3 <12,5> SCL3 <12,5>
2
SDA 23 I2C_GYRO_SCL R4913 1 2 0_0402_5% AUX_CL SCL / SCLK @
6 SCL SCL3 <12,5> 21
7 AUX_DA 19 AUX_DA 12 GYRO_INT
AUX_CL RESV1 21 INT
RESV2 22 +VDD_GYRO18 22
RESV3 nCS 17
R4918 16 NC17 16
0_0402_5% -22mil NC 5 GYRO_AD0 9 NC16 15
1 2 GYRO_AD0 9 NC 4 AD0 / SDO NC15 14
AD0 NC 2 NC14 6
1 NC 10