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Ge GAA FETs and TMD FinFETs for the applications beyond Si- A review

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DOI: 10.1109/JEDS.2016.2590580

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 Received 27 May 2016; accepted 27 June 2016. Date of current version 23 August 2016.
The review of this paper was arranged by Editor M. Ieong.
Digital Object Identifier 10.1109/JEDS.2016.2590580

Ge GAA FETs and TMD FinFETs for the

Applications Beyond Si—A Review
YAO-JEN LEE, GUANG-LI LUO, FU-JU HOU, MIN-CHENG CHEN, CHIH-CHAO YANG,
CHANG-HONG SHEN, WEN-FA WU, JIA-MIN SHIEH, AND WEN-KUAN YEH
National Nano Device Laboratories, Hsinchu 30010, Taiwan
CORRESPONDING AUTHOR: W.-K. YEH (e-mail: wkyeh@narlabs.org.tw)

ABSTRACT Two parts of work are included in this paper. In the first part, the novel Ge gate-all-around
field effect transistors (GAA FETs) are introduced and discussed. Fabrication of Ge GAA FETs requires
only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production.
First, a novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on
SOI achieves a nearly defect-free channel, good gate control triangular gate, larger effective width than
rectangular fin, and have low punch-through current through the Si substrate. By dislocation removal,
the defect-free Ge channel can be formed on nothing. The p-channel triangular Ge GAA FET with fin
width (W fin ) of 52 nm and Lg of 183 nm has Ion /Ioff = 105 , SS = 130 mV/dec, and Ion = 235 µA/µm
at −1 V. Next, due to the highest electron mobility (2200 cm2 /Vs) on (111) Ge surface, the n-channel
triangular Ge GAA FET with (111) sidewalls on Si and Lg = 350 nm shows 2 times enhanced Ion with
respect to the devices with near (110) sidewalls. Electrostatic control of SS = 94 mV/dec (at 1 V) can
be further improved if superior gate stack than EOT = 5.5 nm and Dit = 1×1012 cm−2 ·eV−1 is used.
The Ion can be further enhanced if the line edge roughness (LER) can be reduced. Second, a feasible
pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge GAA FET with
four {111} facets is also reviewed. The proposed dry etching process involves three isotropic/anisotropic
etching steps with different Cl2 /HBr ratios for forming the suspended diamond-shaped channel. Taking
advantages of the GAA configuration, favorable carrier mobility of the {111} surface, and nearly defect-
free suspended channel, nFET and pFET with excellent performance have been demonstrated, including
an Ion /Ioff ratio exceeding 108 , the highest ever reported for Ge-based pFETs. The TMD FinFET devices
are reviewed in the second part of this paper. The TMD FinFET channel is deposited by CVD. MoS2
covered on Si fin and nanowire resulted in improved (+25%) Ion of the FinFET and nanowire FET. The
PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed
heterogeneous Si/TMD 3DFETs can be useful in future electronics. Furthermore, a 4 nm thin transition-
metal dichalcogenide (TMD) body FinFET with back gate control is also proposed and reviewed. Hydrogen
plasma treatment of TMD is employed to lower the series resistance. The 2 nm thin back gate oxide
enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically
configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm
thin monolayer body needed for 2 nm node FinFET.

INDEX TERMS Ge, GAA, triangle, diamond-shaped, TMD, MoS2 , CMOS.

I. INTRODUCTION germanium (Ge) because of their superior carrier mobility

In the past decade, as scaling of silicon based transistor has for both electrons and holes [1]–[5].
approached its physical limit, alternative channel materials However, the Ge MOSFET technology is facing several
for future logic devices to extend the Moor’s law beyond serious challenges, including fast n-type dopant diffusion,
the sub-7 nm node have been made with the main focus on high junction leakage, and enormous dislocation defects
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LEE et al.: Ge GAA FETs AND TMD FinFETs FOR THE APPLICATIONS BEYOND Si

FIGURE 1. Schematic flow for Ge triangular/diamond-shaped FETs and rectangular FinFETs. (a) Ge and grown on (001) SOI. (b)-(b)” fin patterning and
etching using isotropic Cl2 /HBr for triangular(b)’/diamond-shaped (b)” fins and anisotropic Cl2 /O2 (b) for rectangular fins (c) Anisotropic etching using
Cl2 gas only, (d) Isotropic Cl2 / HBr etching. (e) & (e)’ Gate formation with high k/metal gate stack.

in the Ge epi-layer because the 4% lattice mismatch to

Si substrate generates the misfit dislocations, and con-
comitantly induces threading dislocations with a density
as large as 109 cm−2 in the Ge epilayers. This usually
leads to degradation of properties in transistors owing to
the increase in leakage current. It is well known that the
threading dislocations can be guided to the edges of the
active area by elongating the misfit segments [6]. Therefore,
in the first part of this paper, we would like to review some
published papers related to new device structures for Ge
applications [7]–[9].
Multi-gate device configurations are also proposed for sub-
16 nm technology node due to it good gate controllability.
Thanks to the narrow nature of fins, the high defect bottom
layer of Ge can be removed by anisotropic etching with
etched rates enhanced by the defects. Herein, by making the
use of interfacial misfit along the epitaxial Ge on Si, a simple
fabrication process to prepare high quality and defect-free
Ge GAA FETs on insulator is introduced [7].
In addition, for n-channel Ge MOSFET, the highest mobil-
ity is on (111) plane with current direction along <110>,
not on the conventional (100) plane [8]. To combine the
advantages of 3D transistors for good gate control and (111)
Ge surface for high electron mobility, a novel triangular and
diamond-shaped Ge channel on (100) Si with (111) side-
walls and <110> current direction is demonstrated. The
key process is anisotropic etching to remove the dislo-
cated Ge region near Ge/Si interface and to reveal (111)
sidewalls as etching stop planes, achieving a nearly defect-
free epitaxial channel by removing the dislocations near
FIGURE 2. (a) XRD showing a single crystalline Ge layer formation on SOI;
(b) Reciprocal space mapping (RSM). Ge aligning with Si substrate peak to
the origin indicates the formation of relaxed Ge (100).
the Si/Ge interface using top-down lithography. In addi-
tion, a simple dry etching technique was utilized to form
GAA FET with highly tunable shapes on blanket epitaxial
layers.
Graphene, a two-dimensional (2D) material, has shown
a superior carrier mobility of up to 200,000 cm2 /V·s, but
its zero bandgap property limits its application to logic
devices due to low on/off ratios. Transition metal dichalco-
genides (TMDs), MX2 (M=Mo, W; X=S, Se, Te), are
a new class of two-dimensional (2D) materials with numer-
ous unique physical properties, such as atomic-thick layers,
thickness-dependent direct to indirect band-gap transition,
excellent 2D carrier mobility, strong spin-orbit coupling
for valley physics, etc [10], [11]. Transition metal dichalco-
genides have shown great potential in device applications due

VOLUME 4, NO. 5, SEPTEMBER 2016 287


FIGURE 3. Cross-sectional TEM image of triangular fin viewed.
to their satisfied bandgaps, thermal stability, carrier mobility,
and compatibility to silicon CMOS process. MoS2 is one of
the most researched 2D TMD materials.
In addition, TMD have atomically smooth surface with-
out dangling bounds and good mobility in CVD deposited
films of atomic scale thickness are very attractive enablers of
ultimately scaled transistors and 3D ICs [12], [13]. However,
a manufacturing flow must be realized using low-temperature
semiconductor process and TMD by chemical vapor depo-
sition (CVD) [14]. FinFET offers improved leakage and
power consumption and current/footprint for sub-16 nm
CMOS technology nodes and allows Lg reduction through
fin (body) thickness scaling. However, sub-5 nm node
FinFET requires sub-3 nm body thickness for good chan-
nel control (Fig. 1). Most channel materials- Si, Ge and
III-V- face process, mobility or quantum capacitance chal-
lenges at such ultra-thin body thickness [15]. Advanced
two-dimensional transition-metal dichalcogenide (TMD) is
an ideal channel material for its unique sub-nm monolayer
ultra-thin body [16] potential and good transport property
at nm thinness [13]. The CMOS process compatible TMD
3D transistor technology uses novel hybrid Si/MoS2 channel
FinFET and NWFET with improved Ion,n and matched Vth
of N and P devices. In comparison to previously published
TMD transistors, this work reports the shortest gate length,
thinnest gate dielectric, and first high performance at low
voltage. Chemical vapor deposition (CVD) of TMD is a com-
patible growth method with CMOS process integration [14]
and suitable for ultra-thin body formation. Combination of
TMD and multi-gate device [17] is also discussed. Moreover,
we introduce an additional Hydrogen treatment to improve
MoS2 contact series resistance. This paper presents a 4 nm
thin molybdenum disulfide (MoS2) body FinFET that has
dynamically adjustable threshold voltage (Vth) with back
bias control [18] for future low power CMOS technology
applications [19].
Therefore, in this paper, the electrical characteristics
of Ge MOSFETs with 3D structures, from rectangular
288
LEE et al.: Ge GAA FETs AND TMD FinFETs FOR THE APPLICATIONS BEYOND Si
to triangular/diamond-shaped nanowire structures, are dis-
cussed and reviewed. In addition, TMDs ontop finFETs
process for compatible CMOS process is also reviewed.
II. TRIANGULAR/DIAMOND-SHAPED CHANNEL NEARLY
DEFECT-FREE GE GATE-ALL-AROUND FETs ON Si
SUBSTRATES
Figure 1 show the schematic flow for Ge triangular/diamond-
shaped/rectangular FinFETs by utilizing anisotropic etching
process on an epitaxial Ge layer on SOI, while the
triangular/diamond-shaped Ge fin was formed using a multi-
step etching process. The fabrication process started with an
epitaxial Ge layer on a SOI wafer with SiO2 hard mask. The
epitaxial Ge was patterned into fins with desired feature
sizes using e-beam lithography. After hard mask opening,
Figs. 1(b) & (b)’ depict triangular/diamond-shaped pattern-
ing and the first isotropic etching step using Cl2 /HBr. By
tuning the Cl2 /HBr ratio, the etching step can form oppo-
site triangular ridges self-saturated at two {111} facets.
Fig. 1(b)” depicts anisotropic Cl2 /O2 for rectangular fins
etching. Fig. 1(c) shows anisotropic etching using Cl2 gas
only and chuck bias formed a tower-shaped pillar. The final
self-saturated isotropic etching step using Cl2 /HBr undercut
the dislocated Ge region near Si and completed the sus-
pended diamond-shaped structure as shown in Fig. 1(d).
Figures 1 (e) & (e)’ show the Gate formation with high
k/metal gate stack for Ge GAA- and Fin-FETs. Next,
after chemical wet cleaning process, thermally grown (RTO
500◦ C 30s) GeO2 was used as interlayers on Ge channel
to passivate the surface and to improve the interface quality
between Ge and the Al2O3/TiN gate stacks. Source/Drain
were implanted with B or BF2 for p-channel finFETs and
P for n-channel finFETs, and activated by RTA. For the
triangular/diamond-shaped Ge GAA FET, the schematic
cross-sectional view of floating Ge is shown in Figs. 1(e).
The triangular/diamond-shaped Ge fins were formed by care-
fully etching away dislocated Ge. It is observed that the
triangular Ge fins is covered conformably from all sides by
the gate metal thus making a full GAA structure.
The epitaxial Ge film on SOI was characterized by XRD
measurement. In Fig. 2(a), XRD shows a single crystalline
Ge layer formation on SOI, which indicates the formation
of a good crystalline quality. Figure 2(b) shows the recipro-
cal space map (RSM) of XRD reveals that Ge layer grown
on SOI is nearly fully relaxed. The triangular Ge fins were
formed by etching dislocated Ge, as shown in Fig. 3(a).
It is observed that the triangular Ge fins is covered con-
formably from all sides by the gate metal thus making
a full GAA structure. In Fig. 4, the applied bias power
and etching time were tuned to undercut the Ge fin later-
ally. The etching profile results from a faster etching rate
of Ge than Si in Cl2/HBr-based plasma, particularly for
defective Ge, leading to floating triangular Ge fin discon-
nected with parent SOI. Devices with different contact width
between Ge and Si were intentionally fabricated to verify
the impact of dislocations. In Fig. 5, Ion /Ioff ratio as high
VOLUME 4, NO. 5, SEPTEMBER 2016
LEE et al.: Ge GAA FETs AND TMD FinFETs FOR THE APPLICATIONS BEYOND Si
FIGURE 4. Fin formation by anisotropic dry etching. “d” decreases with
increasing side etching. (d: contact width between Ge and Si.)
FIGURE 5. Id-Vg of the triangular Ge GAA FET (device A in Fig. 9).
Ion/Ioff = 1E5 and SS = 130mV/dec are obtained. The EOT=5.5nm and
Dit=2E12cm−2 /eV −1 are used in the simulation to fit experimental data.
FIGURE 6. (a) Left image: cross-sectional TEM image of the triangular Ge
GAA FET with (111) high mobility sidewall (device A) viewed along width
direction. Right image shows gate-all-around gate stack by EDX mapping
of Ti. (b) The schematic cross section viewed along S/D direction.
as 105 and SS of ∼130 mV/dec are obtained for the trian-
gular Ge GAA FET. The large Dit of 2×1012 cm−2 eV−1
for EOT of 5.5 nm is responsible for the SS. Furthermore,
the mobility of the planar devices on (111) Ge is 2 times of
that on (100) Ge. In order to achieve high performance Ge
n-FET, Ge fin with (111) sidewalls are fabricated to take the
VOLUME 4, NO. 5, SEPTEMBER 2016
FIGURE 7. Id-Vg of the triangular Ge GAA FET (device A) with Ion /Ioff =
1.6× 104 and SS = 94mV/dec. The EOT=5.5nm is obtained from planar
devices, and Dit =1×1012 cm−2 eV−1 is extracted from the simulation (solid
lines).
advantage of the sidewall enhanced mobility. The triangu-
lar Ge GAA FET with (111) sidewalls utilizing anisotropic
etching process with Cl2 /HBr gas on an epitaxial Ge
layer on SOI.
For the triangular Ge GAA FET with (111) sidewalls, its
cross-sectional TEM image viewed along fin width direction
is shown in Fig. 6a. The distribution of gate electrode TiN is
proved to fully surround the Ge channel by EDX mapping.
By proper S/D implantation, most current flows through the
Ge channel instead of Si as shown in Fig. 6b.
The Ion /Ioff ratio of 1.6x104 and SS of ∼94 mV/dec are
obtained for the triangular Ge FET with (111) sidewalls, as
shown in Fig. 7. The experimental data in Fig. 7 is fitted by
using the EOT= 5.5nm obtained from planar devices, and
Dit = 1×1012 cm−2 eV−1 is extracted from the simulation.
FIGURE 8. Cross-sectional TEM images of diamond-shaped FET and FinFET.
For diamond-shaped structures, Figs. 8 show the TEM
images of the fabricated diamond-shaped GAA FET and
rectangular FinFET. The short diagonal is defined by the
hard mask width, and the length of the long diagonal is
1.41 times of the hard mask width. The suspended height
can be designed using the Ge thickness and hard mask
289
 LEE et al.: Ge GAA FETs AND TMD FinFETs FOR THE APPLICATIONS BEYOND Si

flows are illustrated in Fig. 10 including tri-gate FinFETs and

nanowire FETs with hybrid Si/TMD 2D electronic double
channels.

FIGURE 9. Id-Vg characteristics of the Ge GAA p-type NWFET with

WMASK /L = 20 nm/90 nm. The Ge GAA device shows a much improved
Ion /Ioff ratio compared to the Ge FinFET shown in the inset.

width, and the Ge recess during the hard mask etching to

achieve nearly defect-free Ge channels. Fig. 9 shows the
Id-Vg characteristics of the Ge GAA p-channel FET with
W/L=20 nm/100 nm. The extremely low Ioff was obtained,
resulting in a record-high Ion /Ioff ratio of 108 among all
reported Ge-based pFETs, and far superior to the rectan-
gular FinFETs with an Ion /Ioff ratio of 4.1 × 104 (the
inset in Fig. 9). Table 1 compares the performance of Ge
GAA NWFETs from different studies, showing the higher
Ion/Ioff ratios for diamond-shape p-type NWFETs.
TABLE 1. Comparison of the device characteristics of Ge FETs in different
studies.
FIGURE 10. The process flows and TEM images of (a) a tri-gate FinFET
and (b) a GAA nanowire FET with hybrid Si/TMD 2D electronic double
channels.
Fig. 11 (a)(b) presents the N/PMOS transfer and output
characteristics of the hybrid channel 3DFETs. Both N/P type
hybrid channel FETs have highly desirable low Vth and per-
fect Vth matching. The flat band and the threshold conditions
and explains the low and matched Vth. While the NMOS
channel is formed in MoS2 [23]. The PMOS channel is
formed in Si. Therefore the Si hole mobility determines the
P-type hybrid Si/MoS2 FinFET performance. The electron
mobility of the hybrid Si/MoS2 channel FinFET is deter-
mined by the electron rich MoS2 and is two times larger
than the electron mobility of the Si channel FinFET.

TABLE 2. Summary table of homogeneous 3DFETs, MoS2 channel and the

heterogeneous hybrid Si/MoS2 channels 3DFETs.

III. TMD FinFET FOR FUTURE LOW POWER TECHNOLOGY

This work made use of our previously reported advanced
FinFET device process platform [22]. The hybrid Si/TMD
channel finFETs and TMD FinFETs by CVD conformal
MoS2 growth were proposed and demonstrated using a fully
CMOS-compatible process.

A. 3DFETS USING HYBRID Si/TMD 2D ELECTRONIC

DOUBLE CHANNELS Regarding the geometric characteristics of the hybrid
Few-layer-MoS2 (3–16 layers, 2–10 nm thick) were fully Si/MoS2 electronic double channels, using several molec-
integrated into the hybrid channel 3DFETs. The process ular layers of MoS2 improved Ion,n by approximately 20%

290 VOLUME 4, NO. 5, SEPTEMBER 2016

LEE et al.: Ge GAA FETs AND TMD FinFETs FOR THE APPLICATIONS BEYOND Si
FIGURE 11. (a) Id-Vg curves and (b) Id-Vd curves of a hybrid 2D electronics
3DFETs; (c)(d) the Ion improvements of the hybrid Si/Mos2 channels 3D
NFETs.
in the hybrid Si/MoS2 FinFETs device in Fig. 11(c)(d).
The Ion,n performance was enhanced (> 25%) by applying
the hybrid Si/MoS2 channels according to the NWFETs.
Table 2 summarizes the demonstrated advantages of the
Si/MoS2 3DFETs over the MoS2 2DFETs in CMOS
operation and Vth matching.
FIGURE 12. The TEM image of MoS2 body on MoS2 FinFET with Si back
gate. Front gate HKMG is to be deposited.
B. TMD FINFET WITH 4 nm THIN BODY AND BACK GATE
CONTROL
Fig. 12 illustrates the process flow of a TMD FinFET with
4 nm Thin Body and Si Back Gate. The transfer and output
characteristics of MoS2 FinFET with 30 nm gate length and
6 layers (4 nm) MoS2 body are shown in Fig. 13(a)(b). The
front gate MoS2 FinFET device has on/off ratio larger than
105 and Ion of about 200 µA/µm for 1 volt operation bias.
The 4 nm MoS2 FinFET can also operate with back gate
bias alone in 2 nm thin BGO (Fig. 13(c)), however the main
purpose of the back gate is to adjust the MoS2 FinFET’s front
Vth as shown in Fig. 13(d). A back gate bias can thus correct
device variations or dynamically configure a device as a high-
performance or low energy consumption device in order to
VOLUME 4, NO. 5, SEPTEMBER 2016
achieve higher speed and/or lower power applications. The
2 nm thin BGO greatly enhances the Vth sensitivity to back
gate bias in comparison to a thick BGO (Fig. 13(e)). The
4 nm thin body and back gate control MoS2 FinFET yields
a record high Ion performance in MoS2 devices [24]–[27]
(Fig. 13(f)).
FIGURE 13. (a) Id-Vg curves and (b) Id-Vd curves of a MoS2 FinFET; (c) the
Id-Vg curve of MoS2 FinFET with back gate bias sweep; (d) the
MoS2 FinFET back gate bias control with TBGO (2nm).
IV. CONCLUSION
In this study, we review several papers published by national
nano device laboratories (NDL) to discuss the fabrication of
advanced devices beyond Si era, including Ge GAA struc-
tures and 2D TMD finFETs. In the first section, with the
removal of dislocation laden Ge near Ge/ Si interface, defect-
free triangular Ge GAA FET can be fabricated with surround
gate. In addition, with the (111) sidewall-enhanced mobility,
triangular Ge n-FET is then demonstrated to have enhanced
performance. This GAA architecture provides optimal elec-
trostatic confinement with the associated short-channel
effect benefits. In addition, the suspended diamond-shaped
GAA FET channel utilizes only the favorable {111} surfaces
with high carrier mobility. More importantly, comparing with
Ge nanowire formed by bottom-up process, the device can
be fabricated easily using the simple dry etching and blanket
Ge epitaxy techniques to meet the targets of the ITRS sub-
7 nm nodes. A manufacturable, nearly defect-free, and high
Ion triangular Ge FET is demonstrated using the highest
mobility (111) sidewalls.
In the second section, hybrid Si/TMD channel FinFETs
and MoS2 FinFET by CVD conformal MoS2 growth were
proposed and demonstrated using a fully CMOS-compatible
process. The Ion,n improved by more than 25% and N/P
device Vth matching was achieved. The novel hybrid Si/
TMD channel is a promising technology for high- perfor-
mance and scaled 2D and 3D FETs in 2D and 3D ICs.
In addition, A MoS2 FinFET with 4 nm thin body and back
291

gate control for future low power technology is proposed
and demonstrated. It points to the possibility of low nm
node FinFET using sub-nm monolayer TMD body. It fur-
ther shows a way to give FinFETs a new feature of strong
back bias control of Vth .
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YAO-JEN LEE was born in Kaohsiung, Taiwan,
in 1976. He received the B.S. degree in physics
from National Chung Hsing University, Taichung,
Taiwan, in 1998, and the M.S. and Ph.D. degrees
from the Institute of Electronics, National Chiao
Tung University, Hsinchu, Taiwan, in 2000 and
2004, respectively. He joined the National Nano
Device Laboratories, Hsinchu, as a Research
Fellow, and partly with the Department of Physics,
National Chung Hsing University.
GUANG-LI LUO received the Ph.D. degree in solid
state physics from the Institute of Physics, Chinese
Academy of Sciences, Beijing, China, in 1997. He
is currently a Research Fellow with National Nano
Device Laboratories, Taiwan.
FU-JU HOU received the M.S. degree in electron-
ics and electro-optical engineering from National
Chiao Tung University, Hsinchu, Taiwan, in 2002,
where he is currently pursuing the Ph.D. degree
with the Department of Electronics Engineering,
Institute of Electronics. He has been an Engineer
with National Nano Device Laboratories, Hsinchu,
since 1996.
VOLUME 4, NO. 5, SEPTEMBER 2016
LEE et al.: Ge GAA FETs AND TMD FinFETs FOR THE APPLICATIONS BEYOND Si
MIN-CHENG CHEN received the Ph.D. degree
in electrics institute from National Chiao Tung
University, Hsinchu, Taiwan, in 2004. He is cur-
rently a Research Fellow with the National Nano
Device Laboratories, Hsinchu. His current research
interests include nanoelectronic semiconductor
devices integration and characteristics.
and technologies, thin film devices and technologies, and nanotechnologies.
CHIH-CHAO YANG received the Ph.D. degree
from National Tsing Hua University, Taiwan, in
2007. He is an Associate Researcher with the
Emerging Device Division, National Nano Device
Laboratories. His research interests now include
the development of monolithic 3-D integrated cir-
cuit and device for Internet of Things. He is now
utilizing low thermal budge pulse laser processes,
including laser crystallization, laser activation and
laser silicide, for fabricating high performance and
sequentially stacked logics and memories. Such
3-D sequential integration technology is the key to realize high performance,
rich function, power efficient, and low cost 3DIC.
CHANG-HONG SHEN received the Ph.D. degree
in physics from National Tsing-Hua University
in 2006. His academic interests include pho-
tovoltaic devices, flexible electronics, and low-
temperature laser/plasma processing. His current
research focuses on developing low-cost, third-
generation Si and CIGS thin-film solar cells, and
monolithic 3-D nanoelectronics.
recent work is focused on the field of nano-scaled FETs, SOI FET, and
3-D FET.
VOLUME 4, NO. 5, SEPTEMBER 2016
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WEN-FA WU was born in Kaohsiung, Taiwan,
in 1967. He received the B.S. degree in elec-
tronics engineering from National Chiao Tung
University, Taiwan, in 1990, and the Ph.D. degree
from the Institute of Electronics, National Chiao
Tung University, in 1994. In 1994, he joined
the National Nano Device Laboratories, Hsinchu,
Taiwan, where he has been a Researcher, since
2003. He has authored or co-authored over
120 journal or conference papers. His research
interests include advanced nano CMOS devices
JIA-MIN SHIEH received the Ph.D. degree
in electro-optics from National Chiao Tung
University, Taiwan, in 1997. He is currently the
Deputy Director General with National Nano
Device Laboratories. His current research focuses
on developing low-cost, third-generation Si and
CIGS thin-film solar cells, Si quantum-dot pho-
tovoltaic/photonic/electronic devices, monolithic
3-D nanoelectronics and circuits, and low power
sensors for IoTs.
WEN-KUAN YEH received the Ph.D. degree in
electronics engineering from National Chiao Tung
University, Taiwan, in 1996. He is currently
a Full Professor with the Electrical Engineering
Department, National University of Kaohsiung,
and also serves as the General Director of National
Nano Device Laboratories, a leading government
lab at Taiwan. He is the Chair of the IEEE
EDS Tainan Local Chapter. He has published
four edited books, over 200 peer reviewed papers,
three book chapters, and over hundred patents. His
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