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Hardware Modeling Using Verilog

Assignment- Week 5
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 X 1 = 20
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QUESTION 1:
Which of the following is/are true for a test bench?

a. A test bench is executed only once during simulation.

b. The input ports of the module being tested have to be declared as outputs /
registers in the test bench.
c. A test bench is synthesized once during synthesis.
d. We cannot use “always” procedural block inside a test bench.

Correct Answer: a, b

Detailed Solution:

A test bench is a Verilog module that is executed only once during simulation, and serves the
purpose of applying test inputs to a module under test. Therefore, the input ports of the
module must be declared as outputs / reg variables in the test bench. Test benches are used
only for simulating “modules under test” and are never synthesized. Both “initial” and “always”
blocks can be used in writing a test bench.
Hence, the correct options are (a) and (b).

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QUESTION 2:
Which of the following is/are false for an “initial” block?

a. It can be used to verify whether a given module is synthesizable.

b. “wire” type variables can be assigned inside the block.
c. The right hand side of the assignments can have both net and register type
variables.
d. All of these.

Correct Answer: a, b

Detailed Solution:
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The “initial” block is used to write a test bench to verify the functional correctness of a module,
and is used only during simulation. Only “register” type variables can be assigned inside an
“initial” block. Also, the right hand side of assignment statements can contain both “net” and
“register” type variables. Thus, the correct options are (a) and (b).

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QUESTION 3:
Which of the following statements are true?

a. The $display command prints the values of the text / variables as soon as it is
executed.
b. The $display command prints the values of the text / variables when one or
more of the specified variables changes value.
c. The $monitor command prints the values of the text / variables as soon as it is
executed.
d. The $monitor command prints the values of the text / variables when one or
more of the specified variables changes value.

Correct Answer: a, d

Detailed Solution:

Whenever the $display statement is encountered, the values specified in the list are printed
immediately. Whereas the $monitor statement is event driven, where the values specified are
printed whenever the value of some variables in the list changes. Thus, the correct options are
(a) and (d).

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QUESTION 4:
What happens when the first parameter of the $dumpvars function is specified as 1?

a. Only the listed variables will be dumped.

b. Only the listed variables and variables of listed modules will be dumped.
c. All variables in the top-level module will be dumped.
d. None of the above.

Correct Answer: b

Detailed Solution:
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The answer follows from the description of the $dumpvars function. The correct option is (b).

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QUESTION 5:
What does the following code segment do?
reg a, b, c, d, e; integer count;
for (count=0; count<32; count=count+1)
begin
{a,b,c,d,e} = count;
end

a. Assign the value of “count" to all the five variables a, b, c, d, e in the loop.
b. Assign all possible 5-bit binary patterns to the variables a, b, c, d, e.
c. The five most significant bits of “count” are assigned to the variables a, b, c, d, e.
d. None of these.

Correct Answer: b

Detailed Solution:

The for loop runs 32 times with the value of the variable “count” ranging from 0 to 31. Being an
integer variable, the variable “count” will be allocated 32 bits. However, in the assignment
statement “{a,b,c,d,e} = count”, the five least significant bits of “count” will be assigned to
variables a, b c, d and e respectively. This will allow all possible binary values from 00000 (i.e. 0)
to 11111 (i.e. 31) to be assigned. Hence, the correct option is (b).

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QUESTION 6:
The time period of the clock (clk) generated by the following code segment will be …….. time
units.
initial
#15 clk = 1’b0;
always
#12 clk = ~clk;

HINT: ( Please provide numeric answer, e.g. 37, do not type thirty seven.)
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Correct Answer: 24

Detailed Solution:

Because the “clk” signal gets toggled after delays of 12 time units in the “always” block, the
signal values will be repeated after 12+12=24 time units. This will also be the time period of
“clk”.

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QUESTION 7:
The duty cycle of a periodic digital signal is defined as the ON period divided by the total time
period. For generating a signal “clk” with duty cycle 0.25, what must be the value of X?
initial
clk = 1’b0;
always
forever begin
#3 clk = 1’b0;
#X clk = 1’b1;
#4 clk = 1’b0;
end

a. 7
b. 8
c. 9
d. 10

Correct Answer: c

Detailed Solution:

Here in the “always” block, the “clk” signal will remain 0 for (X + 3) time units, and will remain 1
for 4 time units in a repetitive loop. In other words, the duty cycle will be given by 4 / (X + 7).
Solving, 4 / (X + 7) = 0.25, we get X = 9.
Thus, the correct option is (c).

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QUESTION 8:
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Which of the following statements is/are true?

a. Moore machine is more general than Mealy machine.

b. The number of states in a Mealy machine must be finite.
c. The number of states in a Moore machine must be finite.
d. A Moore machine can be realized using a combinational circuit.

Correct Answer: b, c

Detailed Solution:

Option (a) is false because in a Moore machine the output depends only on the present state,
while in a Mealy machine the output depends both on the present state and the present input.
Thus Mealy machine is more general.
Both Moore and Mealy machines represent finite state machines, and are realized using
sequential circuits. The number of states in both Moore and Mealy machines must be finite to
be realizable in hardware.
Thus, the correct options are (b) and (c).

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QUESTION 9:
The number of flip-flops will be realized by the following code segment will be:
module myfsm (clk, lamp);
input clk;
output reg [3:0] lamp;
parameter S0=0, S1=1, S2=2; S3=3;
reg [0:1] state;
always @(posedge clk)
case (state)
S0: begin
lamp <= 4’b1100; state <= S1;
end
S1: begin
lamp <= 4’b0110; state <= S2;
end
S2: begin
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lamp <= 4’b0011; state <= S3;

end
S3: begin
lamp <= 4’b1001; state <= S0;
end
endcase
endmodule

a. 4
b. 6
c. 8
d. 16

Correct Answer: b

Detailed Solution:

Here flip-flops will be synthesized for both the state variables (2 in number) and also the
outputs (4 in number). Thus the number of flip-flops will be 2+4=6.
Hence, the correct option is (b).

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QUESTION 10:
The number of flip-flops will be realized by the following code segment will be:
module myfsm (clk, lamp);
input clk;
output reg [3:0] lamp;
parameter S0=0, S1=1, S2=2; S3=3;
reg [0:1] state;
always @(posedge clk)
case (state)
S0: state <= S1;
S1: state <= S2;
S2: state <= S3;
S3: state <= S0;
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endcase
always @(state)
case (state)
S0: lamp = 4’b1100;
S1: lamp = 4’b0110;
S2: lamp = 4’b0011;
S3: lamp = 4’b1001;
endcase
endmodule
a. 2
b. 4
c. 6
d. None of these

Correct Answer: a

Detailed Solution:

Since the outputs are assigned in a separate always block using blocking assignments, they will
be generated using combinational circuits only. We would require only 2 flip-flops for the state.
Hence, the correct option is (a).

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