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Haredare Modeling Using Verilog

Assignment- Week 1
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 X 1 = 10
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QUESTION 1:
What does Moore’s law specify?

a. The number of transistors in a VLSI chip will increase exponentially with time.
b. The power consumption in a VLSI chip will increase linearly with time.
c. The clock speed of a VLSI chip will increase exponentially with time.
d. None of these.

Correct Answer: a

Detailed Solution:

According to Moore’s law, the number of transistors that can be fabricated in a chip will double
every 18 months, which indicates an exponential growth. It does not talk anything about power
consumption or the clock speed. Hence, the correct answer is (a).

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QUESTION 2:
Which of the following does not represent a behavioral representation for the function f = A.B +
B.C + C.A?

a. A truth table of the function f

b. The Verilog specification: assign f = (A & B) | (B & C) | (C & A);
c. A netlist consisting of three 2-input AND and one 3-input OR gate
d. None of these

Correct Answer: c

Detailed Solution:

The truth table description of a function represents behavioral description, and so also is the
logic expression specified using “assign” statement. However, any netlist representing an
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interconnection of circuit blocks represents structural description. Hence, the correct answer is
(c).

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QUESTION 3:
Which of the following functional descriptions can be realized by a single 4-input LUT in a
typical FPGA?

a. F = A’.B.C + B’.C’
b. F = (A.B + A’.B’) . (C.D’ + C’.D)
c. F = A.B.C + B’.D.E
d. All of these

Correct Answer: a,b

Detailed Solution:

The 4-input LUT is typically realized using a small SRAM, and can realize any function of up to 4
variables. Thus, (a) and (b) are true that represent 3-variable and 4-variable functions
respectively. However, (c) is false as it is a 5-variable function. Hence, the correct answers are
(a) and (b).

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QUESTION 4:
For which design style, the following statement is true?
“The fabrication cost of a chip is C = C1 + C2, where C1 represents a cost that is shared among
several customers, while C2 represents a cost that is to be separately borne by every customer.”

a. Gate array
b. FPGA
c. Standard cell
d. Full custom

Correct Answer: a

Detailed Solution:

For gate arrays, fabrication proceeds in two phases. In the first phase, uncommitted transistors
are fabricated that are independent of the functions being implemented. In the second phase,
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the interconnections of the transistors are carried out to realize arbitrary functionality. The first
component of the cost (C1) is shared among all customers who are fabricating gate array chips,
while the second component (C2) is specific to every customer. Hence, correct answer is (a).

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QUESTION 5:
Which of the following are true for standard cell based design?

a. The heights of the cells are fixed but the widths can be different.
b. The number of cells must be equally distributed among the rows.
c. Feed-through cells can be inserted to improve routability.
d. It requires more design effort as compared to full custom design.

Correct Answer: a, c

Detailed Solution:

In standard cell or semi-custom design, cells are arranged in rows with routing space (called
channels) in between. For this purpose, the heights of all the cells are fixed; however, the width
can vary depending on the cell complexity. For connecting two cells that cross more than one
channel, feed-through cells are used to provide connection between adjacent channels. Any
number of cells can be placed in a row. Also, semi-custom design style uses predesigned cells
and requires less design effort in comparison with full custom design where almost all the
functional blocks are designed from scratch. Hence, options (a) and (c) are correct.

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QUESTION 6:
Which of the following results in shortest design turnaround time?

a. Full custom design

b. Standard cell design
c. FPGA based design
d. Gate array design

Correct Answer: c

Detailed Solution:
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For FPGA based design, a given specification can be synthesized and downloaded on the FPGA
device directly without any requirements of special fabrication facilities. Hence, the process is
very fast. However, the other three design styles need the support of a fabrication facility, and
hence take much longer time. Thus, the correct answer is (c).

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QUESTION 7:
Which of the following are examples of structural design representation?

a. A netlist of functional blocks.

b. A netlist of gates and flip-flops.
c. A truth table description.
d. All of these.

Correct Answer: a,b

Detailed Solution:

In structural design, we express a design as a netlist of blocks, where the blocks may be defined
at any level (viz. transistors, gates, functional blocks, etc.). Truth table represents behavioral
description. Hence, (a) and (b) are true.

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QUESTION 8:
Which of the following statements is/are true?

a. A test bench is required when we want to verify a design through simulation.

b. A test bench is also synthesized along with the main module.
c. When we map the design to a FPGA or ASIC, we do not need a test bench.
d. Simulation means generation of a gate level netlist from a behavioral
specification.

Correct Answer: a,c

Detailed Solution:

We use a test bench to verify the working of a module through simulation. Once we have
verified the design, we can synthesize it and map it to FPGA or ASIC. The test bench is used only
for simulation purpose, and is never synthesized. Simulation means analyzing a module
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specified at some higher level with possible set of inputs and observing any deviation from
expected outputs. Thus, options (a) and (c) are correct.

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QUESTION 9:
What function do the following Verilog module implement?
module guess (f, a, b, c);
input a,b,c; output f,
wire t1, t2;
nand #1 G1 (t1,a,b);
or #1 G2 (t2,b,c);
nor #1 G3 (f,t1,t2);
endmodule

a. f = a’.c
b. f = a.c’
c. f = (a + c)’
d. None of these

Correct Answer: d

Detailed Solution:

From the gate descriptions, we can write:

t1 = (a.b)’ = a’ + b’
t2 = b + c
f = (t1 + t2)’ = (a’ + b’ + b + c)’ = (a’ + 1 + c)’ = 1’ = 0
Thus, correct answer is (d).
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QUESTION 10:
What function do the following Verilog module implement?
module guess (f, a, b, c);
input a,b,c; output f,
wire t;
assign t = (a ^ b);
assign f = t & c;
endmodule
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a. f = a’.b.c + a.b’.c
b. f = a’.b.c + a.b.c’
c. f = a’.c + a’.b.c’
d. None of these

Correct Answer: a

Detailed Solution:

From the logic expressions, we can write

t = a.b’ + a’.b
f = (a.b’ + a’.b) . c = a.b’.c + a’.b.c
Hence, correct answer is (a).

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