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2-1
F2833x Block Diagram
Program Bus
ePWM
DMA Bus
12--bit ADC
12
D(31--0)
D(31 Watchdog
PIE
32--bit
32 R-M-W Interrupt CAN 2.0B
32x32 bit Manager
Auxiliary Atomic FPU
Multiplier I2C
Registers ALU
3
Real--Time
Real SCI
32--bit
32
JTAG Register Bus Timers SPI
Emulation CPU
McBSP
Data Bus
GPIO
2-2
F2833x CPU
Program Bus
32--bit
32 R-M-W
32x32 bit
Auxiliary Atomic FPU
Multiplier
Registers ALU 3 PIE
32--bit
32 Interrupt
Register Bus Manager
Timers
CPU
32
ALU (32)
32
ACC (32)
AH (16) AL (16)
AH.MSB AH.LSB AL.MSB AL.LSB
• 32
Shift R/L (0-
(0-16)
32
Data Bus
2-4
F2833x Floating Point Unit FPU
Fixed Point Floating Point
6 LSB
XAR0 DP (16) from IR
XAR1
XAR2
32 22
XAR3
XAR4 MUX
XAR5
XAR6
XAR7
MUX
ARAU
Data Memory
XARn ® 32
32--bits
ARn ® 16
16--bits
2-6
F2833x Internal Bus Structure
PIE
DINTCH1--6
DINTCH1
ADC XINTF
Result 0-
0-15 Zone 0, 6, 7
DMA
L4 SARAM 6-channels
McBSP--A
McBSP
Triggers
L5 SARAM McBSP--B
McBSP
SEQ1INT / SEQ2INT
MXEVTA / MREVTA PWM1
L6 SARAM MXEVTB / MREVTB
XINT1--7 / 13
XINT1 PWM2
TINT0 / 1 / 2 PWM3
L7 SARAM PWM4
PWM5
PWM6
SysCtrlRegs.MAPCNF.bit.MAPCNF
(re-maps PWM regs from PF1 to PF3)
2-8
F2833x Atomic Read/Modify/Write
C F1 F2 D1 D2 R1 R2 E W Instructions
F1 F2 D1 D2 R1 R2 E W
‘E’ and ‘G’
D E & G Access
access same
F1 F2 D1 D2 R1 R2 E W sameaddress
memory address
E
F1 F2 D1 D2 R1 R2 E W
F
G F1 F2 D1 D2 R11 R2 R
E2 W
E W
H F1 F2 D1 D
D22 R1 RR21 R
E2 W
E W
CSM Protected:
L0, L1, L2, L3,
FLASH, ADC CAL,
OTP
Ø 96 dedicated PIE
vectors
Ø No software decision
making required PIE module 28x CPU Interrupt logic
2 - 14
Reset – Bootloader
Reset
OBJMODE = 0 AMODE = 0
ENPIE = 0 INTM = 1
Bootloader sets
OBJMODE = 1
AMODE = 0
Reset vector fetched
from boot ROM Boot determined by
state of GPIO pins
0x3F FFC0
Execution
Entry Point
Note: M0 SARAM
Details of the various boot options will be
discussed in the Reset and Interrupts module
2 - 15
Highlights of the F2833x