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OVERVIEW
1.1 INTRODUCTION
Every PC comes already with at least one serial port and a parallel port to
connect devices such as modems, mouse, printers, etc. to your computer. The
disadvantages of those two are speed as well as expandability. The serial port can
transfer only one bit of data at a time, it transfers data as a series of bits, hence the
name. The parallel port can transfer 8 bits of data at a time.
A PC comes only with a limited number of serial and parallel ports , therefore
you are out of luck once you used them all up. Another inconvenience of serial and
parallel ports is the fact that in order to connect a device to them, you have to turn off
your computer, connect the device, reboot, then manually install the driver. USB was
designed to eliminate all those shortcomings.
USB communication takes the form of packets. Initially, all packets are sent
from the host, via the root hub and possibly more hubs, to devices. Some of those
packets direct a device to send some packets in reply. The computer which takes in
serial data and performs operation cannot accept USB data directly hence USB data
transmission protocols should be first converted into serial data used by the computer.
USB, which stands for Universal Serial Bus, has been quite successful in the
computer market in the last couple of years. It started to show in PCs sometime in
1996 and started to really take off in 1998. USB is another way to connect external
devices to your PC. Popular examples for USB devices are printers, scanners,
keyboards, mice, joysticks, UPSs, speakers, monitors, network kits, Zip drives, digital
cameras, modems, Personal Digital Assistants (PDA) and more.
1
1.3 COMPONENTS AND METHODOLOGY
HARDWARE COMPONENTS
• Microcontrollers
• Power supply
• USB Connector
• PC
• LCD
SOFTWARE TOOLS
• Keil u-Vision
• Embedded ‘C’
• Express PCB
Power
supply
USB to LCD
USB Micro
serial
connecto controller
chip
r
PC
2
• Now the rectified, filtered D.C. voltage is fed to the Voltage Regulator.
• This rectified, filtered and regulated voltage is again filtered for ripples
• The output of 5V is generated first by this section which is fed
to microcontroller to supply operating voltage.
• The microcontroller 89s52 is provided with pull up resistors, crystal oscillator
which is in conjunction with few capacitors.
• MAX 232s are connected to the microcontroller
• USB is given to the receive and transmit pins of the microcontroller
• MAX 232 IC is working as the interface between the USB and
the microcontroller.
• An LCD is connected to the microcontroller.
• Converted serial data can be read by Micro controller serially
and displayed in the LCD
• Popular examples for USB devices are printers, scanners, keyboards, mice,
joysticks, UPS, speakers, monitors, network kits, Zip drives, digital cameras,
modems, Personal Digital Assistants (PDA).
3
CHAPTER 2. POWER SUPPLY
2.1 INTRODUCTION
The power supplies are designed to convert high voltage A.C mains electricity
to a suitable low voltage supply for electronic circuits and other devices. A power
supply can by broken down into a series of blocks, each of which performs a
particular function. A D.C power supply which maintains the output voltage constant
irrespective of A.C mains fluctuations or load variations is known as “Regulated D.C
Power Supply”.
2.2 TRANSFORMER
A transformer is an electrical device which is used to convert electrical power
from one electrical circuit to another without change in frequency. Transformers
convert AC electricity from one voltage to another with little loss of power.
Transformers work only with AC and this is one of the reasons why mains electricity
4
is AC. Step-up transformers increase in output voltage, step-down transformers
decrease in output voltage.
Electrical Transformer
2.3 RECTIFIER
5
A circuit which is used to convert A.C to D.C is known as RECTIFIER. The
process of conversion of A.C to D.C is called “rectification”
TYPES OF RECTIFIERS
Type of Rectifier
Number of diodes
1 2 4
PIV of diodes
Vm 2Vm Vm
Ripple frequency
f 2f 2f
Rectification
efficiency
0.406 0.812 0.812
6
Transformer 0.287 0.693 0.812
utilization Factor(TUF)
From the above comparison we came to know that full wave bridge rectifier
has more advantages than the other two rectifiers. So, in our project we are using full
wave bridge rectifier circuit.
OPERATION
During positive half cycle of secondary voltage, the diodes D2 and D3 are
forward biased while D1 and D4 are reverse biased as shown in the fig(b). The current
floww direction is shown in the figure.
7
During negative half cycle of secondary voltage, the diodes D1 and D4 are forward
biased while D2 and D3 are reverse biased as shown in the fig(c). The current flow
direction is shown in the fig (c) with dotted arrows.
2.4 FILTER
A Filter is a device which removes the a.c component of rectifier output but
allows the d.c component to reach the load.
CAPACITOR FILTER
We have seen that the ripple content in the rectified output of half wave
rectifier is 121% or that of full-wave or bridge rectifier is 48%, such high
percentages of ripples is not acceptable for most of the applications. Ripples can be
removed by one of the following methods of filtering.
(a) A capacitor, in parallel to the load, provides an easier by –pass for the ripples
voltage through it due to low impedance. At ripple frequency and leave the D.C to
appears the load.
(b) An inductor, in series with the load, prevents the passage of the ripple current (due
to high impedance at ripple frequency) while allowing the d.c (due to low resistance
to d.c).
(c) Various combinations of capacitors and inductors, such as L-section filter ‘pi’
section filter, multiple section filter etc. Make use of both the properties mentioned in
(a) and (b) above.
8
Filtering is performed by a large value electrolytic capacitor connected across the DC
supply to act as a reservoir, supplying current to the output when the varying DC
voltage from the rectifier is falling. The capacitor charges quickly near the peak of the
varying DC, and then discharges as it supplies current to the output. Filtering
significantly increases the average DC voltage to almost the peak value (1.4 × RMS
value).
2.5 REGULATOR
9
2.5.1 78XX
The Bay Linear LM78XX is integrated linear positive regulator with three
terminals. The LM78XX offer several fixed output voltages making them useful in
wide range of applications. When used as a zener diode/resistor combination
replacement, the LM78XX usually results in an effective output impedance
improvement of two orders of magnitude, lower quiescent current. The LM78XX is
available in the TO-252, TO-220 & TO-263packages.
FEATURES:
• No External Component
• Output Voltage 5.0V, 6V, 8V, 9V, 10V,12V, 15V, 18V, 24V
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CHAPTER 3. MICROCONTROLLER (AT89S52)
3.1 INTRODUCTION
FEATURES
11
3.2 DESCRIPTION
Block diagram:
12
Pin diagram:
GND - Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin
can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as
high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order
address/data bus during accesses to external program and data memory. In this mode,
P0 has internal pull-ups. Port 0 also receives the code bytes during Flash
programming and outputs the code bytes during program verification. External pull-
ups are required during program verification.
13
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
1 pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups. Port 1 also receives the low-order address bits during Flash
programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
2 pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups. Port 2 also receives the high-order address bits and some control
signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
3 pins that are externally being pulled low will source current (IIL) because of the
pull-ups. Port 3 receives some control signals for Flash programming and
verification. Port 3 also serves the functions of various special features of the
AT89S52, as shown in the following table.
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P3.1 TXD (serial output port)
P3.2 INT0’ (external interrupt 0)
P3.3 INT1’ (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR’ (external data memory write strobe)
P3.7 RD’ (external data memory read strobe)
RST
Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device. This pin drives high for 98 oscillator periods after the
Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to
disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature
is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency and may be used for external timing or
clocking purposes. Note that one ALE pulse is skipped during each access to external
data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR
location 8EH. With the bit set, ALE is active only during a MOVX or MOVC
instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has
no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S52 is executing code from external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to external data memory.
EA/VPP
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External Access Enable. EA must be strapped to GND in order to enable the
device to fetch code from external program memory locations starting at 0000H upto
FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched
on reset. EA should be strapped to VCC for internal program executions. This pin also
receives the 12-volt programming enable voltage (VPP) during Flash programming.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.
XTAL2
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator, as shown in Figs
6.2.3. Either a quartz crystal or ceramic resonator may be used. To drive the device
from an external clock source, XTAL2 should be left unconnected while XTAL1 is
driven as shown in Figure 6.2.4.There are no requirements on the duty cycle of the
external clock signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
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Fig 3.3b External Clock
Drive Configuration
On-chip hardware inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle is terminated by reset, the instruction following the one that
invokes idle should not be the one that writes to a port pin or to external memory.
In the power down mode the oscillator is stopped, and the instruction that
invokes power down is the last instruction executed. The on-chip RAM and Special
Function Registers retain their values until the power down mode is terminated. The
only exit from power down is a hardware reset. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before VCC is restored to
its normal operating level and must be held active long enough to allow the oscillator
to restart and stabilize.
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STATUS OF EXTERNAL PINS DURING IDLE AND POWER DOWN
On the chip are three lock bits which can be left unprogrammed (U) or can be
programmed (P) to obtain the additional features listed in the table 5.4. When lock bit
1 is programmed, the logic level at the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the latch initializes to a random value, and
holds that value until reset is activated. It is necessary that the latched value of EA be
in agreement with the current logic level at that pin in order for the device to function
properly.
3.3 TIMERS
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Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in
the AT89C52. Register pairs (TH0, TL1), (TH1, TL1) are the 16-bit counter registers
for timer/counters 0 and 1.
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performs the same operation, but a 1-to-0 transition at external input T2EX also
causes the current value in TH2 and TL2 to be captured into RCAP2H andRCAP2L,
respectively. In addition, the transition at T2EXcauses bit EXF2 in T2CON to be set.
The EXF2 bit, likeTF2, can generate an interrupt.
- - - - - - T2OE DCEN
7 6 5 4 3 2 1 0
Symbol Function
- Not Implemented,reserved for future
T2OE Timer 2 output enable bit
DCEN When set,this bit allows Timer 2 to be configured as
an up/down counter
Table3.4: T2MOD-Timer 2 Mode Control Register
Bit Addressable
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by
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software.TF2 will not be set when either RCLK = 1 or TCLK = 1
EXF2 Timer 2 external flag set when either a capture or reload is caused by a
negative transition on T2EX and EXEN2=1.When Timer 2 interrupt is
enabled,EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt
routine.EXF2 must be cleared by software.EXF2 does not cause an
interrupt in up/down counter mode
RCLK Receive clock enable.When set,causes the serial port to use Timer 2
overflow pulses for its receive clock in serial port Modes 1 and 3.RCLK =
0 causes Timer 1 overflow to be used for the receive clock
TCLK Transmit clock enable.When set,causes the serial port to use Timer 2 overflow
pulses for its transmit clock in serial port Modes 1 and 3.TCLK = 0 causes Timer
1 overflows to be used for the transmit clock
EXEN2 Timer 2 external enable.When set,allows a capture or reload to occur as a result
of a negative transition on T2EX if Timer 2 is not being used to clock the serial
port.EXEN2 = 0 causes Timer 2 to ignore events at T2EX
TR2 Start/Stop control for Timer 2.TR2 = 1 starts the timer
C/T2’ Timer or counter select for Timer 2.C/T2’ = 0 for timer function.C/T2’ = 1 for
external event counter(falling edge triggered).
CP/RL2’ Capture/Reload select.CP/RL2’ = 1 causes captures to occur on negative
transitions at T2EX if EXEN2 = 1.CP/RL2’ = 0 causes automatic reloads to
occur when Timer 2 overflows or negative transitions occur at T2EX when
EXEN2 = 1.When either RCLK or TCLK = 1,this bit is ignored and the timer is
forced to auto-reload on Timer 2 overflow.
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3.4 INTERRUPTS
The AT89S52 has a total of six interrupt vectors: two external interrupts
(INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port
interrupt. These interrupts are all shown in fig 2.5
Note that Table 5.3 shows that bit position IE.6 is unimplemented. In the
AT89S52, bit position IE.5 is also unimplemented. User software should not write 1s
to these bit positions, since they may be used in future AT89 products.
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EA - ET2 ES ET1 EX1 ET0 EX0
Enable Bit = 1enables the interrupt.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in
which the timers overflow. The values are then polled by the circuitry in the next
cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle
in which the timer overflows.
Special function registers are the areas of memory that control specific
functionality of the 89S52 microcontroller.
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The B register is very similar to accumulator. It may hold 8-bit value. The B
register is used only by MUL AB and DIV AB instructions. In MUL AB the higher
byte of the products gets stored in B register. In DIV AB the quotient gets stored in B
with the remainder in A.
The stack pointer holds 8-bit value. This is used to indicate where the next
value to be removed from the stack should be taken from. When a value is to be
pushed onto the stack, the 8052 first stores the value of SP and then stores the value at
the resulting memory location. When a value is to be popped from the stack, the 8052
returns the value from the memory location indicated by SP and then decrements the
value of SP.
The SFRs DPL and DPH work together to represent a 16-bit value called the
data pointer. The data pointer is used in operations regarding external RAM and some
instructions code memory. It is a 16-bit SFR and also an addressable SFR.
The program counter is a 16 bit register, which contains the 2 byte address,
which tells the next instruction to execute to be found in memory. When the 8052 is
initialized PC starts at 0000H and is incremented each time an instruction is executed.
It is not addressable SFR.
The power control SFR is used to control the 8052’s power control modes.
Certain operation modes of the 8052 allow the 8052 to go into a type of “sleep mode”
which consumes low power.
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g.) TCON (Timer control, 88H)
The timer mode control SFR is used to configure and modify the way in which
the 8052’s two timers operate. This SFR controls whether each of the two timers is
running or stopped and contains a flag to indicate that each timer has overflowed.
Additionally, some non-timer related bits are located in TCON SER. These bits are
used to configure the way in which the external interrupt flags are activated, which
are set when an external interrupt occur.
The timer mode SFR is used to configure the mode of operation of each of the
two timers. Using this SFR your program may configure each timer to be a 16-bit
timer, or 13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you
may configure the timers to only count when an external pin is activated or to count
“events” that are indicated on an external pin.
Gate C/ T M1 M0 Gate C/ T M1 M0
TIMER1 TIMER0
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These two SFRs together represent timer 0. Their exact behavior depends on
how the timer is configured in the TMOD SFR. However, these timers always count
up what is configurable and how and when they increment value.
These two SFRs together represent timer 1. Their exact behavior depends on
how the timer is configured in the TMOD SFR, however, these timers always count
up what is configurable and how and when they increment in value.
This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a
micro controller. Any data to be outputted to port 0 is first written on P0 register. For
e.g., bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this
SFR will send a high level on the corresponding I/O pin whereas a value of 0 will
bring it to low level.
This is port 1 latch. Each bit of this SFR corresponds to one of the pins on a
micro controller. Any data to be outputted to port 1 is first written on P1 register. For
e.g., bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this
SFR will send a high level on the corresponding I/O pin whereas a value of 0 will
bring it to low level.
This is port 2 latch. Each bit of this SFR corresponds to one of the pins on a
micro controller. Any data to be outputted to port 2 is first written on P2 register. For
e.g., bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this
SFR will send a high level on the corresponding I/O pin whereas a value of 0 will
bring it to low level.
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This is port 3 latch. Each bit of this SFR corresponds to one of the pins on a
micro controller. Any data to be outputted to port 3 is first written on P3 register. For
e.g., bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this
SFR will send a high level on the corresponding I/O pin whereas a value of 0 will
bring it to low level.
The interrupt enable SFR is used to enable and disable specific interrupts. The
low 7 bits of the SFR are used to enable/disable the specific interrupts, where the
MSB bit is used to enable or disable all the interrupts. Thus, if the high bit of IE 0 all
interrupts are disabled regardless of whether an individual interrupt is enabled by
setting a lower bit.
___
The interrupt priority SFR is used to specify the relative priority of each
interrupt. On 8052, an interrupt may be either low or high priority. An interrupt may
interrupt interrupts. For e.g., if we configure all interrupts as low priority other than
serial interrupt, the serial interrupt always interrupts the system, even if another
interrupt is currently executing no other interrupt will be able to interrupt the serial
interrupt routine since the serial interrupt routine has the highest priority.
___ ___
The Program Status Word is used to store a number of important bits that are
set and cleared by 8052 instructions. The PSW SFR contains the carry flag, the
auxiliary carry flag, the parity flag and the overflow flag.
27
r.) SBUF (Serial Buffer, 99H)
Further, the program memory and data memory both may be categorized as
on-chip (internal) and external memory, depending upon whether the memory
physically exists on the chip or it is externally interfaced. The 89S52 can address
8Kbytes on-chip memory whose map starts from 0000H and ends at 1FFFH. It can
address 64Kbytes of external program memory under the control of PSEN (low)
signal.
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes
occupy a parallel address space to the Special Function Registers. That means the
upper 128bytes have the same addresses as the SFR space but are physically separate
from SFR space. When an instruction accesses an internal location above address
28
7FH, the address mode used in the instruction specifies whether the CPU accesses the
upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing
access SFR space. For example, the following direct addressing instruction accesses
the SFR at location 0A0H (which is P2).
Instructions that use indirect addressing access the upper128 bytes of RAM. For
example, the following indirect addressing instruction, where R0 contains 0A0H,
accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H)
CHAPTER 4. MAX-232
4.1 INTRODUCTION
So, the maximum RS-232 signal levels are far too high for today's computer
logic electronics, and the negative RS-232 voltage cannot be crooked at all by the
computer logic. Therefore, to receive serial data from an RS-232 interface the voltage
has to be reduced and the 0 and 1 voltage levels are inverted. In the other direction
(sending data from some logic over RS-232) the low logic voltage has to be "bumped
up", and a negative voltage has to be generated, too.
29
+3V ... +15V <-> 0V ... +0.8V <-> 0
All this can be done with conventional analog electronics, e.g. a particular
power supply and a couple of transistors or the once popular 1488 (transmitter) and
1489 (receiver) ICs. However, since more than a decade it has become standard in
amateur electronics to do the necessary signal level conversion with an integrated
circuit (IC) from the MAX232 family (typically a MAX232A or some clone). In fact,
it is hard to find some RS-232 circuitry in amateur electronics without a MAX232A
or some clone.
The MAX232 from Maxim was the first IC which in one package contains the
necessary drivers (two) and receivers (also two), to adapt the RS-232 signal voltage
levels to TTL logic. It became popular, because it just needs one voltage (+5V) and
generates the necessary RS-232 voltage levels (approx. -10V and +10V) internally.
This greatly simplified the design of circuitry. Circuitry designers no longer need to
design and build a power supply with three voltages (e.g. -12V, +5V, and +12V), but
could just provide one +5V power supply, e.g. with the help of a simple 78x05
voltage converter.
The MAX232 has a successor, the MAX232A. The ICs are almost identical,
however, the MAX232A is much more often used than the original MAX232, and the
MAX232A only needs external capacitors 1/10th the capacity of what the original
MAX232 needs.
It should be noted that the MAX232 (A) is just a driver/receiver. It does not
generate the necessary RS-232 sequence of marks and spaces with the right timing, it
does not decode the RS-232 signal, it does not provide a serial/parallel conversion. All
it does is to convert signal voltage levels. Generating serial data with the right timing
and decoding serial data has to be done by additional circuitry, e.g. by a 16550 UART
or one of these small micro controllers (e.g. Atmel AVR, Microchip PIC) getting
more and more popular.
The MAX232 and MAX232A were once rather expensive ICs, but today they
are cheap. It has also helped that many companies now produce clones (ie. Sipex).
30
These clones sometimes need different external circuitry, e.g. the capacities of the
external capacitors vary. It is recommended to check the data sheet of the particular
manufacturer of an IC instead of relying on Maxim's original data sheet.
The original manufacturer (and now some clone manufacturers, too) offers a
large series of similar ICs, with different numbers of receivers and drivers, voltages,
built-in or external capacitors, etc. E.g. The MAX232 and MAX232A need external
capacitors for the internal voltage pump, while the MAX233 has these capacitors
built-in. The MAX233 is also between three and ten times more expensive in
electronic shops than the MAX232A because of its internal capacitors. It is also more
difficult to get the MAX233 than the garden variety MAX232A.
Capacitor Capacitor
Nbr Name Purpose Signal Voltage
Value Value
31
+10V, capacitor should stand at 1µF to 100nF to
2 V+ output of voltage pump
least 16V VCC VCC
1µF to 100nF to
15 GND Ground 0V
VCC VCC
32
V+(2) is also connected to VCC via a capacitor (C3). V-(6) is connected to
GND via a capacitor (C4). And GND (16) and VCC (15) are also connected by a
capacitor (C5), as close as possible to the pins.
The MAX232 (A) has two receivers (converts from RS-232 to TTL voltage
levels) and two drivers (converts from TTL logic to RS-232 voltage levels). This
means only two of the RS-232 signals can be converted in each direction. The old
MC1488/1498 combination provided four drivers and receivers.
• TX and RX
There are not enough drivers/receivers in the MAX232 to connect the DTR,
DSR, and DCD signals. Usually these signals can be omitted when communicating
with a PC's serial interface. If the DTE really requires these signals either a second
MAX232 is needed, or some other IC from the MAX232 family can be used (if it can
be found in consumer electronic shops at all). An alternative for DTR/DSR is also
given below.
33
Fig: 4.2:Max232 Application
C1 1 3
C2 4 5
C3 2 16
C5 16 GND
• +5V: Pin 16
• GND: Pin 15
34
CHAPTER 5: SERIAL TO USB CHIP
FEATURES
35
TYPICAL APPLICATIONS
4 D+ Usb Pin D+
D- Usb Pin D-
PIN DIAGRAM
1 2
8
R 2 2
TX 3 2
6
4 2
D 5 2
- 4 FIG 5.1: PIN
D 6 2
DIAGRAM OF
VC 7 2 GN
GND 2 D
8
XTA 9 2 VCC
0
XTAL 10 1
2 9
11 36 1
14
13
12 1
ASYNCHRONOUS SERIAL DATA BUS (UART) INTERFACE
The UART interface consists of the TX (transmit) and RX (receive) data
signals. The UART does not support RTS/CTS,DSR/DTR and X-On/X-Off
handshaking. The UART supports a variety of data formats and baud rates. The data
format and baud rate programmed into the UART is set during COM port
configuration on the PC. The data formats and baud rates available are listed in table
below.
PARAMETERS VALUES
SYSTEM REQUIREMENTS:
37
•
Fig5.2:Schematic diagram
of serial l2 usb
NOTE:
38
CHAPTER 6: INTERFACING
POWER SUPPLY
The step downed a.c. voltage is being rectified by the Bridge Rectifier. The
diodes used are 1N4007. The rectified a.c voltage is now filtered using a ‘C’ filter.
Now the rectified, filtered D.C. voltage is fed to the Voltage Regulator. This voltage
regulator allows us to have a Regulated Voltage which is +5V.
The rectified; filtered and regulated voltage is again filtered for ripples using
an electrolytic capacitor 100μF. Now the output from this section is fed to 40 th pin of
89c51 microcontroller to supply operating voltage.
The microcontroller 89c51 with Pull up resistors at Port0 and crystal oscillator
of 11.0592 MHz crystal in conjunction with couple of capacitors of is placed at 18th
& 19th pins of 89c51 to make it work (execute) properly.
The 10th and 11th pins of the max232 are connected to the microcontroller p3.0
and p3.1 pins.
The second and third pins of the USB are given to the receive and transmit
pins of the microcontroller i.e pin p3.0, p3.1.
The max232 IC is working as the interface between the USB and the
microcontroller .
The 4th and 5th pins are connected to the burg stripes through the resistances as
shown in the diagram.
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The 12MHz crystal is connected to the 9th and 10th pins of the serial to USB.
The receive and transmit pins are connected to microcontroller pins.
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CONCLUSION:
The project “Development of Serial UART from Mini USB” has been
successfully designed and tested. It has been developed by integrating features of
all the hardware components used. Presence of every module has been reasoned out
and placed carefully thus contributing to the best working of the unit.
Secondly, using highly advanced IC’s and with the help of growing
technology the project has been successfully implemented.
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BIBLIOGRAPHY
[1]. Mr. Mazidi, “The 8051 Microcontroller and Embedded Systems”, PHI, 2000
[2]. Mr. A.V. Deshmuk, “Microcontrollers (Theory & Applications)”, WTMH, 2005
[1]. http://www.atmel.com/dyn/resources/prod_documents/doc1919.pdf
[2]. http://www.lammertbies.nl/comm/info/serial-uart.html
[3]. http://www.beyondlogic.org/serial/serial.htm
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