GaN Transistors for Efficient Power Conversion

Agenda
• How GaN works
• Electrical Characteristics
• Design Basics
• Design Examples
• Summary

2
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How GaN Works

3
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 The Ideal Power Switch
• Block Infinite Voltage
• Carry Infinite Current
• Switch In Zero Time
• Zero Drive Power
• Normally Off

4
4
 Power Switch Wish List
• Faster
• Lower Conduction Loss
• Less Capacitance
• Smaller
• Lower Cost

5
Material Comparison

6 6
GaN + AlGaN
Spontaneous Polarization

AlGaN
GaN

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7
 GaN Magic
V

AlGaN
GaN

“2D Electron Gas”

8
8
GaN Switch
V Applying bias destroys
the polarization

AlGaN
E Field

GaN

9
9
 Now we have a switch
GaN Switch
That has high voltage blocking
V capability,
low on resistance, and is
very, very fast.

AlGaN
GaN

Depletion Mode = Normally On

10
10
Device Construction Concept
Protection Dielectric
AlGaN
Gate
Drain
Source

GaN
Substrate

Early substrate materials: SiC and Sapphire

Are expensive and hard to manufacture. Silicon
substrates are much lower cost and allow
fabrication in a standard CMOS Fab.
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What About Normally Off Devices?
• True enhancement mode GaN HFETs have
been around for years
• There are various methods for dissipating the
electron gas under the gate

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Enhancement Mode

A positive voltage from Gate-To-Source

establishes an electron gas under the gate

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State of the Art

1414
 Body Diode?

A positive voltage from Gate-To-Drain

also establishes an electron gas under the gate

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eGaN® FET Reverse Conduction

MOSFET

+ QRR

eGaN FET

+ Zero QRR

16
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 Threshold vs. Temperature
1.2

1.1
Normalized Thershold Voltage

0.9

0.8

GaN FET
eGaN
MOSFET A
0.7

0.6
-50 -25 0 25 50 75 100 125 150
Junction Temperature (°C)
17
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MOSFET Transfer Characteristics

Negative temperature coefficient region of

silicon MOSFET

Source: www.infineon.com
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eGaN® FET Transfer Characteristics
EPC2001

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eGaN® FET Safe Operating Area

1 ms

10 ms

100 ms

DC

20
eGaN® FET Safe Operating Area

1 ms

10 ms

100 ms

DC

21
eGaN® FET Capacitances
CGS
CDS

GaN

Silicon

CGD

22
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 Total Gate Charge

BSC057N08NS

EPC2001 = 100 V, 5.6 mΩ typ

BSC057N08 = 80 V, 4.7 mΩ typ
23
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 Figure of Merit

FOM = Rdson x Qg (100V)

500

400

300

200

100

0
EPC2001 BSC109N10NS3 IRFH5030 SiR870DP FDMS86101

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eGaN® FET Loss Mechanisms
Like A MOSFET Not Like A MOSFET
• I²R Conduction Loss • High Reverse
• Capacitive Switching Conduction Loss
Losses • No Body Diode Reverse
• Gate Drive Losses Recovery Loss
• V×I Switching Loss

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eGaN® FET Loss Mechanisms
Like A MOSFET Not Like A MOSFET
• I²R Conduction Loss • High Reverse
• Capacitive Switching Conduction Loss
Losses • No Body Diode Reverse
• Gate Drive Losses Recovery Loss
• V×I Switching Loss

Can be much, much better than

comparable silicon MOSFET
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 Package Wish List
• Low parasitic resistance
• Low parasitic inductance
• Low thermal resistance
• Small size
• Low cost

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Flip-Chip LGA Construction

eGaN FET Silicon

Solder
Bar

Copper
Trace

Printed Circuit Board

Absolute minimum
lead resistance and inductance!
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 LGA Construction
Interleaving to reduce
Drain Contacts layout inductance

Substrate

Gate

Source Contacts
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 Size Comparison – 200 V
D-PAK

eGaN FET

5.76 mm²

Drawn To Scale 65.3 mm²

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 Key Applications
• Wireless Power Transmission – GaN Enabled
• RF DC-DC “Envelope Tracking” – GaN Enabled
• RadHard
• Power Over Ethernet
• RF Transmission
• Network and Server Power Supplies
• Point of Load Modules
• Energy Efficient Lighting
• Class D Audio

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 Design Basics Agenda

• Gate Driver Requirements

• Layout
• Thermal Management

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E-Mode Gate Drive - Low VGS(ON) Overhead

VGS(Max) = 6 V

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 Gate Drive Solution
No overshoot:

4( LG + L S )
RG ≥
CGS

• Minimize inductance
– Tight gate drive layout
– BGA and LGA minimizes package inductance
– Choose correct resistance
• Separate source and sink transistors allowing
for separate drive paths.
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 Bootstrap Supply
VIN
HB
+5V

HOH
LEVEL
SHIFT HOL

HS

• Switch can be node

negative during low side
diode conduction
• Regulated high side
supply
• Minimal dead time
and slow bootstrap
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 High Side Regulation – LM5113

• Bootstrap clamp limits floating (HS)

power supply
• Separate control inputs allow accurate,
flexible tuning to minimize dead-time
• Well matched channel-to-channel
propagation delays are critical
• Optional Schottky in parallel

Texas Instruments, “Gate Drivers for Enhancement Mode GaN Power FETs 100 V Half-Bridge and Low-
Side Drivers Enable Greater Efficiency, Power Density, and Simplicity”, SNVB001
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Layout

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 Packaging Evolution

So-8 LFPAK DirectFET LGA eGaN

Device Loss Breakdown 90

So-8
2.5 Package VIN =12V LFPAK
VOUT =1.2V 85
DirectFET

Efficiency (%)
Power Loss (W)

Die
2 IOUT =20A eGaN
80
FS =1MHz
1.5 82%
75
1 73%
70
47% 18%
0.5
18% 27% 53% 82% 65
0 0.5 1 1.5 2 2.5 3 3.5
So-8 LFPAK DirectFET LGA Switching Frequency (MHz)

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Generating Kelvin Source Connection

Source Return RSource

Source CGD

RSeries
Substrate
RG
Gate CGS

RSink
LS
Drain

Minimize Common Source Inductance

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 Buck Converter Parasitics

T Power Loss vs Parasitic Inductance

5.5
5.25
5

Power Loss(W)
4.75
Cin
SR 4.5
4.25
LLoop
4 Ls
3.75
3.5
3.25
LS: Common Source 3
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
Inductance Parasitic Inductance (nH)
VIN=12 V, VOUT=1.2 V,
LLoop: High Frequency FS=1 MHz, IOUT= 20 A
Power Loop Inductance
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 Layout Impact on Efficiency
Measured Efficiency
91
90 Experimental Prototype
89 LLoop≈ LLOOP≈0.4 nH
Efficiency (%)

0.4nH
88 LLoop≈
87 1.0nH

86 LLoop≈
40V MOSFET 1.6nH
85
3x3mm LFPAK LLoop≈
84 LLoop≈3nH 2.9nH
83
2 4 6 8 10 12 14 16 18 20 22 24
Output Current (IOUT)

VIN=12 V, VOUT=1.2 V,
FS=1 MHz, L=150 nH
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Layout Impact on Peak Voltage
LLoop≈1.0 nH LLoop ≈ 0.4 nH

70% Overshoot 30% Overshoot

Switching Node Voltage

VIN=12 V VOUT=1.2 V IOUT=20 A
FS=1 MHz L=150 nH
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Conventional Lateral Layout

Top View Side View

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Conventional Vertical Layout
Top View
Side View

Bottom View
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Optimal Layout
Top View
Side View

Top View
Inner Layer 1
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Power Loss Comparison
4
3.9 Lateral Power
3.8 Loop
Power Loss (W)

3.7
3.6
3.5 Vertical Power
3.4 Loop
3.3
3.2
Optimal Power
3.1
Loop
3
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
High Frequency Loop Inductance (LLOOP)
VIN=12 V VOUT=1.2 V IOUT=20 A FS=1 MHz L=300 nH
T/SR: EPC2015 Driver LM5113 46
46
Efficiency Comparison
91
90
89 Optimal
Efficiency (%)

Design 1
88
Vertical
87 Design 1
86 Lateral
Design 1
85 40V MOSFET
Design 1
84
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2 4 6 8 10 12 14 16 18 20 22 24 26
Output Current (IOUT)
VIN=12 V VOUT=1.2 V FS=1 MHz L=300 nH
T/SR: EPC2015 Driver LM5113 47
47
 eGaN ® FET vs. MOSFET
Si MOSFET

eGaN FET

VIN=12 V VOUT=1.2 V IOUT=20 A FS=1 MHz L=300 nH eGaN FET

T/SR: EPC2015 MOSFET T:BSZ097N04LS SR:BSZ040N04LS
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 Layout Summary
eGaN FETs improve performance in high switching
frequency converters
• CSI is a critical component for maximizing
switching performance
• Gate drive loop inductance limits switching speed
• Optimizing power loop inductance improves
efficiency and minimizes voltage overshoot
• Current measurements affect performance
• Voltage measurements are bandwidth limited
• Reduced ringing reduces EMI
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Thermal Management

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 Thermal Management
Heat Is Generated In GaN Material
Essentially On The Surface Of The Die

Silicon Substrate

Active GaN Device Region

Solder Bars

Copper Traces
Printed Circuit Board

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 Thermal Management

Silicon Substrate
RƟJC
Active GaN Device Region

Solder Bars RƟJB

Copper Traces
Printed Circuit Board

Two Paths For Heat: Through The Back Of The Die Or

Through The Solder Contacts Into The PCB
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Thermal Resistance with Heat Sink

Silicon Substrate
RƟJC
Active GaN Device Region

Solder Bars RƟJB

Copper Traces
Printed Circuit Board

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Thermal Resistance with Heat Sink

2
22

Printed Circuit Board

1
Thermal Interface Material on sides of die too
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Thermal Model with Heat Sink
R θHA
Heatsink Ambient Temperature
Back of Die
temperature R θTIM R θTIM

Junction RθJC RθJC

temperature
Other PCB
RθJB
RθJB losses

R θspread
Device 1 Device 2
Power R θPCBA Power
dissipation dissipation
Ambient
Temperature

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Thermal Results

Possible to remove up
to 5 W from small EPC
die with double sided
cooling
56
 Design Example Agenda
• Hard Switched Circuits
– Buck Converter
– Isolated Full Bridge
– Envelope Tracking
• Resonant Circuits
– Intermediate Bus Converter

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Buck Converters

58
High Frequency Buck Converters

D. Reusch, D. Gilham, Y. Su, and F.C. Lee, C, “Gallium Nitride Based 3D Integrated Non-Isolated Point of
Load Module”, APEC 2012
59
 EPC9107 Optimal Layout
Buck Module
Switching Node Voltage
VIN=28 V IOUT=15 A

EPC9107
Demonstration Board
VIN=12-28 V VOUT=3.3 V
IOUT=15 A FS=1 MHz
2 x EPC2015
5 V/ div
60
EPC9107 Demonstration Board
97
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95
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Efficiency (%)

93
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91
90
89
88
87
12 VIN
86 19 VIN
85 24 VIN
84 28 VIN
83
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Output Current (Io)
VOUT=3.3 V FS=1 MHz
GaN T/SR: EPC2015 Driver LM5113 61
Isolated Full Bridge

62
100 V Hard Switching FOM
160
FOM=(QGD+QGS2)*RDSON (nC*Ω)

140

120 QGS2

100
QGS2
80

60 QGD
QGS2
QGS2 QGD
40

QGS2 QGD QGD

20
QGD
0
100V eGaN®FET 80V MOSFET 1 80V MOSFET 2 80V MOSFET 3 80V MOSFET 4

VDS=0.5*VDS , IDS= 15 A
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 Regulated Full Bridge Converter
EPC9102 Demo board
Full Bridge, 36 - 60 Vin, 12 V, 200 W, 375 kHz

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Efficiency Comparison
375 kHz eGaN FET

250 kHz MOSFET

Regulated 12 V Output
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 Brick Converter Summary
• Topologies varied
• Optimization as important as device selection
• Efficiency is key to power density
• Maximum power loss is fixed.
• Good comparison requires identical designs
• Given topology, eGaN FETs will outperform
MOSFETs based on superior FOM

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 Overview of Envelope Tracking

• World of Radio Frequency Power Amplifiers (RFPA)

is changing.

• Increased efficiency driven by:

– Improved battery life
– Reduced cooling
– Reduced size
– Lower cost of operation
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 Peak to Average Power Ratio

Same average

Normalized
to same peak

Ref: Nujira.com website

68
 Effect of PAPR
Average Peak Power
Power

PAPR = 0dB
Fixed supply
Peak efficiency
up to 65%

Average efficiency Output

only 25 % Probability
Increasing PAPR

Output Power (dBm)

69
Effect of Envelope Tracking
Average efficiency Only 1/3 the losses
> 50 % (incl. ET)

Envelope Tracking

Output
Probability
Average
Power

Output Power (dBm)

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 RFPA Standards*

• Up to 20 MHz Carrier bandwidth required

• Required ET supply BW up to 5x higher if linear control
*Ref: www.open-et.org website
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 Envelope Tracking Supply
• ET power supply topologies vary
– Open loop boost – full BW required
– Closed loop linear-assisted Buck*

Buck ~ 10% Bandwidth

~ 90% Power

Linear AMP ~ 10% Power

Highest 90% of Bandwidth

*V. Yousefzadeh, et. Al, Efficiency optimization in linear-assisted switching power converters for envelope
tracking in RF power amplifiers, ISCAS 2005
72
 eGaN® FET based Buck(s) for ET

1300 W DVB* – 8 MHz BW and 8 dB PAPR

Linear-assisted Buck for ET
4 phase x 1 MHz Buck with up to 800 kHz band
width
45 VIN, 22 VOUT/ 15 AOUT (Avg)
Pure Buck option for ET (Push frequency)
10 phase x 4 MHz Buck with up to 8 MHz band
width
45 VIN, 22 VOUT/ 6 AOUT (Avg)
*Representative of a high power ET buck in HV LDMOS, such as that implemented by ET specialist Nujira.
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 6 AOUT / 4 MHz Single φ Buck
• Modified an EPC9006 development board
45 VIN
Before After

22 VOUT
Common
LM5113TE
Gappad GP1500
60 mil

EPC2007

74
 Efficiency Results
98% 16
10x potential bandwidth require 2.5x more phases and 2x losses
97% 14

96% 12

Power loss (W)

95% 10
Efficiency (%)

94% 8

93% 6
4 MHz Efficiency
92% 1 MHz Efficiency 4

91% 4 MHz Losses 2

1 MHz Losses
90% 0
0 50 100 150 200 250 300 350
Output Power (W)
75
 Loss Breakdown
EPC2007
EPC2001

EPC2001
EPC2007

1 MHz EPC9002 4 MHz EPC9006

Future die size optimization possible 76
76
Higher Frequency ET Results*
EPC1014

20 to 30 pp improvement!
BSC016N04LSG 4 MHz

7 MHz
24 VIN to 12 VOUT Buck 10 MHz

*D. Čučak, et. al, “Application of eGaN FETs for highly efficient Radio Frequency Power Amplifier”, CIPS
2012
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Envelope Tracking Summary
• eGaN FETs are an enabling technology for ET
– Low charge reduces delay and switching times
– Thermally possible - with double sided cooling
• Results are representative, but not optimized
– Improve inductor selection
– Improve thermal design
– Reduce high side peak device temp by reducing low
side device size to reduce QOSS losses
• Power and # of phases application specific

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Resonant Converters

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100 V Soft Switching FOM
350
FOM=(QOSS or QG)*RDSON (nC*Ω)

300

250

200
QOSS QOSS
150
QOSS
100
QG QG
50
QG
0
100 V EPC2001 80 V BSC057N08NS3G 80 V BSZ123N08NS3G

VDS=48 V
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eGaN® FET vs. MOSFET

81
ZVS Switching Comparison

TZVS = 42 nS
eGaN FET VDS
MOSFET VGS
MOSFET VDS
TZVS = 87 nS
eGaN FET VGS

FS = 1.2 MHz, VIN = 48 V, and VOUT = 12 V

82
Duty Cycle Comparison

DeGaN FET = 42%

D MOSFET = 34% eGaN FET VDS
MOSFET VGS

MOSFET VDS
eGaN FET VGS

FS = 1.2 MHz, VIN = 48 V, and VOUT = 12 V

83
 Efficiency Comparison
98 24
1.2 MHz 10 W
12 W 22
97 eGaN FET 14 W 20
1.2 MHz

Power Loss (W)

96
Efficiency (%)

18
16
MOSFET
95
1.2 MHz 14
94
MOSFET 12
93 10
92 8
6 1.2 MHz
91
4 eGaN FET
90 2
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Output Current (IOUT) Output Current (IOUT)

FS = 1.2 MHz, VIN = 48 V, and VOUT = 12 V

84
 Loss Breakdown
Power Loss
(W)
12

10
Gate Drive
8
Transfomrer
Core
6
Conduction +
Turn Off
4

0
eGaN FET MOSFET eGaN FET MOSFET
IOUT = 2.5 A IOUT = 2.5 A IOUT = 20 A IOUT = 20 A

FS = 1.2 MHz, VIN = 48 V, and VOUT = 12 V

85
 EPC9105 Bus Converter
EPC9105 Demonstration Board
36 - 60 VIN, 12 VOUT, 350 W, 1.2 MHz

LIN

2 SR
LK1

Q1 Q3
VIN+ 4:1

*
Q6,Q7 VOUT+

*
LOUT
CIN
CRES COUT
*

VIN- Q2 Q4 2 SR
LK2

Q5,Q8
VOUT-
86
Resonant Converter Summary

• eGaN FETs improve high frequency

resonant converter performance
– Lower output charge
– Lower gate charge
– More power delivery per cycle

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 Summary
• GaN transistors have the potential to replace
silicon power MOSFETs in power conversion
applications with a low-cost and higher
efficiency solution
• eGaN FETs are straightforward to use, but care
must be taken due to the higher switching
speeds compared with power MOSFETs
• GaN transistors enable exciting new
applications such as RF Envelope Tracking

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