IEEE COMMUNICATIONS LETTERS, VOL. 15, NO.
6, JUNE 2011
eIRA LDPC Codes on FPGA
John Ding and Michael Yang
Abstract—eIRA codes [1] are iteratively decodable low-density
parity-check (LDPC) codes. They not only offer superior per-
formance to alternative approaches, but they allow linear-time
encoding. Well-designed eIRA codes also achieve extremely low
error-rate floors. In this letter, we successfully implement a
common FPGA platform for eIRA codes. As a demonstration, we
took an example parity-check matrix from Example 4 in [1]. For
a maximum of seven iterations and 7 bits precision, the error-
rate degradation is less than two tenths of a decibel compared to
the double precision floating point result. It is important to note
that there is no error rate floor close to BER of 10−12 . Such a
performance is often requested in practical applications, but has
never been achieved by graphic codes in the literature so far as
we know.
Index Terms—eIRA codes, LDPC codes, error-rate floor, error
correction codes, FPGA.
I. I NTRODUCTION
L OW-density parity-check (LDPC) codes are linear block
codes defined on sparse parity-check matrices. They
were first proposed by Gallager [5] in the early 1960’s, and
rediscovered by MacKay and Neal in 1996. The error-rate
performance of these codes can be as close as one tenth of
a decibel away from the Shannon limit, given sufficiently
long codeword lengths, surpassing even turbo codes in many
cases. Beside their excellent error correction performance, the
inherent parallel or partially parallel decoder yields a remark-
able throughput, while encoding complexity can be largely
alleviated by the fully structured or semi-random parity-check
matrices, which usually can be categorized as either quasi-
cyclic constructions or algebraic constructions. Therefore, we
have witnessed an explosion of papers surrounding the design
and implementation of LDPC codes in the recent literature.
As a popular subset of LDPC codes, eIRA codes has
been proposed by Yang, et al. [1], where they showed there
was no error-rate floors at BER of 10−9 by floating-point
emulation. These codes also have a linear-time encoder besides
the capacity-approaching error control capability. Given all of
these favorable characteristics, eIRA codes have been consid-
ered good candidates for next-generation forward error control
in high throughput communication and broadcasting applica-
tions, such as ETSI DVB-S2 HDTV broadcasting standard,
IEEE 802.16e and IEEE 802.11n wireless communications
standards, etc. To facilitate hardware implementation, the
parity-check matrices adopted by these standards are mostly in
a fully structured format. However, the fully structured format
not only restrains the capacity-approaching error control capa-
bility, but also confronts an early error-rate floor. On the other
Manuscript received February 16, 2011. The associate editor coordinating
the review of this letter and approving it for publication was V. Stankovic.
The authors are with Syscomm Research, Irvine, CA 92620 USA (e-mail:
John.DingJun@gmail.com).
Digital Object Identifier 10.1109/LCOMM.2011.040711.110336
1089-7798/11$25.00 ⃝
665
hand, many applications forbid an early error-rate floor, such
as magnetic recoding, satellite communication, fiber optical
transmission, etc. Semi-random codes, for these instances, are
more promising than structured codes with both very good
performance and very low error-rate floors [1]-[4].
In this letter, we report a common FPGA platform for any
eIRA codes in both semi-random and quasi-cyclic format.
Thanks to the power of silicon, we are able to exploit the
depth of the error-rate floor close to BER of 10−12 . In section
II, we briefly review several aspects of eIRA codes. The
design as a blueprint in section III outlines the error-rate floor
performance of eIRA decoder. Section IV concludes the letter.
II. E IRA C ODES
A. Linear-Time Encoder
As (𝑛, 𝑘) linear block codes, the parity-check matrix of
eIRA codes can be represented as 𝐻 = [𝐻1 ∣𝐻2 ](𝑛−𝑘)×𝑛 ,
where 𝐻1 is a sparse (𝑛 − 𝑘) × 𝑘 matrix, and 𝐻2 is a full rank
square (𝑛 − 𝑘) × (𝑛 − 𝑘) matrix whose columns are weight-2
except the last one. The main advantage of the dual-diagonal
𝐻2 matrix is that the obtained codes can be encoded in linear
time. Corresponding to the non-systematic bits, this peculiar
matrix format ensures that the degree-2 nodes do not form a
cycle among themselves. It has been shown in [1] that such a
constraint leads to negligible performance losses.
B. High-Speed Decoder
The message-passing (MP) usually refers to the iterative
belief propagation, or sum-product algorithm (SPA); and Min-
Sum algorithm is a reduced-complexity approximation of SPA.
The performance loss of Min-Sum algorithm can be largely
compensated by the linear post-processing, coupling with
either a normalization term or an additive offset term of the
soft information [8].
Mansour [9] proposed the turbo decoding message passing
(TDMP) for LDPC codes. TDMP offers two-time throughput
and significant memory advantage comparing to traditional
two-phase message passing (TPMP). As of FPGA implemen-
tation, LDPC decoder can be implemented in the forms of
fully parallel TPMP, partially parallel TPMP, serial TDMP, and
partially parallel TDMP with reduced-complexity and higher
throughput in the order of this list.
Following Mansour’s pioneer work [9], we implement a
partially parallel TDMP decoder on FPGA. Multiple normal-
ized min-sum processors share the computation of all the
check nodes. Pipeline register has been adopted to increase the
throughput. RAM stores and updates the channel inputs, while
FIFO keeps intermediate data during the decoding process.
The sign of the number in the RAM indicates the bit decision.
c 2011 IEEE
666 IEEE COMMUNICATIONS LETTERS, VOL. 15, NO. 6, JUNE 2011

eIRA (4550, 4095) Code on AWGN Channel

C. Lowering the Error-Rate Floor
−2
10
HW7 Pcw
HW7 Pb
There are many promising technologies targeting the −3
10 HW8 Pcw

dilemma of error-rate floor, including, but not exclusively, −4

HW8 P
SW Pcw
b

by removing the near-codewords [6] and by breaking down

10
SW P
b

the trapping sets [7], etc. All of these advanced technologies −5

10

can be easily applied to the design of a non-structured sparse

matrix 𝐻1 , conditioning on the dual-diagonal 𝐻2 matrix.

Probability of Error Rate

−6
10

Sophisticated design technologies can largely recuperate the −7

10
steep waterfall from a seemly inevitable error-rate floor for
eIRA codes in the relatively high SNR region. Figure 5 in [1] −8
10

exhibits the accomplishment of lowering error-rate floor efforts −9

at a cost of less than two tenths of a decibel by balancing the 10

density of parity-check matrices, removing short cycles from −10

10

matrix 𝐻1 , as well as the inherent strength from cycle-free

matrix 𝐻2 . The same technology has been developed here to −11
10

design the parity-check matrices presented in this letter. −12

10
3.5 4 4.5 5 5.5 6
Eb/N0 (dB)

III. E RROR -R ATE P ERFORMANCE Fig. 1. Performance of the rate-0.9 eIRA code “HW7”: denotes FPGA in 7
bits precision and a maximum of seven iterations; “HW8”: denotes FPGA in
Our FPGA common platform is able to execute both 8 bits precision and a maximum of seven iterations; “SW”: denotes double-
the fully structured and the semi-random eIRA codes. To precision floating point software emulation with a maximum of fifty iterations.
achieve the high speed design goal, the Altera Stratix IV
EP4SE530H40C2ES development board is chosen, and Quar- TABLE I
PARAMETERS FOR E IRA D ECODER
tus II 10.0 SP1 is used for synthesis and fitting.
Development Board Altera Stratix IV
Tools Quartus II 10.0 SP1
A. Example 1 ALUTs 47,002 / 424,960 (11%)
As a demonstration, we took example eIRA code parity- Registers 3,853 (<1%)
check matrix from Example 4 in [1]. The particular parity- RAM(bits) 135,296 / 21,233,664 (<1%)
check matrix has been extensively evaluated by various storage Code Spec (4550, 4095)
companies as well as for deep-space missions. The degree Code Rate 0.9
distributions for this rate-0.9 (4550, 4095) code are, Iteration 7
Parallelism 5
𝜆(𝑥) = 0.0000467𝑥0 + 0.0425𝑥 + 0.9574𝑥4 Quantization 7 bits
(1) Throughput 166 Mbps
𝜌(𝑥) = 0.0000467𝑥45 + 0.9999𝑥46
Frequency 129 MHz
The error-rate performance is presented in Fig. 1. We show
here both the codeword error-rates 𝑃𝑐𝑤 and the bit error-
rates 𝑃𝑏 . For a maximum of seven iterations and 7 bits B. Example 2
precision (i.e., solid-lines denoted as “HW7”), throughout the As another example, we apply the common platform to
measurable region of SNR, the error-rate degradation is less another semi-random eIRA code. The degree distributions for
than two tenths of a decibel compared to the floating point this rate-0.84 (2043, 1718) code are,
result (i.e., dotted-lines denoted as “SW”). The dashed-lines
represent a maximum of seven iterations and 8 bits precision, 𝜆(𝑥) = 0.000108𝑥0 + 0.07014𝑥 + 0.92975𝑥4
(3)
denoted as “HW8” accordingly. It is important to note that 𝜌(𝑥) = 0.5637𝑥27 + 0.4363𝑥28
there is no error-rate floor close to BER of 10−12 .
The error-rate performance is presented in Fig. 2, where we
We implemented this parity-check matrix on our FPGA
still observe the absence of an error-rate floor close to BER
common platform. Compilation report and performance result
of 10−12 with a maximum of ten decoding iterations and 7
are shown in Table 1. Decoding throughput is determined by
bits precision. For the record, we accumulated 15 error-events
the frequency, the dimensions of the parity-check matrix, as
containing 328 error-bits among a total of 25,621,180,004
well as the maximum iteration number.
codewords at 4.92 dB.
𝑘 Table 2 shows the compilation report and performance
𝑇 ℎ𝑟𝑜𝑢𝑔ℎ𝑝𝑢𝑡 = 𝑓𝑐𝑙𝑘 ⋅ (2)
(𝑛 − 𝑘) ⋅ 𝐼𝑡𝑒𝑟𝑎𝑡𝑖𝑜𝑛𝑠 result.

Alternatively, “instant throughput” only considers the aver-

age iteration number at a particular SNR. As of this example, C. Comparison
since the average number is 1.2 iterations around 5 dB, the One TDMP decoder [9] achieves a throughput of 640Mbps
“instant throughput” could be as high as 968 Mbps. at 1.4 dB for a (2048, 1024) structured LDPC code with
DING and YANG: EIRA LDPC CODES ON FPGA 667

eIRA (2043, 1718) Code on AWGN Channel

IV. C ONCLUSION
−3
10
HW7 Pcw

−4
10
HW7 P
b
A few breakthroughs have been made in channel coding
theory in the last decades. In a giant step they brought us to
−5
10 as close as a fraction of dB to the theoretical limit of reliable
transmission of information. These breakthroughs can be in
−6
10 general terms referred to as iteratively decodable codes.
This letter presented the results of our years of continuing
Probability of Error Rate

efforts in both the iterative decoding theory and the hardware

−7
10

−8
implementation. We are so excited about these results not only
10
because of their theoretical beauty, but also because of the
−9
10
fact that they have been implemented in silicon by ourselves.
We have enriched our experience by closing a full research
−10
10 cycle from obscure things as coding theory, graph theory
and applied artificial intelligence to the system architecture,
hardware complexity issues, etc.
−11
10

−12
We have successfully designed semi-random eIRA codes
which superior in performance to alternative approaches with-
10
3.5 4 4.5 5 5.5
Eb/N0 (dB)
out error-rate floor close to BER of 10−12 . The error-rate
Fig. 2. Performance of the rate-0.84 eIRA code “HW7” denotes FPGA in results of a rate-0.9 (4550, 4095) and a rate-0.84 (2043, 1718)
7 bits precision and a maximum of ten iterations. semi-random eIRA codes from our FPGA common platform
well demo its efficacy.
TABLE II
PARAMETERS FOR E IRA D ECODER
ACKNOWLEDGMENT
Development Board Altera Stratix IV The authors would like to thank Prof. W. E. Ryan and Prof.
Tools Quartus II 10.0 SP1 P. H. Siegel for valuable suggestions and helpful comments.
ALUTs 22,767 / 424,960 (5%)
Registers 3,451(<1%) R EFERENCES
RAM(bits) 48,384 / 21,233,664 (<1%)
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Code Spec (2043, 1718) moderate-length high-rate irregular LDPC codes,” IEEE Trans. Commun.,
Code Rate 0.84 vol. 52, no. 4, pp. 564-571, Apr. 2004.
Iteration 10 [2] M. Yang and W. E. Ryan, “Lowering the error-rate floors of moderate-
length high-rate irregular LDPC codes,” in Proc. 2003 Int. Symp. Infor-
Parallelism 5
mation Theory, p. 237, July 2003.
Quantization 7 bits [3] L. Dinoi, F. Sottile, and S. Benedetto, “Design of versatile eIRA codes for
Throughput 75 Mbps parallel decoders,” IEEE Trans. Commun., vol. 56, no. 12, pp. 2060-2070,
Frequency 141 MHz Dec. 2008.
[4] Y. Zhang and W. E. Ryan, “Toward low LDPC-code floors: a case study,”
IEEE Trans. Commun., vol. 57, no. 6, pp. 1566-1573, June 2009.
[5] R. G. Gallager, Low Density Parity Check Codes. MIT Press, 1963.
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parallelism equals 64. We manage a parallelism of 5 for both Margulis low-density parity-check codes,” Electronic Notes Theoretical
examples, which constrains the throughput in second example Computer Science, vol. 74, 2003.
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