IEDM 2017 - Controlling Threshold Voltage With Work Function Metals - SemiWiki PDF

3/31/2020 IEDM 2017 – Controlling Threshold Voltage with Work Function Metals – SemiWiki
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March 31 @ 11:00 AM - IEDM 2017 – Controlling Threshold
12:00 PM Voltage with Work Function Metals
by Scotten Jones on 01-26-2018 at 7:00 am
Prevent and Categories: FinFET, Foundries, IC Knowledge
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Eliminate IR drop
and Power...
As I have said many times, IEDM is one of
March 31 @ 11:00 AM -
12:00 PM the premier conferences for semiconductor
technology. On Sunday before the formal
The Surface
Preparation and conference started I took the “Boosting
Cleaning... Performance, Ensuring Reliability, Managing
April 1 - April 2 Variation in sub-5nm CMOS” short course.
SEMI Texas Spring

The second module in the course was
Forum 2020 “Multi-Vt Engineering and Gate
April 1 Performance Control for Advanced FinFET
Architecture” taught by Steven Hung of
Fast, Accurate
Analog/Mixed- Applied Materials. This excellent module
Signal... was particularly timely because
April 2 @ 11:00 AM - GLOBALFOUNDRIES and Intel gave papers
12:00 PM
on their 7nm and 10nm processes at IEDM
and both processes use work function
SEARCH
metals to control threshold voltages. In this
SEMIWIKI article I will discuss this emerging process
technology.
R EC E N T I C
Introduction
K N OW L E D G E
ARTICLES Simply put, the threshold voltage (Vt) of a
MOSFET is the voltage that is required to
SPIE 2020 – Applied
Materials Material- turn the transistor on. As optimization of
Enabled Patterning power and performance have become
by Scotten Jones March
increasingly important for mobile devices,
13, 2020
the number of different threshold voltages
LithoVision – available on a process have proliferated.
Economics in the 3D
Era
Where one or two threshold voltages were
by Scotten Jones March once typical, today we are seeing four or
4, 2020 even ve threshold voltages. Multiple
threshold voltages allow designers to select
https://semiwiki.com/semiconductor-services/ic-knowledge/7259-iedm-2017-controlling-threshold-voltage-with-work-function-metals/ 1/8
IEDM 2019 – Imec the best option for each section of a design
Interviews trading-off power and performance.
by Scotten Jones January
21, 2020
Setting Threshold Voltage (Vt)
IEDM 2019 – IBM and The Vt of a MOSFET is determined by:
Leti
Interface charges – because interface
8, 2020
charges can vary over time due to traps
IEDM 2019 – Applied charging and discharging, it is generally
Materials panel EUV
Recap desirable to minimize interface charges
by Scotten Jones and they are not used to “tune” the
December 23, 2019 threshold voltage.
300mm Fab Watch Gate dielectric (oxide) thickness – Vt

2019! varies with gate oxide thickness with Vt
by Daniel Nenni August being reduced for thinner oxides, see
9, 2019
gure 1. For current foundry processes, it
Semicon West 2019 is common to have two oxide thicknesses
– Day 2
and sometimes three. A thinner oxide
by Scotten Jones July 18,
may be used in the core for low Vt – high
2019
performance transistors and a thicker
SPIE Advanced
oxide may be used in the I/O area to
Lithography
Conference – Imec support higher voltages.
design papers
by Scotten Jones June
27, 2019
TSMC and Samsung

5nm Comparison
by Scotten Jones May 3,
2019
SPIE Advanced
Lithography
Conference – Imec
and Veeco on EUV
by Scotten Jones April Figure 1. Threshold voltage versus oxide
19, 2019 thickness at a xed channel doping level.
SPIE Advanced
Lithography Channel doping – for many years the
Conference – ASML main method of producing multiple Vts
EUV Update
on the same process has been to use
23, 2019
masked implants to dope selected
channel regions. Figure 2 illustrates Vt
SPIE Advanced
versus channel doping. There are two
Lithography
Conference 2019 main issues with channel doping to set
Overall Impressions Vts. The rst is that doping the channel
reduces mobility and performance.
5, 2019
Secondly, at very small dimensions there
LithoVision 2019 – are only a few dopant atoms in the
Semiconductor
Technology Trends channels and small changes in the
number of dopants referred to as random
and their impact on dopant uctuations (RDF) can lead to

Lithography
variations in Vt.
1, 2019
2018 Semiconductor
Year in Review
4, 2019
IEDM 2018 Imec on

Interconnect Metals
Beyond Copper
by Scotten Jones
December 28, 2018
Figure 2. Threshold voltage versus channel
IEDM 2018 – ASML
doping at a xed oxide thickness.
EUV Update
by Scotten Jones
December 11, 2018 Work function – since the transition to
high-k gate oxides occurred, metal gate
SEMICON West –
Leading Edge electrodes have been used to avoid the
Lithography and EUV polysilicon depletion effect. The high-k
by Scotten Jones August metal gate (HKMG) process typically has
13, 2018
two types of gate electrode metal stacks,
FDSOI Status and one for the pFET and one for the nFET.
Roadmap
The dual work function metals (WFM) is
part of optimizing the nFET and pFET Vts.
2018
Now we are seeing more than two WFM
IITC – Imec Presents
used to “tune” Vt. With the advent of the
Copper, Cobalt and
Ruthenium foundry 7nm processes (Intel 10nm
Interconnect Results process) we are seeing multiple WFMs
used to tune Vts with no channel doping.
2018
This approach improves mobility in the
Imec technology channel and therefore performance and
forum 2018 – the
avoids RDF.
future of scaling
by Scotten Jones June
27, 2018
High-k Metal Gates
In the early days of HKMG there were two
approaches, gate- rst and replacement
metal gate (RMG). In gate rst the HKMG is
formed before the transistor implants,
anneals and raised source/drains. The
problem with this process is that the HKMG
structure must stand up to a lot of high
temperature processing and achieving
optimal Vts is very dif cult. RMG has now
become the standard HKMG process.
In an early version of RMG, an interfacial

oxide, high-k gate oxide and capping layer
are deposited and then covered with a

sacri cial polysilicon layer. The transistor
implants, anneals and raised source/drains
are performed. The sacri cial polysilicon is
then etched out and gate WFM are
deposited. This avoids the WFMs seeing a
lot of high temperatures. In the current
versions of this process an interfacial oxide
is grown, sacri cial polysilicon is deposited
and then the transistor is formed. The
sacri cial polysilicon is etched-out, the
surface is cleaned and then the interfacial
oxide, high-k oxide, capping titanium nitride
(TiN) layer and second sacri cial polysilicon
layers are deposited. An anneal of the high-
k oxide is preformed and the second
sacri cial polysilicon layers is etched away.
The WFM is now deposited. This method
avoids having the high-k oxide exposed to
all the high temperature transistor
formation process steps.
Two Work Function Metals

For many years the standard WFM process
has been to create an n and a p WFM.
The basic process is (does not include

second sacri cial polysilicon deposition,
anneal and removal), see also gure 3:
Form interfacial oxide

Deposit high-k gate oxide
Deposit TiN cap layer
Deposit tantalum nitride (TaN) etch stop
layer
Deposit TN work function layer
Mask and etch TiN off of nFET
Deposit titanium aluminum carbon (TiAlC)
work function layer
Deposit TiN barrier
Deposit tungsten (W) ll
Planarise
Figure 3. Dual work function metals.

It should be noted that although this stack
is shown at for illustrative purposes, the
lms are deposited into a trench.
Four Work Function Metals

At 10nm TSMC implemented the rst four
WFM approach I have seen. In the process
outlined below the net result is two nFET
WFM stacks and two pFET WFM stacks.
This would achieve two Vts and I believe
channel doping is used to achieve additional
Vts. Possibly there would be one nFET and
one pFET with undoped channels for
maximum performance and then perhaps
three additional Vts with doping.
The basic process is (does not include

second sacri cial polysilicon deposition,
anneal and removal), see also gure 4:
Form interfacial oxide

Deposit high-k gate oxide
Deposit TiN cap layer
Deposit tantalum nitride (TaN) etch stop
layer
Deposit TN work function layer
Mask and etch TiN off of everything but
the high Vt pFET
Deposit second TaN layer
Mask and etch TaN2 off of the low Vt
nFET and high Vt pFET
Deposit TiAlC work function layer
Mask and etch TiAlC off of the low Vt
pFET
Deposit TiN barrier
Deposit tungsten (W) ll
Planarise
Figure 4. Four work function metals.

This process ow was developed after
examining cross sections of 10nm TSMC
process provided by TechInsights.
If only two Vts are required, this 4 WFM

process will meet that requirement. If
channel doping is acceptable, then implants
may be used to provide additional Vts.
For the Intel 10nm process (similar to

foundry 7nm) Intel has a base process with
2 Vts achieved with 4 WFMs and an
optional 3 Vt process achieved with 6
WFMs. GLOBALFOUNDRIES 7nm process
has 4 Vts achieved with 8 WFMs. These
processes are not available for analysis yet
and we don’t know how these 6 and 8 WFM
stacks are achieved. In the next section I
will discuss some of the options.
Multiple Work Function Metal Options

Multiple work function can be achieved by
simply using different metals that have
different work functions, but there are a
limited number of suitable metals.
In the “Multi-Vt Engineering and Gate

Performance Control for Advanced FinFET
Architecture: module of the short course I
took, three ways of modifying work
functions were discussed:
[LIST=1]
Thickness modi cation – changing the

thickness of work function metals layers
changes the work function. This allows
changes in the Vt over a wide range but
requires multiple depositions, masks and
etches and very tight thickness control.
This technique results in stacks of different

thicknesses and may be dif cult to
implement for gate-all-around.
Material modi cation – this technique
introduces or removes species such as
oxygen to change Vt. This technique has
less range of values than thickness
modi cation and is most effective when the
layers are closer to the high-k gate oxide.
This technique does not result in different
thickness for each WFM stack. One
technique that has been investigated for
material modi cation is implanting nitrogen
into the WFM, the concern with this
technique is the implanted ions may knock
metal atoms from the WFM into the high-k
gate oxide.
Electrostatic dipole – certain elements
can introduce a dipole into the high-k gate
oxide, for example elements such a
lanthanum (La). Dipole formation with La
and aluminum (Al) was used by the
IBM/GLOBALFOUNDRIES/Samsung
alliance as part of their WFM scheme for
their gate rst process at 28nm. This
technique offers a broad range of Vts but
needs very good thickness control of the
deposited dipole materials and thermal
drive in.
Conclusion
The transition to fully undoped channels
with WFM Vt control is underway. TSMC
has implemented 4 WFM at 10nm, Intel ‘s
10nm (similar to foundry 7nm) will feature 4
and 6 WFM options and
GLOBALFOUDNRIES 7nm will have 8 WFM.
We don’t yet know how this many WFMs
will be achieved but likely it will be a
combination of the techniques outline in
the preceding section.
The change to undoped channels should

improve performance and reduce Vt
variations enabling lower voltage operation
for lower power.
F I N F E T , FO U N D R I E S , I C
K N OW L E D G E
1 0 N M , 7 N M , G LO B A L FO U N D R I E S ,
IBM, IEDM, SAMSUNG, TSMC
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3/31/2020 IEDM 2017 – Controlling Threshold Voltage with Work Function Metals – SemiWiki

SEMI Texas Spring

300mm Fab Watch Gate dielectric (oxide) thickness – Vt

TSMC and Samsung

and their impact on dopant uctuations (RDF) can lead to

IEDM 2018 Imec on

In an early version of RMG, an interfacial

are deposited and then covered with a

Two Work Function Metals

The basic process is (does not include

Form interfacial oxide

Figure 3. Dual work function metals.

Four Work Function Metals

The basic process is (does not include

Form interfacial oxide

Figure 4. Four work function metals.

If only two Vts are required, this 4 WFM

For the Intel 10nm process (similar to

Multiple Work Function Metal Options

In the “Multi-Vt Engineering and Gate

Thickness modi cation – changing the

This technique results in stacks of different

The change to undoped channels should

6 Replies to “IEDM 2017 –

You must register or log in to view/post

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