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Japanese Journal of Applied Physics 54, 124302 (2015) REGULAR PAPER
http://dx.doi.org/10.7567/JJAP.54.124302

A compact effective-current model for power performance analysis

on state-of-the-art technology development and benchmarking
Sangheon Oh1, Changhwan Shin1*, and Wookhyun Kwon2*
1
School of Electrical and Computer Engineering, University of Seoul, Seoul 130-743, Korea
2
Samsung Electronics, Hwasung, Gyeonggi 445-701, Korea
E-mail: cshin@uos.ac.kr; wh.kwon@samsung.com
Received July 27, 2015; revised August 31, 2015; accepted September 24, 2015; published online November 13, 2015

Advances in semiconductor technology have enabled significant performance improvements over the past several decades. However, at the
current pace of the development of semiconductor technology, it is increasingly important to achieve a proper balance between performance
improvement and power consumption. In this study, to quantitatively analyze the performance and power consumption of new technologies, a
compact effective-current model is proposed and used for power performance analysis (PPA). The PPA is performed by separately varying several
device characteristics such as drain-induced barrier lowering (DIBL), mobility, and threshold voltage (VT) to determine which options can provide
more benefits and better balance for new technologies. The analysis results indicate that the performance improvement due to DIBL reduction
(especially below 20 mV/V) is limited. However, VT engineering has more advantages than DIBL and mobility enhancement, unless threshold
voltage scaling induces leakage current degradation. Otherwise, mobility enhancement is the most attractive method. By using the proposed
compact effective-current model for PPA, we enabled the effective and quantitative estimation of the benefits in terms of performance and power
consumption. © 2015 The Japan Society of Applied Physics

1. Introduction
As complementary metal–oxide–semiconductor (CMOS)
technology continues to scale down below 20-nm technol-
ogy,1–4) it is very important not only to meet the performance
requirements of advanced CMOS technology but also to
achieve a reasonable balance between performance im-
provement (e.g., faster speeds) and power consumption.5–7)
Specifically, when developing CMOS technology platforms
for mobile applications, the energy constraint requires
multiple threshold voltages to control the leakage current
(specifically, the leakage current in the critical path in mobile
systems-on-a-chip).7–9) This makes it difficult to quantitatively
predict the benefits of performance enhancement and power
consumption of next-generation CMOS technology. In the
study of Bardon et al.,10) power performance analysis (PPA)
was suggested for evaluating the performance gain between
two different technology nodes. Figure 1 presents the PPA
plot, which determines the speed gain at a given power
consumption (say, metric A) and the power reduction at
the same speed (say, metric B) of a new technology relative
to a reference technology. The results for speed gain at
the same power consumption indicate that the new tech-
nology can achieve faster switching speeds while retaining the
same power consumption as that of the reference technology.
However, the power reduction at the same speed shows
that the new technology can perform the same computational
tasks as the reference technology but with less power
consumption. Metrics A and B are key metrics for circuit
designers. In addition, simple and efficient PPA methods are
necessary.
One commonly used performance indicator is the delay
metric — i.e., CV=I, where I is the on-state saturation current
(IDSAT), V is the power supply voltage (VDD), and C is the
load capacitance.11–14) A simple representative metric for
power consumption is calculated as CV 2 f, where f is the
operational frequency of the inverter chain, which can also
be calculated from the delay metric.15–18) A previous study19)
has claimed that the effective drive current (IEFF) is a better
predictor of the inverter’s delay time because the actual
124302-1
Fig. 1. (Color online) PPA plot. The speed gain at the same power
consumption (see the red solid line) and the power reduction at the same
speed (see the green solid line) for a new technology relative to a reference
technology are explicitly illustrated.
current (I) in the inverter chain does not reach IDSAT during
switching operations. In conventional CMOS digital circuit
blocks (e.g., the NAND stack in flash memory), most of
the transistors in the NAND stack are operating in linear
mode, resulting in a quantitative discrepancy between their
DC and AC performance.20) To accurately estimate the
switching current in the inverter chain (or ring oscillator),
a modified model21) has been suggested. The modified
model considers the linear-mode current of the (N − 2)th
stage’s transistors (where, N indicates the total number of
stages in the inverter chain), so that it can provide the
correlation between the AC performance and the mobility
in the linear region. However, this model still relies on
TCAD simulation results and hardware circuit character-
ization, which require large amounts computational resources
and time.
In this study, we suggest a compact effective-current model
to quantitatively (and efficiently) predict the benefits in terms
of power consumption and performance improvement result-
ing from next-generation technology platforms. This model
can provide circuit designers with quantitative correlations
© 2015 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 54, 124302 (2015) S. Oh et al.

9’
between device parameters and power performance gain.   >
>
W
1
1þ  D m
1 =%
Furthermore, by using the proposed compact effective-current 80 20 20V0
þ l COX   1 þ  VDD ; ð5Þ
L 1
1þ 20 D VDD VT0 20 >
>
model, we quantitatively evaluated the impacts of modifying
1þ ;
the performance parameter [e.g., drain-induced barrier low- ESAT L >
& 8
ering (DIBL), mobility in linear and saturation mode of >   
transistors, and threshold voltage] on the dynamic power $1 >
< W 2VT0 1 þ 12 VDD 1
B¼ 1:15s COX   1 þ  V
2>
DD
consumption and speed (or delay) of devices. >
: 2mL 1þ 12 D VDD VT0 2
1þ ESAT L
2. Effective current model 1 
W 2VT0 2 þ D
To improve the speed and accuracy of the previous PPA þ s COX   ð1 þ VDD Þ
2mL 1
þD VDD VT0
analysis (i.e., using the drain current model22)), a compact= 1 þ 2 ESAT L
analytical effective current model is proposed in this study. 9’
1   >
>
=%
The drain current model includes physical phenomena such W VT0 1
as bulk charge effects,23) DIBL,24) velocity saturation,25) sub- þ l COX  80  1 þ  V ; ð6Þ
L 1
1þ 20 D VDD VT0 20
DD
>
>
threshold conduction,26) and channel length modulation.27) 1þ ;
ESAT L >
Therefore, the power performance gain is closely associated & 8
>  
with the aforementioned physical phenomena; this associa- $1 >
< W V2T0 1
tion means that the model allows easy investigation of the C¼ 1:15s COX   1 þ  VDD
2>>
: 2mL 1þ 12 D VDD VT0 2
correlation between the power-performance improvement 1þ ESAT L
and the device physics.
Using seven different current–voltage (I–V ) targets (i.e., W V2T0
þ s COX   ð1 þ VDD Þ
IDLIN, IDSAT, IDLO, IDHI, IOFF, VTLIN, and VTSAT), the drain 2mL 1
2 þD
VDD VT0
1þ ESAT L
current model used in this study can be applied to reconfigure   1 
the I–V characteristics of a device. Note that IDLIN is IDS  2 VDD
þ 1:15ISUB 1  exp
at VGS = VDD, VDS = VDD=10; IDSAT is IDS at VGS = VDD, VTH
VDS = VDD; IDHI is IDS at VGS = VDD, VDS = VDD=2; IDLO is   
VDD
IDS at VGS = VDD=2, VDS = VDD; and IOFF is IDS at VGS = 0 V, þ ISUB 1  exp
VTH
VDS = VDD. In this study, to analyze the impact of DIBL on 9’
   >
>
the power performance gain, the extraction procedure for VT 1  VDD =% 1
20
was modified: VT depends on VDS because of DIBL, and ION þ ISUB 1  exp ; ð7Þ
4 VTH >
>
is fixed, as in the previous study.28) In the drain current model ;
>
used in this study, VT is expressed as follows:
where μl and μs are the mobility in the linear and saturation
VT ¼ VT0  DVDS ; ð1Þ
regions, respectively; COX is the gate oxide capacitance
where, D is the DIBL factor and VT0 is VT at VDS = 0 V. The per unit area; W is the channel width; L is the channel length;
original drain current model22) defines VT0 as follows: m is the bulk charge factor; VT0 is the threshold voltage at
VDS = 0 V; ESAT is the saturation field, which is the velocity
VT0 ¼ VTLN þ 0:1DVDD : ð2Þ
saturation factor; D is the DIBL factor; ISUB is the constant
In this study, however, the definition (or extraction point) current definition for VT; and VTH is the thermal voltage
of VT0 is modified as follows: (which is 0.026 V at room temperature). To validate the
newly derived compact=analytical effective current model,
VT0 ¼ VTSAT þ DVDD : ð3Þ þ
IEFF calculated from the analytical model is compared to
þ
With the modified compact drain current model, an IEFF extracted using the Sentaurus TCAD simulation (see
analytical model for effective current21) is derived as Fig. 2). As shown in Fig. 2, the error between the TCAD
follows: simulation and the analytical model is within 18% for all VDD
þ 1:15IH þ IL þ GDS,LIN V80
DD bias conditions. The device sample used for the validation
IEFF ¼ is a 22-nm high-k=metal-gate (HK=MG) FinFET with a
2
punch-through stopper (PTS)29) (note that the peak doping
¼ AV2DD  BVDD þ C; ð4Þ concentration is 2 × 1019 cm−3 and the doping gradient is
where, IH is IDS at VGS = VDD and VDS = VDD=2, IL is IDS at 4 nm=decade). In Table I, more detailed device design
VGS = VDD=2 and VDS = VDD, and GDS,LIN = IDS,SUBLIN (i.e., parameters are presented.
IDS at VGS = VDD, VDS = VDD=20)=VDS, and the coefficients in
þ
the IEFF equations are as follows: 3. Results and discussion
& 8 To reveal the key features of the proposed effective current
>  2  
$1> < W 1 þ 12 VDD 1 model, we used a benchmarking method for the PPA. All
A¼ 1:15s COX   1 þ  VDD
2>
>
: 2mL 1þ 12 D VDD VT0 2 quantitative values of the power consumption and perform-
1þ ESAT L ance are normalized to the current technology platform as a
1 2 reference to quantitatively measure the benefits of developing
W þD
þ s COX 2  ð1 þ VDD Þ or adopting a new technology platform.
2mL 1
2 þD VDD VT0 To analyze the impact of modifying device parameters
1þ ESAT L on dynamic power consumption and speed of devices, a
124302-2 © 2015 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 54, 124302 (2015)
þ
Fig. 2. (Color online) IEFF calculated using the analytical model (solid
þ
line) shows good agreement with IEFF extracted from TCAD simulation
results (circle symbol).
Table I. Device design parameters.
Gate length LG (nm) 20
Fin width Dfin (nm) 10
Fin height Hfin (nm) 24
Source=drain doping concentration NSD (cm−3) 1.0 × 1020
Channel doping concentration Nch (cm−3) 1.0 × 1015
Source=drain junction depth Xj (nm) 24
Gate oxide thickness (HfO2) Tox (nm) 3
reference device is generated using TCAD simulation with
the device design parameters in Table I. The parameters
shown in Eqs. (5)–(7) (such as λ, μs, μl, ESAT, D, ISUB, and
VT0) are extracted from the TCAD simulation results of a
þ mobility is enhanced by 0–30%.
reference device. Afterward, IEFF is calculated from the
extracted parameters with Eqs. (4)–(7). The dynamic power
consumption and speed of the device are then evaluated using
2
the dynamic power consumption (i.e., CVDD f ) metric and the
þ
delay metric (i.e., CV=IEFF ), which are already mentioned in
þ
Sect. 1. Finally, the device parameters are modified, and IEFF ,
dynamic power consumption, and device speed are evaluated
from the modified parameters. The results from the reference
device and modified device are then compared to analyze the
impacts of device parameter modification on performance
and dynamic power consumption.
3.1 Mobility
New or upgraded mobility enhancement techniques for
transistors will play a key role in satisfying the minimum
performance targets of next-generation technology plat-
forms.30) Figure 3(a) shows the normalized performance
versus dynamic power consumption when mobility (herein,
mobility refers to mobility in both the linear mode and the
saturation mode of transistors) is improved by 0–30%. The
data for the speed gain at the same power and power reduc-
tion at the same speed extracted from Fig. 3(a) are shown in
Fig. 3(b). As mobility is improved, the curve in the PPA plot
tends to shift toward the right-hand side [see Fig. 3(a)]. With
the improved mobility, the effective current (IEFF) is increas-
ed, resulting in not only faster speed but also larger power
consumption in the circuits at the same power supply voltage
(VDD). Thus, to achieve power consumption in a new
technology comparable to that of the reference technology,
124302-3
S. Oh et al.
(a)
(b)
Fig. 3. (Color online) (a) Impact of mobility improvement in PPA plot
(here, a 0–30% improvement in mobility is assumed). (b) Speed gain at the
same power consumption and power savings at the same speed when the
VDD must be reduced. This indicates that the speed gain (as a
percentage) at the same power consumption is smaller than
the mobility enhancement (as a percentage) [see Fig. 3(b)].
However, improving the mobility is more beneficial to reduce
power consumption at the same speed because lower VDD is
required to maintain the circuit speed.
3.2 Drain-induced barrier lowering
DIBL affects circuit performance because VT and the
corresponding drain current are changed by DIBL or short
channel effects.24) The previous study19) shows that the
effective current increases with decreasing DIBL. Even if a
transistor has the same IDSAT, the smaller the DIBL, the
higher the peak current of an inverter when the state of the
inverter changes.
To investigate the effects of DIBL on speed gain and
power consumption, the normalized performance versus
dynamic power consumption is evaluated as DIBL is varied.
Then, for a given DIBL reduction (i.e., decrease of the DIBL
value) rate, the speed gain at the same power and the power
reduction at the same speed are evaluated. However, the
improvement of DIBL below the original value of the
reference device (i.e., 21.1 mV=V) used in this study was
insufficient to demonstrate the impacts of DIBL on speed
gain and power consumption. Therefore, to clearly illustrate
the effects of DIBL reduction on speed gain and power
consumption, the DIBL of the reference device is increased
© 2015 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 54, 124302 (2015) S. Oh et al.

(a)
Fig. 5. (Color online) Because of the physical limit of SS (i.e., SS > 60
mV=decade at 300 K), VT scaling causes a large increase in off-state leakage
current. For example, as VT decreases by 0.2 V, the off-state leakage current
increases by a factor of 2,154.

(b)

Fig. 4. (Color online) (a) Impact of DIBL on PPA plot (herein, a 0–80%
improvement in DIBL is assumed). (b) The speed gain at the same power and
the power reduction at the same speed are shown when DIBL is varied from
0–80%. Note that to clearly illustrate the speed and power gain induced by
DIBL reduction, the DIBL of the reference device is increased from its (a)
original DIBL value (21.1 mV=V) to 100 mV=V.

from its original value of 21.1 to 100 mV=V. The PPA plot
and the speed gain and power reduction plot of the modified
device are shown in Fig. 4.
As shown in Fig. 4(b), the speed and power consumption
are improved as DIBL is enhanced. However, compared to
the ratio of performance gain to threshold voltage, the ratio of
performance gain to DIBL reduction is quite low. Further-
more, sub-20 mV=V DIBL in recent FinFET technology is
technically difficult to achieve; therefore, further improve-
ment of DIBL in current state-of-the-art CMOS technology is
not an attractive option for improving performance. (b)

3.3 Threshold voltage
The adoption of a low threshold voltage (LVT) is one con-
ventional solution for boosting the drive current of the
transistor for a given power supply voltage.31) However,
because the subthreshold swing (SS) is physically limited to
60 mV=decade at 300 K in recent FinFET technology,32)
VT scaling should result in an exponential increase in off-
state leakage current, which, in turn, results in significantly
increased static power consumption (see Fig. 5).33) In this
section, we focused on dynamic power consumption. The
degradation of static power consumption owing to VT scaling
is discussed in Sect. 3.4.
124302-4
Fig. 6. (Color online) (a) Impact of low VT on PPA plot (herein, 0–80%
reduction in VT is assumed), (b) the speed gain at the same power consump-
tion; the power reduction at the same speed when VT is reduced by 0–40%.
To analyze the impacts of low VT on the PPA plot, we
evaluated the normalized dynamic power and speed of the
reference device when VT is varied from 0 to 80% [see
Fig. 6(a)]. The speed gain at the same power and the power
reduction at the same speed are extracted [see Fig. 6(b)]. It is
noteworthy that both the power reduction at the same speed
and the speed gain at the same power are further improved
with VT reduction relative to other options such as DIBL
© 2015 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 54, 124302 (2015)
Table II. Example of altered device parameters to achieve 20% speed gain at the same power.
Speed gain at same power
VT reduction (Ref. = 0.272 V)
Off-state leakage current increase (Ref. = 1.58 × 10−10 A=µm)
Mobility enhancement (Ref. = 0.012 a.u.)
DIBL reduction (Ref. = 21.1 mV=V)
improvement and mobility enhancement. This indicates that
VT scaling is the most efficient method for improving the
device performance if the leakage current remains constant.
3.4 Discussion
In the previous sections, the impacts of mobility=DIBL=VT
engineering on dynamic power consumption and speed of
devices are separately analyzed. Moreover, speed gain at the
same power and power reduction at the same speed are quan-
titatively estimated using the simulated PPA plot to inves-
tigate (in detail) the impacts of modifying device parameters
on device performance. As mentioned in Sect. 3.3, the full
static power consumption is not considered in the previous
analysis (i.e., Sects. 3.1 to 3.3). Herein, as shown in Table II,
the impacts of modifying device parameters on off-state
leakage current (which is closely associated with static
power consumption) are investigated. Specifically, the device
parameter modification (as a percentage) required to achieve
a 20% speed gain at the same power is investigated.
Results clearly show that the off-state leakage current
exponentially increases as VT is linearly scaled. As shown
in case 1 (see Table II), with 10% VT scaling, the off-state
leakage current is 2.71 times larger, and a 20% speed gain can
be achieved with a 31% mobility enhancement and a 28.5%
DIBL reduction. However, in case 3, with 30% VT scaling,
the off-state leakage current is 20.49 times larger, and a 20%
speed gain can be achieved with only a 15% DIBL reduction
(and without any mobility improvement). This indicates that
(1) off-state leakage current can be significantly increased
because of the threshold voltage scaling without SS improve-
ment, and (2) it is important to set up the target device
parameters to achieve the power-performance target of next-
generation technology without causing a significantly higher
off-state leakage current. In case 2, a 20% speed gain at the
same power is achieved using only 54.8% mobility enhance-
ment. Additionally, a 20% speed gain at the same power
cannot be achieved using only DIBL reduction. This indi-
cates that (1) mobility enhancement enables performance
improvement without significantly degrading the off-state
leakage current and (2) DIBL reduction below 20 mV=V
cannot yield a significant performance improvement.
4. Conclusions
A compact effective-current model is proposed to perform
PPA. Using the newly proposed model, the dynamic power
consumption and speed of devices can be accurately and
efficiently evaluated. From the simulation results, we found
that (1) alleviating DIBL on its own is not an efficient method
124302-5
S. Oh et al.
Case 1 Case 2 Case 3
20% 20% 20%
10% 0% 30%
(−0.027 V) (−0 V) (−0.082 V)
×2.71 ×1 ×20.49
31% 54.8% 0%
(+0.0037 a.u.) (+0.0066 a.u.) (+0 a.u.)
28.5% 0% 15%
(−6.01 mV=V) (−0 mV=V) (−3.17 mV=V)
for developing future technology; (2) as long as the off-state
leakage current is not significantly degraded, VT engineering
is the most efficient way to improve performance; and (3)
otherwise, mobility enhancement is more suitable.
Furthermore, we also verified that with the proposed
compact effective-current model and PPA, the benefits of the
device modification options for next-generation technology
platforms (versus a reference technology platform) can be
quantitatively and effectively predicted in terms of power
consumption and performance.
Acknowledgment
This work was supported by the National Research
Foundation of Korea (NRF) grant funded by the Korea
government (MSIP) (No. 2014R1A2A1A11050637).
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