Epic AZ

Imaging
Electronics Theory

9202-0182 Rev A

Table of Contents

Sec 1: Introduction.........................1-1
Sec 2: AAE Card............................2-1
Sec 3: Epic AZ Motherboard..........3-1
Sec 4:TIC.......................................4-1
Sec 5: Signal Flow .........................5-1

Phillips Medical Systems

540 Alder Drive
Milpitas, CA 95035
PROPRIETARY NOTICE:
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Medical Systems ("Philips") and may not be reproduced, copied in whole or in part, adapted, modified,
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Philips’ first written request.

COPYRIGHT NOTICE:
© August 15, 2004, Koninklijke Philips Electronics N.V. All Rights Reserved.

WARRANTY DISCLAIMER:
Philips provides this document without warranty of any kind, either implied or expressed, including, but
not limited to, the implied warranties of merchantability and fitness for a particular purpose.

LIMITATION OF LIABILITY:
Philips has taken care to ensure the accuracy of this document. However, Philips assumes no liability for
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or program(s) described in this document at any time.

ABOUT THIS MANUAL

This Field Service Manual contains functional descriptions of the Epic AZ Imaging
Electronics.

2 9202-0182 Revision A
 SECTION 1
INTRODUCTION
SCOPE
This section describes the overall structure of the Epic AZ Imaging Electronics at a
block diagram level. Subsequent sections of this manual describe each board at a more
detailed level.
In this section, the term Epic AZ Imaging Electronics includes:
• the printed circuit boards in the detector head, and
• printed circuit boards in the camera gantry (Forte) or PC tower (Skylight) that
involve image collection.

OVERALL SYSTEM BLOCK DIAGRAM

Figure 1-1 on page 2 shows the overall relationships between the various components
of the Epic AZ Imaging Electronics.
Figure 1-2 on page 3 shows a more detailed view of the relationships between the
various components of the Epic AZ Imaging Electronics.
Detector Components:
• Crystal
• Photo Multiplier Tubes (PMTs)
• Epic AZ Mother Board
• Analog Acquisition Electronics (AAE) board
• Single Board Computer (SBC)
Gantry Electronic Components:
• Tag Injection Circuit (TIC) board
• Image Creation Processor

PHYSICAL LOCATION
The components listed above as Detector components physically reside in the Detector
Head. The components listed above as Gantry Electronic components physically reside
in the Power Pack enclosure on the Forte system and in the PC Tower on the Skylight
system.

9202-0182 Revision A 1-1

1-2
EKG
Section 1

Acquisition Server
(image binner)
192.168.1.11
X,Y,Z (corrected image data) "Hotlink" Camera

Parallel Cable (carrying gantry motion data)

TIC
Detector #1 Det #1Twisted Pair
Electronics
(192.168.1.13) Det #2Twisted Pair
4 3 Touch Serial Port
DSL CABLE Twisted Pair Screen
Detector #2 5 ROUTER 1

Twisted Pair
Electronics Twisted Pair
Display VGA Raptor
(192.168.1.14) 2 WAN Panel GFX TTYB
Twisted Pair

Motion Control
Acquisition PC PCI-BUS
Subsystem (graphical user interface)
(192.168.1.12)

Gantry PC 10 Base T Ethernet E-net

Gantry PC, Twisted Pair

Board & Transcvr CPU TTYA
(gantry motion) 10/100
(192.168.1.15)
Hard Disk COM2
Floppy Parallel Port
PC BUS PC BUS Floppy SCSI-2

Fig 1.1 Epic AZ Imaging Electronics

SCSI-1

CANbus Serial E-net

Mtr Cntrl Port 10/100 VGA Floppy CPU CDROM CDRW Hard
Drive Disk

Local
Image/Text Ethernet Bus
Mouse Keyboard Ethernet
Monitor

Handcontroller Acquisition Terminal Imaging Work Station

9202-0182 Revision A
INTRODUCTION
 INTRODUCTION

Control ribbon
Dynodes ribbon High

9202-0182 Revision A
Voltage

Epic AZ
Motherboard
PMT1 coaxial AAE
1 Cards
X,Y,Z (Corrected image data) Hotlink
1-8
.
. AAE Card 17
.

AAE Network Cable Imaging

55 100bT 100bT
Cards SBC Work Station
PMT55 coaxial PCI Bus
9-14
Crystal

HotLink TIC Trigger

EKG
PCI Card
Floppy Parallel
PCI
Floppy I/F

Acquisition Video
Server Gantry Status
DSL 100bT
Hand RS-232 Gantry PC (Image Binner) Monitor and
Gantry and Table Control Cable camera Touch Screen
(Cameragantry)
Router
100bT RS-232 RS-232
100bT

Control (Forte+ only) Multi-IF

(Forte + only)
CD-RW
Can Bus e-net SCSI
Canbus ISA
Floppy
Acquisition PC Floppy I/F
Operator's
(Graphic User
Acquisition
Crystal Interface) Vid, P/S 2(x2)
PMT55 coaxial AAE Terminal
(Cameraclient)
55 Cards Epic AZ
1-8 Motherboard
.
. AAE Card 17
. 100bT

Figure 1-2 Epic AZ Imaging Electronics Block Diagram

AAE
1 Cards CD-R
PMT1 coaxial
9-14 IDE

Floppy
Floppy I/F
High
Dynodes ribbon Voltage SBC
Control ribbon
PCI Bus

1-3
Section 1
Section 1 INTRODUCTION

ETHERNET INTERFACES
As shown in Figure 1-3, the Detector Electronics for Detectors 1 and 2, the Gantry PC
(for gantry control) the Acquisition PC (for data acquisition control), and the
Acquisition Server (for image binning) are internal to the Epic AZ. The imaging work
station (for image processing and review) and the DSL Cable Server are nodes on the
Local Ethernet.

Client

100bT
Detector
(cameradet1)
192.168.1.13 Local Ethernet

Client
10M 10M

Gantry PC
(cameragantry)
100bT
192.168.1.15
Imaging
DSL Work Station
Cable
Router
Client
Server
Acquisition PC 100bT
(Graphic User Acquisition
100bT
Interface) Server
(cameraclient) (Image Binner)
192.168.1.12 Camera
192.168.1.11

Client
T

Detector
(cameradet2)
100bT
192.168.1.14 Host Names Shown in Italics

Figure 1-3. Ethernet Interfaces.

Using the above IP addresses, Field Service Engineers can "Telnet" through the DSL
Cable Router into the client and server machines.
In a common diagnostic procedure, FSEs will "Telnet" from the Acquisition Terminal
which interfaces to the Epic AZ through the DSL Cable Router into the Gantry PC
(192.168.1.15). Once logged into the Gantry PC, FSEs can run the motion control
diagnostic (motdiag) residing on the Gantry PC.
Epic AZ software files physically reside on the Acquisition PC’s hard disk and the
Acquisition Server.

1-4 9202-0182 Revision A

INTRODUCTION Section 1

DETECTOR ELECTRONICS
Figure 1-4 shows the major components of the Detector Electronics. These include:
• the NaI crystal and assembly of 55 Photomultiplier Tubes (PMTs),
• the High Voltage Distribution system,
• Analog Acquisition Electronics (AAE),
• Epic AZ Detector Mother Board,
• the off-the-shelf, Single Board Computer and
• the Tag Injection Circuit (TIC) board

NaI Crystal and PMTs.

The Detector is a positive high voltage system. Positive high voltage allows each PM
Tube cathode to stay at ground potential. This requires the Pre-amplifiers to be AC
coupled to the PM Tubes.
The honey-comb mu-metal shield around the PM Tubes and the aluminum face plate of
the crystal are tied to ground through a 1 megohm resistor.
The Epic AZ Detector contains 55 PM Tubes (forty-nine 76 mm and six 50 mm PM
Tubes).

High Voltage Distribution System.

The high voltage distribution system consists of ribbon cables to the PM Tubes, a High
Voltage Distribution board, a High Voltage Power Supply and control mechanisms
through the Epic AZ Motherboard.
The High Voltage Distribution board supplies and distributes high voltage to the
dynodes of all 55 PM Tubes.
The High Voltage Power Supply generates + 1500 volts (max) at 2 ma and is set to a
nominal value of 1000 volts.

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Section 1 INTRODUCTION

Corrections/Calibrations
Epic AZ applies gain, energy, linearity, uniformity correction and energy
discrimination to each event in the detector before sending the event to the Acquisition
Server (Image Binner) via the Hotlink interface.
During spectrum calibration autogain runs at each calibration point.
To stabilize performance, high voltage usually does not change. However if the
maximum energy window is above approximately 340 KeV or below approximately 90
KeV, the system may use other high voltage values. The idea is to use the gain DAC’s
for as wide a range as possible, and only change the high voltage if it is really required.

1-6 9202-0182 Revision A

INTRODUCTION Section 1

CRYSTAL #1

PMT PMT
#1 55

REMOTE Epic AZ
HV Motherboard
HIGH VOLTAGE HV CONTROL
DISTRIBUTION POWER
PCB SUPPLY Syschip

PEPC
55

SIGNALS 55 SIGNALS
0- 27 28 - 54

AAE AAE
Cards Cards

DIGITAL CONTROL BUS

PMT BUS 14
40

SINGLE
FROM HEAD #2 X, Y, Z CORRECTED X, Y, Z CORRECTED BOARD
HIGH SPEED SERIAL HIGH SPEED SERIAL COMPUTER
EVENTS DATA (HEAD #2) EVENTS DATA (HEAD #1)

DETECTOR HEAD TOWER

TAG
INJECTION
CIRCUIT

Local
DATA TO PERSONAL COMPUTER Ethernet

Figure 1-4 Detector Electronics Block Diagram

9202-0182 Revision A 1-7

Section 1 INTRODUCTION

Single Board Computer.

A Power PC, PCI bus Single Board Computer (Figure 1-4) resides in the Detector Card
Cage. The Single Board Computer (SBC) provides an interface to the detector system
and handles detector-specific functions such as table downloads, diagnostics,
calibrations and Auto Gain adjustments.

OVERALL FUNCTIONAL DESCRIPTION

Figure 1-5 illustrates:
• the functional relationship between the Analog Acquisition Electronics (AAE)
cards and the Position and Energy Processor Chip (PEPC) on the Motherboard.
• the digital feedback loop between the Position and Energy Processor Chip and
the AAE cards which provides baseline stability and Auto Gain adjustment.
• the primary functions of the Position and Energy Processor Chip and the
Position and Energy Correction Module (PECM) of the PEPC:
• Photo Multiplier Tube data transfer, integration sequencing and
spatial position calculation,
• the PECM performs energy, linearity and uniformity corrections on
signals from associated detectors and energy window discrimination.

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 INTRODUCTION Section 1

CRYSTAL
4 4 4 3 4 4 4 4 4 4 4 4 4 4 Photomultiplier Tubes

1 2 3 4 5 6 7 8 9 10 11 12 13 14 Analog Acquisition Electronics Cards

SETUP & DIAGNOSTICS

CONTROL
AND
DIAGNOSTICS REALTIME SAMPLING
CONTROL
DIGITAL FEEDBACK:
ENERGY OPTIMIZED
Baseline
PM TUBE RESPONSE
Stabilization PEPC
(Position
Individual SPATIALLY WEIGHTED and Energy
Auto Gain POSITION CALCULATION Processor
Adjustment Chip)
12 12 12

X Y Z SINGLE
BOARD
COMPUTER
ENERGY CORRECTION AND NORMALIZATION
(256 x 256 x 16)
PECM
(Position
LINEARITY CORRECTION and Energy
512 X 512 X 16 Correction
Module)
UNIFORMITY CORRECTION of the
256 X 256 X 16 PEPC

TAG
ENERGY WINDOW DISCRIMINATION
INJECTION
16384 X 16
CIRCUIT

Epic AZ Motherboard

Figure 1-5 Functional Block Diagram

9202-0182 Revision A 1-9

Section 1 INTRODUCTION

TROUBLESHOOTING
To troubleshoot the imaging system use the instructions in Jetstream Epic-AZ Imaging
Diagnostics manual (9202-0200).

1 - 10 9202-0182 Revision A
 SECTION 2
EPIC AZ MOTHER BOARD
SCOPE
This section describes the Epic AZ Mother Board (2159-5002) at the block diagram
level.

BRIEF DESCRIPTION
The Epic AZ Mother Board:
• is located in the detector head electronics card cage.
• processes signals from the AAE boards,
• sends data to the TIC board
Epic AZ Motherboard

FUNCTIONAL DESCRIPTION
The Epic AZ detector mother board consists of four main functional areas: PMT signal
processing card backplane, event readout and system control, event packet processing,
and PCI bus support.
• Controls high voltage.
• PMT signal processing cards (AAE3) convert analog PMT signals to digitally
integrated values. See Section 2 on AAE cards.
• Event readout system controls triggering, readout, and event packet formatting.
• System control provides a way to program gain and offset DAC's and FPGA
registers that control triggering and integration modes.
• Event packet processing determines the events' position and energy.

9202-0182 Revision A 2-1

Section 2 Epic AZ Mother board

• PCI bus is used to transfer data between each of these functional areas and a
PowerPC based Processor Card in a standardized and modular way.

HARDWARE ARCHITECTURE
The main detector level system components are shown in Figure 3-1. The Epic AZ
detector electronics includes three main subsystems: the detector motherboard, high
voltage assembly, and power distribution assembly.

24 VDC

Dynodes
High Voltage
ribbon cable

To TIC Board
high voltage control Hotlink
PEPC
50 ohm mini-coax

AAE3
x4 event data
PMT1 AAE3
coaxial x4
Event readout
1 Card17
c + system PCI Bus
r control
. AAE3
y . x4
s .
t AAE3
PMT55
a
PrPM600

PMC slot

coaxial x2
l 55

Epic AZ Detector
Camera bucket Motherboard
Power Distribution 100bT
CAT5 twisted pair
RS-232
Twisted Pair
To DSC Cable
Router

DC/DC Power Supply

3.3 V digital Epic AZ Detector
5.0 V digital
48 VDC 5.0 V analog Electronics
-5.0 V analog

Figure 3-1 Main System Components of the Epic AZ Detector Electronics

2-2 9202-0182 Revision A

 SECTION 3
ANALOG ACQUISITION ELECTRONICS (AAE)
SCOPE
This section describes the Analog Acquisition Electronics (AAE) card (2159-5003) at
the block diagram level.

BRIEF DESCRIPTION
Analog Acquisition Electronics (AAE) Cards:
• 14 AAE cards are located in each detector head, mounted on the Epic AZ
Motherboard.
.
AAE Cards
14 Plcs

• Each card receives the signal from four PMTs except card 4 which receives a
signal from only 3 PMTs.
• The cards digitize each signal and send the digitally integrated results to the
Epic AZ Motherboard for further processing.

9202-0182 Revision A 3-1

Section 3 Analog Acquisition Electronics (AAE)

FUNCTIONAL DESCRIPTION
The AAE3 card:
•Receives the small electrical current from the PMTs and amplifies these signals
to usable levels
• Shapes the signals
• Normalizes and filters the signal
• Digitizes each signal
• Integrates the signal
• Sends the data to the Epic AZ Motherboard for position and energy processing
The input signal can be switched from the actual PMT signal to a test signal used with
diagnostics software.

Analog Signal
PMT #4
Processing – High Speed
Input + A/D

Analog Signal
PMT #3
Processing – High Speed
Input + A/D
FPGA
Reconfigurable
Analog Signal Digital Logic
PMT #2
Processing – High Speed
Input + A/D

PMT #1 Analog Signal

Processing – High Speed
Input + A/D

DC Clock
Controls/Data
Configuration

References PLL
Analog Test

Serial DAC
Controls
Signal

Controls
Event
Status
Event

Event
Data

System
Clock

AAE Card Block Diagram

3-2 9202-0182 Revision A

Analog Acquisition Electronics (AAE) Section 3

SYSTEM PERFORMANCE
Each AAE3 Card consists of four analog signal processing and 60 MHz 10-bit A/D
converter channels. The gain control for each channel exceeds 30 dB and each channel
can be individually changed using a 13-bit DAC setting for high precision control. The
AAE3 inputs are AC-coupled to the PMT signal, and a high-performance analog
baseline restorer circuit maintains the baseline, eliminating the need to remove the long
time-constant light output of the crystal at very high rates.
The analog signal shape of the signal can be selected through software to support both
normal (tail of about 800 ns) and high-count rate (tail of about 300 ns) modes of
operation. A single 100K gate SpartanII FPGA processes four continuously sampled
streams of digitized outputs that are used for triggering, integration, and signal
management.

9202-0182 Revision A 3-3

Section 3 Analog Acquisition Electronics (AAE)

3-4 9202-0182 Revision A

 SECTION 4
TAG INJECTION CIRCUIT (TIC)
SCOPE
This section describes the Tag Injection Circuit board (TIC) (2159-5400) at the block
diagram level.

PHYSICAL LOCATION
The Tag Injection Circuit (TIC) board is located in:
• Skylight, mounted on the Axi CPU motherboard in the top section of
the PC Tower.
PC Tower Top Section Front View

TIC board

• Forte, mounted on the Axi CPU motherboard in the Power Pack

enclosure.

BRIEF DESCRIPTION
The Tag Injection Circuit (TIC) board:
• is a standard PCI card that interfaces via custom designed interfaces to the
camera system.
• synchronizes and tags the incoming data from the detectors, gantry and control
server. It organizes and combines the data into a single data stream for gamma
camera imaging and transfers the data to the Acquisition Server’s (Image
Binner) memory space.

9202-0182 Revision A 4-1

Section 4 Tag Injection Circuit (TIC)

FUNCTIONAL DESCRIPTION
The Tag Injection Board (TIC) (Figure 4-1):
• Receives data from several external devices:
Detectors (for image data),
Gantry devices and
Cardiac gate.
• Includes:
a time mark generator,
a sync tag generator, and
a Control Server (for study start/stop/pause/resume).
• Organizes and combines all data and control tags into a single data stream.
• Transfers this data stream to the Acquisition Server’s (Image Binner) memory
space via a DMA operation.

4-2 9202-0182 Revision A

 FIFO
D a t a w i d t h 64 bits (8x8)
M o tio n
FIFO Tags
P a ra lle l D a ta

9202-0182 Revision A
DET1
S e ria l I/F MUX FIFO

FIFO D e te c to r
P a ra lle l D a ta D a ta
Tag Injection Circuit (TIC)

DET2
S e ria l I/F
FIFO

Gantry D a ta p a th IN
M o tio n and O U T of
Interface GPC Tags M U X is 16 bits
Parallel O ff C h ip 3 2 -b it p a th
Port FIFO B u rs t F IF O
Interface P C I B us
1 6 -b it p a th 3 2 b its

E x te rn a l CSTP Acquisition
T rig g e rs PCI Server
Event
FIFO FIFO FIFO I/F
Detect
(Image
Binner)
Local Data Bus
FIFO

Figure 4-1 TIC Board Block Diagram

TMG
B u rs t F IF O Direct
Cardiac C o n tro l
Memory
Gate Access
Controller
D a ta
F IF O E m p ty F la g s A s s e m b ly
S equencer
TIC Board

4-3
Section 4
Section 4 Tag Injection Circuit (TIC)

4-4 9202-0182 Revision A

 SECTION 5
SIGNAL FLOW
SCOPE
This section describes the flow of data and major signals between the previously
described Epic AZ Detector boards.

EVENT DATA PATH

The event data path is as follows:
1. A patient is administered a radioactive substance and positioned in front of a
detector. During the decay of the radioactive material gamma rays are emitted. Of
those events a certain percentage of those will be parallel to the holes in the
collimator and interact with the Sodium Iodine Crystal.
2. The AC-coupled Photo Multiplier Tube (PMT) signals are amplified, offset
adjusted, converted to a digital value and integrated on the Analog Acquisition
Electronics (AAE) cards.
3. All PMT signals are fed into the Position and Energy Processor chip (PEPC)
where the event positioning and energy accumulation occurs. The signal is
corrected for energy, linearity and uniformity distortions and energy window
discriminated.
4. The event location and energy value is packaged into a 64-bit event structure and
sent over to the TIC board that resides in the Ultra AXi via the serial Hotlink
interface.
5. The TIC board receives the following input signals:
• event data from both detectors via separate Hotlink interfaces,
• gantry device information via the parallel cable between the gantry PC and the
TIC board,
• External trigger signals, such as EKG gate signal, and
• Control server generated event tags, such as start, stop, pause and resume tags.
Besides these input signals, the board itself can inject data time mark and sync
tags into the data stream.
6. Data and event tags are binned into image frames by the binner.
7. The binner will save the acquired data in XML format locally on the Ultra AXi’s
hard disk under atlas/data/Patients/<name of the patient>.

9202-0182 Revision A 5-1

Section 5 SIGNAL FLOW

8. The program xml2pega will translate the XML file to Pegasys.img format and
send it over to the database host. Alternatively the program xml2dcm will
translate the date to DICOM format and send it over to the Odyssey or Jetstream
workspace. A storage confirmation scheme ensures that the data sent actually
ends up in the database on the database host.

SIGNAL FLOWS
Figure 5-1 shows the major signal flows between major Epic AZ subsystems.

SIGNAL FLOW DESCRIPTION

The major run-time signals shown in Figure 5-1 are as follows:
• The Syschip produces and sends the control signal to the High Voltage Power
Supply.
• The output of the High Voltage Power Supply is distributed to the Photo
Multiplier Tubes (PMT) from the High Voltage Distribution board.
• The raw PMT analog output signals go to the AAE cards, where upon receipt
of a signal from the Syschip they are amplified, converted to digital data and
passed to the Motherboard.
• DSPA and DSPB perform position and energy calculations on the data.
• The Single Board Computer reads the integrated baseline data from the PEPC,
runs a program called Baseline and sends baseline offset adjustment signals
back to the PEPC.
• During Autogain, the software reads position and energy signals from the
PEPC, calculates gain correction values based upon the energy peak signal and
sets the PMT gain DAC’s on the AAE cards as needed.
• The Motherboard’s PEPC performs linearity, uniformity, energy corrections
and energy discrimination on the position and energy data. It then sends the
corrected data to the Tag Injection Circuit (TIC).
• The Tag Injection Circuit (TIC) organizes and combines all data and control
tags into a single data stream and then transfers this data stream to the
Acquisition Server’s memory space via DMA operations.

5-2 9202-0182 Revision A

SIGNAL FLOW Section 5

CRYSTAL #1
PMT
OUTPUTS PMTs DETECTOR HEAD TOWER
#1 - 55

HIGH
VOLTAGE
HIGH VOLTAGE CONTROL
HV
DISTRIBUTION POWER
PCB SUPPLY

Epic AZ Motherboard Gain & Offset

Control
Syschip

Uncorrected
X,Y, Z Events Control & Data

Analog
Acquisition DSPB DSPA Position and
Electronics Energy Processor
Chip
Cards Raw Integrated (PEPC)
(AAE) PMT Data

RAW INTEGRATED
PMT DATA

SINGLE
CORRECTED BOARD
X, Y, Z COMPUTER
FROM HEAD #2

High Speed High Speed

Serial Serial
Events Data Events Data
DETECTOR HEAD (Head #2) (Head #1)

TOWER

Local Ethernet
TAG INJECTION CIRCUIT
(TIC)

Acquisition
Server
SINGLE STREAM DATA Memory
Space

Figure 5-1 Epic AZ Run-time Signal Flow Diagram

9202-0182 Revision A 5-3

Section 5 SIGNAL FLOW

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