10 nm vs 10 nm technology node comparison

Chao-Wei Chen, Yu-Han Chen, Cheng-Hsing Chen,

Cheng-Huang Yang, Bang-Hao Huang, and Shih-Hsin Chang∗
MSSCORPS CO., LTD. Hsinchu, Taiwan
(Dated: February 26, 2018)

∗
Corresponding author: Shih-Hsin.Chang@msscorps.com
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I. INTRODUCTION

The popularity of smartphone has drastically changed our daily lifestyle. Thanks to the progress
of advanced fabrication technology, the performance of smartphone is enhanced by every year.
There are more and more jobs carried out by PC before can now be easily done with smartphones.
Among numerous components in a smart phone, there is no doubt that the central processing
unit (CPU) plays a decisive role on its performance. For fabricating faster and more powerful
chips, dimension scaling is a dominant way and the trend, the so-called Moores law, was already
predicted by intel co-founder Gordon Moore in 1975 [1]. Surprisingly, the fabrication technology
still follows the law and new generation of technology node will be continuously delivered [2].
In order to attract more orders from smartphone companies, keen technology node competition
among main chip manufacturers in the world is in full swing and will not stop in the next coming
years.

The top two market share smartphone companies in 2017Q3 are Samsung (22.3 %) and Apple
(12.5 %) [3]. The latest Samsung smartphone is Galaxy S8 with its 10 nm own-designed/fabricated
CPU, Exynos8895. Exynos was given from two Greek words Exypnos and Prasinos. It was
claimed that the performance and energy consumption of S8 is 27 % better and 40 % less than those
of previous generation, i.e. 14 nm node. The latest Apple smartphone (iPhone 8 and iPhone X),
on the hand, was released in September, 2017. The CPU was called A11 Bionic and fabricated by
Taiwan Semiconductor Manufacturing Company (tsmc) with 10 nm node. The most powerful and
smartest chip ever in a smartphone said by Phil Schiller, the vice president of Apple, indicating its
superior performance than others. According to Geekbench Browser results, A11 receives better
scores than Exynos8895 not only on single-core (215 % higher) but multi-core (157 % higher) [4].
Similar comparison between these two 10 nm node chips can be found from afterward articles and
internet platforms.

In this report, we, MSSCORPS, try to adopt another approach, material analysis, to understand
differences between these two chips shown in Figure 1. It is well-known that the base architecture
of A11 and Exynos8895 is 10 nm node FinFET structure. Advanced analytic tools are therefore
needed. Transmission electron microscopy (TEM) with sub-nanometer resolution was used to
unveil the fine structures of FinFET. For elemental analysis, energy dispersive X-ray spectroscopy
(EDS) was utilized. Similar reverse engineering by comparing two intel 14 nm node CPU chips
has been published last year [5].
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FIG. 1. OM pictures of A11 (a) and Exynos8895 (b) chips used in the present investigation. Inserts show
the die logo.

intel tsmc Samsung

CPU Skylate Ksbylake A11 Bionic Exynos8895
Technology node 14 nm 14 nm + 10 nm 10 nm
Fin height (H) 42.0 46.0 42.1 48.6
Fin width (d) 8.0 7.0 5.4 5.9
Fin pitch (W) 42.0 45.0 35.1 46.8
Area of 6T-SRAM 69,167 70,158 40,233 49,648

TABLE I. Fin parameters for four CPUs. The definition of H, W, and d is shown in the left-hand side fin
model. Unit for H, W, and d is nm, for area is nm2 .

II. 6T-SRAM

6T-SRAM, static random-access memory, has been widely used for CPU cache due to its low
power consumption, reliability, and speed. To investigate and compare the details of fabrication
processes from different Fabs and technology nodes, therefore, 6T-SRAM is a nice target for such
purpose. According to the intels presentation by Mark Bohr in 2017 [6], the transistor density is
over double (2.1-2.7 times) from generation to generation. It is expected that the transistor density
of 10 nm node will be 2.7 times higher than that of 14 nm node. Since we have studied intel 14 nm
and 14 nm plus before [5], from engineer point of view, it will be interesting and desirable to learn
how to achieve technology progress to make an even denser chip, i.e. 10 nm node. In this report,
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FIG. 2. Plane-view STEM images on 6T-SRAM area for A11 (a) and Exynos8895 (b), (c) and (d) are
corresponding EDS mappings of (a) and (b), respectively.

two 10 nm node CPUs are introduced and compared, see Figure 1, one is i8-A11 Bionic, iPhone 8
CPU fabricated by tsmc and the other is Exynos8895, Galaxy S8 CPU fabricated by Samsung.

III. PHYSICAL AND CHEMICAL PROPERTIES OF FINFET STRUCTURE

With the help of TEM images and EDS mapping, detailed fin structure between these two
chips can be well investigated. We start with the plane-view observation. Figure 2(a) and (b)
show plane-view STEM images on 6T-SRAM area for both chips. It is clearly found that the fin
pitch for A11 is smaller than that for Exynos8895 (see table 1). It turns out that the unit cell of
the 6T-SRAM for A11 (310.2 nm×129.7 nm) is 18.8 % smaller than that for Exynos8895 (382.2
nm×129.9 nm). In other words, in the same 6T-SRAM area, the number of transistor for A11
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FIG. 3. Cross-section,perpendicular to the fin direction, TEM images on 6T-SRAM area for A11 (a) and
Exynos8895 (b). (c) and (d) are corresponding EDS mappings of (a) and (b), respectively.

could be 1.23 times higher than that for Exynos8895. Chemical distribution and identify were
analyzed by EDS mapping shown in Figure 2(c) and (d) exhibit that no obvious material selection
is found by comparing these two chips.

Figure 3(a) and (b) show cross-section (perpendicular to the fin direction) TEM images, where
two types of fins (N-fins and P-fins) can be clearly identified, for A11 and Exynos8895, respec-
tively. Based on the results, several differences on fin structure between these two chips are found:
Firstly, etching process for N-fins is different. For A11, the fin etching process between two
neighboring N-fins stops at about half of the fin height. Etching down to the bottom of the N-fins,
however, is found for Exynos8895.

Structurally, fin dimensions are different and key parameters are summarized in table 1. For
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FIG. 4. Cross-section HAADF images for A11 (a) and Exynos8895 (b). Super-thin TEM lamella (5-10
nm) were prepared in the direction marked by red dotted lines in the inserts of (a) and (b). (c) and (d) are
corresponding EDS mappings of (a) and (b), respectively.

comparison, parameters for two intel chips [5] are listed as well. It seems that the 10 nm design rule
for these two world-renowned Fabs goes to different approaches in order to gain chip performance.
Samsung takes more efforts on fin height and width. Higher fin height and broader fin width
indicate, in principle, bigger channel area and then increasing performance. For tsmc A11, on
the other hand, an eminent breakthrough on the density scaling is found, i.e. fin pitch is 25 %
smaller than Samsung Exynos8895. With the same 6T-SRAM volume, it can drastically reduce
the memory area to save chip space.

The EDS mappings are shown in Figure 3(c) and (d). Essentially, no obvious differences on
material selection are found between A11 and Exynos8895. For the generation of 10 nm tech-
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nology node, apparently, Si fin is still dominate. In order to gain more device performance [7],
it is scheduled to be adopted SiGe fin for 7 nm technology node by Globalfoundries, IBM, and
Samsung [8, 9].

IV. SIGE STRUCTURE AND ITS STRAIN

FIG. 5. Cross-section SEM images of A11 (a) and Exynos8895 (b).The metal thickness from M1 to M11
for A11 (h1) and Exynos8895 (h2) is 2.88 µm and 3.21 µm.

It is well-known that SiGe process is one of critical steps for advanced technology node. Be-
cause of build-up strain induced by lattice mismatch between Si and SiGe, the carry mobility can
be remarkably increased to enhance the chip performance. It is therefore important to understand
the details of SiGe. A very thin TEM sample (5-10 nm) was prepared in order to clearly unveil the
desired structures. Figure 4 shows high-angle annular dark-field (HAADF) images and EDS map-
pings of A11 and Exynos8895 parallel with P-fin. Details of W contact formation (M0) processes
for these two chips can be clearly found and compared. An interesting finding about the chemical
composition of SiGe shown in EDS mappings (Figure 4(c) and (d)) is two clear Ge composition
distributions are observed for both chips. Similar finding was also found for intel 14 nm plus
chip [5]. It is expected that such Ge composition variation has certain effects on increasing carry
mobility to enhance the chip performance.
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V. METAL INTER-CONNECTION AND DIMENSION SCALING

The metal inter-connection comparison was investigated by SEM shown in Figure 5. The metal
thickness from M1 to M11 for A11 is approximate 300 nm thinner than that for Exynos8895. It
is expected that in principle A11 should have worse side effects such as parasitic capacitance and
signal RC relay. There are two ways to reduce the RC delay, by changing metal material with a
lower resistivity and using IMD with a lower dielectric constant. To keep the chip performance, it
is believed that tsmc should pay more efforts on this issue. Deeper investigations will be carried
out to unveil the details.

VI. SUMMARY

In summary, in this report we have delivered material analysis on two CPUs with 10 nm tech-
nology node from most advanced mobile phones in the market. Samsung, Exynos8895 has a
higher fin height and broader fin with, tsmc A11, on the other hand, has shorter fin pitch and
thinner inter-connection thickness. Still, there are many factors not discussed in the present report
will cause effects on chip performance. But one thing is for sure that not only tsmc and Samsung
but intel and Globalfoundries will keep fabricating chips with even more advanced technology
node. Engineers will face challenging tasks in all respects for such small dimensions. Therefore,
advanced material analysis is needed. As the best material analysis provider and R&D partner, we,
MSSCORPS, will also progress with our customers and continually deliver precise and accurate
analysis.

VII. ACKNOWLEDGEMENT

The authors would like to thank TEM team in MSSCORPS for their great support.

[1] G. Moore, ”Progress in digital integrated electronics”, IEEE, IEDM Tech Digest, 11, 1975.
[2] R. Merritt, ”4 views of the silicon roadmap”, EE Times, 19 May, 2017.
[3] IDC webpage, https://www.idc.com.
[4] Geekbench, https://browser.geekbench.com/.
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[5] MSScorps, ”Evolution of intel 14 nm vs. 14 nm plus from material analysis point of view”, EE Times
Taiwan, 8 May, 2017.
[6] Mark Bohr, ”Moores law leadership”, intel newsroom, 28 March, 2017.
[7] S.E. Thompson et al., ”A logic nanotechnology featuring strained-silicon”, IEEE Electron Device Let-
ters, 25, 4 (2004); T. Ghani et al., ”A 90 nm high volume manufacturing logic technology featuring
novel 45nm gate length strained silicon CMOS transistors”, DOI: 10.1109/IEDM.2003.1269442; A.S.
Zoolfakar and A. Ahmad, ”Holes mobility enhancement using strained silicon, SiGe technology”, DOI:
10.1109/CSPA.2009.5069248.
[8] D. James, ”IEDM-setting the stage for 7/5 nm”, Solid State Technology, 2016.
[9] Xie et al., ”A 7 nm FinFET technology featuring EUV patterning and dual strained high mobility
channels”, IEEE, IEDM, 47, 2016.