UNIVERSITY OF GUYANA

Phase Lock Loops

ELE 3114

NAME: SHAWN RAMDEO

USI: 1024273
Phase Lock Loops
Definition
A PLL (Phase Lock Loop) is a feedback system that includes a VCO, phase detector, and low pass filter
within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input
when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to
have a phase offset between input and output, but when locked, the frequencies must exactly track.
This all works because frequency and phase are related by:

1 dϕ ( t )
ϕ ( t )=2 π ∫ f ( t ) dt=f ( t )= .
2 π dt

Components of PLL
Phase Detector
A phase detector has two inputs and one output; the two inputs receive electronic signals, which the phase
detector compares the phase relationship between. The phase detector outputs a voltage based on the
phase relationship between these two signals. Phase detectors are typically of two types, called Type I and
Type II.
A Type I detector is designed to be driven by analog signals or square-wave digital signals and produces
an output pulse at the difference frequency. The Type I detector always produces an output waveform,
which must be filtered to control the phase-locked loop voltage-controlled oscillator (VCO). A type II
detector is sensitive only to the relative timing of the edges of the input and reference pulses, and
produces a constant output proportional to phase difference when both signals are at the same frequency.
This output will tend not to produce ripple in the control voltage of the VCO. Based on the input signal
different phase detectors are used.
 For Type I detectors, where the input is analog say
some radio frequency signal, a device called a
Double Balanced Diode Mixer can be used, this
is pretty much a multiplier and produces lots for
frequencies, i.e. sum, difference, harmonics, etc.
These unwanted frequencies need to be filtered out
since we are only interested in the difference
between the phases.

In the case
where our input is digital we ca use a simple XOR logic gate, recall
from digital logic that such a gate will output a 0 if both of its inputs
are the same (i.e. both 1 and both 0), but it will output a 1 if the
inputs are different. Therefore, an XOR acts as a sort of "out-of-
phase alarm", creating a high voltage whenever its inputs are out of
phase, but staying dormant as long as both of the inputs are perfectly
in sync. With the use of an XOR gate, another device called a charge
pump is usually needed, as the output of the gate is just an error
pulse, the charge pump converts the digital error pulse to an analog
error current. The charge pump can be thought of as a device that
essentially has two current sources that are precisely matched and
these are going to be hooked up together by some switch so that they
feed one output. The switches are toggled so that one increases the
output frequency and one lowers the output frequency. This device is usually built in within most PLL
chips.
Charge Pump
The charge-pump consists of a set of current sources
with magnitudes of IP1 and IP2 amps respectively. In
most cases the current sources are symmetrical
thus IP1 = IP2 = IP
One source is connected to the positive supply rail
while the other is connected to the negative supply
rail. The sources are separated by two
switches S1 and S2. The output of the phase detector
provides the gating signals U (up) and D (down)
which turn on S1 and S2 respectively. The phase
detector is designed such that switches are never on
simultaneously. When U is high and D is low
then S1 is on and S2 is off which causes current to
flow out of the pump and into the loop-filter.
When U is low and D is high then Q1 is off and Q2 is on which causes current to flow out of loop-filter
and into the pump.
 Type II detectors
Type II detectors are a bit different since they
respond to the edges or which signal is
leading. One such device is a Phase
Frequency Detector (PFD)
The PFD works by looking to the edges of the
signal and then sends either a positive or
negative pulse based on the edge used. To put
light on to that, say that our VCO signal is too
slow, then the PFD will send positive pulses
in order to speed that signal up, while going
into a high impedance state if the VCO is
leading. The PFD is also used with a Charge
pump. The PFD has advantages since it has
frequency detection, won’t lock on harmonics, and signals don’t have to be 50% duty cycles. Contrary to
this it is not a good at handling noisy signals as type I detectors.

Loop Filter
Loop filter:   This filter is used to filter the output from the phase comparator in the phase locked loop,
PLL. It is used to remove any components of the signals of which the phase is being compared from the
VCO line, i.e. the reference and VCO input. It also governs many of the characteristics of the loop
including the loop stability, speed of lock, etc. 
The loop filter characteristics affect a number of areas of the phase locked loop performance.
 Filter comparison frequency:  
One of the major functions of the
loop filter is to remove unwanted
components of the phase detection
or phase comparison frequencies.
If they appear at the input to the
VCO, then sidebands will appear
offset from the carrier by a
frequency equal to the phase
comparison frequency.
Loop stability:   The break points
and roll off of the loop filter are of
particular importance. The filter should be designed to give the required fall in loop gain at the
unity gain point for the loop, otherwise the loop can become unstable.
 Transient response / tracking:   In some applications it may be necessary for the phase locked
loop to track another signal or change frequency. The loop filter acts to slow the response down.
The narrower the loop bandwidth, i.e. the lower the cut-off frequency of the filter, the slower the
response of the loop to responding to changes. Conversely if the loop requires a fast response to
changes in frequency, then it will need a wide loop bandwidth.
The low pass filter is used to allow all the high frequencies from the mixer to ground. The figure shows a
passive filter, active filters can also be used.
VCO (voltage-controlled oscillator)
The VCO is just that: An oscillator with an input line that will vary the speed of oscillation. Typically, a
higher voltage going into the VCO will make it speed up, while a lower voltage will make it slow down.
VCOs generally also have a fundamental frequency they run at when the input voltage is zero; this may
be known as the fundamental frequency, the center frequency, the free-running frequency, or the
quiescent frequency. These terms mean the same thing; they're just a matter of terminology. The VCO
must be monotonic meaning the slope has to always be positive.
When designing a voltage controlled oscillator, VCO, there are several parameters that must be
considered before the design starts. These define the key performance parameters needed for the VCO.
 VCO tuning range:   It is obvious that the voltage controlled oscillator must be able to tune over
the range that the loop is expected to operate over. This requirement is not always easy to meet
and may require the VCO or resonant circuit to be switched in some extreme circumstances.
 VCO tuning gain:   The gain of the voltage controlled oscillator is important. It is measured in
terms of volts per Hz (or V/MHz, etc.). As implied by the units it is the tuning shift for a given
change in voltage. The voltage controlled oscillator gain affects some of the overall loop design
considerations and calculations. 
 VCO V/f slope:   It is a key
requirement for any voltage
controlled oscillator used in a
phase locked loop that the
voltage to frequency curve is
monotonic, i.e. it always
changes in the same sense,
typically increasing frequency
for increasing voltage. If it
changes, as can happen in
some instances normally as a
result of spurious resonances,
etc., this can cause the loop to
become unstable. Accordingly,
this must be prevented if the
phase locked loop is to operate satisfactorily.
Like any oscillator, a VCO may be considered as an
amplifier and a feedback loop. The gain of the
amplifier may be denoted as A and the feedback as
B.

For the circuit to oscillate the total phase shift around

the loop must be 360° and the gain must be unity. In
this way signals are fed back round the loop so that
they are additive and as a result, any small
disturbance in the loop is fed back and builds up. In
view of the fact that the feedback network is
frequency dependent, the build-up of signal will
occur on one frequency, the resonant frequency of the feedback network, and a single frequency signal is
produced.

This circuit and the one above are both VCOs, one
uses an op amp while the other doesn’t. The VCO its
pretty much an integrator as we will see later on.

Analysis of Loop Behavior

The analysis of PLL can be done differently based on if
the input signal is digital or analog. The basic operation
stays the same however.
In the basic PLL, input signal and the signal from the
voltage controlled oscillator are connected to the two
input ports of the phase detector. The output from the
phase detector is passed to the loop filter and then filtered
signal is applied to the voltage controlled oscillator.
The Voltage Controlled Oscillator, VCO, within the PLL produces a signal which enters the phase
detector. Here the phase of the signals from the VCO and the incoming signal are compared and a
resulting difference or error voltage is produced. This corresponds to the phase difference between the
two signals.
The error signal from the phase detector passes through a low pass filter which governs many of the
properties of the loop and removes any high frequency elements on the signal. Once through the filter the
error signal is applied to the control terminal of the VCO as its tuning voltage. The sense of any change in
this voltage is such that it tries to reduce the phase difference and hence the frequency between the two
signals. Initially the loop will be out of lock, and the error voltage will pull the frequency of the VCO
towards that of the input, until it cannot reduce the error any further and the loop is locked.
When the PLL, phase locked loop, is in lock a steady state error voltage is produced. By using an
amplifier between the phase detector and the VCO, the actual error between the signals can be reduced to
very small levels. However some voltage must always be present at the control terminal of the VCO as
this is what puts onto the correct frequency. The fact that a steady error voltage is present means that the
phase difference between the input signal and the VCO is not changing. As the phase between these two
signals is not changing means that the two signals are on exactly the same frequency.
Mathematical Analysis

Phase detector: compares the phase at each

input and generates an error signal, Ve (t),
proportional to the phase difference between
the two inputs. KD is the gain of the phase
detector (V/rad).

Recall that the mixer takes the product of

two inputs.
Ve (t) = A
(t) B (t).

Since the two inputs are at the same frequency when the loop is locked, we have one output at twice the
input frequency and an output proportional to the cosine of the phase difference. The doubled frequency
component must be removed by the low pass loop filter. Any phase difference then shows up as the
control voltage to the VCO, a DC or slowly varying AC signal after filtering.
VCO. In PLL applications, the VCO is treated as a linear, time-
invariant system. Excess phase of the VCO is the system output.
The VCO oscillates at an angular frequency, ωout. Its frequency is
set to a nominal ω0 when the control voltage is zero. Frequency is
assumed to be linearly proportional to the control voltage with a
gain coefficient KO or KVCO (rad/s/v)
Thus, to obtain an arbitrary output frequency (within the VCO
tuning range, of course), a
finite Vcont is required. Let’s
define φout – φin = φο.
In the figure to the right, the
two inputs to the phase
detector are depicted as
square waves. The XOR function produces an output pulse whenever there is a phase misalignment.
Suppose that an output frequency ω1 is needed. From the upper right figure, we see that a control voltage
V1 will be necessary to produce this output frequency. The phase detector can produce this V1 only by
maintaining a phase offset φ0 at its input. In order to minimize the required phase offset or error, the PLL
loop gain, KD KO, should be maximized, since

Thus, a high loop gain is beneficial for reducing phase errors

PLL dynamic response: To see how the PLL works, suppose that
we introduce a phase step at the input at t = t1.
Since we have a step in phase, it is
clear that the initial and final
frequencies must be identical: ω1.
But, a temporary change in
frequency is necessary to shift the
phase by φ1. The area under ωout
gives the additional phase because
Vcont is proportional to frequency.

After settling, all parameters are as

before since the initial and final frequencies are the same. This shows that Vcont(t) [shown as VLPF (t) in
the figure above] can be used to monitor the dynamic phase response of the PLL
Now, let’s investigate the behavior during a frequency step:
The frequency step will cause the phase difference to grow with time
since a frequency step is a phase ramp. This in turn causes the control
voltage, Vcont, to increase, moving the VCO frequency up to catch up with the input reference signal. In
this case, we have a permanent change in ωout since a higher Vcont is required to sustain a higher ωout.
If the frequency step is too large, the
PLL will lose lock.
Lock Range. Range of input signal
frequencies over which the loop
remains locked once it has captured
the input signal. This can be limited
either by the phase detector or the
VCO frequency range.
Capture range: Range of input
frequencies around the VCO center
frequency onto which the loop will lock when starting from an unlocked condition. Sometimes a
frequency detector is added to the phase detector to assist in initial acquisition of lock

Applications

FM demodulation:   One major phase locked loop application is that of a FM demodulator. With PLL
chips now relatively cheap, this PLL applications enables high quality audio to be demodulated from an
FM signal.
Indirect frequency synthesizers:   Use within a frequency synthesizer is one of the most important phase
locked loop applications. Although direct digital synthesis is also used, indirect frequency synthesis forms
one of the major phase locked loop applications.
Signal recovery:   The fact that the phase locked loop is able to lock to a signal enables it to provide a
clean signal, and remember the signal frequency if there is a short interruption. This phase locked loop
application is used in a number of areas where signals may be interrupted for short periods of time, for
example when using pulsed transmissions.
Timing distribution:   Another phase locked loop application is in the distribution precisely timed clock
pulses in digital logic circuits and system, for example within a microprocessor system.
Clock recovery: Some data streams, especially high-speed serial data streams (such as the raw stream of
data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver
generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the
data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work,
the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator.
Typically, some sort of line code, such as 8b/10b encoding, is used to put a hard upper bound on the
maximum time between transitions.
Signal cleanup: Another excellent application for PLLs is signal cleanup. Suppose you have a noisy
signal, afflicted with occasional glitches that might wreak havoc on a digital circuit if you're using that
signal as a timing clock. You can make the PLL smooth this noisy clock out if you add a low-pass filter
(LPF) between the phase detector's output and the VCO's input.

References:
UCSB/ECE Department Prof S. Long 4/27/05 – PDF
https://web.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf
Introduction to the phase-locked loop (PLL) - PDF
http://lateblt.tripod.com/pll.htm
Phase-Locked Loop (PLL) Fundamentals – PDF by Ian Collins
https://www.analog.com/en/analog-dialogue/articles/phase-locked-loop-pll-fundamentals.html
All About Circuits – Article by March 09, 2018 by Robert Keim
https://www.allaboutcircuits.com/technical-articles/what-exactly-is-a-phase-locked-loop-anyways/
Phase Lock Loops and Frequency Synthesis V.F. Kroupa 2003 John Wiley & Sons, Ltd ISBN: 0-470-
84866-9
https://catalogimages.wiley.com/images/db/pdf/0470848669.excerpt.pdf